1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2002 Benno Rice.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/conf.h>
32 #include <sys/kernel.h>
33 #include <sys/ktr.h>
34 #include <sys/proc.h>
35 #include <sys/rman.h>
36 #include <sys/sched.h>
37 #include <sys/smp.h>
38
39 #include <machine/bus.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/md_var.h>
42 #include <machine/pio.h>
43 #include <machine/resource.h>
44
45 #include <vm/vm.h>
46 #include <vm/pmap.h>
47
48 #include <machine/openpicreg.h>
49 #include <machine/openpicvar.h>
50
51 #include "pic_if.h"
52
53 #define OPENPIC_NIPIS 4
54
55 /*
56 * Local routines
57 */
58 static int openpic_intr(void *arg);
59
60 static __inline uint32_t
openpic_read(struct openpic_softc * sc,u_int reg)61 openpic_read(struct openpic_softc *sc, u_int reg)
62 {
63 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
64 }
65
66 static __inline void
openpic_write(struct openpic_softc * sc,u_int reg,uint32_t val)67 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
68 {
69 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
70 }
71
72 int
openpic_common_attach(device_t dev,uint32_t node)73 openpic_common_attach(device_t dev, uint32_t node)
74 {
75 struct openpic_softc *sc;
76 u_int cpu, ipi, irq;
77 u_int32_t x;
78
79 sc = device_get_softc(dev);
80 sc->sc_dev = dev;
81
82 sc->sc_rid = 0;
83 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
84 RF_ACTIVE);
85
86 if (sc->sc_memr == NULL) {
87 device_printf(dev, "Could not alloc mem resource!\n");
88 return (ENXIO);
89 }
90
91 sc->sc_bt = rman_get_bustag(sc->sc_memr);
92 sc->sc_bh = rman_get_bushandle(sc->sc_memr);
93
94 /* Reset the PIC */
95 x = openpic_read(sc, OPENPIC_CONFIG);
96 x |= OPENPIC_CONFIG_RESET;
97 openpic_write(sc, OPENPIC_CONFIG, x);
98
99 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
100 powerpc_sync();
101 DELAY(100);
102 }
103
104 /* Check if this is a cascaded PIC */
105 sc->sc_irq = 0;
106 sc->sc_intr = NULL;
107 do {
108 struct resource_list *rl;
109
110 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
111 if (rl == NULL)
112 break;
113 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
114 break;
115
116 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
117 &sc->sc_irq, RF_ACTIVE);
118
119 /* XXX Cascaded PICs pass NULL trapframes! */
120 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
121 openpic_intr, NULL, dev, &sc->sc_icookie);
122 } while (0);
123
124 /* Reset the PIC */
125 x = openpic_read(sc, OPENPIC_CONFIG);
126 x |= OPENPIC_CONFIG_RESET;
127 openpic_write(sc, OPENPIC_CONFIG, x);
128
129 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
130 powerpc_sync();
131 DELAY(100);
132 }
133
134 x = openpic_read(sc, OPENPIC_FEATURE);
135 switch (x & OPENPIC_FEATURE_VERSION_MASK) {
136 case 1:
137 sc->sc_version = "1.0";
138 break;
139 case 2:
140 sc->sc_version = "1.2";
141 break;
142 case 3:
143 sc->sc_version = "1.3";
144 break;
145 default:
146 sc->sc_version = "unknown";
147 break;
148 }
149
150 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
151 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
152 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
153 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
154 /*
155 * Generate the vector mask used for IACK.
156 * Some PICs may not support the full 11 bit vector width, so clamp the
157 * mask to only the next-power-of-2 from the max IRQ.
158 */
159 sc->sc_vec_mask = (1 << fls(sc->sc_nirq)) - 1;
160
161 /*
162 * PSIM seems to report 1 too many IRQs and CPUs
163 */
164 if (sc->sc_psim) {
165 sc->sc_nirq--;
166 sc->sc_ncpu--;
167 }
168
169 if (bootverbose)
170 device_printf(dev,
171 "Version %s, supports %d CPUs and %d irqs\n",
172 sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
173
174 /*
175 * Allow more IRQs than what the PIC says it handles. Some Freescale PICs
176 * have MSIs that show up above the PIC's self-described 196 IRQs
177 * (P5020 starts MSI IRQs at 224).
178 */
179 if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS)
180 sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS;
181
182 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
183 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
184
185 /* Reset and disable all interrupts. */
186 for (irq = 0; irq < sc->sc_nirq; irq++) {
187 x = irq; /* irq == vector. */
188 x |= OPENPIC_IMASK;
189 x |= OPENPIC_POLARITY_NEGATIVE;
190 x |= OPENPIC_SENSE_LEVEL;
191 x |= 8 << OPENPIC_PRIORITY_SHIFT;
192 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
193 }
194
195 /* Reset and disable all IPIs. */
196 for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) {
197 x = sc->sc_nirq + ipi;
198 x |= OPENPIC_IMASK;
199 x |= 15 << OPENPIC_PRIORITY_SHIFT;
200 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
201 }
202
203 /* we don't need 8259 passthrough mode */
204 x = openpic_read(sc, OPENPIC_CONFIG);
205 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
206 openpic_write(sc, OPENPIC_CONFIG, x);
207
208 /* send all interrupts to cpu 0 */
209 for (irq = 0; irq < sc->sc_nirq; irq++)
210 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
211
212 /* clear all pending interrupts from cpu 0 */
213 for (irq = 0; irq < sc->sc_nirq; irq++) {
214 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
215 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
216 }
217
218 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
219 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
220
221 powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE);
222
223 /* If this is not a cascaded PIC, it must be the root PIC */
224 if (sc->sc_intr == NULL)
225 root_pic = dev;
226
227 return (0);
228 }
229
230 /*
231 * PIC I/F methods
232 */
233
234 static void
openpic_bind(device_t dev,u_int irq,cpuset_t cpumask,void ** priv __unused)235 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
236 {
237 struct openpic_softc *sc;
238 uint32_t mask;
239
240 /* If we aren't directly connected to the CPU, this won't work */
241 if (dev != root_pic)
242 return;
243
244 sc = device_get_softc(dev);
245
246 /*
247 * XXX: openpic_write() is very special and just needs a 32 bits mask.
248 * For the moment, just play dirty and get the first half word.
249 */
250 mask = cpumask.__bits[0] & 0xffffffff;
251 if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
252 int i = mftb() % CPU_COUNT(&cpumask);
253 int cpu, ncpu;
254
255 ncpu = 0;
256 CPU_FOREACH(cpu) {
257 if (!(mask & (1 << cpu)))
258 continue;
259 if (ncpu == i)
260 break;
261 ncpu++;
262 }
263 mask = (1 << __pcpu[cpu].pc_pic);
264 }
265
266 openpic_write(sc, OPENPIC_IDEST(irq), mask);
267 }
268
269 void
openpic_config(device_t dev,u_int irq,enum intr_trigger trig,enum intr_polarity pol)270 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
271 enum intr_polarity pol)
272 {
273 struct openpic_softc *sc;
274 uint32_t x;
275
276 sc = device_get_softc(dev);
277 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
278 if (pol == INTR_POLARITY_LOW)
279 x &= ~OPENPIC_POLARITY_POSITIVE;
280 else
281 x |= OPENPIC_POLARITY_POSITIVE;
282 if (trig == INTR_TRIGGER_EDGE)
283 x &= ~OPENPIC_SENSE_LEVEL;
284 else
285 x |= OPENPIC_SENSE_LEVEL;
286 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
287 }
288
289 static void
openpic_dispatch(device_t dev,struct trapframe * tf)290 openpic_dispatch(device_t dev, struct trapframe *tf)
291 {
292 struct openpic_softc *sc;
293 u_int cpuid, vector;
294
295 CTR1(KTR_INTR, "%s: got interrupt", __func__);
296
297 sc = device_get_softc(dev);
298
299 cpuid = (dev == root_pic) ? PCPU_GET(pic) : 0;
300
301 while (1) {
302 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
303 vector &= sc->sc_vec_mask;
304 if (vector == sc->sc_vec_mask)
305 break;
306 powerpc_dispatch_intr(vector, tf);
307 }
308 }
309
310 static int
openpic_intr(void * arg)311 openpic_intr(void *arg)
312 {
313 device_t dev = (device_t)(arg);
314
315 /* XXX Cascaded PICs do not pass non-NULL trapframes! */
316 openpic_dispatch(dev, NULL);
317
318 return (FILTER_HANDLED);
319 }
320
321 void
openpic_enable(device_t dev,u_int irq,u_int vector,void ** priv __unused)322 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
323 {
324 struct openpic_softc *sc;
325 uint32_t x;
326
327 sc = device_get_softc(dev);
328 if (irq < sc->sc_nirq) {
329 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
330 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
331 x |= vector;
332 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
333 } else {
334 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
335 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
336 x |= vector;
337 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
338 }
339 }
340
341 void
openpic_eoi(device_t dev,u_int irq __unused,void * priv __unused)342 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
343 {
344 struct openpic_softc *sc;
345 u_int cpuid;
346
347 sc = device_get_softc(dev);
348 cpuid = (dev == root_pic) ? PCPU_GET(pic) : 0;
349
350 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
351 }
352
353 static void
openpic_ipi(device_t dev,u_int cpu)354 openpic_ipi(device_t dev, u_int cpu)
355 {
356 struct openpic_softc *sc;
357
358 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
359
360 sc = device_get_softc(dev);
361 sched_pin();
362 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(pic), 0),
363 1u << pcpu_find(cpu)->pc_pic);
364 sched_unpin();
365 }
366
367 static void
openpic_mask(device_t dev,u_int irq,void * priv __unused)368 openpic_mask(device_t dev, u_int irq, void *priv __unused)
369 {
370 struct openpic_softc *sc;
371 uint32_t x;
372
373 sc = device_get_softc(dev);
374 if (irq < sc->sc_nirq) {
375 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
376 x |= OPENPIC_IMASK;
377 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
378 } else {
379 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
380 x |= OPENPIC_IMASK;
381 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
382 }
383 }
384
385 void
openpic_unmask(device_t dev,u_int irq,void * priv __unused)386 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
387 {
388 struct openpic_softc *sc;
389 uint32_t x;
390
391 sc = device_get_softc(dev);
392 if (irq < sc->sc_nirq) {
393 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
394 x &= ~OPENPIC_IMASK;
395 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
396 } else {
397 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
398 x &= ~OPENPIC_IMASK;
399 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
400 }
401 }
402
403 static int
openpic_suspend(device_t dev)404 openpic_suspend(device_t dev)
405 {
406 struct openpic_softc *sc;
407 int i;
408
409 sc = device_get_softc(dev);
410
411 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
412 for (i = 0; i < OPENPIC_NIPIS; i++) {
413 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
414 }
415
416 for (i = 0; i < 4; i++) {
417 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
418 }
419
420 for (i = 0; i < OPENPIC_TIMERS; i++) {
421 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
422 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
423 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
424 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
425 }
426
427 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
428 sc->sc_saved_vectors[i] =
429 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
430
431 return (0);
432 }
433
434 static int
openpic_resume(device_t dev)435 openpic_resume(device_t dev)
436 {
437 struct openpic_softc *sc;
438 int i;
439
440 sc = device_get_softc(dev);
441
442 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
443 for (i = 0; i < OPENPIC_NIPIS; i++) {
444 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
445 }
446
447 for (i = 0; i < 4; i++) {
448 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
449 }
450
451 for (i = 0; i < OPENPIC_TIMERS; i++) {
452 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
453 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
454 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
455 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
456 }
457
458 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
459 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
460
461 return (0);
462 }
463
464 static void
openpic_ap_init(device_t dev)465 openpic_ap_init(device_t dev)
466 {
467 struct openpic_softc *sc;
468
469 if (dev != root_pic)
470 return;
471
472 /*
473 * Not everything implements the full OpenPIC specification.
474 *
475 * Notably the CPC945 Bridge and Memory Controller User Manual, which
476 * is in the PPC 970 (ie Apple G5) CPUs, calls out a set of
477 * deviations from the specification. Thus we can't just assume
478 * WHOAMI is available everywhere.
479 *
480 * See 9.5.3.3 - Deviations from the OpenPIC specification.
481 * Notably - the WhoAmI register is actually 0xF8000050 for all CPUs.
482 */
483
484 sc = device_get_softc(dev);
485 if (sc->sc_quirks & OPENPIC_QUIRK_WHOAMI_WORKS)
486 PCPU_SET(pic, bus_read_4(sc->sc_memr, OPENPIC_WHOAMI));
487 else
488 PCPU_SET(pic, PCPU_GET(cpuid));
489 }
490
491 static device_method_t openpic_methods[] = {
492 /* Device interface */
493 DEVMETHOD(device_suspend, openpic_suspend),
494 DEVMETHOD(device_resume, openpic_resume),
495
496 /* PIC interface */
497 DEVMETHOD(pic_bind, openpic_bind),
498 DEVMETHOD(pic_config, openpic_config),
499 DEVMETHOD(pic_dispatch, openpic_dispatch),
500 DEVMETHOD(pic_enable, openpic_enable),
501 DEVMETHOD(pic_eoi, openpic_eoi),
502 DEVMETHOD(pic_ipi, openpic_ipi),
503 DEVMETHOD(pic_mask, openpic_mask),
504 DEVMETHOD(pic_unmask, openpic_unmask),
505 DEVMETHOD(pic_ap_init, openpic_ap_init),
506
507 DEVMETHOD_END
508 };
509
510 DEFINE_CLASS_0(openpic, openpic_class, openpic_methods,
511 sizeof(struct openpic_softc));
512