1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port 4 * 5 * Copyright (C) 2009 - 2011 Texas Instruments 6 * 7 * Author: Misael Lopez Cruz <misael.lopez@ti.com> 8 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com> 9 * Margarita Olaya <magi.olaya@ti.com> 10 * Peter Ujfalusi <peter.ujfalusi@ti.com> 11 */ 12 13 #include <linux/init.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/interrupt.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/slab.h> 22 #include <linux/pm_runtime.h> 23 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/dmaengine_pcm.h> 29 30 #include "omap-mcpdm.h" 31 #include "sdma-pcm.h" 32 33 struct mcpdm_link_config { 34 u32 link_mask; /* channel mask for the direction */ 35 u32 threshold; /* FIFO threshold */ 36 }; 37 38 struct omap_mcpdm { 39 struct device *dev; 40 unsigned long phys_base; 41 void __iomem *io_base; 42 int irq; 43 struct pm_qos_request pm_qos_req; 44 int latency[2]; 45 46 struct mutex mutex; 47 48 /* Playback/Capture configuration */ 49 struct mcpdm_link_config config[2]; 50 51 /* McPDM dn offsets for rx1, and 2 channels */ 52 u32 dn_rx_offset; 53 54 /* McPDM needs to be restarted due to runtime reconfiguration */ 55 bool restart; 56 57 /* pm state for suspend/resume handling */ 58 int pm_active_count; 59 60 struct snd_dmaengine_dai_dma_data dma_data[2]; 61 }; 62 63 /* 64 * Stream DMA parameters 65 */ 66 67 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val) 68 { 69 writel_relaxed(val, mcpdm->io_base + reg); 70 } 71 72 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg) 73 { 74 return readl_relaxed(mcpdm->io_base + reg); 75 } 76 77 #ifdef DEBUG 78 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) 79 { 80 dev_dbg(mcpdm->dev, "***********************\n"); 81 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", 82 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW)); 83 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n", 84 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS)); 85 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n", 86 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET)); 87 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n", 88 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR)); 89 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n", 90 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN)); 91 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n", 92 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET)); 93 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n", 94 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR)); 95 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n", 96 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN)); 97 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n", 98 omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL)); 99 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n", 100 omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA)); 101 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n", 102 omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA)); 103 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n", 104 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN)); 105 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n", 106 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP)); 107 dev_dbg(mcpdm->dev, "***********************\n"); 108 } 109 #else 110 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {} 111 #endif 112 113 /* 114 * Enables the transfer through the PDM interface to/from the Phoenix 115 * codec by enabling the corresponding UP or DN channels. 116 */ 117 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm) 118 { 119 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); 120 u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask; 121 122 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); 123 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); 124 125 ctrl |= link_mask; 126 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); 127 128 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); 129 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); 130 } 131 132 /* 133 * Disables the transfer through the PDM interface to/from the Phoenix 134 * codec by disabling the corresponding UP or DN channels. 135 */ 136 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm) 137 { 138 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); 139 u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK; 140 141 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); 142 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); 143 144 ctrl &= ~(link_mask); 145 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); 146 147 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); 148 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); 149 150 } 151 152 /* 153 * Is the physical McPDM interface active. 154 */ 155 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm) 156 { 157 return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) & 158 (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK); 159 } 160 161 /* 162 * Configures McPDM uplink, and downlink for audio. 163 * This function should be called before omap_mcpdm_start. 164 */ 165 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm) 166 { 167 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); 168 169 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN); 170 171 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET, 172 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL | 173 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL); 174 175 /* Enable DN RX1/2 offset cancellation feature, if configured */ 176 if (mcpdm->dn_rx_offset) { 177 u32 dn_offset = mcpdm->dn_rx_offset; 178 179 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset); 180 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN); 181 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset); 182 } 183 184 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, 185 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold); 186 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, 187 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold); 188 189 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET, 190 MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE); 191 } 192 193 /* 194 * Cleans McPDM uplink, and downlink configuration. 195 * This function should be called when the stream is closed. 196 */ 197 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm) 198 { 199 /* Disable irq request generation for downlink */ 200 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR, 201 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL); 202 203 /* Disable DMA request generation for downlink */ 204 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE); 205 206 /* Disable irq request generation for uplink */ 207 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR, 208 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL); 209 210 /* Disable DMA request generation for uplink */ 211 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE); 212 213 /* Disable RX1/2 offset cancellation */ 214 if (mcpdm->dn_rx_offset) 215 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0); 216 } 217 218 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id) 219 { 220 struct omap_mcpdm *mcpdm = dev_id; 221 int irq_status; 222 223 irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS); 224 225 /* Acknowledge irq event */ 226 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status); 227 228 if (irq_status & MCPDM_DN_IRQ_FULL) 229 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n"); 230 231 if (irq_status & MCPDM_DN_IRQ_EMPTY) 232 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n"); 233 234 if (irq_status & MCPDM_DN_IRQ) 235 dev_dbg(mcpdm->dev, "DN (playback) write request\n"); 236 237 if (irq_status & MCPDM_UP_IRQ_FULL) 238 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n"); 239 240 if (irq_status & MCPDM_UP_IRQ_EMPTY) 241 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n"); 242 243 if (irq_status & MCPDM_UP_IRQ) 244 dev_dbg(mcpdm->dev, "UP (capture) write request\n"); 245 246 return IRQ_HANDLED; 247 } 248 249 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream, 250 struct snd_soc_dai *dai) 251 { 252 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); 253 254 guard(mutex)(&mcpdm->mutex); 255 256 if (!snd_soc_dai_active(dai)) 257 omap_mcpdm_open_streams(mcpdm); 258 259 return 0; 260 } 261 262 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream, 263 struct snd_soc_dai *dai) 264 { 265 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); 266 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 267 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 268 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 269 270 guard(mutex)(&mcpdm->mutex); 271 272 if (!snd_soc_dai_active(dai)) { 273 if (omap_mcpdm_active(mcpdm)) { 274 omap_mcpdm_stop(mcpdm); 275 omap_mcpdm_close_streams(mcpdm); 276 mcpdm->config[0].link_mask = 0; 277 mcpdm->config[1].link_mask = 0; 278 } 279 } 280 281 if (mcpdm->latency[stream2]) 282 cpu_latency_qos_update_request(&mcpdm->pm_qos_req, 283 mcpdm->latency[stream2]); 284 else if (mcpdm->latency[stream1]) 285 cpu_latency_qos_remove_request(&mcpdm->pm_qos_req); 286 287 mcpdm->latency[stream1] = 0; 288 } 289 290 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, 291 struct snd_pcm_hw_params *params, 292 struct snd_soc_dai *dai) 293 { 294 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); 295 int stream = substream->stream; 296 struct snd_dmaengine_dai_dma_data *dma_data; 297 u32 threshold; 298 int channels, latency; 299 int link_mask = 0; 300 301 channels = params_channels(params); 302 switch (channels) { 303 case 5: 304 if (stream == SNDRV_PCM_STREAM_CAPTURE) 305 /* up to 3 channels for capture */ 306 return -EINVAL; 307 link_mask |= 1 << 4; 308 fallthrough; 309 case 4: 310 if (stream == SNDRV_PCM_STREAM_CAPTURE) 311 /* up to 3 channels for capture */ 312 return -EINVAL; 313 link_mask |= 1 << 3; 314 fallthrough; 315 case 3: 316 link_mask |= 1 << 2; 317 fallthrough; 318 case 2: 319 link_mask |= 1 << 1; 320 fallthrough; 321 case 1: 322 link_mask |= 1 << 0; 323 break; 324 default: 325 /* unsupported number of channels */ 326 return -EINVAL; 327 } 328 329 dma_data = snd_soc_dai_get_dma_data(dai, substream); 330 331 threshold = mcpdm->config[stream].threshold; 332 /* Configure McPDM channels, and DMA packet size */ 333 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 334 link_mask <<= 3; 335 336 /* If capture is not running assume a stereo stream to come */ 337 if (!mcpdm->config[!stream].link_mask) 338 mcpdm->config[!stream].link_mask = 0x3; 339 340 dma_data->maxburst = 341 (MCPDM_DN_THRES_MAX - threshold) * channels; 342 latency = threshold; 343 } else { 344 /* If playback is not running assume a stereo stream to come */ 345 if (!mcpdm->config[!stream].link_mask) 346 mcpdm->config[!stream].link_mask = (0x3 << 3); 347 348 dma_data->maxburst = threshold * channels; 349 latency = (MCPDM_DN_THRES_MAX - threshold); 350 } 351 352 /* 353 * The DMA must act to a DMA request within latency time (usec) to avoid 354 * under/overflow 355 */ 356 mcpdm->latency[stream] = latency * USEC_PER_SEC / params_rate(params); 357 358 if (!mcpdm->latency[stream]) 359 mcpdm->latency[stream] = 10; 360 361 /* Check if we need to restart McPDM with this stream */ 362 if (mcpdm->config[stream].link_mask && 363 mcpdm->config[stream].link_mask != link_mask) 364 mcpdm->restart = true; 365 366 mcpdm->config[stream].link_mask = link_mask; 367 368 return 0; 369 } 370 371 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream, 372 struct snd_soc_dai *dai) 373 { 374 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); 375 struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req; 376 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 377 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 378 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 379 int latency = mcpdm->latency[stream2]; 380 381 /* Prevent omap hardware from hitting off between FIFO fills */ 382 if (!latency || mcpdm->latency[stream1] < latency) 383 latency = mcpdm->latency[stream1]; 384 385 if (cpu_latency_qos_request_active(pm_qos_req)) 386 cpu_latency_qos_update_request(pm_qos_req, latency); 387 else if (latency) 388 cpu_latency_qos_add_request(pm_qos_req, latency); 389 390 if (!omap_mcpdm_active(mcpdm)) { 391 omap_mcpdm_start(mcpdm); 392 omap_mcpdm_reg_dump(mcpdm); 393 } else if (mcpdm->restart) { 394 omap_mcpdm_stop(mcpdm); 395 omap_mcpdm_start(mcpdm); 396 mcpdm->restart = false; 397 omap_mcpdm_reg_dump(mcpdm); 398 } 399 400 return 0; 401 } 402 403 static int omap_mcpdm_probe(struct snd_soc_dai *dai) 404 { 405 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); 406 int ret; 407 408 pm_runtime_enable(mcpdm->dev); 409 410 /* Disable lines while request is ongoing */ 411 pm_runtime_get_sync(mcpdm->dev); 412 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00); 413 414 ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM", 415 (void *)mcpdm); 416 417 pm_runtime_put_sync(mcpdm->dev); 418 419 if (ret) { 420 dev_err(mcpdm->dev, "Request for IRQ failed\n"); 421 pm_runtime_disable(mcpdm->dev); 422 } 423 424 /* Configure McPDM threshold values */ 425 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2; 426 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold = 427 MCPDM_UP_THRES_MAX - 3; 428 429 snd_soc_dai_init_dma_data(dai, 430 &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK], 431 &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]); 432 433 return ret; 434 } 435 436 static int omap_mcpdm_remove(struct snd_soc_dai *dai) 437 { 438 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); 439 440 free_irq(mcpdm->irq, (void *)mcpdm); 441 pm_runtime_disable(mcpdm->dev); 442 443 if (cpu_latency_qos_request_active(&mcpdm->pm_qos_req)) 444 cpu_latency_qos_remove_request(&mcpdm->pm_qos_req); 445 446 return 0; 447 } 448 449 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = { 450 .probe = omap_mcpdm_probe, 451 .remove = omap_mcpdm_remove, 452 .startup = omap_mcpdm_dai_startup, 453 .shutdown = omap_mcpdm_dai_shutdown, 454 .hw_params = omap_mcpdm_dai_hw_params, 455 .prepare = omap_mcpdm_prepare, 456 .probe_order = SND_SOC_COMP_ORDER_LATE, 457 .remove_order = SND_SOC_COMP_ORDER_EARLY, 458 }; 459 460 #ifdef CONFIG_PM_SLEEP 461 static int omap_mcpdm_suspend(struct snd_soc_component *component) 462 { 463 struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component); 464 465 if (snd_soc_component_active(component)) { 466 omap_mcpdm_stop(mcpdm); 467 omap_mcpdm_close_streams(mcpdm); 468 } 469 470 mcpdm->pm_active_count = 0; 471 while (pm_runtime_active(mcpdm->dev)) { 472 pm_runtime_put_sync(mcpdm->dev); 473 mcpdm->pm_active_count++; 474 } 475 476 return 0; 477 } 478 479 static int omap_mcpdm_resume(struct snd_soc_component *component) 480 { 481 struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component); 482 483 if (mcpdm->pm_active_count) { 484 while (mcpdm->pm_active_count--) 485 pm_runtime_get_sync(mcpdm->dev); 486 487 if (snd_soc_component_active(component)) { 488 omap_mcpdm_open_streams(mcpdm); 489 omap_mcpdm_start(mcpdm); 490 } 491 } 492 493 494 return 0; 495 } 496 #else 497 #define omap_mcpdm_suspend NULL 498 #define omap_mcpdm_resume NULL 499 #endif 500 501 #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) 502 #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE 503 504 static struct snd_soc_dai_driver omap_mcpdm_dai = { 505 .playback = { 506 .channels_min = 1, 507 .channels_max = 5, 508 .rates = OMAP_MCPDM_RATES, 509 .formats = OMAP_MCPDM_FORMATS, 510 .sig_bits = 24, 511 }, 512 .capture = { 513 .channels_min = 1, 514 .channels_max = 3, 515 .rates = OMAP_MCPDM_RATES, 516 .formats = OMAP_MCPDM_FORMATS, 517 .sig_bits = 24, 518 }, 519 .ops = &omap_mcpdm_dai_ops, 520 }; 521 522 static const struct snd_soc_component_driver omap_mcpdm_component = { 523 .name = "omap-mcpdm", 524 .suspend = omap_mcpdm_suspend, 525 .resume = omap_mcpdm_resume, 526 .legacy_dai_naming = 1, 527 }; 528 529 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd, 530 u8 rx1, u8 rx2) 531 { 532 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0)); 533 534 mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2); 535 } 536 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets); 537 538 static int asoc_mcpdm_probe(struct platform_device *pdev) 539 { 540 struct omap_mcpdm *mcpdm; 541 struct resource *res; 542 int ret; 543 544 mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL); 545 if (!mcpdm) 546 return -ENOMEM; 547 548 platform_set_drvdata(pdev, mcpdm); 549 550 mutex_init(&mcpdm->mutex); 551 552 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 553 if (res == NULL) 554 return -ENOMEM; 555 556 mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA; 557 mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA; 558 559 mcpdm->dma_data[0].filter_data = "dn_link"; 560 mcpdm->dma_data[1].filter_data = "up_link"; 561 562 mcpdm->io_base = devm_platform_ioremap_resource_byname(pdev, "mpu"); 563 if (IS_ERR(mcpdm->io_base)) 564 return PTR_ERR(mcpdm->io_base); 565 566 mcpdm->irq = platform_get_irq(pdev, 0); 567 if (mcpdm->irq < 0) 568 return mcpdm->irq; 569 570 mcpdm->dev = &pdev->dev; 571 572 ret = devm_snd_soc_register_component(&pdev->dev, 573 &omap_mcpdm_component, 574 &omap_mcpdm_dai, 1); 575 if (ret) 576 return ret; 577 578 return sdma_pcm_platform_register(&pdev->dev, "dn_link", "up_link"); 579 } 580 581 static const struct of_device_id omap_mcpdm_of_match[] = { 582 { .compatible = "ti,omap4-mcpdm", }, 583 { } 584 }; 585 MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match); 586 587 static struct platform_driver asoc_mcpdm_driver = { 588 .driver = { 589 .name = "omap-mcpdm", 590 .of_match_table = omap_mcpdm_of_match, 591 }, 592 593 .probe = asoc_mcpdm_probe, 594 }; 595 596 module_platform_driver(asoc_mcpdm_driver); 597 598 MODULE_ALIAS("platform:omap-mcpdm"); 599 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>"); 600 MODULE_DESCRIPTION("OMAP PDM SoC Interface"); 601 MODULE_LICENSE("GPL"); 602