1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/iio/buffer.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/kfifo_buf.h>
13 #include <linux/iio/sysfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/unaligned.h>
19
20 #include "adxl367.h"
21
22 #define ADXL367_REG_DEVID 0x00
23 #define ADXL367_DEVID_AD 0xAD
24
25 #define ADXL367_REG_STATUS 0x0B
26 #define ADXL367_STATUS_INACT_MASK BIT(5)
27 #define ADXL367_STATUS_ACT_MASK BIT(4)
28 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
29
30 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
31
32 #define ADXL367_REG_X_DATA_H 0x0E
33 #define ADXL367_REG_Y_DATA_H 0x10
34 #define ADXL367_REG_Z_DATA_H 0x12
35 #define ADXL367_REG_TEMP_DATA_H 0x14
36 #define ADXL367_REG_EX_ADC_DATA_H 0x16
37 #define ADXL367_DATA_MASK GENMASK(15, 2)
38
39 #define ADXL367_TEMP_25C 165
40 #define ADXL367_TEMP_PER_C 54
41
42 #define ADXL367_VOLTAGE_OFFSET 8192
43 #define ADXL367_VOLTAGE_MAX_MV 1000
44 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
45
46 #define ADXL367_REG_RESET 0x1F
47 #define ADXL367_RESET_CODE 0x52
48
49 #define ADXL367_REG_THRESH_ACT_H 0x20
50 #define ADXL367_REG_THRESH_INACT_H 0x23
51 #define ADXL367_THRESH_MAX GENMASK(12, 0)
52 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
53 #define ADXL367_THRESH_H_MASK GENMASK(6, 0)
54 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
55 #define ADXL367_THRESH_L_MASK GENMASK(7, 2)
56
57 #define ADXL367_REG_TIME_ACT 0x22
58 #define ADXL367_REG_TIME_INACT_H 0x25
59 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
60 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
61 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
62 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
63 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
64 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
65
66 #define ADXL367_REG_ACT_INACT_CTL 0x27
67 #define ADXL367_ACT_EN_MASK GENMASK(1, 0)
68 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
69
70 #define ADXL367_REG_FIFO_CTL 0x28
71 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
72 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
73
74 #define ADXL367_REG_FIFO_SAMPLES 0x29
75 #define ADXL367_FIFO_SIZE 512
76 #define ADXL367_FIFO_MAX_WATERMARK 511
77
78 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
79 #define ADXL367_SAMPLES_H_MASK BIT(2)
80 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
81 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
82
83 #define ADXL367_REG_INT1_MAP 0x2A
84 #define ADXL367_INT_INACT_MASK BIT(5)
85 #define ADXL367_INT_ACT_MASK BIT(4)
86 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
87
88 #define ADXL367_REG_FILTER_CTL 0x2C
89 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)
90 #define ADXL367_2G_RANGE_1G 4095
91 #define ADXL367_2G_RANGE_100MG 409
92 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)
93
94 #define ADXL367_REG_POWER_CTL 0x2D
95 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)
96
97 #define ADXL367_REG_ADC_CTL 0x3C
98 #define ADXL367_REG_TEMP_CTL 0x3D
99 #define ADXL367_ADC_EN_MASK BIT(0)
100
101 enum adxl367_range {
102 ADXL367_2G_RANGE,
103 ADXL367_4G_RANGE,
104 ADXL367_8G_RANGE,
105 };
106
107 enum adxl367_fifo_mode {
108 ADXL367_FIFO_MODE_DISABLED = 0b00,
109 ADXL367_FIFO_MODE_STREAM = 0b10,
110 };
111
112 enum adxl367_fifo_format {
113 ADXL367_FIFO_FORMAT_XYZ,
114 ADXL367_FIFO_FORMAT_X,
115 ADXL367_FIFO_FORMAT_Y,
116 ADXL367_FIFO_FORMAT_Z,
117 ADXL367_FIFO_FORMAT_XYZT,
118 ADXL367_FIFO_FORMAT_XT,
119 ADXL367_FIFO_FORMAT_YT,
120 ADXL367_FIFO_FORMAT_ZT,
121 ADXL367_FIFO_FORMAT_XYZA,
122 ADXL367_FIFO_FORMAT_XA,
123 ADXL367_FIFO_FORMAT_YA,
124 ADXL367_FIFO_FORMAT_ZA,
125 };
126
127 enum adxl367_op_mode {
128 ADXL367_OP_STANDBY = 0b00,
129 ADXL367_OP_MEASURE = 0b10,
130 };
131
132 enum adxl367_act_proc_mode {
133 ADXL367_LOOPED = 0b11,
134 };
135
136 enum adxl367_act_en_mode {
137 ADXL367_ACT_DISABLED = 0b00,
138 ADCL367_ACT_REF_ENABLED = 0b11,
139 };
140
141 enum adxl367_activity_type {
142 ADXL367_ACTIVITY,
143 ADXL367_INACTIVITY,
144 };
145
146 enum adxl367_odr {
147 ADXL367_ODR_12P5HZ,
148 ADXL367_ODR_25HZ,
149 ADXL367_ODR_50HZ,
150 ADXL367_ODR_100HZ,
151 ADXL367_ODR_200HZ,
152 ADXL367_ODR_400HZ,
153 };
154
155 struct adxl367_state {
156 const struct adxl367_ops *ops;
157 void *context;
158
159 struct device *dev;
160 struct regmap *regmap;
161
162 /*
163 * Synchronize access to members of driver state, and ensure atomicity
164 * of consecutive regmap operations.
165 */
166 struct mutex lock;
167
168 enum adxl367_odr odr;
169 enum adxl367_range range;
170
171 unsigned int act_threshold;
172 unsigned int act_time_ms;
173 unsigned int inact_threshold;
174 unsigned int inact_time_ms;
175
176 unsigned int fifo_set_size;
177 unsigned int fifo_watermark;
178
179 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
180 __be16 sample_buf;
181 u8 act_threshold_buf[2];
182 u8 inact_time_buf[2];
183 u8 status_buf[3];
184 };
185
186 static const unsigned int adxl367_threshold_h_reg_tbl[] = {
187 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H,
188 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H,
189 };
190
191 static const unsigned int adxl367_act_en_shift_tbl[] = {
192 [ADXL367_ACTIVITY] = 0,
193 [ADXL367_INACTIVITY] = 2,
194 };
195
196 static const unsigned int adxl367_act_int_mask_tbl[] = {
197 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK,
198 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK,
199 };
200
201 static const int adxl367_samp_freq_tbl[][2] = {
202 [ADXL367_ODR_12P5HZ] = {12, 500000},
203 [ADXL367_ODR_25HZ] = {25, 0},
204 [ADXL367_ODR_50HZ] = {50, 0},
205 [ADXL367_ODR_100HZ] = {100, 0},
206 [ADXL367_ODR_200HZ] = {200, 0},
207 [ADXL367_ODR_400HZ] = {400, 0},
208 };
209
210 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */
211 static const int adxl367_range_scale_tbl[][2] = {
212 [ADXL367_2G_RANGE] = {0, 2394347},
213 [ADXL367_4G_RANGE] = {0, 4788695},
214 [ADXL367_8G_RANGE] = {0, 9577391},
215 };
216
217 static const int adxl367_range_scale_factor_tbl[] = {
218 [ADXL367_2G_RANGE] = 1,
219 [ADXL367_4G_RANGE] = 2,
220 [ADXL367_8G_RANGE] = 4,
221 };
222
223 enum {
224 ADXL367_X_CHANNEL_INDEX,
225 ADXL367_Y_CHANNEL_INDEX,
226 ADXL367_Z_CHANNEL_INDEX,
227 ADXL367_TEMP_CHANNEL_INDEX,
228 ADXL367_EX_ADC_CHANNEL_INDEX
229 };
230
231 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX)
232 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX)
233 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX)
234 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX)
235 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX)
236
237 static const enum adxl367_fifo_format adxl367_fifo_formats[] = {
238 ADXL367_FIFO_FORMAT_X,
239 ADXL367_FIFO_FORMAT_Y,
240 ADXL367_FIFO_FORMAT_Z,
241 ADXL367_FIFO_FORMAT_XT,
242 ADXL367_FIFO_FORMAT_YT,
243 ADXL367_FIFO_FORMAT_ZT,
244 ADXL367_FIFO_FORMAT_XA,
245 ADXL367_FIFO_FORMAT_YA,
246 ADXL367_FIFO_FORMAT_ZA,
247 ADXL367_FIFO_FORMAT_XYZ,
248 ADXL367_FIFO_FORMAT_XYZT,
249 ADXL367_FIFO_FORMAT_XYZA,
250 };
251
252 static const unsigned long adxl367_channel_masks[] = {
253 ADXL367_X_CHANNEL_MASK,
254 ADXL367_Y_CHANNEL_MASK,
255 ADXL367_Z_CHANNEL_MASK,
256 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
257 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
258 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
259 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
260 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
261 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
262 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK,
263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
264 ADXL367_TEMP_CHANNEL_MASK,
265 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
266 ADXL367_EX_ADC_CHANNEL_MASK,
267 0,
268 };
269
adxl367_set_measure_en(struct adxl367_state * st,bool en)270 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)
271 {
272 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE
273 : ADXL367_OP_STANDBY;
274 int ret;
275
276 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,
277 ADXL367_POWER_CTL_MODE_MASK,
278 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK,
279 op_mode));
280 if (ret)
281 return ret;
282
283 /*
284 * Wait for acceleration output to settle after entering
285 * measure mode.
286 */
287 if (en)
288 msleep(100);
289
290 return 0;
291 }
292
adxl367_scale_act_thresholds(struct adxl367_state * st,enum adxl367_range old_range,enum adxl367_range new_range)293 static void adxl367_scale_act_thresholds(struct adxl367_state *st,
294 enum adxl367_range old_range,
295 enum adxl367_range new_range)
296 {
297 st->act_threshold = st->act_threshold
298 * adxl367_range_scale_factor_tbl[old_range]
299 / adxl367_range_scale_factor_tbl[new_range];
300 st->inact_threshold = st->inact_threshold
301 * adxl367_range_scale_factor_tbl[old_range]
302 / adxl367_range_scale_factor_tbl[new_range];
303 }
304
_adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)305 static int _adxl367_set_act_threshold(struct adxl367_state *st,
306 enum adxl367_activity_type act,
307 unsigned int threshold)
308 {
309 u8 reg = adxl367_threshold_h_reg_tbl[act];
310 int ret;
311
312 if (threshold > ADXL367_THRESH_MAX)
313 return -EINVAL;
314
315 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,
316 FIELD_GET(ADXL367_THRESH_VAL_H_MASK,
317 threshold));
318 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,
319 FIELD_GET(ADXL367_THRESH_VAL_L_MASK,
320 threshold));
321
322 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,
323 sizeof(st->act_threshold_buf));
324 if (ret)
325 return ret;
326
327 if (act == ADXL367_ACTIVITY)
328 st->act_threshold = threshold;
329 else
330 st->inact_threshold = threshold;
331
332 return 0;
333 }
334
adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)335 static int adxl367_set_act_threshold(struct adxl367_state *st,
336 enum adxl367_activity_type act,
337 unsigned int threshold)
338 {
339 int ret;
340
341 guard(mutex)(&st->lock);
342
343 ret = adxl367_set_measure_en(st, false);
344 if (ret)
345 return ret;
346
347 ret = _adxl367_set_act_threshold(st, act, threshold);
348 if (ret)
349 return ret;
350
351 return adxl367_set_measure_en(st, true);
352 }
353
adxl367_set_act_proc_mode(struct adxl367_state * st,enum adxl367_act_proc_mode mode)354 static int adxl367_set_act_proc_mode(struct adxl367_state *st,
355 enum adxl367_act_proc_mode mode)
356 {
357 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
358 ADXL367_ACT_LINKLOOP_MASK,
359 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK,
360 mode));
361 }
362
adxl367_set_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool en)363 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
364 enum adxl367_activity_type act,
365 bool en)
366 {
367 unsigned int mask = adxl367_act_int_mask_tbl[act];
368
369 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
370 mask, en ? mask : 0);
371 }
372
adxl367_get_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool * en)373 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
374 enum adxl367_activity_type act,
375 bool *en)
376 {
377 unsigned int mask = adxl367_act_int_mask_tbl[act];
378 unsigned int val;
379 int ret;
380
381 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
382 if (ret)
383 return ret;
384
385 *en = !!(val & mask);
386
387 return 0;
388 }
389
adxl367_set_act_en(struct adxl367_state * st,enum adxl367_activity_type act,enum adxl367_act_en_mode en)390 static int adxl367_set_act_en(struct adxl367_state *st,
391 enum adxl367_activity_type act,
392 enum adxl367_act_en_mode en)
393 {
394 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act];
395
396 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
397 ADXL367_ACT_EN_MASK << ctl_shift,
398 en << ctl_shift);
399 }
400
adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state * st,bool en)401 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
402 bool en)
403 {
404 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
405 ADXL367_INT_FIFO_WATERMARK_MASK,
406 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
407 }
408
adxl367_get_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode * fifo_mode)409 static int adxl367_get_fifo_mode(struct adxl367_state *st,
410 enum adxl367_fifo_mode *fifo_mode)
411 {
412 unsigned int val;
413 int ret;
414
415 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);
416 if (ret)
417 return ret;
418
419 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val);
420
421 return 0;
422 }
423
adxl367_set_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode fifo_mode)424 static int adxl367_set_fifo_mode(struct adxl367_state *st,
425 enum adxl367_fifo_mode fifo_mode)
426 {
427 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
428 ADXL367_FIFO_CTL_MODE_MASK,
429 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK,
430 fifo_mode));
431 }
432
adxl367_set_fifo_format(struct adxl367_state * st,enum adxl367_fifo_format fifo_format)433 static int adxl367_set_fifo_format(struct adxl367_state *st,
434 enum adxl367_fifo_format fifo_format)
435 {
436 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
437 ADXL367_FIFO_CTL_FORMAT_MASK,
438 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK,
439 fifo_format));
440 }
441
adxl367_set_fifo_watermark(struct adxl367_state * st,unsigned int fifo_watermark)442 static int adxl367_set_fifo_watermark(struct adxl367_state *st,
443 unsigned int fifo_watermark)
444 {
445 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;
446 unsigned int fifo_samples_h, fifo_samples_l;
447 int ret;
448
449 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK)
450 fifo_samples = ADXL367_FIFO_MAX_WATERMARK;
451
452 fifo_samples /= st->fifo_set_size;
453
454 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK,
455 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK,
456 fifo_samples));
457 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK,
458 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK,
459 fifo_samples));
460
461 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
462 ADXL367_SAMPLES_H_MASK, fifo_samples_h);
463 if (ret)
464 return ret;
465
466 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,
467 ADXL367_SAMPLES_L_MASK, fifo_samples_l);
468 if (ret)
469 return ret;
470
471 st->fifo_watermark = fifo_watermark;
472
473 return 0;
474 }
475
adxl367_set_range(struct iio_dev * indio_dev,enum adxl367_range range)476 static int adxl367_set_range(struct iio_dev *indio_dev,
477 enum adxl367_range range)
478 {
479 struct adxl367_state *st = iio_priv(indio_dev);
480 int ret;
481
482 guard(mutex)(&st->lock);
483
484 ret = adxl367_set_measure_en(st, false);
485 if (ret)
486 return ret;
487
488 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
489 ADXL367_FILTER_CTL_RANGE_MASK,
490 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK,
491 range));
492 if (ret)
493 return ret;
494
495 adxl367_scale_act_thresholds(st, st->range, range);
496
497 /* Activity thresholds depend on range */
498 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
499 st->act_threshold);
500 if (ret)
501 return ret;
502
503 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
504 st->inact_threshold);
505 if (ret)
506 return ret;
507
508 ret = adxl367_set_measure_en(st, true);
509 if (ret)
510 return ret;
511
512 st->range = range;
513
514 return 0;
515 }
516
adxl367_time_ms_to_samples(struct adxl367_state * st,unsigned int ms)517 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)
518 {
519 int freq_hz = adxl367_samp_freq_tbl[st->odr][0];
520 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];
521 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */
522 int freq_dhz = freq_hz * 10 + freq_microhz / 100000;
523
524 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000);
525 }
526
_adxl367_set_act_time_ms(struct adxl367_state * st,unsigned int ms)527 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)
528 {
529 unsigned int val = adxl367_time_ms_to_samples(st, ms);
530 int ret;
531
532 if (val > ADXL367_TIME_ACT_MAX)
533 val = ADXL367_TIME_ACT_MAX;
534
535 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);
536 if (ret)
537 return ret;
538
539 st->act_time_ms = ms;
540
541 return 0;
542 }
543
_adxl367_set_inact_time_ms(struct adxl367_state * st,unsigned int ms)544 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)
545 {
546 unsigned int val = adxl367_time_ms_to_samples(st, ms);
547 int ret;
548
549 if (val > ADXL367_TIME_INACT_MAX)
550 val = ADXL367_TIME_INACT_MAX;
551
552 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,
553 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK,
554 val));
555 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,
556 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK,
557 val));
558
559 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,
560 st->inact_time_buf, sizeof(st->inact_time_buf));
561 if (ret)
562 return ret;
563
564 st->inact_time_ms = ms;
565
566 return 0;
567 }
568
adxl367_set_act_time_ms(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int ms)569 static int adxl367_set_act_time_ms(struct adxl367_state *st,
570 enum adxl367_activity_type act,
571 unsigned int ms)
572 {
573 int ret;
574
575 guard(mutex)(&st->lock);
576
577 ret = adxl367_set_measure_en(st, false);
578 if (ret)
579 return ret;
580
581 if (act == ADXL367_ACTIVITY)
582 ret = _adxl367_set_act_time_ms(st, ms);
583 else
584 ret = _adxl367_set_inact_time_ms(st, ms);
585
586 if (ret)
587 return ret;
588
589 return adxl367_set_measure_en(st, true);
590 }
591
_adxl367_set_odr(struct adxl367_state * st,enum adxl367_odr odr)592 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)
593 {
594 int ret;
595
596 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
597 ADXL367_FILTER_CTL_ODR_MASK,
598 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK,
599 odr));
600 if (ret)
601 return ret;
602
603 st->odr = odr;
604
605 /* Activity timers depend on ODR */
606 ret = _adxl367_set_act_time_ms(st, st->act_time_ms);
607 if (ret)
608 return ret;
609
610 return _adxl367_set_inact_time_ms(st, st->inact_time_ms);
611 }
612
adxl367_set_odr(struct iio_dev * indio_dev,enum adxl367_odr odr)613 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr)
614 {
615 struct adxl367_state *st = iio_priv(indio_dev);
616 int ret;
617
618 guard(mutex)(&st->lock);
619
620 ret = adxl367_set_measure_en(st, false);
621 if (ret)
622 return ret;
623
624 ret = _adxl367_set_odr(st, odr);
625 if (ret)
626 return ret;
627
628 return adxl367_set_measure_en(st, true);
629 }
630
adxl367_set_temp_adc_en(struct adxl367_state * st,unsigned int reg,bool en)631 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,
632 bool en)
633 {
634 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,
635 en ? ADXL367_ADC_EN_MASK : 0);
636 }
637
adxl367_set_temp_adc_reg_en(struct adxl367_state * st,unsigned int reg,bool en)638 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,
639 unsigned int reg, bool en)
640 {
641 int ret;
642
643 switch (reg) {
644 case ADXL367_REG_TEMP_DATA_H:
645 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
646 break;
647 case ADXL367_REG_EX_ADC_DATA_H:
648 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
649 break;
650 default:
651 return 0;
652 }
653
654 if (ret)
655 return ret;
656
657 if (en)
658 msleep(100);
659
660 return 0;
661 }
662
adxl367_set_temp_adc_mask_en(struct adxl367_state * st,const unsigned long * active_scan_mask,bool en)663 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,
664 const unsigned long *active_scan_mask,
665 bool en)
666 {
667 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK)
668 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
669 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK)
670 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
671
672 return 0;
673 }
674
adxl367_find_odr(struct adxl367_state * st,int val,int val2,enum adxl367_odr * odr)675 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
676 enum adxl367_odr *odr)
677 {
678 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl);
679 int i;
680
681 for (i = 0; i < size; i++)
682 if (val == adxl367_samp_freq_tbl[i][0] &&
683 val2 == adxl367_samp_freq_tbl[i][1])
684 break;
685
686 if (i == size)
687 return -EINVAL;
688
689 *odr = i;
690
691 return 0;
692 }
693
adxl367_find_range(struct adxl367_state * st,int val,int val2,enum adxl367_range * range)694 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
695 enum adxl367_range *range)
696 {
697 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl);
698 int i;
699
700 for (i = 0; i < size; i++)
701 if (val == adxl367_range_scale_tbl[i][0] &&
702 val2 == adxl367_range_scale_tbl[i][1])
703 break;
704
705 if (i == size)
706 return -EINVAL;
707
708 *range = i;
709
710 return 0;
711 }
712
adxl367_read_sample(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)713 static int adxl367_read_sample(struct iio_dev *indio_dev,
714 struct iio_chan_spec const *chan,
715 int *val)
716 {
717 struct adxl367_state *st = iio_priv(indio_dev);
718 u16 sample;
719 int ret;
720
721 guard(mutex)(&st->lock);
722
723 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);
724 if (ret)
725 return ret;
726
727 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,
728 sizeof(st->sample_buf));
729 if (ret)
730 return ret;
731
732 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));
733 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
734
735 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);
736 if (ret)
737 return ret;
738
739 return IIO_VAL_INT;
740 }
741
adxl367_get_status(struct adxl367_state * st,u8 * status,u16 * fifo_entries)742 static int adxl367_get_status(struct adxl367_state *st, u8 *status,
743 u16 *fifo_entries)
744 {
745 int ret;
746
747 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */
748 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,
749 st->status_buf, sizeof(st->status_buf));
750 if (ret)
751 return ret;
752
753 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;
754
755 *status = st->status_buf[0];
756 *fifo_entries = get_unaligned_le16(&st->status_buf[1]);
757
758 return 0;
759 }
760
adxl367_push_event(struct iio_dev * indio_dev,u8 status)761 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status)
762 {
763 unsigned int ev_dir;
764
765 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status))
766 ev_dir = IIO_EV_DIR_RISING;
767 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status))
768 ev_dir = IIO_EV_DIR_FALLING;
769 else
770 return false;
771
772 iio_push_event(indio_dev,
773 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
774 IIO_EV_TYPE_THRESH, ev_dir),
775 iio_get_time_ns(indio_dev));
776
777 return true;
778 }
779
adxl367_push_fifo_data(struct iio_dev * indio_dev,u8 status,u16 fifo_entries)780 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status,
781 u16 fifo_entries)
782 {
783 struct adxl367_state *st = iio_priv(indio_dev);
784 int ret;
785 int i;
786
787 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status))
788 return false;
789
790 fifo_entries -= fifo_entries % st->fifo_set_size;
791
792 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);
793 if (ret) {
794 dev_err(st->dev, "Failed to read FIFO: %d\n", ret);
795 return true;
796 }
797
798 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
799 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
800
801 return true;
802 }
803
adxl367_irq_handler(int irq,void * private)804 static irqreturn_t adxl367_irq_handler(int irq, void *private)
805 {
806 struct iio_dev *indio_dev = private;
807 struct adxl367_state *st = iio_priv(indio_dev);
808 u16 fifo_entries;
809 bool handled;
810 u8 status;
811 int ret;
812
813 ret = adxl367_get_status(st, &status, &fifo_entries);
814 if (ret)
815 return IRQ_NONE;
816
817 handled = adxl367_push_event(indio_dev, status);
818 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries);
819
820 return handled ? IRQ_HANDLED : IRQ_NONE;
821 }
822
adxl367_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)823 static int adxl367_reg_access(struct iio_dev *indio_dev,
824 unsigned int reg,
825 unsigned int writeval,
826 unsigned int *readval)
827 {
828 struct adxl367_state *st = iio_priv(indio_dev);
829
830 if (readval)
831 return regmap_read(st->regmap, reg, readval);
832 else
833 return regmap_write(st->regmap, reg, writeval);
834 }
835
adxl367_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)836 static int adxl367_read_raw(struct iio_dev *indio_dev,
837 struct iio_chan_spec const *chan,
838 int *val, int *val2, long info)
839 {
840 struct adxl367_state *st = iio_priv(indio_dev);
841 int ret;
842
843 switch (info) {
844 case IIO_CHAN_INFO_RAW:
845 if (!iio_device_claim_direct(indio_dev))
846 return -EBUSY;
847 ret = adxl367_read_sample(indio_dev, chan, val);
848 iio_device_release_direct(indio_dev);
849 return ret;
850 case IIO_CHAN_INFO_SCALE:
851 switch (chan->type) {
852 case IIO_ACCEL: {
853 guard(mutex)(&st->lock);
854 *val = adxl367_range_scale_tbl[st->range][0];
855 *val2 = adxl367_range_scale_tbl[st->range][1];
856 return IIO_VAL_INT_PLUS_NANO;
857 }
858 case IIO_TEMP:
859 *val = 1000;
860 *val2 = ADXL367_TEMP_PER_C;
861 return IIO_VAL_FRACTIONAL;
862 case IIO_VOLTAGE:
863 *val = ADXL367_VOLTAGE_MAX_MV;
864 *val2 = ADXL367_VOLTAGE_MAX_RAW;
865 return IIO_VAL_FRACTIONAL;
866 default:
867 return -EINVAL;
868 }
869 case IIO_CHAN_INFO_OFFSET:
870 switch (chan->type) {
871 case IIO_TEMP:
872 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C;
873 return IIO_VAL_INT;
874 case IIO_VOLTAGE:
875 *val = ADXL367_VOLTAGE_OFFSET;
876 return IIO_VAL_INT;
877 default:
878 return -EINVAL;
879 }
880 case IIO_CHAN_INFO_SAMP_FREQ: {
881 guard(mutex)(&st->lock);
882 *val = adxl367_samp_freq_tbl[st->odr][0];
883 *val2 = adxl367_samp_freq_tbl[st->odr][1];
884 return IIO_VAL_INT_PLUS_MICRO;
885 }
886 default:
887 return -EINVAL;
888 }
889 }
890
adxl367_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)891 static int adxl367_write_raw(struct iio_dev *indio_dev,
892 struct iio_chan_spec const *chan,
893 int val, int val2, long info)
894 {
895 struct adxl367_state *st = iio_priv(indio_dev);
896 int ret;
897
898 switch (info) {
899 case IIO_CHAN_INFO_SAMP_FREQ: {
900 enum adxl367_odr odr;
901
902 ret = adxl367_find_odr(st, val, val2, &odr);
903 if (ret)
904 return ret;
905
906 if (!iio_device_claim_direct(indio_dev))
907 return -EBUSY;
908
909 ret = adxl367_set_odr(indio_dev, odr);
910 iio_device_release_direct(indio_dev);
911 return ret;
912 }
913 case IIO_CHAN_INFO_SCALE: {
914 enum adxl367_range range;
915
916 ret = adxl367_find_range(st, val, val2, &range);
917 if (ret)
918 return ret;
919
920 if (!iio_device_claim_direct(indio_dev))
921 return -EBUSY;
922
923 ret = adxl367_set_range(indio_dev, range);
924 iio_device_release_direct(indio_dev);
925 return ret;
926 }
927 default:
928 return -EINVAL;
929 }
930 }
931
adxl367_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)932 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev,
933 struct iio_chan_spec const *chan,
934 long info)
935 {
936 switch (info) {
937 case IIO_CHAN_INFO_SCALE:
938 if (chan->type != IIO_ACCEL)
939 return -EINVAL;
940
941 return IIO_VAL_INT_PLUS_NANO;
942 default:
943 return IIO_VAL_INT_PLUS_MICRO;
944 }
945 }
946
adxl367_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)947 static int adxl367_read_avail(struct iio_dev *indio_dev,
948 struct iio_chan_spec const *chan,
949 const int **vals, int *type, int *length,
950 long info)
951 {
952 switch (info) {
953 case IIO_CHAN_INFO_SCALE:
954 if (chan->type != IIO_ACCEL)
955 return -EINVAL;
956
957 *vals = (int *)adxl367_range_scale_tbl;
958 *type = IIO_VAL_INT_PLUS_NANO;
959 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2;
960 return IIO_AVAIL_LIST;
961 case IIO_CHAN_INFO_SAMP_FREQ:
962 *vals = (int *)adxl367_samp_freq_tbl;
963 *type = IIO_VAL_INT_PLUS_MICRO;
964 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2;
965 return IIO_AVAIL_LIST;
966 default:
967 return -EINVAL;
968 }
969 }
970
adxl367_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)971 static int adxl367_read_event_value(struct iio_dev *indio_dev,
972 const struct iio_chan_spec *chan,
973 enum iio_event_type type,
974 enum iio_event_direction dir,
975 enum iio_event_info info,
976 int *val, int *val2)
977 {
978 struct adxl367_state *st = iio_priv(indio_dev);
979
980 guard(mutex)(&st->lock);
981 switch (info) {
982 case IIO_EV_INFO_VALUE: {
983 switch (dir) {
984 case IIO_EV_DIR_RISING:
985 *val = st->act_threshold;
986 return IIO_VAL_INT;
987 case IIO_EV_DIR_FALLING:
988 *val = st->inact_threshold;
989 return IIO_VAL_INT;
990 default:
991 return -EINVAL;
992 }
993 }
994 case IIO_EV_INFO_PERIOD:
995 switch (dir) {
996 case IIO_EV_DIR_RISING:
997 *val = st->act_time_ms;
998 *val2 = 1000;
999 return IIO_VAL_FRACTIONAL;
1000 case IIO_EV_DIR_FALLING:
1001 *val = st->inact_time_ms;
1002 *val2 = 1000;
1003 return IIO_VAL_FRACTIONAL;
1004 default:
1005 return -EINVAL;
1006 }
1007 default:
1008 return -EINVAL;
1009 }
1010 }
1011
adxl367_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1012 static int adxl367_write_event_value(struct iio_dev *indio_dev,
1013 const struct iio_chan_spec *chan,
1014 enum iio_event_type type,
1015 enum iio_event_direction dir,
1016 enum iio_event_info info,
1017 int val, int val2)
1018 {
1019 struct adxl367_state *st = iio_priv(indio_dev);
1020
1021 switch (info) {
1022 case IIO_EV_INFO_VALUE:
1023 if (val < 0)
1024 return -EINVAL;
1025
1026 switch (dir) {
1027 case IIO_EV_DIR_RISING:
1028 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);
1029 case IIO_EV_DIR_FALLING:
1030 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);
1031 default:
1032 return -EINVAL;
1033 }
1034 case IIO_EV_INFO_PERIOD:
1035 if (val < 0)
1036 return -EINVAL;
1037
1038 val = val * 1000 + DIV_ROUND_UP(val2, 1000);
1039 switch (dir) {
1040 case IIO_EV_DIR_RISING:
1041 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);
1042 case IIO_EV_DIR_FALLING:
1043 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);
1044 default:
1045 return -EINVAL;
1046 }
1047 default:
1048 return -EINVAL;
1049 }
1050 }
1051
adxl367_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1052 static int adxl367_read_event_config(struct iio_dev *indio_dev,
1053 const struct iio_chan_spec *chan,
1054 enum iio_event_type type,
1055 enum iio_event_direction dir)
1056 {
1057 struct adxl367_state *st = iio_priv(indio_dev);
1058 bool en;
1059 int ret;
1060
1061 switch (dir) {
1062 case IIO_EV_DIR_RISING:
1063 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);
1064 return ret ?: en;
1065 case IIO_EV_DIR_FALLING:
1066 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);
1067 return ret ?: en;
1068 default:
1069 return -EINVAL;
1070 }
1071 }
1072
__adxl367_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1073 static int __adxl367_write_event_config(struct iio_dev *indio_dev,
1074 const struct iio_chan_spec *chan,
1075 enum iio_event_type type,
1076 enum iio_event_direction dir,
1077 bool state)
1078 {
1079 struct adxl367_state *st = iio_priv(indio_dev);
1080 enum adxl367_activity_type act;
1081 int ret;
1082
1083 switch (dir) {
1084 case IIO_EV_DIR_RISING:
1085 act = ADXL367_ACTIVITY;
1086 break;
1087 case IIO_EV_DIR_FALLING:
1088 act = ADXL367_INACTIVITY;
1089 break;
1090 default:
1091 return -EINVAL;
1092 }
1093
1094 guard(mutex)(&st->lock);
1095
1096 ret = adxl367_set_measure_en(st, false);
1097 if (ret)
1098 return ret;
1099
1100 ret = adxl367_set_act_interrupt_en(st, act, state);
1101 if (ret)
1102 return ret;
1103
1104 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED
1105 : ADXL367_ACT_DISABLED);
1106 if (ret)
1107 return ret;
1108
1109 return adxl367_set_measure_en(st, true);
1110 }
1111
adxl367_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1112 static int adxl367_write_event_config(struct iio_dev *indio_dev,
1113 const struct iio_chan_spec *chan,
1114 enum iio_event_type type,
1115 enum iio_event_direction dir,
1116 bool state)
1117 {
1118 int ret;
1119
1120 if (!iio_device_claim_direct(indio_dev))
1121 return -EBUSY;
1122
1123 ret = __adxl367_write_event_config(indio_dev, chan, type, dir, state);
1124 iio_device_release_direct(indio_dev);
1125 return ret;
1126 }
1127
adxl367_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1128 static ssize_t adxl367_get_fifo_enabled(struct device *dev,
1129 struct device_attribute *attr,
1130 char *buf)
1131 {
1132 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1133 enum adxl367_fifo_mode fifo_mode;
1134 int ret;
1135
1136 ret = adxl367_get_fifo_mode(st, &fifo_mode);
1137 if (ret)
1138 return ret;
1139
1140 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED);
1141 }
1142
adxl367_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1143 static ssize_t adxl367_get_fifo_watermark(struct device *dev,
1144 struct device_attribute *attr,
1145 char *buf)
1146 {
1147 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1148 unsigned int fifo_watermark;
1149
1150 guard(mutex)(&st->lock);
1151 fifo_watermark = st->fifo_watermark;
1152
1153 return sysfs_emit(buf, "%d\n", fifo_watermark);
1154 }
1155
1156 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1157 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1158 __stringify(ADXL367_FIFO_MAX_WATERMARK));
1159 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1160 adxl367_get_fifo_watermark, NULL, 0);
1161 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1162 adxl367_get_fifo_enabled, NULL, 0);
1163
1164 static const struct iio_dev_attr *adxl367_fifo_attributes[] = {
1165 &iio_dev_attr_hwfifo_watermark_min,
1166 &iio_dev_attr_hwfifo_watermark_max,
1167 &iio_dev_attr_hwfifo_watermark,
1168 &iio_dev_attr_hwfifo_enabled,
1169 NULL,
1170 };
1171
adxl367_set_watermark(struct iio_dev * indio_dev,unsigned int val)1172 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1173 {
1174 struct adxl367_state *st = iio_priv(indio_dev);
1175 int ret;
1176
1177 if (val > ADXL367_FIFO_MAX_WATERMARK)
1178 return -EINVAL;
1179
1180 guard(mutex)(&st->lock);
1181
1182 ret = adxl367_set_measure_en(st, false);
1183 if (ret)
1184 return ret;
1185
1186 ret = adxl367_set_fifo_watermark(st, val);
1187 if (ret)
1188 return ret;
1189
1190 return adxl367_set_measure_en(st, true);
1191 }
1192
adxl367_find_mask_fifo_format(const unsigned long * scan_mask,enum adxl367_fifo_format * fifo_format)1193 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask,
1194 enum adxl367_fifo_format *fifo_format)
1195 {
1196 size_t size = ARRAY_SIZE(adxl367_fifo_formats);
1197 int i;
1198
1199 for (i = 0; i < size; i++)
1200 if (*scan_mask == adxl367_channel_masks[i])
1201 break;
1202
1203 if (i == size)
1204 return false;
1205
1206 *fifo_format = adxl367_fifo_formats[i];
1207
1208 return true;
1209 }
1210
adxl367_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)1211 static int adxl367_update_scan_mode(struct iio_dev *indio_dev,
1212 const unsigned long *active_scan_mask)
1213 {
1214 struct adxl367_state *st = iio_priv(indio_dev);
1215 enum adxl367_fifo_format fifo_format;
1216 int ret;
1217
1218 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format))
1219 return -EINVAL;
1220
1221 guard(mutex)(&st->lock);
1222
1223 ret = adxl367_set_measure_en(st, false);
1224 if (ret)
1225 return ret;
1226
1227 ret = adxl367_set_fifo_format(st, fifo_format);
1228 if (ret)
1229 return ret;
1230
1231 ret = adxl367_set_measure_en(st, true);
1232 if (ret)
1233 return ret;
1234
1235 st->fifo_set_size = bitmap_weight(active_scan_mask,
1236 iio_get_masklength(indio_dev));
1237
1238 return 0;
1239 }
1240
adxl367_buffer_postenable(struct iio_dev * indio_dev)1241 static int adxl367_buffer_postenable(struct iio_dev *indio_dev)
1242 {
1243 struct adxl367_state *st = iio_priv(indio_dev);
1244 int ret;
1245
1246 guard(mutex)(&st->lock);
1247
1248 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1249 true);
1250 if (ret)
1251 return ret;
1252
1253 ret = adxl367_set_measure_en(st, false);
1254 if (ret)
1255 return ret;
1256
1257 ret = adxl367_set_fifo_watermark_interrupt_en(st, true);
1258 if (ret)
1259 return ret;
1260
1261 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);
1262 if (ret)
1263 return ret;
1264
1265 return adxl367_set_measure_en(st, true);
1266 }
1267
adxl367_buffer_predisable(struct iio_dev * indio_dev)1268 static int adxl367_buffer_predisable(struct iio_dev *indio_dev)
1269 {
1270 struct adxl367_state *st = iio_priv(indio_dev);
1271 int ret;
1272
1273 guard(mutex)(&st->lock);
1274
1275 ret = adxl367_set_measure_en(st, false);
1276 if (ret)
1277 return ret;
1278
1279 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);
1280 if (ret)
1281 return ret;
1282
1283 ret = adxl367_set_fifo_watermark_interrupt_en(st, false);
1284 if (ret)
1285 return ret;
1286
1287 ret = adxl367_set_measure_en(st, true);
1288 if (ret)
1289 return ret;
1290
1291 return adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1292 false);
1293 }
1294
1295 static const struct iio_buffer_setup_ops adxl367_buffer_ops = {
1296 .postenable = adxl367_buffer_postenable,
1297 .predisable = adxl367_buffer_predisable,
1298 };
1299
1300 static const struct iio_info adxl367_info = {
1301 .read_raw = adxl367_read_raw,
1302 .write_raw = adxl367_write_raw,
1303 .write_raw_get_fmt = adxl367_write_raw_get_fmt,
1304 .read_avail = adxl367_read_avail,
1305 .read_event_config = adxl367_read_event_config,
1306 .write_event_config = adxl367_write_event_config,
1307 .read_event_value = adxl367_read_event_value,
1308 .write_event_value = adxl367_write_event_value,
1309 .debugfs_reg_access = adxl367_reg_access,
1310 .hwfifo_set_watermark = adxl367_set_watermark,
1311 .update_scan_mode = adxl367_update_scan_mode,
1312 };
1313
1314 static const struct iio_event_spec adxl367_events[] = {
1315 {
1316 .type = IIO_EV_TYPE_MAG_REFERENCED,
1317 .dir = IIO_EV_DIR_RISING,
1318 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1319 BIT(IIO_EV_INFO_PERIOD) |
1320 BIT(IIO_EV_INFO_VALUE),
1321 },
1322 {
1323 .type = IIO_EV_TYPE_MAG_REFERENCED,
1324 .dir = IIO_EV_DIR_FALLING,
1325 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1326 BIT(IIO_EV_INFO_PERIOD) |
1327 BIT(IIO_EV_INFO_VALUE),
1328 },
1329 };
1330
1331 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \
1332 .type = IIO_ACCEL, \
1333 .address = (reg), \
1334 .modified = 1, \
1335 .channel2 = IIO_MOD_##axis, \
1336 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1337 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1338 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
1339 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1340 .info_mask_shared_by_all_available = \
1341 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1342 .event_spec = adxl367_events, \
1343 .num_event_specs = ARRAY_SIZE(adxl367_events), \
1344 .scan_index = (index), \
1345 .scan_type = { \
1346 .sign = 's', \
1347 .realbits = 14, \
1348 .storagebits = 16, \
1349 .endianness = IIO_BE, \
1350 }, \
1351 }
1352
1353 #define ADXL367_CHANNEL(index, reg, _type) { \
1354 .type = (_type), \
1355 .address = (reg), \
1356 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1357 BIT(IIO_CHAN_INFO_OFFSET) | \
1358 BIT(IIO_CHAN_INFO_SCALE), \
1359 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1360 .scan_index = (index), \
1361 .scan_type = { \
1362 .sign = 's', \
1363 .realbits = 14, \
1364 .storagebits = 16, \
1365 .endianness = IIO_BE, \
1366 }, \
1367 }
1368
1369 static const struct iio_chan_spec adxl367_channels[] = {
1370 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X),
1371 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y),
1372 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z),
1373 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H,
1374 IIO_TEMP),
1375 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H,
1376 IIO_VOLTAGE),
1377 };
1378
adxl367_verify_devid(struct adxl367_state * st)1379 static int adxl367_verify_devid(struct adxl367_state *st)
1380 {
1381 unsigned int val;
1382 int ret;
1383
1384 ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val);
1385 if (ret)
1386 return dev_err_probe(st->dev, ret, "Failed to read dev id\n");
1387
1388 if (val != ADXL367_DEVID_AD)
1389 return dev_err_probe(st->dev, -ENODEV,
1390 "Invalid dev id 0x%02X, expected 0x%02X\n",
1391 val, ADXL367_DEVID_AD);
1392
1393 return 0;
1394 }
1395
adxl367_setup(struct adxl367_state * st)1396 static int adxl367_setup(struct adxl367_state *st)
1397 {
1398 int ret;
1399
1400 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
1401 ADXL367_2G_RANGE_1G);
1402 if (ret)
1403 return ret;
1404
1405 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
1406 ADXL367_2G_RANGE_100MG);
1407 if (ret)
1408 return ret;
1409
1410 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);
1411 if (ret)
1412 return ret;
1413
1414 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);
1415 if (ret)
1416 return ret;
1417
1418 ret = _adxl367_set_act_time_ms(st, 10);
1419 if (ret)
1420 return ret;
1421
1422 ret = _adxl367_set_inact_time_ms(st, 10000);
1423 if (ret)
1424 return ret;
1425
1426 return adxl367_set_measure_en(st, true);
1427 }
1428
adxl367_probe(struct device * dev,const struct adxl367_ops * ops,void * context,struct regmap * regmap,int irq)1429 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
1430 void *context, struct regmap *regmap, int irq)
1431 {
1432 static const char * const regulator_names[] = { "vdd", "vddio" };
1433 struct iio_dev *indio_dev;
1434 struct adxl367_state *st;
1435 int ret;
1436
1437 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1438 if (!indio_dev)
1439 return -ENOMEM;
1440
1441 st = iio_priv(indio_dev);
1442 st->dev = dev;
1443 st->regmap = regmap;
1444 st->context = context;
1445 st->ops = ops;
1446
1447 ret = devm_mutex_init(dev, &st->lock);
1448 if (ret)
1449 return ret;
1450
1451 indio_dev->channels = adxl367_channels;
1452 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels);
1453 indio_dev->available_scan_masks = adxl367_channel_masks;
1454 indio_dev->name = "adxl367";
1455 indio_dev->info = &adxl367_info;
1456 indio_dev->modes = INDIO_DIRECT_MODE;
1457
1458 ret = devm_regulator_bulk_get_enable(st->dev,
1459 ARRAY_SIZE(regulator_names),
1460 regulator_names);
1461 if (ret)
1462 return dev_err_probe(st->dev, ret,
1463 "Failed to get regulators\n");
1464
1465 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);
1466 if (ret)
1467 return ret;
1468
1469 fsleep(15000);
1470
1471 ret = adxl367_verify_devid(st);
1472 if (ret)
1473 return ret;
1474
1475 ret = adxl367_setup(st);
1476 if (ret)
1477 return ret;
1478
1479 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1480 &adxl367_buffer_ops,
1481 adxl367_fifo_attributes);
1482 if (ret)
1483 return ret;
1484
1485 ret = devm_request_threaded_irq(st->dev, irq, NULL,
1486 adxl367_irq_handler, IRQF_ONESHOT,
1487 indio_dev->name, indio_dev);
1488 if (ret)
1489 return ret;
1490
1491 return devm_iio_device_register(dev, indio_dev);
1492 }
1493 EXPORT_SYMBOL_NS_GPL(adxl367_probe, "IIO_ADXL367");
1494
1495 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1496 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver");
1497 MODULE_LICENSE("GPL");
1498