1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap-divider.h"
18 #include "common.h"
19 #include "gdsc.h"
20 #include "reset.h"
21
22 enum {
23 P_BI_TCXO,
24 P_DISP_CC_PLL0_OUT_MAIN,
25 P_DISP_CC_PLL1_OUT_EVEN,
26 P_DISP_CC_PLL1_OUT_MAIN,
27 P_DP_PHY_PLL_LINK_CLK,
28 P_DP_PHY_PLL_VCO_DIV_CLK,
29 P_DPTX1_PHY_PLL_LINK_CLK,
30 P_DPTX1_PHY_PLL_VCO_DIV_CLK,
31 P_DPTX2_PHY_PLL_LINK_CLK,
32 P_DPTX2_PHY_PLL_VCO_DIV_CLK,
33 P_EDP_PHY_PLL_LINK_CLK,
34 P_EDP_PHY_PLL_VCO_DIV_CLK,
35 P_DSI0_PHY_PLL_OUT_BYTECLK,
36 P_DSI0_PHY_PLL_OUT_DSICLK,
37 P_DSI1_PHY_PLL_OUT_BYTECLK,
38 P_DSI1_PHY_PLL_OUT_DSICLK,
39 };
40
41 static const struct pll_vco vco_table[] = {
42 { 249600000, 2000000000, 0 },
43 };
44
45 static const struct pll_vco lucid_5lpe_vco[] = {
46 { 249600000, 1750000000, 0 },
47 };
48
49 static struct alpha_pll_config disp_cc_pll0_config = {
50 .l = 0x47,
51 .alpha = 0xE000,
52 .config_ctl_val = 0x20485699,
53 .config_ctl_hi_val = 0x00002261,
54 .config_ctl_hi1_val = 0x329A699C,
55 .user_ctl_val = 0x00000000,
56 .user_ctl_hi_val = 0x00000805,
57 .user_ctl_hi1_val = 0x00000000,
58 };
59
60 static struct clk_init_data disp_cc_pll0_init = {
61 .name = "disp_cc_pll0",
62 .parent_data = &(const struct clk_parent_data){
63 .fw_name = "bi_tcxo",
64 },
65 .num_parents = 1,
66 .ops = &clk_alpha_pll_lucid_ops,
67 };
68
69 static struct clk_alpha_pll disp_cc_pll0 = {
70 .offset = 0x0,
71 .vco_table = vco_table,
72 .num_vco = ARRAY_SIZE(vco_table),
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
74 .clkr.hw.init = &disp_cc_pll0_init
75 };
76
77 static struct alpha_pll_config disp_cc_pll1_config = {
78 .l = 0x1F,
79 .alpha = 0x4000,
80 .config_ctl_val = 0x20485699,
81 .config_ctl_hi_val = 0x00002261,
82 .config_ctl_hi1_val = 0x329A699C,
83 .user_ctl_val = 0x00000000,
84 .user_ctl_hi_val = 0x00000805,
85 .user_ctl_hi1_val = 0x00000000,
86 };
87
88 static struct clk_init_data disp_cc_pll1_init = {
89 .name = "disp_cc_pll1",
90 .parent_data = &(const struct clk_parent_data){
91 .fw_name = "bi_tcxo",
92 },
93 .num_parents = 1,
94 .ops = &clk_alpha_pll_lucid_ops,
95 };
96
97 static struct clk_alpha_pll disp_cc_pll1 = {
98 .offset = 0x1000,
99 .vco_table = vco_table,
100 .num_vco = ARRAY_SIZE(vco_table),
101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
102 .clkr.hw.init = &disp_cc_pll1_init
103 };
104
105 static const struct parent_map disp_cc_parent_map_0[] = {
106 { P_BI_TCXO, 0 },
107 { P_DP_PHY_PLL_LINK_CLK, 1 },
108 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
109 { P_DPTX1_PHY_PLL_LINK_CLK, 3 },
110 { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
111 { P_DPTX2_PHY_PLL_LINK_CLK, 5 },
112 { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
113 };
114
115 static const struct clk_parent_data disp_cc_parent_data_0[] = {
116 { .fw_name = "bi_tcxo" },
117 { .fw_name = "dp_phy_pll_link_clk" },
118 { .fw_name = "dp_phy_pll_vco_div_clk" },
119 { .fw_name = "dptx1_phy_pll_link_clk" },
120 { .fw_name = "dptx1_phy_pll_vco_div_clk" },
121 { .fw_name = "dptx2_phy_pll_link_clk" },
122 { .fw_name = "dptx2_phy_pll_vco_div_clk" },
123 };
124
125 static const struct parent_map disp_cc_parent_map_1[] = {
126 { P_BI_TCXO, 0 },
127 };
128
129 static const struct clk_parent_data disp_cc_parent_data_1[] = {
130 { .fw_name = "bi_tcxo" },
131 };
132
133 static const struct parent_map disp_cc_parent_map_2[] = {
134 { P_BI_TCXO, 0 },
135 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
136 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
137 };
138
139 static const struct clk_parent_data disp_cc_parent_data_2[] = {
140 { .fw_name = "bi_tcxo" },
141 { .fw_name = "dsi0_phy_pll_out_byteclk" },
142 { .fw_name = "dsi1_phy_pll_out_byteclk" },
143 };
144
145 static const struct parent_map disp_cc_parent_map_3[] = {
146 { P_BI_TCXO, 0 },
147 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
148 };
149
150 static const struct clk_parent_data disp_cc_parent_data_3[] = {
151 { .fw_name = "bi_tcxo" },
152 { .hw = &disp_cc_pll1.clkr.hw },
153 };
154
155 static const struct parent_map disp_cc_parent_map_4[] = {
156 { P_BI_TCXO, 0 },
157 { P_EDP_PHY_PLL_LINK_CLK, 1 },
158 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
159 };
160
161 static const struct clk_parent_data disp_cc_parent_data_4[] = {
162 { .fw_name = "bi_tcxo" },
163 { .fw_name = "edp_phy_pll_link_clk" },
164 { .fw_name = "edp_phy_pll_vco_div_clk" },
165 };
166
167 static const struct parent_map disp_cc_parent_map_5[] = {
168 { P_BI_TCXO, 0 },
169 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
170 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
171 };
172
173 static const struct clk_parent_data disp_cc_parent_data_5[] = {
174 { .fw_name = "bi_tcxo" },
175 { .hw = &disp_cc_pll0.clkr.hw },
176 { .hw = &disp_cc_pll1.clkr.hw },
177 };
178
179 static const struct parent_map disp_cc_parent_map_6[] = {
180 { P_BI_TCXO, 0 },
181 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
182 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
183 };
184
185 static const struct clk_parent_data disp_cc_parent_data_6[] = {
186 { .fw_name = "bi_tcxo" },
187 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
188 { .fw_name = "dsi1_phy_pll_out_dsiclk" },
189 };
190
191 static const struct parent_map disp_cc_parent_map_7[] = {
192 { P_BI_TCXO, 0 },
193 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
194 /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
195 };
196
197 static const struct clk_parent_data disp_cc_parent_data_7[] = {
198 { .fw_name = "bi_tcxo" },
199 { .hw = &disp_cc_pll1.clkr.hw },
200 /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
201 };
202
203 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
204 F(19200000, P_BI_TCXO, 1, 0, 0),
205 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
206 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
207 { }
208 };
209
210 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
211 .cmd_rcgr = 0x22bc,
212 .mnd_width = 0,
213 .hid_width = 5,
214 .parent_map = disp_cc_parent_map_3,
215 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
216 .clkr.hw.init = &(const struct clk_init_data) {
217 .name = "disp_cc_mdss_ahb_clk_src",
218 .parent_data = disp_cc_parent_data_3,
219 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
220 .flags = CLK_SET_RATE_PARENT,
221 .ops = &clk_rcg2_shared_ops,
222 },
223 };
224
225 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
226 F(19200000, P_BI_TCXO, 1, 0, 0),
227 { }
228 };
229
230 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
231 .cmd_rcgr = 0x2110,
232 .mnd_width = 0,
233 .hid_width = 5,
234 .parent_map = disp_cc_parent_map_2,
235 .clkr.hw.init = &(const struct clk_init_data) {
236 .name = "disp_cc_mdss_byte0_clk_src",
237 .parent_data = disp_cc_parent_data_2,
238 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
239 .flags = CLK_SET_RATE_PARENT,
240 .ops = &clk_byte2_ops,
241 },
242 };
243
244 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
245 .cmd_rcgr = 0x212c,
246 .mnd_width = 0,
247 .hid_width = 5,
248 .parent_map = disp_cc_parent_map_2,
249 .clkr.hw.init = &(const struct clk_init_data) {
250 .name = "disp_cc_mdss_byte1_clk_src",
251 .parent_data = disp_cc_parent_data_2,
252 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
253 .flags = CLK_SET_RATE_PARENT,
254 .ops = &clk_byte2_ops,
255 },
256 };
257
258 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
259 .cmd_rcgr = 0x2240,
260 .mnd_width = 0,
261 .hid_width = 5,
262 .parent_map = disp_cc_parent_map_1,
263 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
264 .clkr.hw.init = &(const struct clk_init_data) {
265 .name = "disp_cc_mdss_dp_aux1_clk_src",
266 .parent_data = disp_cc_parent_data_1,
267 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
268 .flags = CLK_SET_RATE_PARENT,
269 .ops = &clk_rcg2_ops,
270 },
271 };
272
273 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
274 .cmd_rcgr = 0x21dc,
275 .mnd_width = 0,
276 .hid_width = 5,
277 .parent_map = disp_cc_parent_map_1,
278 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
279 .clkr.hw.init = &(const struct clk_init_data) {
280 .name = "disp_cc_mdss_dp_aux_clk_src",
281 .parent_data = disp_cc_parent_data_1,
282 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
283 .flags = CLK_SET_RATE_PARENT,
284 .ops = &clk_rcg2_ops,
285 },
286 };
287
288 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
289 .cmd_rcgr = 0x220c,
290 .mnd_width = 0,
291 .hid_width = 5,
292 .parent_map = disp_cc_parent_map_0,
293 .clkr.hw.init = &(const struct clk_init_data) {
294 .name = "disp_cc_mdss_dp_link1_clk_src",
295 .parent_data = disp_cc_parent_data_0,
296 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
297 .ops = &clk_byte2_ops,
298 },
299 };
300
301 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
302 .cmd_rcgr = 0x2178,
303 .mnd_width = 0,
304 .hid_width = 5,
305 .parent_map = disp_cc_parent_map_0,
306 .clkr.hw.init = &(const struct clk_init_data) {
307 .name = "disp_cc_mdss_dp_link_clk_src",
308 .parent_data = disp_cc_parent_data_0,
309 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
310 .ops = &clk_byte2_ops,
311 },
312 };
313
314 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
315 .cmd_rcgr = 0x21c4,
316 .mnd_width = 16,
317 .hid_width = 5,
318 .parent_map = disp_cc_parent_map_0,
319 .clkr.hw.init = &(const struct clk_init_data) {
320 .name = "disp_cc_mdss_dp_pixel1_clk_src",
321 .parent_data = disp_cc_parent_data_0,
322 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
323 .ops = &clk_dp_ops,
324 },
325 };
326
327 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
328 .cmd_rcgr = 0x21f4,
329 .mnd_width = 16,
330 .hid_width = 5,
331 .parent_map = disp_cc_parent_map_0,
332 .clkr.hw.init = &(const struct clk_init_data) {
333 .name = "disp_cc_mdss_dp_pixel2_clk_src",
334 .parent_data = disp_cc_parent_data_0,
335 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
336 .ops = &clk_dp_ops,
337 },
338 };
339
340 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
341 .cmd_rcgr = 0x21ac,
342 .mnd_width = 16,
343 .hid_width = 5,
344 .parent_map = disp_cc_parent_map_0,
345 .clkr.hw.init = &(const struct clk_init_data) {
346 .name = "disp_cc_mdss_dp_pixel_clk_src",
347 .parent_data = disp_cc_parent_data_0,
348 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
349 .ops = &clk_dp_ops,
350 },
351 };
352
353 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
354 .cmd_rcgr = 0x228c,
355 .mnd_width = 0,
356 .hid_width = 5,
357 .parent_map = disp_cc_parent_map_1,
358 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
359 .clkr.hw.init = &(const struct clk_init_data) {
360 .name = "disp_cc_mdss_edp_aux_clk_src",
361 .parent_data = disp_cc_parent_data_1,
362 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
363 .flags = CLK_SET_RATE_PARENT,
364 .ops = &clk_rcg2_ops,
365 },
366 };
367
368 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
369 .cmd_rcgr = 0x22a4,
370 .mnd_width = 0,
371 .hid_width = 5,
372 .parent_map = disp_cc_parent_map_7,
373 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
374 .clkr.hw.init = &(const struct clk_init_data) {
375 .name = "disp_cc_mdss_edp_gtc_clk_src",
376 .parent_data = disp_cc_parent_data_7,
377 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
378 .flags = CLK_SET_RATE_PARENT,
379 .ops = &clk_rcg2_ops,
380 },
381 };
382
383 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
384 .cmd_rcgr = 0x2270,
385 .mnd_width = 0,
386 .hid_width = 5,
387 .parent_map = disp_cc_parent_map_4,
388 .clkr.hw.init = &(const struct clk_init_data) {
389 .name = "disp_cc_mdss_edp_link_clk_src",
390 .parent_data = disp_cc_parent_data_4,
391 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
392 .flags = CLK_SET_RATE_PARENT,
393 .ops = &clk_byte2_ops,
394 },
395 };
396
397 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
398 .cmd_rcgr = 0x2258,
399 .mnd_width = 16,
400 .hid_width = 5,
401 .parent_map = disp_cc_parent_map_4,
402 .clkr.hw.init = &(const struct clk_init_data) {
403 .name = "disp_cc_mdss_edp_pixel_clk_src",
404 .parent_data = disp_cc_parent_data_4,
405 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
406 .ops = &clk_dp_ops,
407 },
408 };
409
410 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
411 .halt_reg = 0x2078,
412 .halt_check = BRANCH_HALT,
413 .clkr = {
414 .enable_reg = 0x2078,
415 .enable_mask = BIT(0),
416 .hw.init = &(const struct clk_init_data) {
417 .name = "disp_cc_mdss_edp_aux_clk",
418 .parent_hws = (const struct clk_hw*[]){
419 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
420 },
421 .num_parents = 1,
422 .flags = CLK_SET_RATE_PARENT,
423 .ops = &clk_branch2_ops,
424 },
425 },
426 };
427
428 static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
429 .halt_reg = 0x207c,
430 .halt_check = BRANCH_HALT,
431 .clkr = {
432 .enable_reg = 0x207c,
433 .enable_mask = BIT(0),
434 .hw.init = &(const struct clk_init_data) {
435 .name = "disp_cc_mdss_edp_gtc_clk",
436 .parent_hws = (const struct clk_hw*[]){
437 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
438 },
439 .num_parents = 1,
440 .flags = CLK_SET_RATE_PARENT,
441 .ops = &clk_branch2_ops,
442 },
443 },
444 };
445
446 static struct clk_branch disp_cc_mdss_edp_link_clk = {
447 .halt_reg = 0x2070,
448 .halt_check = BRANCH_HALT,
449 .clkr = {
450 .enable_reg = 0x2070,
451 .enable_mask = BIT(0),
452 .hw.init = &(const struct clk_init_data) {
453 .name = "disp_cc_mdss_edp_link_clk",
454 .parent_hws = (const struct clk_hw*[]){
455 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
456 },
457 .num_parents = 1,
458 .flags = CLK_SET_RATE_PARENT,
459 .ops = &clk_branch2_ops,
460 },
461 },
462 };
463
464 static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
465 .reg = 0x2288,
466 .shift = 0,
467 .width = 2,
468 .clkr.hw.init = &(const struct clk_init_data) {
469 .name = "disp_cc_mdss_edp_link_div_clk_src",
470 .parent_hws = (const struct clk_hw*[]){
471 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
472 },
473 .num_parents = 1,
474 .ops = &clk_regmap_div_ro_ops,
475 },
476 };
477
478 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
479 .halt_reg = 0x2074,
480 .halt_check = BRANCH_HALT,
481 .clkr = {
482 .enable_reg = 0x2074,
483 .enable_mask = BIT(0),
484 .hw.init = &(const struct clk_init_data) {
485 .name = "disp_cc_mdss_edp_link_intf_clk",
486 .parent_hws = (const struct clk_hw*[]){
487 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
488 },
489 .num_parents = 1,
490 .flags = CLK_GET_RATE_NOCACHE,
491 .ops = &clk_branch2_ops,
492 },
493 },
494 };
495
496 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
497 .halt_reg = 0x206c,
498 .halt_check = BRANCH_HALT,
499 .clkr = {
500 .enable_reg = 0x206c,
501 .enable_mask = BIT(0),
502 .hw.init = &(const struct clk_init_data) {
503 .name = "disp_cc_mdss_edp_pixel_clk",
504 .parent_hws = (const struct clk_hw*[]){
505 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
506 },
507 .num_parents = 1,
508 .flags = CLK_SET_RATE_PARENT,
509 .ops = &clk_branch2_ops,
510 },
511 },
512 };
513
514 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
515 .cmd_rcgr = 0x2148,
516 .mnd_width = 0,
517 .hid_width = 5,
518 .parent_map = disp_cc_parent_map_2,
519 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
520 .clkr.hw.init = &(const struct clk_init_data) {
521 .name = "disp_cc_mdss_esc0_clk_src",
522 .parent_data = disp_cc_parent_data_2,
523 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_rcg2_ops,
526 },
527 };
528
529 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
530 .cmd_rcgr = 0x2160,
531 .mnd_width = 0,
532 .hid_width = 5,
533 .parent_map = disp_cc_parent_map_2,
534 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
535 .clkr.hw.init = &(const struct clk_init_data) {
536 .name = "disp_cc_mdss_esc1_clk_src",
537 .parent_data = disp_cc_parent_data_2,
538 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
539 .flags = CLK_SET_RATE_PARENT,
540 .ops = &clk_rcg2_ops,
541 },
542 };
543
544 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
545 F(19200000, P_BI_TCXO, 1, 0, 0),
546 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
547 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
548 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
549 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
550 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
551 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
552 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
553 { }
554 };
555
556 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
557 .cmd_rcgr = 0x20c8,
558 .mnd_width = 0,
559 .hid_width = 5,
560 .parent_map = disp_cc_parent_map_5,
561 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
562 .clkr.hw.init = &(const struct clk_init_data) {
563 .name = "disp_cc_mdss_mdp_clk_src",
564 .parent_data = disp_cc_parent_data_5,
565 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
566 .flags = CLK_SET_RATE_PARENT,
567 .ops = &clk_rcg2_shared_ops,
568 },
569 };
570
571 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
572 .cmd_rcgr = 0x2098,
573 .mnd_width = 8,
574 .hid_width = 5,
575 .parent_map = disp_cc_parent_map_6,
576 .clkr.hw.init = &(const struct clk_init_data) {
577 .name = "disp_cc_mdss_pclk0_clk_src",
578 .parent_data = disp_cc_parent_data_6,
579 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
580 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
581 .ops = &clk_pixel_ops,
582 },
583 };
584
585 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
586 .cmd_rcgr = 0x20b0,
587 .mnd_width = 8,
588 .hid_width = 5,
589 .parent_map = disp_cc_parent_map_6,
590 .clkr.hw.init = &(const struct clk_init_data) {
591 .name = "disp_cc_mdss_pclk1_clk_src",
592 .parent_data = disp_cc_parent_data_6,
593 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
594 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
595 .ops = &clk_pixel_ops,
596 },
597 };
598
599 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
600 F(19200000, P_BI_TCXO, 1, 0, 0),
601 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
602 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
603 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
604 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
605 { }
606 };
607
608 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
609 .cmd_rcgr = 0x20e0,
610 .mnd_width = 0,
611 .hid_width = 5,
612 .parent_map = disp_cc_parent_map_5,
613 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
614 .clkr.hw.init = &(const struct clk_init_data) {
615 .name = "disp_cc_mdss_rot_clk_src",
616 .parent_data = disp_cc_parent_data_5,
617 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
618 .flags = CLK_SET_RATE_PARENT,
619 .ops = &clk_rcg2_shared_ops,
620 },
621 };
622
623 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
624 .cmd_rcgr = 0x20f8,
625 .mnd_width = 0,
626 .hid_width = 5,
627 .parent_map = disp_cc_parent_map_1,
628 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
629 .clkr.hw.init = &(const struct clk_init_data) {
630 .name = "disp_cc_mdss_vsync_clk_src",
631 .parent_data = disp_cc_parent_data_1,
632 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
633 .flags = CLK_SET_RATE_PARENT,
634 .ops = &clk_rcg2_shared_ops,
635 },
636 };
637
638 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
639 .reg = 0x2128,
640 .shift = 0,
641 .width = 2,
642 .clkr.hw.init = &(const struct clk_init_data) {
643 .name = "disp_cc_mdss_byte0_div_clk_src",
644 .parent_hws = (const struct clk_hw*[]){
645 &disp_cc_mdss_byte0_clk_src.clkr.hw,
646 },
647 .num_parents = 1,
648 .ops = &clk_regmap_div_ops,
649 },
650 };
651
652
653 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
654 .reg = 0x2144,
655 .shift = 0,
656 .width = 2,
657 .clkr.hw.init = &(const struct clk_init_data) {
658 .name = "disp_cc_mdss_byte1_div_clk_src",
659 .parent_hws = (const struct clk_hw*[]){
660 &disp_cc_mdss_byte1_clk_src.clkr.hw,
661 },
662 .num_parents = 1,
663 .ops = &clk_regmap_div_ops,
664 },
665 };
666
667 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
668 .reg = 0x2224,
669 .shift = 0,
670 .width = 2,
671 .clkr.hw.init = &(const struct clk_init_data) {
672 .name = "disp_cc_mdss_dp_link1_div_clk_src",
673 .parent_hws = (const struct clk_hw*[]){
674 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
675 },
676 .num_parents = 1,
677 .ops = &clk_regmap_div_ro_ops,
678 },
679 };
680
681 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
682 .reg = 0x2190,
683 .shift = 0,
684 .width = 2,
685 .clkr.hw.init = &(const struct clk_init_data) {
686 .name = "disp_cc_mdss_dp_link_div_clk_src",
687 .parent_hws = (const struct clk_hw*[]){
688 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
689 },
690 .num_parents = 1,
691 .ops = &clk_regmap_div_ro_ops,
692 },
693 };
694
695 static struct clk_branch disp_cc_mdss_ahb_clk = {
696 .halt_reg = 0x2080,
697 .halt_check = BRANCH_HALT,
698 .clkr = {
699 .enable_reg = 0x2080,
700 .enable_mask = BIT(0),
701 .hw.init = &(const struct clk_init_data) {
702 .name = "disp_cc_mdss_ahb_clk",
703 .parent_hws = (const struct clk_hw*[]){
704 &disp_cc_mdss_ahb_clk_src.clkr.hw,
705 },
706 .num_parents = 1,
707 .flags = CLK_SET_RATE_PARENT,
708 .ops = &clk_branch2_ops,
709 },
710 },
711 };
712
713 static struct clk_branch disp_cc_mdss_byte0_clk = {
714 .halt_reg = 0x2028,
715 .halt_check = BRANCH_HALT,
716 .clkr = {
717 .enable_reg = 0x2028,
718 .enable_mask = BIT(0),
719 .hw.init = &(const struct clk_init_data) {
720 .name = "disp_cc_mdss_byte0_clk",
721 .parent_hws = (const struct clk_hw*[]){
722 &disp_cc_mdss_byte0_clk_src.clkr.hw,
723 },
724 .num_parents = 1,
725 .flags = CLK_SET_RATE_PARENT,
726 .ops = &clk_branch2_ops,
727 },
728 },
729 };
730
731 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
732 .halt_reg = 0x202c,
733 .halt_check = BRANCH_HALT,
734 .clkr = {
735 .enable_reg = 0x202c,
736 .enable_mask = BIT(0),
737 .hw.init = &(const struct clk_init_data) {
738 .name = "disp_cc_mdss_byte0_intf_clk",
739 .parent_hws = (const struct clk_hw*[]){
740 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
741 },
742 .num_parents = 1,
743 .flags = CLK_SET_RATE_PARENT,
744 .ops = &clk_branch2_ops,
745 },
746 },
747 };
748
749 static struct clk_branch disp_cc_mdss_byte1_clk = {
750 .halt_reg = 0x2030,
751 .halt_check = BRANCH_HALT,
752 .clkr = {
753 .enable_reg = 0x2030,
754 .enable_mask = BIT(0),
755 .hw.init = &(const struct clk_init_data) {
756 .name = "disp_cc_mdss_byte1_clk",
757 .parent_hws = (const struct clk_hw*[]){
758 &disp_cc_mdss_byte1_clk_src.clkr.hw,
759 },
760 .num_parents = 1,
761 .flags = CLK_SET_RATE_PARENT,
762 .ops = &clk_branch2_ops,
763 },
764 },
765 };
766
767 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
768 .halt_reg = 0x2034,
769 .halt_check = BRANCH_HALT,
770 .clkr = {
771 .enable_reg = 0x2034,
772 .enable_mask = BIT(0),
773 .hw.init = &(const struct clk_init_data) {
774 .name = "disp_cc_mdss_byte1_intf_clk",
775 .parent_hws = (const struct clk_hw*[]){
776 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
777 },
778 .num_parents = 1,
779 .flags = CLK_SET_RATE_PARENT,
780 .ops = &clk_branch2_ops,
781 },
782 },
783 };
784
785 static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
786 .halt_reg = 0x2068,
787 .halt_check = BRANCH_HALT,
788 .clkr = {
789 .enable_reg = 0x2068,
790 .enable_mask = BIT(0),
791 .hw.init = &(const struct clk_init_data) {
792 .name = "disp_cc_mdss_dp_aux1_clk",
793 .parent_hws = (const struct clk_hw*[]){
794 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
795 },
796 .num_parents = 1,
797 .flags = CLK_SET_RATE_PARENT,
798 .ops = &clk_branch2_ops,
799 },
800 },
801 };
802
803 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
804 .halt_reg = 0x2054,
805 .halt_check = BRANCH_HALT,
806 .clkr = {
807 .enable_reg = 0x2054,
808 .enable_mask = BIT(0),
809 .hw.init = &(const struct clk_init_data) {
810 .name = "disp_cc_mdss_dp_aux_clk",
811 .parent_hws = (const struct clk_hw*[]){
812 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
813 },
814 .num_parents = 1,
815 .flags = CLK_SET_RATE_PARENT,
816 .ops = &clk_branch2_ops,
817 },
818 },
819 };
820
821 static struct clk_branch disp_cc_mdss_dp_link1_clk = {
822 .halt_reg = 0x205c,
823 .halt_check = BRANCH_HALT,
824 .clkr = {
825 .enable_reg = 0x205c,
826 .enable_mask = BIT(0),
827 .hw.init = &(const struct clk_init_data) {
828 .name = "disp_cc_mdss_dp_link1_clk",
829 .parent_hws = (const struct clk_hw*[]){
830 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
831 },
832 .num_parents = 1,
833 .flags = CLK_SET_RATE_PARENT,
834 .ops = &clk_branch2_ops,
835 },
836 },
837 };
838
839 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
840 .halt_reg = 0x2060,
841 .halt_check = BRANCH_HALT,
842 .clkr = {
843 .enable_reg = 0x2060,
844 .enable_mask = BIT(0),
845 .hw.init = &(const struct clk_init_data) {
846 .name = "disp_cc_mdss_dp_link1_intf_clk",
847 .parent_hws = (const struct clk_hw*[]){
848 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
849 },
850 .num_parents = 1,
851 .flags = CLK_SET_RATE_PARENT,
852 .ops = &clk_branch2_ops,
853 },
854 },
855 };
856
857 static struct clk_branch disp_cc_mdss_dp_link_clk = {
858 .halt_reg = 0x2040,
859 .halt_check = BRANCH_HALT,
860 .clkr = {
861 .enable_reg = 0x2040,
862 .enable_mask = BIT(0),
863 .hw.init = &(const struct clk_init_data) {
864 .name = "disp_cc_mdss_dp_link_clk",
865 .parent_hws = (const struct clk_hw*[]){
866 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
867 },
868 .num_parents = 1,
869 .flags = CLK_SET_RATE_PARENT,
870 .ops = &clk_branch2_ops,
871 },
872 },
873 };
874
875 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
876 .halt_reg = 0x2044,
877 .halt_check = BRANCH_HALT,
878 .clkr = {
879 .enable_reg = 0x2044,
880 .enable_mask = BIT(0),
881 .hw.init = &(const struct clk_init_data) {
882 .name = "disp_cc_mdss_dp_link_intf_clk",
883 .parent_hws = (const struct clk_hw*[]){
884 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
885 },
886 .num_parents = 1,
887 .flags = CLK_SET_RATE_PARENT,
888 .ops = &clk_branch2_ops,
889 },
890 },
891 };
892
893 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
894 .halt_reg = 0x2050,
895 .halt_check = BRANCH_HALT,
896 .clkr = {
897 .enable_reg = 0x2050,
898 .enable_mask = BIT(0),
899 .hw.init = &(const struct clk_init_data) {
900 .name = "disp_cc_mdss_dp_pixel1_clk",
901 .parent_hws = (const struct clk_hw*[]){
902 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
903 },
904 .num_parents = 1,
905 .flags = CLK_SET_RATE_PARENT,
906 .ops = &clk_branch2_ops,
907 },
908 },
909 };
910
911 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
912 .halt_reg = 0x2058,
913 .halt_check = BRANCH_HALT,
914 .clkr = {
915 .enable_reg = 0x2058,
916 .enable_mask = BIT(0),
917 .hw.init = &(const struct clk_init_data) {
918 .name = "disp_cc_mdss_dp_pixel2_clk",
919 .parent_hws = (const struct clk_hw*[]){
920 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
921 },
922 .num_parents = 1,
923 .flags = CLK_SET_RATE_PARENT,
924 .ops = &clk_branch2_ops,
925 },
926 },
927 };
928
929 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
930 .halt_reg = 0x204c,
931 .halt_check = BRANCH_HALT,
932 .clkr = {
933 .enable_reg = 0x204c,
934 .enable_mask = BIT(0),
935 .hw.init = &(const struct clk_init_data) {
936 .name = "disp_cc_mdss_dp_pixel_clk",
937 .parent_hws = (const struct clk_hw*[]){
938 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
939 },
940 .num_parents = 1,
941 .flags = CLK_SET_RATE_PARENT,
942 .ops = &clk_branch2_ops,
943 },
944 },
945 };
946
947 static struct clk_branch disp_cc_mdss_esc0_clk = {
948 .halt_reg = 0x2038,
949 .halt_check = BRANCH_HALT,
950 .clkr = {
951 .enable_reg = 0x2038,
952 .enable_mask = BIT(0),
953 .hw.init = &(const struct clk_init_data) {
954 .name = "disp_cc_mdss_esc0_clk",
955 .parent_hws = (const struct clk_hw*[]){
956 &disp_cc_mdss_esc0_clk_src.clkr.hw,
957 },
958 .num_parents = 1,
959 .flags = CLK_SET_RATE_PARENT,
960 .ops = &clk_branch2_ops,
961 },
962 },
963 };
964
965 static struct clk_branch disp_cc_mdss_esc1_clk = {
966 .halt_reg = 0x203c,
967 .halt_check = BRANCH_HALT,
968 .clkr = {
969 .enable_reg = 0x203c,
970 .enable_mask = BIT(0),
971 .hw.init = &(const struct clk_init_data) {
972 .name = "disp_cc_mdss_esc1_clk",
973 .parent_hws = (const struct clk_hw*[]){
974 &disp_cc_mdss_esc1_clk_src.clkr.hw,
975 },
976 .num_parents = 1,
977 .flags = CLK_SET_RATE_PARENT,
978 .ops = &clk_branch2_ops,
979 },
980 },
981 };
982
983 static struct clk_branch disp_cc_mdss_mdp_clk = {
984 .halt_reg = 0x200c,
985 .halt_check = BRANCH_HALT,
986 .clkr = {
987 .enable_reg = 0x200c,
988 .enable_mask = BIT(0),
989 .hw.init = &(const struct clk_init_data) {
990 .name = "disp_cc_mdss_mdp_clk",
991 .parent_hws = (const struct clk_hw*[]){
992 &disp_cc_mdss_mdp_clk_src.clkr.hw,
993 },
994 .num_parents = 1,
995 .flags = CLK_SET_RATE_PARENT,
996 .ops = &clk_branch2_ops,
997 },
998 },
999 };
1000
1001 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1002 .halt_reg = 0x201c,
1003 .halt_check = BRANCH_VOTED,
1004 .clkr = {
1005 .enable_reg = 0x201c,
1006 .enable_mask = BIT(0),
1007 .hw.init = &(const struct clk_init_data) {
1008 .name = "disp_cc_mdss_mdp_lut_clk",
1009 .parent_hws = (const struct clk_hw*[]){
1010 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1011 },
1012 .num_parents = 1,
1013 .flags = CLK_SET_RATE_PARENT,
1014 .ops = &clk_branch2_ops,
1015 },
1016 },
1017 };
1018
1019 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1020 .halt_reg = 0x4004,
1021 .halt_check = BRANCH_VOTED,
1022 .clkr = {
1023 .enable_reg = 0x4004,
1024 .enable_mask = BIT(0),
1025 .hw.init = &(const struct clk_init_data) {
1026 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1027 .parent_hws = (const struct clk_hw*[]){
1028 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1029 },
1030 .num_parents = 1,
1031 .flags = CLK_SET_RATE_PARENT,
1032 .ops = &clk_branch2_ops,
1033 },
1034 },
1035 };
1036
1037 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1038 .halt_reg = 0x2004,
1039 .halt_check = BRANCH_HALT,
1040 .clkr = {
1041 .enable_reg = 0x2004,
1042 .enable_mask = BIT(0),
1043 .hw.init = &(const struct clk_init_data) {
1044 .name = "disp_cc_mdss_pclk0_clk",
1045 .parent_hws = (const struct clk_hw*[]){
1046 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1047 },
1048 .num_parents = 1,
1049 .flags = CLK_SET_RATE_PARENT,
1050 .ops = &clk_branch2_ops,
1051 },
1052 },
1053 };
1054
1055 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1056 .halt_reg = 0x2008,
1057 .halt_check = BRANCH_HALT,
1058 .clkr = {
1059 .enable_reg = 0x2008,
1060 .enable_mask = BIT(0),
1061 .hw.init = &(const struct clk_init_data) {
1062 .name = "disp_cc_mdss_pclk1_clk",
1063 .parent_hws = (const struct clk_hw*[]){
1064 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1065 },
1066 .num_parents = 1,
1067 .flags = CLK_SET_RATE_PARENT,
1068 .ops = &clk_branch2_ops,
1069 },
1070 },
1071 };
1072
1073 static struct clk_branch disp_cc_mdss_rot_clk = {
1074 .halt_reg = 0x2014,
1075 .halt_check = BRANCH_HALT,
1076 .clkr = {
1077 .enable_reg = 0x2014,
1078 .enable_mask = BIT(0),
1079 .hw.init = &(const struct clk_init_data) {
1080 .name = "disp_cc_mdss_rot_clk",
1081 .parent_hws = (const struct clk_hw*[]){
1082 &disp_cc_mdss_rot_clk_src.clkr.hw,
1083 },
1084 .num_parents = 1,
1085 .flags = CLK_SET_RATE_PARENT,
1086 .ops = &clk_branch2_ops,
1087 },
1088 },
1089 };
1090
1091 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1092 .halt_reg = 0x400c,
1093 .halt_check = BRANCH_HALT,
1094 .clkr = {
1095 .enable_reg = 0x400c,
1096 .enable_mask = BIT(0),
1097 .hw.init = &(const struct clk_init_data) {
1098 .name = "disp_cc_mdss_rscc_ahb_clk",
1099 .parent_hws = (const struct clk_hw*[]){
1100 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1101 },
1102 .num_parents = 1,
1103 .flags = CLK_SET_RATE_PARENT,
1104 .ops = &clk_branch2_ops,
1105 },
1106 },
1107 };
1108
1109 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1110 .halt_reg = 0x4008,
1111 .halt_check = BRANCH_HALT,
1112 .clkr = {
1113 .enable_reg = 0x4008,
1114 .enable_mask = BIT(0),
1115 .hw.init = &(const struct clk_init_data) {
1116 .name = "disp_cc_mdss_rscc_vsync_clk",
1117 .parent_hws = (const struct clk_hw*[]){
1118 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1119 },
1120 .num_parents = 1,
1121 .flags = CLK_SET_RATE_PARENT,
1122 .ops = &clk_branch2_ops,
1123 },
1124 },
1125 };
1126
1127 static struct clk_branch disp_cc_mdss_vsync_clk = {
1128 .halt_reg = 0x2024,
1129 .halt_check = BRANCH_HALT,
1130 .clkr = {
1131 .enable_reg = 0x2024,
1132 .enable_mask = BIT(0),
1133 .hw.init = &(const struct clk_init_data) {
1134 .name = "disp_cc_mdss_vsync_clk",
1135 .parent_hws = (const struct clk_hw*[]){
1136 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1137 },
1138 .num_parents = 1,
1139 .flags = CLK_SET_RATE_PARENT,
1140 .ops = &clk_branch2_ops,
1141 },
1142 },
1143 };
1144
1145 static struct gdsc mdss_gdsc = {
1146 .gdscr = 0x3000,
1147 .en_rest_wait_val = 0x2,
1148 .en_few_wait_val = 0x2,
1149 .clk_dis_wait_val = 0xf,
1150 .pd = {
1151 .name = "mdss_gdsc",
1152 },
1153 .pwrsts = PWRSTS_OFF_ON,
1154 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1155 };
1156
1157 static struct clk_regmap *disp_cc_sm8250_clocks[] = {
1158 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1159 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1160 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1161 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1162 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1163 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1164 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1165 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1166 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1167 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1168 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
1169 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
1170 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
1171 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
1172 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
1173 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
1174 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
1175 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
1176 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
1177 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
1178 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
1179 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
1180 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
1181 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
1182 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
1183 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
1184 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
1185 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
1186 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
1187 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
1188 [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
1189 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
1190 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
1191 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
1192 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr,
1193 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
1194 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
1195 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
1196 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1197 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1198 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1199 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1200 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1201 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1202 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1203 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1204 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1205 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1206 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1207 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1208 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1209 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1210 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1211 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1212 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1213 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1214 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1215 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1216 };
1217
1218 static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1219 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1220 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1221 };
1222
1223 static struct gdsc *disp_cc_sm8250_gdscs[] = {
1224 [MDSS_GDSC] = &mdss_gdsc,
1225 };
1226
1227 static const struct regmap_config disp_cc_sm8250_regmap_config = {
1228 .reg_bits = 32,
1229 .reg_stride = 4,
1230 .val_bits = 32,
1231 .max_register = 0x10000,
1232 .fast_io = true,
1233 };
1234
1235 static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1236 .config = &disp_cc_sm8250_regmap_config,
1237 .clks = disp_cc_sm8250_clocks,
1238 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1239 .resets = disp_cc_sm8250_resets,
1240 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1241 .gdscs = disp_cc_sm8250_gdscs,
1242 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1243 };
1244
1245 static const struct of_device_id disp_cc_sm8250_match_table[] = {
1246 { .compatible = "qcom,sc8180x-dispcc" },
1247 { .compatible = "qcom,sm8150-dispcc" },
1248 { .compatible = "qcom,sm8250-dispcc" },
1249 { .compatible = "qcom,sm8350-dispcc" },
1250 { }
1251 };
1252 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1253
disp_cc_sm8250_probe(struct platform_device * pdev)1254 static int disp_cc_sm8250_probe(struct platform_device *pdev)
1255 {
1256 struct regmap *regmap;
1257 int ret;
1258
1259 ret = devm_pm_runtime_enable(&pdev->dev);
1260 if (ret)
1261 return ret;
1262
1263 ret = pm_runtime_resume_and_get(&pdev->dev);
1264 if (ret)
1265 return ret;
1266
1267 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
1268 if (IS_ERR(regmap)) {
1269 pm_runtime_put(&pdev->dev);
1270 return PTR_ERR(regmap);
1271 }
1272
1273 /* Apply differences for SM8150 and SM8350 */
1274 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1275 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1276 of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1277 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1278 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1279 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1280 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1281 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1282 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1283 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1284 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1285
1286 disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1287 &disp_cc_mdss_dp_link_clk_src.clkr.hw;
1288 disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
1289 &disp_cc_mdss_dp_link1_clk_src.clkr.hw;
1290 disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1291 &disp_cc_mdss_edp_link_clk_src.clkr.hw;
1292
1293 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
1294 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
1295 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
1296 } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1297 static struct clk_rcg2 * const rcgs[] = {
1298 &disp_cc_mdss_byte0_clk_src,
1299 &disp_cc_mdss_byte1_clk_src,
1300 &disp_cc_mdss_dp_aux1_clk_src,
1301 &disp_cc_mdss_dp_aux_clk_src,
1302 &disp_cc_mdss_dp_link1_clk_src,
1303 &disp_cc_mdss_dp_link_clk_src,
1304 &disp_cc_mdss_dp_pixel1_clk_src,
1305 &disp_cc_mdss_dp_pixel2_clk_src,
1306 &disp_cc_mdss_dp_pixel_clk_src,
1307 &disp_cc_mdss_edp_aux_clk_src,
1308 &disp_cc_mdss_edp_link_clk_src,
1309 &disp_cc_mdss_edp_pixel_clk_src,
1310 &disp_cc_mdss_esc0_clk_src,
1311 &disp_cc_mdss_esc1_clk_src,
1312 &disp_cc_mdss_mdp_clk_src,
1313 &disp_cc_mdss_pclk0_clk_src,
1314 &disp_cc_mdss_pclk1_clk_src,
1315 &disp_cc_mdss_rot_clk_src,
1316 &disp_cc_mdss_vsync_clk_src,
1317 };
1318 static struct clk_regmap_div * const divs[] = {
1319 &disp_cc_mdss_byte0_div_clk_src,
1320 &disp_cc_mdss_byte1_div_clk_src,
1321 &disp_cc_mdss_dp_link1_div_clk_src,
1322 &disp_cc_mdss_dp_link_div_clk_src,
1323 &disp_cc_mdss_edp_link_div_clk_src,
1324 };
1325 unsigned int i;
1326 static bool offset_applied;
1327
1328 /*
1329 * note: trion == lucid, except for the prepare() op
1330 * only apply the offsets once (in case of deferred probe)
1331 */
1332 if (!offset_applied) {
1333 for (i = 0; i < ARRAY_SIZE(rcgs); i++)
1334 rcgs[i]->cmd_rcgr -= 4;
1335
1336 for (i = 0; i < ARRAY_SIZE(divs); i++) {
1337 divs[i]->reg -= 4;
1338 divs[i]->width = 4;
1339 }
1340
1341 disp_cc_mdss_ahb_clk.halt_reg -= 4;
1342 disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
1343
1344 offset_applied = true;
1345 }
1346
1347 disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
1348
1349 disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
1350 disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
1351 disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1352 disp_cc_pll0.vco_table = lucid_5lpe_vco;
1353 disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
1354 disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
1355 disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1356 disp_cc_pll1.vco_table = lucid_5lpe_vco;
1357
1358 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
1359 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
1360 }
1361
1362 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1363 clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1364 clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1365 } else {
1366 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1367 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1368 }
1369
1370 /* Enable clock gating for MDP clocks */
1371 regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
1372
1373 /* Keep some clocks always-on */
1374 qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
1375
1376 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap);
1377
1378 pm_runtime_put(&pdev->dev);
1379
1380 return ret;
1381 }
1382
1383 static struct platform_driver disp_cc_sm8250_driver = {
1384 .probe = disp_cc_sm8250_probe,
1385 .driver = {
1386 .name = "disp_cc-sm8250",
1387 .of_match_table = disp_cc_sm8250_match_table,
1388 },
1389 };
1390
1391 module_platform_driver(disp_cc_sm8250_driver);
1392
1393 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1394 MODULE_LICENSE("GPL v2");
1395