1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 21 /* REGISTER OFFSET */ 22 #define SSICR 0x000 23 #define SSISR 0x004 24 #define SSIFCR 0x010 25 #define SSIFSR 0x014 26 #define SSIFTDR 0x018 27 #define SSIFRDR 0x01c 28 #define SSIOFR 0x020 29 #define SSISCR 0x024 30 31 /* SSI REGISTER BITS */ 32 #define SSICR_DWL(x) (((x) & 0x7) << 19) 33 #define SSICR_SWL(x) (((x) & 0x7) << 16) 34 35 #define SSICR_CKS BIT(30) 36 #define SSICR_TUIEN BIT(29) 37 #define SSICR_TOIEN BIT(28) 38 #define SSICR_RUIEN BIT(27) 39 #define SSICR_ROIEN BIT(26) 40 #define SSICR_MST BIT(14) 41 #define SSICR_BCKP BIT(13) 42 #define SSICR_LRCKP BIT(12) 43 #define SSICR_PDTA BIT(9) 44 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 45 #define SSICR_TEN BIT(1) 46 #define SSICR_REN BIT(0) 47 48 #define SSISR_TUIRQ BIT(29) 49 #define SSISR_TOIRQ BIT(28) 50 #define SSISR_RUIRQ BIT(27) 51 #define SSISR_ROIRQ BIT(26) 52 #define SSISR_IIRQ BIT(25) 53 54 #define SSIFCR_AUCKE BIT(31) 55 #define SSIFCR_SSIRST BIT(16) 56 #define SSIFCR_TIE BIT(3) 57 #define SSIFCR_RIE BIT(2) 58 #define SSIFCR_TFRST BIT(1) 59 #define SSIFCR_RFRST BIT(0) 60 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 61 62 #define SSIFSR_TDC_MASK 0x3f 63 #define SSIFSR_TDC_SHIFT 24 64 #define SSIFSR_RDC_MASK 0x3f 65 #define SSIFSR_RDC_SHIFT 8 66 67 #define SSIFSR_TDE BIT(16) 68 #define SSIFSR_RDF BIT(0) 69 70 #define SSIOFR_LRCONT BIT(8) 71 72 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 73 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 74 75 /* Pre allocated buffers sizes */ 76 #define PREALLOC_BUFFER (SZ_32K) 77 #define PREALLOC_BUFFER_MAX (SZ_32K) 78 79 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ 80 #define SSI_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 81 SNDRV_PCM_FMTBIT_S32_LE) 82 #define SSI_CHAN_MIN 2 83 #define SSI_CHAN_MAX 2 84 #define SSI_FIFO_DEPTH 32 85 86 struct rz_ssi_priv; 87 88 struct rz_ssi_stream { 89 struct rz_ssi_priv *priv; 90 struct snd_pcm_substream *substream; 91 int fifo_sample_size; /* sample capacity of SSI FIFO */ 92 int period_counter; /* for keeping track of periods transferred */ 93 int buffer_pos; /* current frame position in the buffer */ 94 int running; /* 0=stopped, 1=running */ 95 96 int uerr_num; 97 int oerr_num; 98 99 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 100 }; 101 102 struct rz_ssi_priv { 103 void __iomem *base; 104 struct reset_control *rstc; 105 struct device *dev; 106 struct clk *sfr_clk; 107 struct clk *clk; 108 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 int irq_rt; 113 114 spinlock_t lock; 115 116 /* 117 * The SSI supports full-duplex transmission and reception. 118 * However, if an error occurs, channel reset (both transmission 119 * and reception reset) is required. 120 * So it is better to use as half-duplex (playing and recording 121 * should be done on separate channels). 122 */ 123 struct rz_ssi_stream playback; 124 struct rz_ssi_stream capture; 125 126 /* clock */ 127 unsigned long audio_mck; 128 unsigned long audio_clk_1; 129 unsigned long audio_clk_2; 130 131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 133 bool dma_rt; 134 135 struct { 136 bool tx_active; 137 bool rx_active; 138 bool one_stream_triggered; 139 } dup; 140 141 /* Full duplex communication support */ 142 struct { 143 unsigned int rate; 144 unsigned int channels; 145 unsigned int sample_width; 146 unsigned int sample_bits; 147 } hw_params_cache; 148 149 struct snd_dmaengine_dai_dma_data dma_dais[SNDRV_PCM_STREAM_LAST + 1]; 150 struct dma_chan *dmas[SNDRV_PCM_STREAM_LAST + 1]; 151 }; 152 153 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 154 { 155 writel(data, (priv->base + reg)); 156 } 157 158 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 159 { 160 return readl(priv->base + reg); 161 } 162 163 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 164 u32 bclr, u32 bset) 165 { 166 u32 val; 167 168 val = readl(priv->base + reg); 169 val = (val & ~bclr) | bset; 170 writel(val, (priv->base + reg)); 171 } 172 173 static inline struct rz_ssi_stream * 174 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 175 { 176 return (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? &ssi->playback : &ssi->capture; 177 } 178 179 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 180 { 181 return !ssi->playback.transfer && !ssi->capture.transfer; 182 } 183 184 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 185 struct snd_pcm_substream *substream) 186 { 187 struct rz_ssi_priv *ssi = strm->priv; 188 189 guard(spinlock_irqsave)(&ssi->lock); 190 191 strm->substream = substream; 192 } 193 194 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 195 struct rz_ssi_stream *strm) 196 { 197 guard(spinlock_irqsave)(&ssi->lock); 198 199 return strm->substream && strm->substream->runtime; 200 } 201 202 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 203 { 204 return strm->substream && strm->running; 205 } 206 207 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 208 struct snd_pcm_substream *substream) 209 { 210 rz_ssi_set_substream(strm, substream); 211 strm->period_counter = 0; 212 strm->buffer_pos = 0; 213 214 strm->oerr_num = 0; 215 strm->uerr_num = 0; 216 strm->running = 0; 217 218 /* fifo init */ 219 strm->fifo_sample_size = SSI_FIFO_DEPTH; 220 } 221 222 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 223 struct rz_ssi_stream *strm) 224 { 225 struct device *dev = ssi->dev; 226 227 rz_ssi_set_substream(strm, NULL); 228 229 if (strm->oerr_num > 0) 230 dev_info(dev, "overrun = %d\n", strm->oerr_num); 231 232 if (strm->uerr_num > 0) 233 dev_info(dev, "underrun = %d\n", strm->uerr_num); 234 } 235 236 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream, 237 unsigned int rate, unsigned int channels) 238 { 239 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 240 unsigned int channel_bits = 32; /* System Word Length */ 241 unsigned long bclk_rate = rate * channels * channel_bits; 242 struct snd_dmaengine_dai_dma_data *dma_dai; 243 unsigned int div; 244 unsigned int i; 245 u32 ssicr = 0; 246 u32 clk_ckdv; 247 248 /* Clear AUCKE so we can set MST */ 249 rz_ssi_reg_writel(ssi, SSIFCR, 0); 250 251 /* Continue to output LRCK pin even when idle */ 252 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 253 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 254 if (ssi->audio_clk_1 % bclk_rate) 255 ssi->audio_mck = ssi->audio_clk_2; 256 else 257 ssi->audio_mck = ssi->audio_clk_1; 258 } 259 260 /* Clock setting */ 261 ssicr |= SSICR_MST; 262 if (ssi->audio_mck == ssi->audio_clk_1) 263 ssicr |= SSICR_CKS; 264 if (ssi->bckp_rise) 265 ssicr |= SSICR_BCKP; 266 if (ssi->lrckp_fsync_fall) 267 ssicr |= SSICR_LRCKP; 268 269 /* Determine the clock divider */ 270 clk_ckdv = 0; 271 div = ssi->audio_mck / bclk_rate; 272 /* try to find an match */ 273 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 274 if (ckdv[i] == div) { 275 clk_ckdv = i; 276 break; 277 } 278 } 279 280 if (i == ARRAY_SIZE(ckdv)) { 281 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 282 return -EINVAL; 283 } 284 285 dma_dai = &ssi->dma_dais[substream->stream]; 286 287 /* 288 * DWL: Data Word Length = {16, 24, 32} bits 289 * SWL: System Word Length = 32 bits 290 */ 291 ssicr |= SSICR_CKDV(clk_ckdv); 292 switch (ssi->hw_params_cache.sample_width) { 293 case 16: 294 ssicr |= SSICR_DWL(1); 295 dma_dai->addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 296 break; 297 case 24: 298 ssicr |= SSICR_DWL(5) | SSICR_PDTA; 299 dma_dai->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 300 break; 301 case 32: 302 ssicr |= SSICR_DWL(6); 303 dma_dai->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 304 break; 305 default: 306 dev_err(ssi->dev, "Not support %u data width", 307 ssi->hw_params_cache.sample_width); 308 return -EINVAL; 309 } 310 311 ssicr |= SSICR_SWL(3); 312 rz_ssi_reg_writel(ssi, SSICR, ssicr); 313 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 314 315 return 0; 316 } 317 318 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 319 { 320 u32 tmp; 321 int ret; 322 323 /* Disable irqs */ 324 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 325 SSICR_RUIEN | SSICR_ROIEN, 0); 326 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 327 328 /* Clear all error flags */ 329 rz_ssi_reg_mask_setl(ssi, SSISR, 330 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 331 SSISR_RUIRQ), 0); 332 333 /* Wait for idle */ 334 ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100); 335 if (ret) 336 dev_warn_ratelimited(ssi->dev, "timeout waiting for SSI idle\n"); 337 338 /* Hold FIFOs in reset */ 339 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 340 } 341 342 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 343 { 344 bool is_play = strm->substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 345 bool is_full_duplex; 346 u32 ssicr, ssifcr; 347 348 is_full_duplex = ssi->dup.tx_active && ssi->dup.rx_active; 349 ssicr = rz_ssi_reg_readl(ssi, SSICR); 350 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 351 if (!is_full_duplex) { 352 ssifcr &= ~0xF; 353 } else if (ssi->dup.one_stream_triggered) { 354 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 355 rz_ssi_set_idle(ssi); 356 ssifcr &= ~SSIFCR_FIFO_RST; 357 } 358 359 /* FIFO interrupt thresholds */ 360 if (rz_ssi_is_dma_enabled(ssi)) 361 rz_ssi_reg_writel(ssi, SSISCR, 0); 362 else 363 rz_ssi_reg_writel(ssi, SSISCR, 364 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 365 SSISCR_RDFS(0)); 366 367 /* enable IRQ */ 368 if (is_play) { 369 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 370 ssifcr |= SSIFCR_TIE; 371 if (!is_full_duplex) 372 ssifcr |= SSIFCR_RFRST; 373 } else { 374 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 375 ssifcr |= SSIFCR_RIE; 376 if (!is_full_duplex) 377 ssifcr |= SSIFCR_TFRST; 378 } 379 380 rz_ssi_reg_writel(ssi, SSICR, ssicr); 381 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 382 383 /* Clear all error flags */ 384 rz_ssi_reg_mask_setl(ssi, SSISR, 385 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 386 SSISR_RUIRQ), 0); 387 388 strm->running = 1; 389 if (!is_full_duplex) { 390 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 391 rz_ssi_reg_writel(ssi, SSICR, ssicr); 392 } else if (ssi->dup.one_stream_triggered) { 393 ssicr |= SSICR_TEN | SSICR_REN; 394 rz_ssi_reg_writel(ssi, SSICR, ssicr); 395 ssi->dup.one_stream_triggered = false; 396 } else { 397 ssi->dup.one_stream_triggered = true; 398 } 399 400 return 0; 401 } 402 403 static int rz_ssi_swreset(struct rz_ssi_priv *ssi) 404 { 405 u32 tmp; 406 407 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 408 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 409 return readl_poll_timeout_atomic(ssi->base + SSIFCR, tmp, !(tmp & SSIFCR_SSIRST), 1, 5); 410 } 411 412 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 413 { 414 strm->running = 0; 415 416 if (rz_ssi_is_stream_running(&ssi->playback) || 417 rz_ssi_is_stream_running(&ssi->capture)) 418 return 0; 419 420 /* Disable TX/RX */ 421 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 422 423 rz_ssi_set_idle(ssi); 424 425 return 0; 426 } 427 428 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 429 { 430 struct snd_pcm_substream *substream = strm->substream; 431 struct snd_pcm_runtime *runtime; 432 int current_period; 433 434 if (!strm->running || !substream || !substream->runtime) 435 return; 436 437 runtime = substream->runtime; 438 strm->buffer_pos += frames; 439 WARN_ON(strm->buffer_pos > runtime->buffer_size); 440 441 /* ring buffer */ 442 if (strm->buffer_pos == runtime->buffer_size) 443 strm->buffer_pos = 0; 444 445 current_period = strm->buffer_pos / runtime->period_size; 446 if (strm->period_counter != current_period) { 447 snd_pcm_period_elapsed(strm->substream); 448 strm->period_counter = current_period; 449 } 450 } 451 452 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 453 { 454 struct snd_pcm_substream *substream = strm->substream; 455 struct snd_pcm_runtime *runtime; 456 int fifo_samples; 457 int frames_left; 458 int samples; 459 int i; 460 461 if (!rz_ssi_stream_is_valid(ssi, strm)) 462 return -EINVAL; 463 464 runtime = substream->runtime; 465 466 do { 467 /* frames left in this period */ 468 frames_left = runtime->period_size - 469 (strm->buffer_pos % runtime->period_size); 470 if (!frames_left) 471 frames_left = runtime->period_size; 472 473 /* Samples in RX FIFO */ 474 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 475 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 476 477 /* Only read full frames at a time */ 478 samples = 0; 479 while (frames_left && (fifo_samples >= runtime->channels)) { 480 samples += runtime->channels; 481 fifo_samples -= runtime->channels; 482 frames_left--; 483 } 484 485 /* not enough samples yet */ 486 if (!samples) 487 break; 488 489 /* calculate new buffer index */ 490 if (ssi->hw_params_cache.sample_width == 16) { 491 u16 *buf; 492 493 buf = (u16 *)runtime->dma_area; 494 buf += strm->buffer_pos * runtime->channels; 495 496 for (i = 0; i < samples; i++) 497 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 498 } else { 499 u32 *buf; 500 501 buf = (u32 *)runtime->dma_area; 502 buf += strm->buffer_pos * runtime->channels; 503 504 for (i = 0; i < samples; i++) 505 *buf++ = rz_ssi_reg_readl(ssi, SSIFRDR); 506 } 507 508 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 509 rz_ssi_pointer_update(strm, samples / runtime->channels); 510 } while (!frames_left && fifo_samples >= runtime->channels); 511 512 return 0; 513 } 514 515 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 516 { 517 struct snd_pcm_substream *substream = strm->substream; 518 struct snd_pcm_runtime *runtime = substream->runtime; 519 int sample_space; 520 int samples = 0; 521 int frames_left; 522 int i; 523 u32 ssifsr; 524 525 if (!rz_ssi_stream_is_valid(ssi, strm)) 526 return -EINVAL; 527 528 /* frames left in this period */ 529 frames_left = runtime->period_size - (strm->buffer_pos % 530 runtime->period_size); 531 if (frames_left == 0) 532 frames_left = runtime->period_size; 533 534 sample_space = strm->fifo_sample_size; 535 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 536 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 537 if (sample_space < 0) 538 return -EINVAL; 539 540 /* Only add full frames at a time */ 541 while (frames_left && (sample_space >= runtime->channels)) { 542 samples += runtime->channels; 543 sample_space -= runtime->channels; 544 frames_left--; 545 } 546 547 /* no space to send anything right now */ 548 if (samples == 0) 549 return 0; 550 551 /* calculate new buffer index */ 552 if (ssi->hw_params_cache.sample_width == 16) { 553 u16 *buf; 554 555 buf = (u16 *)(runtime->dma_area); 556 buf += strm->buffer_pos * runtime->channels; 557 558 for (i = 0; i < samples; i++) 559 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 560 } else { 561 u32 *buf; 562 563 buf = (u32 *)(runtime->dma_area); 564 buf += strm->buffer_pos * runtime->channels; 565 566 for (i = 0; i < samples; i++) 567 rz_ssi_reg_writel(ssi, SSIFTDR, *buf++); 568 } 569 570 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 571 rz_ssi_pointer_update(strm, samples / runtime->channels); 572 573 return 0; 574 } 575 576 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 577 { 578 struct rz_ssi_stream *strm_playback = NULL; 579 struct rz_ssi_stream *strm_capture = NULL; 580 struct rz_ssi_priv *ssi = data; 581 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 582 583 if (ssi->playback.substream) 584 strm_playback = &ssi->playback; 585 if (ssi->capture.substream) 586 strm_capture = &ssi->capture; 587 588 if (!strm_playback && !strm_capture) 589 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 590 591 if (irq == ssi->irq_int) { /* error or idle */ 592 bool is_stopped = !!(ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | 593 SSISR_TUIRQ | SSISR_TOIRQ)); 594 595 if (ssi->capture.substream && is_stopped) { 596 if (ssisr & SSISR_RUIRQ) 597 strm_capture->uerr_num++; 598 if (ssisr & SSISR_ROIRQ) 599 strm_capture->oerr_num++; 600 601 rz_ssi_stop(ssi, strm_capture); 602 } 603 604 if (ssi->playback.substream && is_stopped) { 605 if (ssisr & SSISR_TUIRQ) 606 strm_playback->uerr_num++; 607 if (ssisr & SSISR_TOIRQ) 608 strm_playback->oerr_num++; 609 610 rz_ssi_stop(ssi, strm_playback); 611 } 612 613 if (!rz_ssi_is_stream_running(&ssi->playback) && 614 !rz_ssi_is_stream_running(&ssi->capture) && 615 rz_ssi_is_dma_enabled(ssi) && is_stopped) { 616 if (ssi->playback.substream && 617 ssi->dmas[SNDRV_PCM_STREAM_PLAYBACK]) 618 dmaengine_pause(ssi->dmas[SNDRV_PCM_STREAM_PLAYBACK]); 619 if (ssi->capture.substream && 620 ssi->dmas[SNDRV_PCM_STREAM_CAPTURE] && 621 /* Avoid calling pause twice in case of half duplex. */ 622 ssi->dmas[SNDRV_PCM_STREAM_PLAYBACK] != 623 ssi->dmas[SNDRV_PCM_STREAM_CAPTURE]) 624 dmaengine_pause(ssi->dmas[SNDRV_PCM_STREAM_CAPTURE]); 625 } 626 627 /* Clear all flags */ 628 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 629 SSISR_ROIRQ | SSISR_RUIRQ, 0); 630 631 /* Add/remove more data */ 632 if (ssi->capture.substream && is_stopped) { 633 if (rz_ssi_is_dma_enabled(ssi)) { 634 if (ssi->dmas[SNDRV_PCM_STREAM_CAPTURE]) 635 dmaengine_resume(ssi->dmas[SNDRV_PCM_STREAM_CAPTURE]); 636 } else { 637 strm_capture->transfer(ssi, strm_capture); 638 } 639 } 640 641 if (ssi->playback.substream && is_stopped) { 642 if (rz_ssi_is_dma_enabled(ssi)) { 643 if (ssi->dmas[SNDRV_PCM_STREAM_PLAYBACK]) 644 dmaengine_resume(ssi->dmas[SNDRV_PCM_STREAM_PLAYBACK]); 645 } else { 646 strm_playback->transfer(ssi, strm_playback); 647 } 648 } 649 650 /* Resume */ 651 if (ssi->playback.substream && is_stopped) 652 rz_ssi_start(ssi, &ssi->playback); 653 if (ssi->capture.substream && is_stopped) 654 rz_ssi_start(ssi, &ssi->capture); 655 } 656 657 if (!rz_ssi_is_stream_running(&ssi->playback) && 658 !rz_ssi_is_stream_running(&ssi->capture)) 659 return IRQ_HANDLED; 660 661 /* tx data empty */ 662 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 663 strm_playback->transfer(ssi, &ssi->playback); 664 665 /* rx data full */ 666 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 667 strm_capture->transfer(ssi, &ssi->capture); 668 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 669 } 670 671 if (irq == ssi->irq_rt) { 672 if (ssi->playback.substream) { 673 strm_playback->transfer(ssi, &ssi->playback); 674 } else { 675 strm_capture->transfer(ssi, &ssi->capture); 676 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 677 } 678 } 679 680 return IRQ_HANDLED; 681 } 682 683 static int rz_ssi_trigger_resume(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 684 { 685 struct snd_pcm_substream *substream = strm->substream; 686 int ret; 687 688 if (rz_ssi_is_stream_running(&ssi->playback) || 689 rz_ssi_is_stream_running(&ssi->capture)) 690 return 0; 691 692 ret = rz_ssi_swreset(ssi); 693 if (ret) 694 return ret; 695 696 return rz_ssi_clk_setup(ssi, substream, ssi->hw_params_cache.rate, 697 ssi->hw_params_cache.channels); 698 } 699 700 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 701 struct snd_soc_dai *dai) 702 { 703 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 704 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 705 int ret = 0; 706 707 switch (cmd) { 708 case SNDRV_PCM_TRIGGER_RESUME: 709 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 710 ret = rz_ssi_trigger_resume(ssi, strm); 711 if (ret) 712 return ret; 713 714 fallthrough; 715 716 case SNDRV_PCM_TRIGGER_START: 717 if (cmd == SNDRV_PCM_TRIGGER_START) 718 rz_ssi_stream_init(strm, substream); 719 720 if (!rz_ssi_is_dma_enabled(ssi)) { 721 ret = strm->transfer(ssi, strm); 722 if (ret) 723 return ret; 724 } 725 726 ret = rz_ssi_start(ssi, strm); 727 break; 728 729 case SNDRV_PCM_TRIGGER_SUSPEND: 730 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 731 rz_ssi_stop(ssi, strm); 732 break; 733 734 case SNDRV_PCM_TRIGGER_STOP: 735 rz_ssi_stop(ssi, strm); 736 rz_ssi_stream_quit(ssi, strm); 737 break; 738 } 739 740 return ret; 741 } 742 743 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 744 { 745 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 746 747 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 748 case SND_SOC_DAIFMT_BP_FP: 749 break; 750 default: 751 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 752 return -EINVAL; 753 } 754 755 /* 756 * set clock polarity 757 * 758 * "normal" BCLK = Signal is available at rising edge of BCLK 759 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 760 */ 761 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 762 case SND_SOC_DAIFMT_NB_NF: 763 ssi->bckp_rise = false; 764 ssi->lrckp_fsync_fall = false; 765 break; 766 case SND_SOC_DAIFMT_NB_IF: 767 ssi->bckp_rise = false; 768 ssi->lrckp_fsync_fall = true; 769 break; 770 case SND_SOC_DAIFMT_IB_NF: 771 ssi->bckp_rise = true; 772 ssi->lrckp_fsync_fall = false; 773 break; 774 case SND_SOC_DAIFMT_IB_IF: 775 ssi->bckp_rise = true; 776 ssi->lrckp_fsync_fall = true; 777 break; 778 default: 779 return -EINVAL; 780 } 781 782 /* only i2s support */ 783 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 784 case SND_SOC_DAIFMT_I2S: 785 break; 786 default: 787 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 788 return -EINVAL; 789 } 790 791 return 0; 792 } 793 794 static int rz_ssi_startup(struct snd_pcm_substream *substream, 795 struct snd_soc_dai *dai) 796 { 797 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 798 799 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 800 ssi->dup.tx_active = true; 801 else 802 ssi->dup.rx_active = true; 803 804 return 0; 805 } 806 807 static void rz_ssi_shutdown(struct snd_pcm_substream *substream, 808 struct snd_soc_dai *dai) 809 { 810 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 811 812 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 813 ssi->dup.tx_active = false; 814 else 815 ssi->dup.rx_active = false; 816 817 ssi->dmas[substream->stream] = NULL; 818 } 819 820 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 821 unsigned int channels, 822 unsigned int sample_width, 823 unsigned int sample_bits) 824 { 825 if (ssi->hw_params_cache.rate != rate || 826 ssi->hw_params_cache.channels != channels || 827 ssi->hw_params_cache.sample_width != sample_width || 828 ssi->hw_params_cache.sample_bits != sample_bits) 829 return false; 830 831 return true; 832 } 833 834 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 835 unsigned int channels, 836 unsigned int sample_width, 837 unsigned int sample_bits) 838 { 839 ssi->hw_params_cache.rate = rate; 840 ssi->hw_params_cache.channels = channels; 841 ssi->hw_params_cache.sample_width = sample_width; 842 ssi->hw_params_cache.sample_bits = sample_bits; 843 } 844 845 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 846 struct snd_pcm_hw_params *params, 847 struct snd_soc_dai *dai) 848 { 849 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 850 unsigned int sample_bits = hw_param_interval(params, 851 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 852 unsigned int sample_width = params_width(params); 853 unsigned int channels = params_channels(params); 854 unsigned int rate = params_rate(params); 855 int ret; 856 857 if (!(sample_bits == 16 || sample_bits == 24 || sample_bits == 32)) { 858 dev_err(ssi->dev, "Unsupported sample width: %d\n", 859 sample_bits); 860 return -EINVAL; 861 } 862 863 if (channels != 2) { 864 dev_err(ssi->dev, "Number of channels not matched: %d\n", 865 channels); 866 return -EINVAL; 867 } 868 869 /* Save the DMA channels for recovery. */ 870 if (rz_ssi_is_dma_enabled(ssi)) 871 ssi->dmas[substream->stream] = snd_dmaengine_pcm_get_chan(substream); 872 else 873 ssi->dmas[substream->stream] = NULL; 874 875 if (rz_ssi_is_stream_running(&ssi->playback) || 876 rz_ssi_is_stream_running(&ssi->capture)) { 877 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, sample_width, sample_bits)) 878 return 0; 879 880 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 881 return -EINVAL; 882 } 883 884 rz_ssi_cache_hw_params(ssi, rate, channels, sample_width, sample_bits); 885 886 ret = rz_ssi_swreset(ssi); 887 if (ret) 888 return ret; 889 890 return rz_ssi_clk_setup(ssi, substream, rate, channels); 891 } 892 893 static int rz_ssi_dai_probe(struct snd_soc_dai *dai) 894 { 895 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 896 897 snd_soc_dai_init_dma_data(dai, &ssi->dma_dais[SNDRV_PCM_STREAM_PLAYBACK], 898 &ssi->dma_dais[SNDRV_PCM_STREAM_CAPTURE]); 899 900 return 0; 901 } 902 903 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 904 .probe = rz_ssi_dai_probe, 905 .startup = rz_ssi_startup, 906 .shutdown = rz_ssi_shutdown, 907 .trigger = rz_ssi_dai_trigger, 908 .set_fmt = rz_ssi_dai_set_fmt, 909 .hw_params = rz_ssi_dai_hw_params, 910 }; 911 912 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 913 .info = SNDRV_PCM_INFO_INTERLEAVED | 914 SNDRV_PCM_INFO_MMAP | 915 SNDRV_PCM_INFO_MMAP_VALID | 916 SNDRV_PCM_INFO_RESUME | 917 SNDRV_PCM_INFO_PAUSE, 918 .buffer_bytes_max = 192 * 1024, 919 .period_bytes_min = 32, 920 .period_bytes_max = 48 * 1024, 921 .channels_min = SSI_CHAN_MIN, 922 .channels_max = SSI_CHAN_MAX, 923 .periods_min = 1, 924 .periods_max = 32, 925 .fifo_size = 32 * 2, 926 }; 927 928 static int rz_ssi_pcm_open_pio(struct snd_soc_component *component, 929 struct snd_pcm_substream *substream) 930 { 931 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 932 933 return snd_pcm_hw_constraint_integer(substream->runtime, 934 SNDRV_PCM_HW_PARAM_PERIODS); 935 } 936 937 static int rz_ssi_pcm_open_dma(struct snd_soc_component *component, 938 struct snd_pcm_substream *substream) 939 { 940 return snd_pcm_hw_constraint_integer(substream->runtime, 941 SNDRV_PCM_HW_PARAM_PERIODS); 942 } 943 944 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 945 struct snd_pcm_substream *substream) 946 { 947 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 948 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); 949 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 950 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 951 952 return strm->buffer_pos; 953 } 954 955 static int rz_ssi_pcm_new(struct snd_soc_component *component, 956 struct snd_soc_pcm_runtime *rtd) 957 { 958 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 959 rtd->card->snd_card->dev, 960 rz_ssi_pcm_hardware.buffer_bytes_max, 961 rz_ssi_pcm_hardware.buffer_bytes_max); 962 return 0; 963 } 964 965 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 966 { 967 .name = "rz-ssi-dai", 968 .playback = { 969 .rates = SSI_RATES, 970 .formats = SSI_FMTS, 971 .channels_min = SSI_CHAN_MIN, 972 .channels_max = SSI_CHAN_MAX, 973 }, 974 .capture = { 975 .rates = SSI_RATES, 976 .formats = SSI_FMTS, 977 .channels_min = SSI_CHAN_MIN, 978 .channels_max = SSI_CHAN_MAX, 979 }, 980 .ops = &rz_ssi_dai_ops, 981 }, 982 }; 983 984 static const struct snd_soc_component_driver rz_ssi_soc_component_pio = { 985 .name = "rz-ssi", 986 .open = rz_ssi_pcm_open_pio, 987 .pointer = rz_ssi_pcm_pointer, 988 .pcm_new = rz_ssi_pcm_new, 989 .legacy_dai_naming = 1, 990 }; 991 992 static const struct snd_soc_component_driver rz_ssi_soc_component_dma = { 993 .name = "rz-ssi", 994 .open = rz_ssi_pcm_open_dma, 995 .legacy_dai_naming = 1, 996 }; 997 998 static const struct snd_dmaengine_pcm_config rz_ssi_dmaengine_pcm_conf = { 999 .pcm_hardware = &rz_ssi_pcm_hardware, 1000 .prealloc_buffer_size = 192 * 1024, 1001 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1002 }; 1003 1004 static int rz_ssi_probe(struct platform_device *pdev) 1005 { 1006 const struct snd_soc_component_driver *component_driver; 1007 struct device_node *np = pdev->dev.of_node; 1008 struct device *dev = &pdev->dev; 1009 struct rz_ssi_priv *ssi; 1010 struct clk *audio_clk; 1011 struct resource *res; 1012 int ret; 1013 1014 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); 1015 if (!ssi) 1016 return -ENOMEM; 1017 1018 ssi->dev = dev; 1019 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1020 if (IS_ERR(ssi->base)) 1021 return PTR_ERR(ssi->base); 1022 1023 ssi->clk = devm_clk_get(dev, "ssi"); 1024 if (IS_ERR(ssi->clk)) 1025 return PTR_ERR(ssi->clk); 1026 1027 ssi->sfr_clk = devm_clk_get(dev, "ssi_sfr"); 1028 if (IS_ERR(ssi->sfr_clk)) 1029 return PTR_ERR(ssi->sfr_clk); 1030 1031 audio_clk = devm_clk_get(dev, "audio_clk1"); 1032 if (IS_ERR(audio_clk)) 1033 return dev_err_probe(dev, PTR_ERR(audio_clk), "no audio clk1"); 1034 1035 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1036 audio_clk = devm_clk_get(dev, "audio_clk2"); 1037 if (IS_ERR(audio_clk)) 1038 return dev_err_probe(dev, PTR_ERR(audio_clk), "no audio clk2"); 1039 1040 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1041 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1042 return dev_err_probe(dev, -EINVAL, "no audio clk1 or audio clk2"); 1043 1044 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1045 1046 ssi->dma_dais[SNDRV_PCM_STREAM_PLAYBACK].addr = (dma_addr_t)res->start + SSIFTDR; 1047 ssi->dma_dais[SNDRV_PCM_STREAM_CAPTURE].addr = (dma_addr_t)res->start + SSIFRDR; 1048 1049 if (of_property_present(np, "dma-names")) { 1050 struct snd_dmaengine_pcm_config *config; 1051 unsigned int flags = 0; 1052 1053 config = devm_kzalloc(dev, sizeof(*config), GFP_KERNEL); 1054 if (!config) 1055 return -ENOMEM; 1056 1057 config->pcm_hardware = rz_ssi_dmaengine_pcm_conf.pcm_hardware; 1058 config->prealloc_buffer_size = rz_ssi_dmaengine_pcm_conf.prealloc_buffer_size; 1059 config->prepare_slave_config = rz_ssi_dmaengine_pcm_conf.prepare_slave_config; 1060 1061 if (of_property_match_string(np, "dma-names", "rt") == 0) { 1062 flags = SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX; 1063 config->chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "rt"; 1064 } else { 1065 config->chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "tx"; 1066 config->chan_names[SNDRV_PCM_STREAM_CAPTURE] = "rx"; 1067 } 1068 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, config, flags); 1069 } else { 1070 ret = -ENODEV; 1071 } 1072 1073 if (ret == -EPROBE_DEFER) { 1074 return ret; 1075 } else if (ret) { 1076 dev_warn(dev, "DMA not available, using PIO\n"); 1077 ssi->playback.transfer = rz_ssi_pio_send; 1078 ssi->capture.transfer = rz_ssi_pio_recv; 1079 component_driver = &rz_ssi_soc_component_pio; 1080 } else { 1081 dev_info(dev, "DMA enabled\n"); 1082 component_driver = &rz_ssi_soc_component_dma; 1083 } 1084 1085 ssi->playback.priv = ssi; 1086 ssi->capture.priv = ssi; 1087 1088 spin_lock_init(&ssi->lock); 1089 dev_set_drvdata(dev, ssi); 1090 1091 /* Error Interrupt */ 1092 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1093 if (ssi->irq_int < 0) 1094 return ssi->irq_int; 1095 1096 ret = devm_request_irq(dev, ssi->irq_int, rz_ssi_interrupt, 1097 0, dev_name(dev), ssi); 1098 if (ret < 0) 1099 return dev_err_probe(dev, ret, "irq request error (int_req)\n"); 1100 1101 if (!rz_ssi_is_dma_enabled(ssi)) { 1102 /* Tx and Rx interrupts (pio only) */ 1103 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1104 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1105 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1106 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1107 if (ssi->irq_rt < 0) 1108 return ssi->irq_rt; 1109 1110 ret = devm_request_irq(dev, ssi->irq_rt, 1111 rz_ssi_interrupt, 0, 1112 dev_name(dev), ssi); 1113 if (ret < 0) 1114 return dev_err_probe(dev, ret, 1115 "irq request error (dma_rt)\n"); 1116 } else { 1117 if (ssi->irq_tx < 0) 1118 return ssi->irq_tx; 1119 1120 if (ssi->irq_rx < 0) 1121 return ssi->irq_rx; 1122 1123 ret = devm_request_irq(dev, ssi->irq_tx, 1124 rz_ssi_interrupt, 0, 1125 dev_name(dev), ssi); 1126 if (ret < 0) 1127 return dev_err_probe(dev, ret, 1128 "irq request error (dma_tx)\n"); 1129 1130 ret = devm_request_irq(dev, ssi->irq_rx, 1131 rz_ssi_interrupt, 0, 1132 dev_name(dev), ssi); 1133 if (ret < 0) 1134 return dev_err_probe(dev, ret, 1135 "irq request error (dma_rx)\n"); 1136 } 1137 } 1138 1139 ssi->rstc = devm_reset_control_get_exclusive(dev, NULL); 1140 if (IS_ERR(ssi->rstc)) 1141 return dev_err_probe(dev, PTR_ERR(ssi->rstc), "Failed to get reset\n"); 1142 1143 /* Default 0 for power saving. Can be overridden via sysfs. */ 1144 pm_runtime_set_autosuspend_delay(dev, 0); 1145 pm_runtime_use_autosuspend(dev); 1146 ret = devm_pm_runtime_enable(dev); 1147 if (ret < 0) 1148 return dev_err_probe(dev, ret, "Failed to enable runtime PM!\n"); 1149 1150 return devm_snd_soc_register_component(dev, component_driver, 1151 rz_ssi_soc_dai, 1152 ARRAY_SIZE(rz_ssi_soc_dai)); 1153 } 1154 1155 static const struct of_device_id rz_ssi_of_match[] = { 1156 { .compatible = "renesas,rz-ssi", }, 1157 { /* Sentinel */ } 1158 }; 1159 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1160 1161 static int rz_ssi_runtime_suspend(struct device *dev) 1162 { 1163 struct rz_ssi_priv *ssi = dev_get_drvdata(dev); 1164 1165 return reset_control_assert(ssi->rstc); 1166 } 1167 1168 static int rz_ssi_runtime_resume(struct device *dev) 1169 { 1170 struct rz_ssi_priv *ssi = dev_get_drvdata(dev); 1171 1172 return reset_control_deassert(ssi->rstc); 1173 } 1174 1175 static const struct dev_pm_ops rz_ssi_pm_ops = { 1176 RUNTIME_PM_OPS(rz_ssi_runtime_suspend, rz_ssi_runtime_resume, NULL) 1177 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1178 }; 1179 1180 static struct platform_driver rz_ssi_driver = { 1181 .driver = { 1182 .name = "rz-ssi-pcm-audio", 1183 .of_match_table = rz_ssi_of_match, 1184 .pm = pm_ptr(&rz_ssi_pm_ops), 1185 }, 1186 .probe = rz_ssi_probe, 1187 }; 1188 1189 module_platform_driver(rz_ssi_driver); 1190 1191 MODULE_LICENSE("GPL v2"); 1192 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1193 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1194