1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/slab.h> 27 28 #include "hwmgr.h" 29 #include "amd_powerplay.h" 30 #include "vega20_smumgr.h" 31 #include "hardwaremanager.h" 32 #include "ppatomfwctrl.h" 33 #include "atomfirmware.h" 34 #include "cgs_common.h" 35 #include "vega20_powertune.h" 36 #include "vega20_inc.h" 37 #include "pppcielanes.h" 38 #include "vega20_hwmgr.h" 39 #include "vega20_processpptables.h" 40 #include "vega20_pptable.h" 41 #include "vega20_thermal.h" 42 #include "vega20_ppsmc.h" 43 #include "pp_debug.h" 44 #include "amd_pcie_helpers.h" 45 #include "ppinterrupt.h" 46 #include "pp_overdriver.h" 47 #include "pp_thermal.h" 48 #include "soc15_common.h" 49 #include "vega20_baco.h" 50 #include "smuio/smuio_9_0_offset.h" 51 #include "smuio/smuio_9_0_sh_mask.h" 52 #include "nbio/nbio_7_4_sh_mask.h" 53 54 #define smnPCIE_LC_SPEED_CNTL 0x11140290 55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 56 57 #define LINK_WIDTH_MAX 6 58 #define LINK_SPEED_MAX 3 59 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 60 static const int link_speed[] = {25, 50, 80, 160}; 61 62 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) 63 { 64 struct vega20_hwmgr *data = 65 (struct vega20_hwmgr *)(hwmgr->backend); 66 67 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT; 68 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT; 69 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT; 70 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT; 71 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT; 72 73 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT; 74 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 75 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 76 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 77 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 78 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 79 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 80 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 81 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 82 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 83 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 84 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 85 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 86 87 /* 88 * Disable the following features for now: 89 * GFXCLK DS 90 * SOCLK DS 91 * LCLK DS 92 * DCEFCLK DS 93 * FCLK DS 94 * MP1CLK DS 95 * MP0CLK DS 96 */ 97 data->registry_data.disallowed_features = 0xE0041C00; 98 /* ECC feature should be disabled on old SMUs */ 99 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version); 100 if (hwmgr->smu_version < 0x282100) 101 data->registry_data.disallowed_features |= FEATURE_ECC_MASK; 102 103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) 104 data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK; 105 106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) 107 data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK; 108 109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) 110 data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK; 111 112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) 113 data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK; 114 115 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) 116 data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK; 117 118 if (!(hwmgr->feature_mask & PP_ULV_MASK)) 119 data->registry_data.disallowed_features |= FEATURE_ULV_MASK; 120 121 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) 122 data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK; 123 124 data->registry_data.od_state_in_dc_support = 0; 125 data->registry_data.thermal_support = 1; 126 data->registry_data.skip_baco_hardware = 0; 127 128 data->registry_data.log_avfs_param = 0; 129 data->registry_data.sclk_throttle_low_notification = 1; 130 data->registry_data.force_dpm_high = 0; 131 data->registry_data.stable_pstate_sclk_dpm_percentage = 75; 132 133 data->registry_data.didt_support = 0; 134 if (data->registry_data.didt_support) { 135 data->registry_data.didt_mode = 6; 136 data->registry_data.sq_ramping_support = 1; 137 data->registry_data.db_ramping_support = 0; 138 data->registry_data.td_ramping_support = 0; 139 data->registry_data.tcp_ramping_support = 0; 140 data->registry_data.dbr_ramping_support = 0; 141 data->registry_data.edc_didt_support = 1; 142 data->registry_data.gc_didt_support = 0; 143 data->registry_data.psm_didt_support = 0; 144 } 145 146 data->registry_data.pcie_lane_override = 0xff; 147 data->registry_data.pcie_speed_override = 0xff; 148 data->registry_data.pcie_clock_override = 0xffffffff; 149 data->registry_data.regulator_hot_gpio_support = 1; 150 data->registry_data.ac_dc_switch_gpio_support = 0; 151 data->registry_data.quick_transition_support = 0; 152 data->registry_data.zrpm_start_temp = 0xffff; 153 data->registry_data.zrpm_stop_temp = 0xffff; 154 data->registry_data.od8_feature_enable = 1; 155 data->registry_data.disable_water_mark = 0; 156 data->registry_data.disable_pp_tuning = 0; 157 data->registry_data.disable_xlpp_tuning = 0; 158 data->registry_data.disable_workload_policy = 0; 159 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; 160 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; 161 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; 162 data->registry_data.force_workload_policy_mask = 0; 163 data->registry_data.disable_3d_fs_detection = 0; 164 data->registry_data.fps_support = 1; 165 data->registry_data.disable_auto_wattman = 1; 166 data->registry_data.auto_wattman_debug = 0; 167 data->registry_data.auto_wattman_sample_period = 100; 168 data->registry_data.fclk_gfxclk_ratio = 0; 169 data->registry_data.auto_wattman_threshold = 50; 170 data->registry_data.gfxoff_controlled_by_driver = 1; 171 data->gfxoff_allowed = false; 172 data->counter_gfxoff = 0; 173 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 174 } 175 176 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) 177 { 178 struct vega20_hwmgr *data = 179 (struct vega20_hwmgr *)(hwmgr->backend); 180 struct amdgpu_device *adev = hwmgr->adev; 181 182 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE) 183 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 184 PHM_PlatformCaps_ControlVDDCI); 185 186 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 187 PHM_PlatformCaps_TablelessHardwareInterface); 188 189 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 190 PHM_PlatformCaps_BACO); 191 192 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 193 PHM_PlatformCaps_EnableSMU7ThermalManagement); 194 195 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 196 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 197 PHM_PlatformCaps_UVDPowerGating); 198 199 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 201 PHM_PlatformCaps_VCEPowerGating); 202 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_UnTabledHardwareInterface); 205 206 if (data->registry_data.od8_feature_enable) 207 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 208 PHM_PlatformCaps_OD8inACSupport); 209 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_ActivityReporting); 212 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 213 PHM_PlatformCaps_FanSpeedInTableIsRPM); 214 215 if (data->registry_data.od_state_in_dc_support) { 216 if (data->registry_data.od8_feature_enable) 217 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 218 PHM_PlatformCaps_OD8inDCSupport); 219 } 220 221 if (data->registry_data.thermal_support && 222 data->registry_data.fuzzy_fan_control_support && 223 hwmgr->thermal_controller.advanceFanControlParameters.usTMax) 224 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 225 PHM_PlatformCaps_ODFuzzyFanControlSupport); 226 227 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_DynamicPowerManagement); 229 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 230 PHM_PlatformCaps_SMC); 231 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 232 PHM_PlatformCaps_ThermalPolicyDelay); 233 234 if (data->registry_data.force_dpm_high) 235 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 236 PHM_PlatformCaps_ExclusiveModeAlwaysHigh); 237 238 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 239 PHM_PlatformCaps_DynamicUVDState); 240 241 if (data->registry_data.sclk_throttle_low_notification) 242 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 243 PHM_PlatformCaps_SclkThrottleLowNotification); 244 245 /* power tune caps */ 246 /* assume disabled */ 247 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 248 PHM_PlatformCaps_PowerContainment); 249 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 250 PHM_PlatformCaps_DiDtSupport); 251 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 252 PHM_PlatformCaps_SQRamping); 253 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 254 PHM_PlatformCaps_DBRamping); 255 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 256 PHM_PlatformCaps_TDRamping); 257 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 258 PHM_PlatformCaps_TCPRamping); 259 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 260 PHM_PlatformCaps_DBRRamping); 261 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 262 PHM_PlatformCaps_DiDtEDCEnable); 263 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 264 PHM_PlatformCaps_GCEDC); 265 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 266 PHM_PlatformCaps_PSM); 267 268 if (data->registry_data.didt_support) { 269 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 270 PHM_PlatformCaps_DiDtSupport); 271 if (data->registry_data.sq_ramping_support) 272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 273 PHM_PlatformCaps_SQRamping); 274 if (data->registry_data.db_ramping_support) 275 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 276 PHM_PlatformCaps_DBRamping); 277 if (data->registry_data.td_ramping_support) 278 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 279 PHM_PlatformCaps_TDRamping); 280 if (data->registry_data.tcp_ramping_support) 281 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 282 PHM_PlatformCaps_TCPRamping); 283 if (data->registry_data.dbr_ramping_support) 284 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 285 PHM_PlatformCaps_DBRRamping); 286 if (data->registry_data.edc_didt_support) 287 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 288 PHM_PlatformCaps_DiDtEDCEnable); 289 if (data->registry_data.gc_didt_support) 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_GCEDC); 292 if (data->registry_data.psm_didt_support) 293 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 294 PHM_PlatformCaps_PSM); 295 } 296 297 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 298 PHM_PlatformCaps_RegulatorHot); 299 300 if (data->registry_data.ac_dc_switch_gpio_support) { 301 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 302 PHM_PlatformCaps_AutomaticDCTransition); 303 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 304 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 305 } 306 307 if (data->registry_data.quick_transition_support) { 308 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 309 PHM_PlatformCaps_AutomaticDCTransition); 310 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 311 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 312 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 313 PHM_PlatformCaps_Falcon_QuickTransition); 314 } 315 316 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) { 317 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 318 PHM_PlatformCaps_LowestUclkReservedForUlv); 319 if (data->lowest_uclk_reserved_for_ulv == 1) 320 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 321 PHM_PlatformCaps_LowestUclkReservedForUlv); 322 } 323 324 if (data->registry_data.custom_fan_support) 325 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 326 PHM_PlatformCaps_CustomFanControlSupport); 327 328 return 0; 329 } 330 331 static int vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr) 332 { 333 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 334 struct amdgpu_device *adev = hwmgr->adev; 335 uint32_t top32, bottom32; 336 int i, ret; 337 338 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 339 FEATURE_DPM_PREFETCHER_BIT; 340 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 341 FEATURE_DPM_GFXCLK_BIT; 342 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 343 FEATURE_DPM_UCLK_BIT; 344 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 345 FEATURE_DPM_SOCCLK_BIT; 346 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 347 FEATURE_DPM_UVD_BIT; 348 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 349 FEATURE_DPM_VCE_BIT; 350 data->smu_features[GNLD_ULV].smu_feature_id = 351 FEATURE_ULV_BIT; 352 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 353 FEATURE_DPM_MP0CLK_BIT; 354 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 355 FEATURE_DPM_LINK_BIT; 356 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 357 FEATURE_DPM_DCEFCLK_BIT; 358 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 359 FEATURE_DS_GFXCLK_BIT; 360 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 361 FEATURE_DS_SOCCLK_BIT; 362 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 363 FEATURE_DS_LCLK_BIT; 364 data->smu_features[GNLD_PPT].smu_feature_id = 365 FEATURE_PPT_BIT; 366 data->smu_features[GNLD_TDC].smu_feature_id = 367 FEATURE_TDC_BIT; 368 data->smu_features[GNLD_THERMAL].smu_feature_id = 369 FEATURE_THERMAL_BIT; 370 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 371 FEATURE_GFX_PER_CU_CG_BIT; 372 data->smu_features[GNLD_RM].smu_feature_id = 373 FEATURE_RM_BIT; 374 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 375 FEATURE_DS_DCEFCLK_BIT; 376 data->smu_features[GNLD_ACDC].smu_feature_id = 377 FEATURE_ACDC_BIT; 378 data->smu_features[GNLD_VR0HOT].smu_feature_id = 379 FEATURE_VR0HOT_BIT; 380 data->smu_features[GNLD_VR1HOT].smu_feature_id = 381 FEATURE_VR1HOT_BIT; 382 data->smu_features[GNLD_FW_CTF].smu_feature_id = 383 FEATURE_FW_CTF_BIT; 384 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 385 FEATURE_LED_DISPLAY_BIT; 386 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 387 FEATURE_FAN_CONTROL_BIT; 388 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 389 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; 390 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; 391 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT; 392 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT; 393 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT; 394 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT; 395 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT; 396 data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT; 397 398 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 399 data->smu_features[i].smu_feature_bitmap = 400 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); 401 data->smu_features[i].allowed = 402 ((data->registry_data.disallowed_features >> i) & 1) ? 403 false : true; 404 } 405 406 /* Get the SN to turn into a Unique ID */ 407 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 408 if (ret) 409 return ret; 410 411 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 412 if (ret) 413 return ret; 414 415 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 416 417 return 0; 418 } 419 420 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 421 { 422 return 0; 423 } 424 425 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 426 { 427 kfree(hwmgr->backend); 428 hwmgr->backend = NULL; 429 430 return 0; 431 } 432 433 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 434 { 435 struct vega20_hwmgr *data; 436 struct amdgpu_device *adev = hwmgr->adev; 437 int result; 438 439 data = kzalloc_obj(struct vega20_hwmgr); 440 if (data == NULL) 441 return -ENOMEM; 442 443 hwmgr->backend = data; 444 445 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 446 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 447 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 448 449 vega20_set_default_registry_data(hwmgr); 450 451 data->disable_dpm_mask = 0xff; 452 453 /* need to set voltage control types before EVV patching */ 454 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE; 455 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE; 456 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE; 457 458 data->water_marks_bitmap = 0; 459 data->avfs_exist = false; 460 461 vega20_set_features_platform_caps(hwmgr); 462 463 result = vega20_init_dpm_defaults(hwmgr); 464 if (result) { 465 pr_err("%s failed\n", __func__); 466 return result; 467 } 468 /* Parse pptable data read from VBIOS */ 469 vega20_set_private_data_based_on_pptable(hwmgr); 470 471 data->is_tlu_enabled = false; 472 473 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 474 VEGA20_MAX_HARDWARE_POWERLEVELS; 475 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 476 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 477 478 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 479 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 480 hwmgr->platform_descriptor.clockStep.engineClock = 500; 481 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 482 483 data->total_active_cus = adev->gfx.cu_info.number; 484 data->is_custom_profile_set = false; 485 486 return 0; 487 } 488 489 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr) 490 { 491 struct vega20_hwmgr *data = 492 (struct vega20_hwmgr *)(hwmgr->backend); 493 494 data->low_sclk_interrupt_threshold = 0; 495 496 return 0; 497 } 498 499 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr) 500 { 501 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 502 int ret = 0; 503 bool use_baco = (amdgpu_in_reset(adev) && 504 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 505 (adev->in_runpm && amdgpu_asic_supports_baco(adev)); 506 507 ret = vega20_init_sclk_threshold(hwmgr); 508 PP_ASSERT_WITH_CODE(!ret, 509 "Failed to init sclk threshold!", 510 return ret); 511 512 if (use_baco) { 513 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr); 514 if (ret) 515 pr_err("Failed to apply vega20 baco workaround!\n"); 516 } 517 518 return ret; 519 } 520 521 /* 522 * @fn vega20_init_dpm_state 523 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 524 * 525 * @param dpm_state - the address of the DPM Table to initiailize. 526 * @return None. 527 */ 528 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state) 529 { 530 dpm_state->soft_min_level = 0x0; 531 dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT; 532 dpm_state->hard_min_level = 0x0; 533 dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT; 534 } 535 536 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 537 PPCLK_e clk_id, uint32_t *num_of_levels) 538 { 539 int ret = 0; 540 541 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 542 PPSMC_MSG_GetDpmFreqByIndex, 543 (clk_id << 16 | 0xFF), 544 num_of_levels); 545 PP_ASSERT_WITH_CODE(!ret, 546 "[GetNumOfDpmLevel] failed to get dpm levels!", 547 return ret); 548 549 return ret; 550 } 551 552 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 553 PPCLK_e clk_id, uint32_t index, uint32_t *clk) 554 { 555 int ret = 0; 556 557 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 558 PPSMC_MSG_GetDpmFreqByIndex, 559 (clk_id << 16 | index), 560 clk); 561 PP_ASSERT_WITH_CODE(!ret, 562 "[GetDpmFreqByIndex] failed to get dpm freq by index!", 563 return ret); 564 565 return ret; 566 } 567 568 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, 569 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) 570 { 571 int ret = 0; 572 uint32_t i, num_of_levels, clk; 573 574 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); 575 PP_ASSERT_WITH_CODE(!ret, 576 "[SetupSingleDpmTable] failed to get clk levels!", 577 return ret); 578 579 dpm_table->count = num_of_levels; 580 581 for (i = 0; i < num_of_levels; i++) { 582 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); 583 PP_ASSERT_WITH_CODE(!ret, 584 "[SetupSingleDpmTable] failed to get clk of specific level!", 585 return ret); 586 dpm_table->dpm_levels[i].value = clk; 587 dpm_table->dpm_levels[i].enabled = true; 588 } 589 590 return ret; 591 } 592 593 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr) 594 { 595 struct vega20_hwmgr *data = 596 (struct vega20_hwmgr *)(hwmgr->backend); 597 struct vega20_single_dpm_table *dpm_table; 598 int ret = 0; 599 600 dpm_table = &(data->dpm_table.gfx_table); 601 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 602 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 603 PP_ASSERT_WITH_CODE(!ret, 604 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", 605 return ret); 606 } else { 607 dpm_table->count = 1; 608 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 609 } 610 611 return ret; 612 } 613 614 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr) 615 { 616 struct vega20_hwmgr *data = 617 (struct vega20_hwmgr *)(hwmgr->backend); 618 struct vega20_single_dpm_table *dpm_table; 619 int ret = 0; 620 621 dpm_table = &(data->dpm_table.mem_table); 622 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 623 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); 624 PP_ASSERT_WITH_CODE(!ret, 625 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", 626 return ret); 627 } else { 628 dpm_table->count = 1; 629 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 630 } 631 632 return ret; 633 } 634 635 /* 636 * This function is to initialize all DPM state tables 637 * for SMU based on the dependency table. 638 * Dynamic state patching function will then trim these 639 * state tables to the allowed range based 640 * on the power policy or external client requests, 641 * such as UVD request, etc. 642 */ 643 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 644 { 645 struct vega20_hwmgr *data = 646 (struct vega20_hwmgr *)(hwmgr->backend); 647 struct vega20_single_dpm_table *dpm_table; 648 int ret = 0; 649 650 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 651 652 /* socclk */ 653 dpm_table = &(data->dpm_table.soc_table); 654 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 655 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); 656 PP_ASSERT_WITH_CODE(!ret, 657 "[SetupDefaultDpmTable] failed to get socclk dpm levels!", 658 return ret); 659 } else { 660 dpm_table->count = 1; 661 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 662 } 663 vega20_init_dpm_state(&(dpm_table->dpm_state)); 664 665 /* gfxclk */ 666 dpm_table = &(data->dpm_table.gfx_table); 667 ret = vega20_setup_gfxclk_dpm_table(hwmgr); 668 if (ret) 669 return ret; 670 vega20_init_dpm_state(&(dpm_table->dpm_state)); 671 672 /* memclk */ 673 dpm_table = &(data->dpm_table.mem_table); 674 ret = vega20_setup_memclk_dpm_table(hwmgr); 675 if (ret) 676 return ret; 677 vega20_init_dpm_state(&(dpm_table->dpm_state)); 678 679 /* eclk */ 680 dpm_table = &(data->dpm_table.eclk_table); 681 if (data->smu_features[GNLD_DPM_VCE].enabled) { 682 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); 683 PP_ASSERT_WITH_CODE(!ret, 684 "[SetupDefaultDpmTable] failed to get eclk dpm levels!", 685 return ret); 686 } else { 687 dpm_table->count = 1; 688 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 689 } 690 vega20_init_dpm_state(&(dpm_table->dpm_state)); 691 692 /* vclk */ 693 dpm_table = &(data->dpm_table.vclk_table); 694 if (data->smu_features[GNLD_DPM_UVD].enabled) { 695 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); 696 PP_ASSERT_WITH_CODE(!ret, 697 "[SetupDefaultDpmTable] failed to get vclk dpm levels!", 698 return ret); 699 } else { 700 dpm_table->count = 1; 701 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 702 } 703 vega20_init_dpm_state(&(dpm_table->dpm_state)); 704 705 /* dclk */ 706 dpm_table = &(data->dpm_table.dclk_table); 707 if (data->smu_features[GNLD_DPM_UVD].enabled) { 708 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); 709 PP_ASSERT_WITH_CODE(!ret, 710 "[SetupDefaultDpmTable] failed to get dclk dpm levels!", 711 return ret); 712 } else { 713 dpm_table->count = 1; 714 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 715 } 716 vega20_init_dpm_state(&(dpm_table->dpm_state)); 717 718 /* dcefclk */ 719 dpm_table = &(data->dpm_table.dcef_table); 720 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 721 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); 722 PP_ASSERT_WITH_CODE(!ret, 723 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", 724 return ret); 725 } else { 726 dpm_table->count = 1; 727 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 728 } 729 vega20_init_dpm_state(&(dpm_table->dpm_state)); 730 731 /* pixclk */ 732 dpm_table = &(data->dpm_table.pixel_table); 733 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 734 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); 735 PP_ASSERT_WITH_CODE(!ret, 736 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", 737 return ret); 738 } else 739 dpm_table->count = 0; 740 vega20_init_dpm_state(&(dpm_table->dpm_state)); 741 742 /* dispclk */ 743 dpm_table = &(data->dpm_table.display_table); 744 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 745 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); 746 PP_ASSERT_WITH_CODE(!ret, 747 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", 748 return ret); 749 } else 750 dpm_table->count = 0; 751 vega20_init_dpm_state(&(dpm_table->dpm_state)); 752 753 /* phyclk */ 754 dpm_table = &(data->dpm_table.phy_table); 755 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 756 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); 757 PP_ASSERT_WITH_CODE(!ret, 758 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", 759 return ret); 760 } else 761 dpm_table->count = 0; 762 vega20_init_dpm_state(&(dpm_table->dpm_state)); 763 764 /* fclk */ 765 dpm_table = &(data->dpm_table.fclk_table); 766 if (data->smu_features[GNLD_DPM_FCLK].enabled) { 767 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK); 768 PP_ASSERT_WITH_CODE(!ret, 769 "[SetupDefaultDpmTable] failed to get fclk dpm levels!", 770 return ret); 771 } else { 772 dpm_table->count = 1; 773 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100; 774 } 775 vega20_init_dpm_state(&(dpm_table->dpm_state)); 776 777 /* save a copy of the default DPM table */ 778 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 779 sizeof(struct vega20_dpm_table)); 780 781 return 0; 782 } 783 784 /** 785 * vega20_init_smc_table - Initializes the SMC table and uploads it 786 * 787 * @hwmgr: the address of the powerplay hardware manager. 788 * return: always 0 789 */ 790 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr) 791 { 792 int result; 793 struct vega20_hwmgr *data = 794 (struct vega20_hwmgr *)(hwmgr->backend); 795 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 796 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 797 struct phm_ppt_v3_information *pptable_information = 798 (struct phm_ppt_v3_information *)hwmgr->pptable; 799 800 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 801 PP_ASSERT_WITH_CODE(!result, 802 "[InitSMCTable] Failed to get vbios bootup values!", 803 return result); 804 805 data->vbios_boot_state.vddc = boot_up_values.usVddc; 806 data->vbios_boot_state.vddci = boot_up_values.usVddci; 807 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 808 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 809 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 810 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 811 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 812 data->vbios_boot_state.eclock = boot_up_values.ulEClk; 813 data->vbios_boot_state.vclock = boot_up_values.ulVClk; 814 data->vbios_boot_state.dclock = boot_up_values.ulDClk; 815 data->vbios_boot_state.fclock = boot_up_values.ulFClk; 816 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; 817 818 smum_send_msg_to_smc_with_parameter(hwmgr, 819 PPSMC_MSG_SetMinDeepSleepDcefclk, 820 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 821 NULL); 822 823 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 824 825 result = smum_smc_table_manager(hwmgr, 826 (uint8_t *)pp_table, TABLE_PPTABLE, false); 827 PP_ASSERT_WITH_CODE(!result, 828 "[InitSMCTable] Failed to upload PPtable!", 829 return result); 830 831 return 0; 832 } 833 834 /* 835 * Override PCIe link speed and link width for DPM Level 1. PPTable entries 836 * reflect the ASIC capabilities and not the system capabilities. For e.g. 837 * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch 838 * to DPM1, it fails as system doesn't support Gen4. 839 */ 840 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr) 841 { 842 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 843 struct vega20_hwmgr *data = 844 (struct vega20_hwmgr *)(hwmgr->backend); 845 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; 846 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 847 int i; 848 int ret; 849 850 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 851 pcie_gen = 3; 852 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 853 pcie_gen = 2; 854 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 855 pcie_gen = 1; 856 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 857 pcie_gen = 0; 858 859 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 860 pcie_width = 6; 861 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 862 pcie_width = 5; 863 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 864 pcie_width = 4; 865 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 866 pcie_width = 3; 867 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 868 pcie_width = 2; 869 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 870 pcie_width = 1; 871 872 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 873 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 874 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 875 */ 876 for (i = 0; i < NUM_LINK_LEVELS; i++) { 877 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : 878 pp_table->PcieGenSpeed[i]; 879 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : 880 pp_table->PcieLaneCount[i]; 881 882 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != 883 pp_table->PcieLaneCount[i]) { 884 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; 885 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 886 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 887 NULL); 888 PP_ASSERT_WITH_CODE(!ret, 889 "[OverridePcieParameters] Attempt to override pcie params failed!", 890 return ret); 891 } 892 893 /* update the pptable */ 894 pp_table->PcieGenSpeed[i] = pcie_gen_arg; 895 pp_table->PcieLaneCount[i] = pcie_width_arg; 896 } 897 898 /* override to the highest if it's disabled from ppfeaturmask */ 899 if (data->registry_data.pcie_dpm_key_disabled) { 900 for (i = 0; i < NUM_LINK_LEVELS; i++) { 901 smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; 902 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 903 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 904 NULL); 905 PP_ASSERT_WITH_CODE(!ret, 906 "[OverridePcieParameters] Attempt to override pcie params failed!", 907 return ret); 908 909 pp_table->PcieGenSpeed[i] = pcie_gen; 910 pp_table->PcieLaneCount[i] = pcie_width; 911 } 912 ret = vega20_enable_smc_features(hwmgr, 913 false, 914 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); 915 PP_ASSERT_WITH_CODE(!ret, 916 "Attempt to Disable DPM LINK Failed!", 917 return ret); 918 data->smu_features[GNLD_DPM_LINK].enabled = false; 919 data->smu_features[GNLD_DPM_LINK].supported = false; 920 } 921 922 return 0; 923 } 924 925 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) 926 { 927 struct vega20_hwmgr *data = 928 (struct vega20_hwmgr *)(hwmgr->backend); 929 uint32_t allowed_features_low = 0, allowed_features_high = 0; 930 int i; 931 int ret = 0; 932 933 for (i = 0; i < GNLD_FEATURES_MAX; i++) 934 if (data->smu_features[i].allowed) 935 data->smu_features[i].smu_feature_id > 31 ? 936 (allowed_features_high |= 937 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) 938 & 0xFFFFFFFF)) : 939 (allowed_features_low |= 940 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) 941 & 0xFFFFFFFF)); 942 943 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 944 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL); 945 PP_ASSERT_WITH_CODE(!ret, 946 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!", 947 return ret); 948 949 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 950 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL); 951 PP_ASSERT_WITH_CODE(!ret, 952 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", 953 return ret); 954 955 return 0; 956 } 957 958 static int vega20_run_btc(struct pp_hwmgr *hwmgr) 959 { 960 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL); 961 } 962 963 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr) 964 { 965 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL); 966 } 967 968 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr) 969 { 970 struct vega20_hwmgr *data = 971 (struct vega20_hwmgr *)(hwmgr->backend); 972 uint64_t features_enabled; 973 int i; 974 bool enabled; 975 int ret = 0; 976 977 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, 978 PPSMC_MSG_EnableAllSmuFeatures, 979 NULL)) == 0, 980 "[EnableAllSMUFeatures] Failed to enable all smu features!", 981 return ret); 982 983 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 984 PP_ASSERT_WITH_CODE(!ret, 985 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 986 return ret); 987 988 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 989 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? 990 true : false; 991 data->smu_features[i].enabled = enabled; 992 data->smu_features[i].supported = enabled; 993 994 #if 0 995 if (data->smu_features[i].allowed && !enabled) 996 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i); 997 else if (!data->smu_features[i].allowed && enabled) 998 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i); 999 #endif 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr) 1006 { 1007 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1008 1009 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1010 return smum_send_msg_to_smc_with_parameter(hwmgr, 1011 PPSMC_MSG_SetUclkFastSwitch, 1012 1, 1013 NULL); 1014 1015 return 0; 1016 } 1017 1018 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr) 1019 { 1020 struct vega20_hwmgr *data = 1021 (struct vega20_hwmgr *)(hwmgr->backend); 1022 1023 return smum_send_msg_to_smc_with_parameter(hwmgr, 1024 PPSMC_MSG_SetFclkGfxClkRatio, 1025 data->registry_data.fclk_gfxclk_ratio, 1026 NULL); 1027 } 1028 1029 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) 1030 { 1031 struct vega20_hwmgr *data = 1032 (struct vega20_hwmgr *)(hwmgr->backend); 1033 int i, ret = 0; 1034 1035 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, 1036 PPSMC_MSG_DisableAllSmuFeatures, 1037 NULL)) == 0, 1038 "[DisableAllSMUFeatures] Failed to disable all smu features!", 1039 return ret); 1040 1041 for (i = 0; i < GNLD_FEATURES_MAX; i++) 1042 data->smu_features[i].enabled = 0; 1043 1044 return 0; 1045 } 1046 1047 static int vega20_od8_set_feature_capabilities( 1048 struct pp_hwmgr *hwmgr) 1049 { 1050 struct phm_ppt_v3_information *pptable_information = 1051 (struct phm_ppt_v3_information *)hwmgr->pptable; 1052 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1053 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1054 struct vega20_od8_settings *od_settings = &(data->od8_settings); 1055 1056 od_settings->overdrive8_capabilities = 0; 1057 1058 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1059 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] && 1060 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 && 1061 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 && 1062 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >= 1063 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) 1064 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS; 1065 1066 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] && 1067 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >= 1068 pp_table->MinVoltageGfx / VOLTAGE_SCALE) && 1069 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <= 1070 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) && 1071 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >= 1072 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1])) 1073 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE; 1074 } 1075 1076 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1077 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] = 1078 data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value; 1079 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] && 1080 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 && 1081 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 && 1082 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >= 1083 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX])) 1084 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX; 1085 } 1086 1087 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] && 1088 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 && 1089 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 && 1090 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 && 1091 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100) 1092 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT; 1093 1094 if (data->smu_features[GNLD_FAN_CONTROL].enabled) { 1095 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] && 1096 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 && 1097 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 && 1098 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >= 1099 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) 1100 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK; 1101 1102 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] && 1103 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >= 1104 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) && 1105 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 && 1106 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >= 1107 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) 1108 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN; 1109 } 1110 1111 if (data->smu_features[GNLD_THERMAL].enabled) { 1112 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] && 1113 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 && 1114 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 && 1115 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >= 1116 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) 1117 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN; 1118 1119 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] && 1120 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 && 1121 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 && 1122 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >= 1123 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) 1124 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM; 1125 } 1126 1127 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE]) 1128 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE; 1129 1130 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] && 1131 pp_table->FanZeroRpmEnable) 1132 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL; 1133 1134 if (!od_settings->overdrive8_capabilities) 1135 hwmgr->od_enabled = false; 1136 1137 return 0; 1138 } 1139 1140 static int vega20_od8_set_feature_id( 1141 struct pp_hwmgr *hwmgr) 1142 { 1143 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1144 struct vega20_od8_settings *od_settings = &(data->od8_settings); 1145 1146 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) { 1147 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id = 1148 OD8_GFXCLK_LIMITS; 1149 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id = 1150 OD8_GFXCLK_LIMITS; 1151 } else { 1152 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id = 1153 0; 1154 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id = 1155 0; 1156 } 1157 1158 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) { 1159 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id = 1160 OD8_GFXCLK_CURVE; 1161 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id = 1162 OD8_GFXCLK_CURVE; 1163 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id = 1164 OD8_GFXCLK_CURVE; 1165 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id = 1166 OD8_GFXCLK_CURVE; 1167 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id = 1168 OD8_GFXCLK_CURVE; 1169 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id = 1170 OD8_GFXCLK_CURVE; 1171 } else { 1172 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id = 1173 0; 1174 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id = 1175 0; 1176 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id = 1177 0; 1178 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id = 1179 0; 1180 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id = 1181 0; 1182 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id = 1183 0; 1184 } 1185 1186 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX) 1187 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX; 1188 else 1189 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0; 1190 1191 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT) 1192 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT; 1193 else 1194 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0; 1195 1196 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK) 1197 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id = 1198 OD8_ACOUSTIC_LIMIT_SCLK; 1199 else 1200 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id = 1201 0; 1202 1203 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN) 1204 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id = 1205 OD8_FAN_SPEED_MIN; 1206 else 1207 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id = 1208 0; 1209 1210 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN) 1211 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id = 1212 OD8_TEMPERATURE_FAN; 1213 else 1214 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id = 1215 0; 1216 1217 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM) 1218 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id = 1219 OD8_TEMPERATURE_SYSTEM; 1220 else 1221 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id = 1222 0; 1223 1224 return 0; 1225 } 1226 1227 static int vega20_od8_get_gfx_clock_base_voltage( 1228 struct pp_hwmgr *hwmgr, 1229 uint32_t *voltage, 1230 uint32_t freq) 1231 { 1232 int ret = 0; 1233 1234 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1235 PPSMC_MSG_GetAVFSVoltageByDpm, 1236 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq), 1237 voltage); 1238 PP_ASSERT_WITH_CODE(!ret, 1239 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!", 1240 return ret); 1241 1242 *voltage = *voltage / VOLTAGE_SCALE; 1243 1244 return 0; 1245 } 1246 1247 static int vega20_od8_initialize_default_settings( 1248 struct pp_hwmgr *hwmgr) 1249 { 1250 struct phm_ppt_v3_information *pptable_information = 1251 (struct phm_ppt_v3_information *)hwmgr->pptable; 1252 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1253 struct vega20_od8_settings *od8_settings = &(data->od8_settings); 1254 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); 1255 int i, ret = 0; 1256 1257 /* Set Feature Capabilities */ 1258 vega20_od8_set_feature_capabilities(hwmgr); 1259 1260 /* Map FeatureID to individual settings */ 1261 vega20_od8_set_feature_id(hwmgr); 1262 1263 /* Set default values */ 1264 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true); 1265 PP_ASSERT_WITH_CODE(!ret, 1266 "Failed to export over drive table!", 1267 return ret); 1268 1269 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) { 1270 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value = 1271 od_table->GfxclkFmin; 1272 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value = 1273 od_table->GfxclkFmax; 1274 } else { 1275 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value = 1276 0; 1277 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value = 1278 0; 1279 } 1280 1281 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) { 1282 od_table->GfxclkFreq1 = od_table->GfxclkFmin; 1283 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value = 1284 od_table->GfxclkFreq1; 1285 1286 od_table->GfxclkFreq3 = od_table->GfxclkFmax; 1287 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value = 1288 od_table->GfxclkFreq3; 1289 1290 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2; 1291 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value = 1292 od_table->GfxclkFreq2; 1293 1294 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, 1295 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value), 1296 od_table->GfxclkFreq1), 1297 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", 1298 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0); 1299 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value 1300 * VOLTAGE_SCALE; 1301 1302 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, 1303 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value), 1304 od_table->GfxclkFreq2), 1305 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", 1306 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0); 1307 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value 1308 * VOLTAGE_SCALE; 1309 1310 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, 1311 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value), 1312 od_table->GfxclkFreq3), 1313 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", 1314 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0); 1315 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value 1316 * VOLTAGE_SCALE; 1317 } else { 1318 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value = 1319 0; 1320 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 1321 0; 1322 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value = 1323 0; 1324 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 1325 0; 1326 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value = 1327 0; 1328 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 1329 0; 1330 } 1331 1332 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX) 1333 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value = 1334 od_table->UclkFmax; 1335 else 1336 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value = 1337 0; 1338 1339 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT) 1340 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value = 1341 od_table->OverDrivePct; 1342 else 1343 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value = 1344 0; 1345 1346 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK) 1347 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value = 1348 od_table->FanMaximumRpm; 1349 else 1350 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value = 1351 0; 1352 1353 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN) 1354 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value = 1355 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100; 1356 else 1357 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value = 1358 0; 1359 1360 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN) 1361 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value = 1362 od_table->FanTargetTemperature; 1363 else 1364 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value = 1365 0; 1366 1367 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM) 1368 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value = 1369 od_table->MaxOpTemp; 1370 else 1371 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value = 1372 0; 1373 1374 for (i = 0; i < OD8_SETTING_COUNT; i++) { 1375 if (od8_settings->od8_settings_array[i].feature_id) { 1376 od8_settings->od8_settings_array[i].min_value = 1377 pptable_information->od_settings_min[i]; 1378 od8_settings->od8_settings_array[i].max_value = 1379 pptable_information->od_settings_max[i]; 1380 od8_settings->od8_settings_array[i].current_value = 1381 od8_settings->od8_settings_array[i].default_value; 1382 } else { 1383 od8_settings->od8_settings_array[i].min_value = 1384 0; 1385 od8_settings->od8_settings_array[i].max_value = 1386 0; 1387 od8_settings->od8_settings_array[i].current_value = 1388 0; 1389 } 1390 } 1391 1392 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false); 1393 PP_ASSERT_WITH_CODE(!ret, 1394 "Failed to import over drive table!", 1395 return ret); 1396 1397 return 0; 1398 } 1399 1400 static int vega20_od8_set_settings( 1401 struct pp_hwmgr *hwmgr, 1402 uint32_t index, 1403 uint32_t value) 1404 { 1405 OverDriveTable_t od_table; 1406 int ret = 0; 1407 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1408 struct vega20_od8_single_setting *od8_settings = 1409 data->od8_settings.od8_settings_array; 1410 1411 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true); 1412 PP_ASSERT_WITH_CODE(!ret, 1413 "Failed to export over drive table!", 1414 return ret); 1415 1416 switch (index) { 1417 case OD8_SETTING_GFXCLK_FMIN: 1418 od_table.GfxclkFmin = (uint16_t)value; 1419 break; 1420 case OD8_SETTING_GFXCLK_FMAX: 1421 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value || 1422 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) 1423 return -EINVAL; 1424 1425 od_table.GfxclkFmax = (uint16_t)value; 1426 break; 1427 case OD8_SETTING_GFXCLK_FREQ1: 1428 od_table.GfxclkFreq1 = (uint16_t)value; 1429 break; 1430 case OD8_SETTING_GFXCLK_VOLTAGE1: 1431 od_table.GfxclkVolt1 = (uint16_t)value; 1432 break; 1433 case OD8_SETTING_GFXCLK_FREQ2: 1434 od_table.GfxclkFreq2 = (uint16_t)value; 1435 break; 1436 case OD8_SETTING_GFXCLK_VOLTAGE2: 1437 od_table.GfxclkVolt2 = (uint16_t)value; 1438 break; 1439 case OD8_SETTING_GFXCLK_FREQ3: 1440 od_table.GfxclkFreq3 = (uint16_t)value; 1441 break; 1442 case OD8_SETTING_GFXCLK_VOLTAGE3: 1443 od_table.GfxclkVolt3 = (uint16_t)value; 1444 break; 1445 case OD8_SETTING_UCLK_FMAX: 1446 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value || 1447 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) 1448 return -EINVAL; 1449 od_table.UclkFmax = (uint16_t)value; 1450 break; 1451 case OD8_SETTING_POWER_PERCENTAGE: 1452 od_table.OverDrivePct = (int16_t)value; 1453 break; 1454 case OD8_SETTING_FAN_ACOUSTIC_LIMIT: 1455 od_table.FanMaximumRpm = (uint16_t)value; 1456 break; 1457 case OD8_SETTING_FAN_MIN_SPEED: 1458 od_table.FanMinimumPwm = (uint16_t)value; 1459 break; 1460 case OD8_SETTING_FAN_TARGET_TEMP: 1461 od_table.FanTargetTemperature = (uint16_t)value; 1462 break; 1463 case OD8_SETTING_OPERATING_TEMP_MAX: 1464 od_table.MaxOpTemp = (uint16_t)value; 1465 break; 1466 } 1467 1468 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false); 1469 PP_ASSERT_WITH_CODE(!ret, 1470 "Failed to import over drive table!", 1471 return ret); 1472 1473 return 0; 1474 } 1475 1476 static int vega20_get_sclk_od( 1477 struct pp_hwmgr *hwmgr) 1478 { 1479 struct vega20_hwmgr *data = hwmgr->backend; 1480 struct vega20_single_dpm_table *sclk_table = 1481 &(data->dpm_table.gfx_table); 1482 struct vega20_single_dpm_table *golden_sclk_table = 1483 &(data->golden_dpm_table.gfx_table); 1484 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 1485 int golden_value = golden_sclk_table->dpm_levels 1486 [golden_sclk_table->count - 1].value; 1487 1488 /* od percentage */ 1489 value -= golden_value; 1490 value = DIV_ROUND_UP(value * 100, golden_value); 1491 1492 return value; 1493 } 1494 1495 static int vega20_set_sclk_od( 1496 struct pp_hwmgr *hwmgr, uint32_t value) 1497 { 1498 struct vega20_hwmgr *data = hwmgr->backend; 1499 struct vega20_single_dpm_table *golden_sclk_table = 1500 &(data->golden_dpm_table.gfx_table); 1501 uint32_t od_sclk; 1502 int ret = 0; 1503 1504 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value; 1505 od_sclk /= 100; 1506 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 1507 1508 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk); 1509 PP_ASSERT_WITH_CODE(!ret, 1510 "[SetSclkOD] failed to set od gfxclk!", 1511 return ret); 1512 1513 /* retrieve updated gfxclk table */ 1514 ret = vega20_setup_gfxclk_dpm_table(hwmgr); 1515 PP_ASSERT_WITH_CODE(!ret, 1516 "[SetSclkOD] failed to refresh gfxclk table!", 1517 return ret); 1518 1519 return 0; 1520 } 1521 1522 static int vega20_get_mclk_od( 1523 struct pp_hwmgr *hwmgr) 1524 { 1525 struct vega20_hwmgr *data = hwmgr->backend; 1526 struct vega20_single_dpm_table *mclk_table = 1527 &(data->dpm_table.mem_table); 1528 struct vega20_single_dpm_table *golden_mclk_table = 1529 &(data->golden_dpm_table.mem_table); 1530 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 1531 int golden_value = golden_mclk_table->dpm_levels 1532 [golden_mclk_table->count - 1].value; 1533 1534 /* od percentage */ 1535 value -= golden_value; 1536 value = DIV_ROUND_UP(value * 100, golden_value); 1537 1538 return value; 1539 } 1540 1541 static int vega20_set_mclk_od( 1542 struct pp_hwmgr *hwmgr, uint32_t value) 1543 { 1544 struct vega20_hwmgr *data = hwmgr->backend; 1545 struct vega20_single_dpm_table *golden_mclk_table = 1546 &(data->golden_dpm_table.mem_table); 1547 uint32_t od_mclk; 1548 int ret = 0; 1549 1550 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value; 1551 od_mclk /= 100; 1552 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 1553 1554 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk); 1555 PP_ASSERT_WITH_CODE(!ret, 1556 "[SetMclkOD] failed to set od memclk!", 1557 return ret); 1558 1559 /* retrieve updated memclk table */ 1560 ret = vega20_setup_memclk_dpm_table(hwmgr); 1561 PP_ASSERT_WITH_CODE(!ret, 1562 "[SetMclkOD] failed to refresh memclk table!", 1563 return ret); 1564 1565 return 0; 1566 } 1567 1568 static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1569 { 1570 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1571 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); 1572 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); 1573 1574 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && 1575 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) { 1576 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 1577 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 1578 } else { 1579 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; 1580 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; 1581 } 1582 1583 hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value; 1584 hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value; 1585 } 1586 1587 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, 1588 PP_Clock *clock, PPCLK_e clock_select) 1589 { 1590 int ret = 0; 1591 1592 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1593 PPSMC_MSG_GetDcModeMaxDpmFreq, 1594 (clock_select << 16), 1595 clock)) == 0, 1596 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!", 1597 return ret); 1598 1599 /* if DC limit is zero, return AC limit */ 1600 if (*clock == 0) { 1601 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1602 PPSMC_MSG_GetMaxDpmFreq, 1603 (clock_select << 16), 1604 clock)) == 0, 1605 "[GetMaxSustainableClock] failed to get max AC clock from SMC!", 1606 return ret); 1607 } 1608 1609 return 0; 1610 } 1611 1612 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr) 1613 { 1614 struct vega20_hwmgr *data = 1615 (struct vega20_hwmgr *)(hwmgr->backend); 1616 struct vega20_max_sustainable_clocks *max_sustainable_clocks = 1617 &(data->max_sustainable_clocks); 1618 int ret = 0; 1619 1620 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100; 1621 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100; 1622 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100; 1623 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 1624 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 1625 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 1626 1627 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1628 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1629 &(max_sustainable_clocks->uclock), 1630 PPCLK_UCLK)) == 0, 1631 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!", 1632 return ret); 1633 1634 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) 1635 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1636 &(max_sustainable_clocks->soc_clock), 1637 PPCLK_SOCCLK)) == 0, 1638 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!", 1639 return ret); 1640 1641 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1642 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1643 &(max_sustainable_clocks->dcef_clock), 1644 PPCLK_DCEFCLK)) == 0, 1645 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!", 1646 return ret); 1647 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1648 &(max_sustainable_clocks->display_clock), 1649 PPCLK_DISPCLK)) == 0, 1650 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!", 1651 return ret); 1652 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1653 &(max_sustainable_clocks->phy_clock), 1654 PPCLK_PHYCLK)) == 0, 1655 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!", 1656 return ret); 1657 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1658 &(max_sustainable_clocks->pixel_clock), 1659 PPCLK_PIXCLK)) == 0, 1660 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!", 1661 return ret); 1662 } 1663 1664 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 1665 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 1666 1667 return 0; 1668 } 1669 1670 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) 1671 { 1672 int result; 1673 1674 result = smum_send_msg_to_smc(hwmgr, 1675 PPSMC_MSG_SetMGpuFanBoostLimitRpm, 1676 NULL); 1677 PP_ASSERT_WITH_CODE(!result, 1678 "[EnableMgpuFan] Failed to enable mgpu fan boost!", 1679 return result); 1680 1681 return 0; 1682 } 1683 1684 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) 1685 { 1686 struct vega20_hwmgr *data = 1687 (struct vega20_hwmgr *)(hwmgr->backend); 1688 1689 data->uvd_power_gated = true; 1690 data->vce_power_gated = true; 1691 } 1692 1693 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1694 { 1695 int result = 0; 1696 1697 smum_send_msg_to_smc_with_parameter(hwmgr, 1698 PPSMC_MSG_NumOfDisplays, 0, NULL); 1699 1700 result = vega20_set_allowed_featuresmask(hwmgr); 1701 PP_ASSERT_WITH_CODE(!result, 1702 "[EnableDPMTasks] Failed to set allowed featuresmask!\n", 1703 return result); 1704 1705 result = vega20_init_smc_table(hwmgr); 1706 PP_ASSERT_WITH_CODE(!result, 1707 "[EnableDPMTasks] Failed to initialize SMC table!", 1708 return result); 1709 1710 result = vega20_run_btc(hwmgr); 1711 PP_ASSERT_WITH_CODE(!result, 1712 "[EnableDPMTasks] Failed to run btc!", 1713 return result); 1714 1715 result = vega20_run_btc_afll(hwmgr); 1716 PP_ASSERT_WITH_CODE(!result, 1717 "[EnableDPMTasks] Failed to run btc afll!", 1718 return result); 1719 1720 result = vega20_enable_all_smu_features(hwmgr); 1721 PP_ASSERT_WITH_CODE(!result, 1722 "[EnableDPMTasks] Failed to enable all smu features!", 1723 return result); 1724 1725 result = vega20_override_pcie_parameters(hwmgr); 1726 PP_ASSERT_WITH_CODE(!result, 1727 "[EnableDPMTasks] Failed to override pcie parameters!", 1728 return result); 1729 1730 result = vega20_notify_smc_display_change(hwmgr); 1731 PP_ASSERT_WITH_CODE(!result, 1732 "[EnableDPMTasks] Failed to notify smc display change!", 1733 return result); 1734 1735 result = vega20_send_clock_ratio(hwmgr); 1736 PP_ASSERT_WITH_CODE(!result, 1737 "[EnableDPMTasks] Failed to send clock ratio!", 1738 return result); 1739 1740 /* Initialize UVD/VCE powergating state */ 1741 vega20_init_powergate_state(hwmgr); 1742 1743 result = vega20_setup_default_dpm_tables(hwmgr); 1744 PP_ASSERT_WITH_CODE(!result, 1745 "[EnableDPMTasks] Failed to setup default DPM tables!", 1746 return result); 1747 1748 result = vega20_init_max_sustainable_clocks(hwmgr); 1749 PP_ASSERT_WITH_CODE(!result, 1750 "[EnableDPMTasks] Failed to get maximum sustainable clocks!", 1751 return result); 1752 1753 result = vega20_power_control_set_level(hwmgr); 1754 PP_ASSERT_WITH_CODE(!result, 1755 "[EnableDPMTasks] Failed to power control set level!", 1756 return result); 1757 1758 result = vega20_od8_initialize_default_settings(hwmgr); 1759 PP_ASSERT_WITH_CODE(!result, 1760 "[EnableDPMTasks] Failed to initialize odn settings!", 1761 return result); 1762 1763 vega20_populate_umdpstate_clocks(hwmgr); 1764 1765 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit, 1766 POWER_SOURCE_AC << 16, &hwmgr->default_power_limit); 1767 PP_ASSERT_WITH_CODE(!result, 1768 "[GetPptLimit] get default PPT limit failed!", 1769 return result); 1770 hwmgr->power_limit = 1771 hwmgr->default_power_limit; 1772 1773 return 0; 1774 } 1775 1776 static uint32_t vega20_find_lowest_dpm_level( 1777 struct vega20_single_dpm_table *table) 1778 { 1779 uint32_t i; 1780 1781 for (i = 0; i < table->count; i++) { 1782 if (table->dpm_levels[i].enabled) 1783 break; 1784 } 1785 if (i >= table->count) { 1786 i = 0; 1787 table->dpm_levels[i].enabled = true; 1788 } 1789 1790 return i; 1791 } 1792 1793 static uint32_t vega20_find_highest_dpm_level( 1794 struct vega20_single_dpm_table *table) 1795 { 1796 int i = 0; 1797 1798 PP_ASSERT_WITH_CODE(table != NULL, 1799 "[FindHighestDPMLevel] DPM Table does not exist!", 1800 return 0); 1801 PP_ASSERT_WITH_CODE(table->count > 0, 1802 "[FindHighestDPMLevel] DPM Table has no entry!", 1803 return 0); 1804 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, 1805 "[FindHighestDPMLevel] DPM Table has too many entries!", 1806 return MAX_REGULAR_DPM_NUMBER - 1); 1807 1808 for (i = table->count - 1; i >= 0; i--) { 1809 if (table->dpm_levels[i].enabled) 1810 break; 1811 } 1812 if (i < 0) { 1813 i = 0; 1814 table->dpm_levels[i].enabled = true; 1815 } 1816 1817 return i; 1818 } 1819 1820 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) 1821 { 1822 struct vega20_hwmgr *data = 1823 (struct vega20_hwmgr *)(hwmgr->backend); 1824 uint32_t min_freq; 1825 int ret = 0; 1826 1827 if (data->smu_features[GNLD_DPM_GFXCLK].enabled && 1828 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 1829 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1830 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1831 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1832 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), 1833 NULL)), 1834 "Failed to set soft min gfxclk !", 1835 return ret); 1836 } 1837 1838 if (data->smu_features[GNLD_DPM_UCLK].enabled && 1839 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 1840 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1841 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1842 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1843 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1844 NULL)), 1845 "Failed to set soft min memclk !", 1846 return ret); 1847 } 1848 1849 if (data->smu_features[GNLD_DPM_UVD].enabled && 1850 (feature_mask & FEATURE_DPM_UVD_MASK)) { 1851 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1852 1853 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1854 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1855 (PPCLK_VCLK << 16) | (min_freq & 0xffff), 1856 NULL)), 1857 "Failed to set soft min vclk!", 1858 return ret); 1859 1860 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1861 1862 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1863 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1864 (PPCLK_DCLK << 16) | (min_freq & 0xffff), 1865 NULL)), 1866 "Failed to set soft min dclk!", 1867 return ret); 1868 } 1869 1870 if (data->smu_features[GNLD_DPM_VCE].enabled && 1871 (feature_mask & FEATURE_DPM_VCE_MASK)) { 1872 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1873 1874 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1875 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1876 (PPCLK_ECLK << 16) | (min_freq & 0xffff), 1877 NULL)), 1878 "Failed to set soft min eclk!", 1879 return ret); 1880 } 1881 1882 if (data->smu_features[GNLD_DPM_SOCCLK].enabled && 1883 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 1884 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1885 1886 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1887 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1888 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), 1889 NULL)), 1890 "Failed to set soft min socclk!", 1891 return ret); 1892 } 1893 1894 if (data->smu_features[GNLD_DPM_FCLK].enabled && 1895 (feature_mask & FEATURE_DPM_FCLK_MASK)) { 1896 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level; 1897 1898 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1899 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1900 (PPCLK_FCLK << 16) | (min_freq & 0xffff), 1901 NULL)), 1902 "Failed to set soft min fclk!", 1903 return ret); 1904 } 1905 1906 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled && 1907 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) { 1908 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; 1909 1910 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1911 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1912 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), 1913 NULL)), 1914 "Failed to set hard min dcefclk!", 1915 return ret); 1916 } 1917 1918 return ret; 1919 } 1920 1921 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) 1922 { 1923 struct vega20_hwmgr *data = 1924 (struct vega20_hwmgr *)(hwmgr->backend); 1925 uint32_t max_freq; 1926 int ret = 0; 1927 1928 if (data->smu_features[GNLD_DPM_GFXCLK].enabled && 1929 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 1930 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1931 1932 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1933 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1934 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), 1935 NULL)), 1936 "Failed to set soft max gfxclk!", 1937 return ret); 1938 } 1939 1940 if (data->smu_features[GNLD_DPM_UCLK].enabled && 1941 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 1942 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1943 1944 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1945 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1946 (PPCLK_UCLK << 16) | (max_freq & 0xffff), 1947 NULL)), 1948 "Failed to set soft max memclk!", 1949 return ret); 1950 } 1951 1952 if (data->smu_features[GNLD_DPM_UVD].enabled && 1953 (feature_mask & FEATURE_DPM_UVD_MASK)) { 1954 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1955 1956 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1957 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1958 (PPCLK_VCLK << 16) | (max_freq & 0xffff), 1959 NULL)), 1960 "Failed to set soft max vclk!", 1961 return ret); 1962 1963 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1964 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1965 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1966 (PPCLK_DCLK << 16) | (max_freq & 0xffff), 1967 NULL)), 1968 "Failed to set soft max dclk!", 1969 return ret); 1970 } 1971 1972 if (data->smu_features[GNLD_DPM_VCE].enabled && 1973 (feature_mask & FEATURE_DPM_VCE_MASK)) { 1974 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1975 1976 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1977 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1978 (PPCLK_ECLK << 16) | (max_freq & 0xffff), 1979 NULL)), 1980 "Failed to set soft max eclk!", 1981 return ret); 1982 } 1983 1984 if (data->smu_features[GNLD_DPM_SOCCLK].enabled && 1985 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 1986 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1987 1988 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1989 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1990 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), 1991 NULL)), 1992 "Failed to set soft max socclk!", 1993 return ret); 1994 } 1995 1996 if (data->smu_features[GNLD_DPM_FCLK].enabled && 1997 (feature_mask & FEATURE_DPM_FCLK_MASK)) { 1998 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level; 1999 2000 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 2001 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 2002 (PPCLK_FCLK << 16) | (max_freq & 0xffff), 2003 NULL)), 2004 "Failed to set soft max fclk!", 2005 return ret); 2006 } 2007 2008 return ret; 2009 } 2010 2011 static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 2012 { 2013 struct vega20_hwmgr *data = 2014 (struct vega20_hwmgr *)(hwmgr->backend); 2015 int ret = 0; 2016 2017 if (data->smu_features[GNLD_DPM_VCE].supported) { 2018 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) { 2019 if (enable) 2020 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n"); 2021 else 2022 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n"); 2023 } 2024 2025 ret = vega20_enable_smc_features(hwmgr, 2026 enable, 2027 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap); 2028 PP_ASSERT_WITH_CODE(!ret, 2029 "Attempt to Enable/Disable DPM VCE Failed!", 2030 return ret); 2031 data->smu_features[GNLD_DPM_VCE].enabled = enable; 2032 } 2033 2034 return 0; 2035 } 2036 2037 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr, 2038 uint32_t *clock, 2039 PPCLK_e clock_select, 2040 bool max) 2041 { 2042 int ret; 2043 *clock = 0; 2044 2045 if (max) { 2046 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2047 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16), 2048 clock)) == 0, 2049 "[GetClockRanges] Failed to get max clock from SMC!", 2050 return ret); 2051 } else { 2052 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2053 PPSMC_MSG_GetMinDpmFreq, 2054 (clock_select << 16), 2055 clock)) == 0, 2056 "[GetClockRanges] Failed to get min clock from SMC!", 2057 return ret); 2058 } 2059 2060 return 0; 2061 } 2062 2063 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 2064 { 2065 struct vega20_hwmgr *data = 2066 (struct vega20_hwmgr *)(hwmgr->backend); 2067 uint32_t gfx_clk; 2068 int ret = 0; 2069 2070 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled, 2071 "[GetSclks]: gfxclk dpm not enabled!\n", 2072 return -EPERM); 2073 2074 if (low) { 2075 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false); 2076 PP_ASSERT_WITH_CODE(!ret, 2077 "[GetSclks]: fail to get min PPCLK_GFXCLK\n", 2078 return ret); 2079 } else { 2080 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true); 2081 PP_ASSERT_WITH_CODE(!ret, 2082 "[GetSclks]: fail to get max PPCLK_GFXCLK\n", 2083 return ret); 2084 } 2085 2086 return (gfx_clk * 100); 2087 } 2088 2089 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 2090 { 2091 struct vega20_hwmgr *data = 2092 (struct vega20_hwmgr *)(hwmgr->backend); 2093 uint32_t mem_clk; 2094 int ret = 0; 2095 2096 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled, 2097 "[MemMclks]: memclk dpm not enabled!\n", 2098 return -EPERM); 2099 2100 if (low) { 2101 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false); 2102 PP_ASSERT_WITH_CODE(!ret, 2103 "[GetMclks]: fail to get min PPCLK_UCLK\n", 2104 return ret); 2105 } else { 2106 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true); 2107 PP_ASSERT_WITH_CODE(!ret, 2108 "[GetMclks]: fail to get max PPCLK_UCLK\n", 2109 return ret); 2110 } 2111 2112 return (mem_clk * 100); 2113 } 2114 2115 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, 2116 SmuMetrics_t *metrics_table, 2117 bool bypass_cache) 2118 { 2119 struct vega20_hwmgr *data = 2120 (struct vega20_hwmgr *)(hwmgr->backend); 2121 int ret = 0; 2122 2123 if (bypass_cache || 2124 !data->metrics_time || 2125 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { 2126 ret = smum_smc_table_manager(hwmgr, 2127 (uint8_t *)(&data->metrics_table), 2128 TABLE_SMU_METRICS, 2129 true); 2130 if (ret) { 2131 pr_info("Failed to export SMU metrics table!\n"); 2132 return ret; 2133 } 2134 data->metrics_time = jiffies; 2135 } 2136 2137 if (metrics_table) 2138 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); 2139 2140 return ret; 2141 } 2142 2143 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, int idx, 2144 uint32_t *query) 2145 { 2146 int ret = 0; 2147 SmuMetrics_t metrics_table; 2148 2149 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2150 if (ret) 2151 return ret; 2152 2153 /* For the 40.46 release, they changed the value name */ 2154 switch (idx) { 2155 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 2156 if (hwmgr->smu_version == 0x282e00) 2157 *query = metrics_table.AverageSocketPower << 8; 2158 else 2159 ret = -EOPNOTSUPP; 2160 break; 2161 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2162 *query = metrics_table.CurrSocketPower << 8; 2163 break; 2164 } 2165 2166 return ret; 2167 } 2168 2169 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr, 2170 PPCLK_e clk_id, uint32_t *clk_freq) 2171 { 2172 int ret = 0; 2173 2174 *clk_freq = 0; 2175 2176 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2177 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16), 2178 clk_freq)) == 0, 2179 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!", 2180 return ret); 2181 2182 *clk_freq = *clk_freq * 100; 2183 2184 return 0; 2185 } 2186 2187 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr, 2188 int idx, 2189 uint32_t *activity_percent) 2190 { 2191 int ret = 0; 2192 SmuMetrics_t metrics_table; 2193 2194 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2195 if (ret) 2196 return ret; 2197 2198 switch (idx) { 2199 case AMDGPU_PP_SENSOR_GPU_LOAD: 2200 *activity_percent = metrics_table.AverageGfxActivity; 2201 break; 2202 case AMDGPU_PP_SENSOR_MEM_LOAD: 2203 *activity_percent = metrics_table.AverageUclkActivity; 2204 break; 2205 default: 2206 pr_err("Invalid index for retrieving clock activity\n"); 2207 return -EINVAL; 2208 } 2209 2210 return ret; 2211 } 2212 2213 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, 2214 void *value, int *size) 2215 { 2216 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2217 struct amdgpu_device *adev = hwmgr->adev; 2218 SmuMetrics_t metrics_table; 2219 uint32_t val_vid; 2220 int ret = 0; 2221 2222 switch (idx) { 2223 case AMDGPU_PP_SENSOR_GFX_SCLK: 2224 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2225 if (ret) 2226 return ret; 2227 2228 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100; 2229 *size = 4; 2230 break; 2231 case AMDGPU_PP_SENSOR_GFX_MCLK: 2232 ret = vega20_get_current_clk_freq(hwmgr, 2233 PPCLK_UCLK, 2234 (uint32_t *)value); 2235 if (!ret) 2236 *size = 4; 2237 break; 2238 case AMDGPU_PP_SENSOR_GPU_LOAD: 2239 case AMDGPU_PP_SENSOR_MEM_LOAD: 2240 ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); 2241 if (!ret) 2242 *size = 4; 2243 break; 2244 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2245 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr); 2246 *size = 4; 2247 break; 2248 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2249 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2250 if (ret) 2251 return ret; 2252 2253 *((uint32_t *)value) = metrics_table.TemperatureEdge * 2254 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2255 *size = 4; 2256 break; 2257 case AMDGPU_PP_SENSOR_MEM_TEMP: 2258 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2259 if (ret) 2260 return ret; 2261 2262 *((uint32_t *)value) = metrics_table.TemperatureHBM * 2263 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2264 *size = 4; 2265 break; 2266 case AMDGPU_PP_SENSOR_UVD_POWER: 2267 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 2268 *size = 4; 2269 break; 2270 case AMDGPU_PP_SENSOR_VCE_POWER: 2271 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 2272 *size = 4; 2273 break; 2274 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 2275 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2276 *size = 16; 2277 ret = vega20_get_gpu_power(hwmgr, idx, (uint32_t *)value); 2278 break; 2279 case AMDGPU_PP_SENSOR_VDDGFX: 2280 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & 2281 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 2282 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 2283 *((uint32_t *)value) = 2284 (uint32_t)convert_to_vddc((uint8_t)val_vid); 2285 break; 2286 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2287 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value); 2288 if (!ret) 2289 *size = 8; 2290 break; 2291 default: 2292 ret = -EOPNOTSUPP; 2293 break; 2294 } 2295 return ret; 2296 } 2297 2298 static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 2299 struct pp_display_clock_request *clock_req) 2300 { 2301 int result = 0; 2302 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2303 enum amd_pp_clock_type clk_type = clock_req->clock_type; 2304 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 2305 PPCLK_e clk_select = 0; 2306 uint32_t clk_request = 0; 2307 2308 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 2309 switch (clk_type) { 2310 case amd_pp_dcef_clock: 2311 clk_select = PPCLK_DCEFCLK; 2312 break; 2313 case amd_pp_disp_clock: 2314 clk_select = PPCLK_DISPCLK; 2315 break; 2316 case amd_pp_pixel_clock: 2317 clk_select = PPCLK_PIXCLK; 2318 break; 2319 case amd_pp_phy_clock: 2320 clk_select = PPCLK_PHYCLK; 2321 break; 2322 default: 2323 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 2324 result = -EINVAL; 2325 break; 2326 } 2327 2328 if (!result) { 2329 clk_request = (clk_select << 16) | clk_freq; 2330 result = smum_send_msg_to_smc_with_parameter(hwmgr, 2331 PPSMC_MSG_SetHardMinByFreq, 2332 clk_request, 2333 NULL); 2334 } 2335 } 2336 2337 return result; 2338 } 2339 2340 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 2341 PHM_PerformanceLevelDesignation designation, uint32_t index, 2342 PHM_PerformanceLevel *level) 2343 { 2344 return 0; 2345 } 2346 2347 static int vega20_notify_smc_display_config_after_ps_adjustment( 2348 struct pp_hwmgr *hwmgr) 2349 { 2350 struct vega20_hwmgr *data = 2351 (struct vega20_hwmgr *)(hwmgr->backend); 2352 struct vega20_single_dpm_table *dpm_table = 2353 &data->dpm_table.mem_table; 2354 struct PP_Clocks min_clocks = {0}; 2355 struct pp_display_clock_request clock_req; 2356 int ret = 0; 2357 2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 2361 2362 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { 2363 clock_req.clock_type = amd_pp_dcef_clock; 2364 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; 2365 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { 2366 if (data->smu_features[GNLD_DS_DCEFCLK].supported) 2367 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter( 2368 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 2369 min_clocks.dcefClockInSR / 100, 2370 NULL)) == 0, 2371 "Attempt to set divider for DCEFCLK Failed!", 2372 return ret); 2373 } else { 2374 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 2375 } 2376 } 2377 2378 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 2379 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; 2380 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2381 PPSMC_MSG_SetHardMinByFreq, 2382 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level, 2383 NULL)), 2384 "[SetHardMinFreq] Set hard min uclk failed!", 2385 return ret); 2386 } 2387 2388 return 0; 2389 } 2390 2391 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr) 2392 { 2393 struct vega20_hwmgr *data = 2394 (struct vega20_hwmgr *)(hwmgr->backend); 2395 uint32_t soft_level; 2396 int ret = 0; 2397 2398 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 2399 2400 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2401 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2402 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 2403 2404 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); 2405 2406 data->dpm_table.mem_table.dpm_state.soft_min_level = 2407 data->dpm_table.mem_table.dpm_state.soft_max_level = 2408 data->dpm_table.mem_table.dpm_levels[soft_level].value; 2409 2410 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); 2411 2412 data->dpm_table.soc_table.dpm_state.soft_min_level = 2413 data->dpm_table.soc_table.dpm_state.soft_max_level = 2414 data->dpm_table.soc_table.dpm_levels[soft_level].value; 2415 2416 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2417 FEATURE_DPM_UCLK_MASK | 2418 FEATURE_DPM_SOCCLK_MASK); 2419 PP_ASSERT_WITH_CODE(!ret, 2420 "Failed to upload boot level to highest!", 2421 return ret); 2422 2423 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2424 FEATURE_DPM_UCLK_MASK | 2425 FEATURE_DPM_SOCCLK_MASK); 2426 PP_ASSERT_WITH_CODE(!ret, 2427 "Failed to upload dpm max level to highest!", 2428 return ret); 2429 2430 return 0; 2431 } 2432 2433 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) 2434 { 2435 struct vega20_hwmgr *data = 2436 (struct vega20_hwmgr *)(hwmgr->backend); 2437 uint32_t soft_level; 2438 int ret = 0; 2439 2440 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 2441 2442 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2443 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2444 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 2445 2446 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 2447 2448 data->dpm_table.mem_table.dpm_state.soft_min_level = 2449 data->dpm_table.mem_table.dpm_state.soft_max_level = 2450 data->dpm_table.mem_table.dpm_levels[soft_level].value; 2451 2452 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 2453 2454 data->dpm_table.soc_table.dpm_state.soft_min_level = 2455 data->dpm_table.soc_table.dpm_state.soft_max_level = 2456 data->dpm_table.soc_table.dpm_levels[soft_level].value; 2457 2458 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2459 FEATURE_DPM_UCLK_MASK | 2460 FEATURE_DPM_SOCCLK_MASK); 2461 PP_ASSERT_WITH_CODE(!ret, 2462 "Failed to upload boot level to highest!", 2463 return ret); 2464 2465 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2466 FEATURE_DPM_UCLK_MASK | 2467 FEATURE_DPM_SOCCLK_MASK); 2468 PP_ASSERT_WITH_CODE(!ret, 2469 "Failed to upload dpm max level to highest!", 2470 return ret); 2471 2472 return 0; 2473 2474 } 2475 2476 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 2477 { 2478 struct vega20_hwmgr *data = 2479 (struct vega20_hwmgr *)(hwmgr->backend); 2480 uint32_t soft_min_level, soft_max_level; 2481 int ret = 0; 2482 2483 /* gfxclk soft min/max settings */ 2484 soft_min_level = 2485 vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 2486 soft_max_level = 2487 vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 2488 2489 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2490 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2491 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2492 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2493 2494 /* uclk soft min/max settings */ 2495 soft_min_level = 2496 vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 2497 soft_max_level = 2498 vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); 2499 2500 data->dpm_table.mem_table.dpm_state.soft_min_level = 2501 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2502 data->dpm_table.mem_table.dpm_state.soft_max_level = 2503 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2504 2505 /* socclk soft min/max settings */ 2506 soft_min_level = 2507 vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 2508 soft_max_level = 2509 vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); 2510 2511 data->dpm_table.soc_table.dpm_state.soft_min_level = 2512 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2513 data->dpm_table.soc_table.dpm_state.soft_max_level = 2514 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2515 2516 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2517 FEATURE_DPM_UCLK_MASK | 2518 FEATURE_DPM_SOCCLK_MASK); 2519 PP_ASSERT_WITH_CODE(!ret, 2520 "Failed to upload DPM Bootup Levels!", 2521 return ret); 2522 2523 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2524 FEATURE_DPM_UCLK_MASK | 2525 FEATURE_DPM_SOCCLK_MASK); 2526 PP_ASSERT_WITH_CODE(!ret, 2527 "Failed to upload DPM Max Levels!", 2528 return ret); 2529 2530 return 0; 2531 } 2532 2533 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 2534 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 2535 { 2536 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2537 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 2538 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 2539 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); 2540 2541 *sclk_mask = 0; 2542 *mclk_mask = 0; 2543 *soc_mask = 0; 2544 2545 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && 2546 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL && 2547 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) { 2548 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; 2549 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; 2550 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; 2551 } 2552 2553 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2554 *sclk_mask = 0; 2555 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 2556 *mclk_mask = 0; 2557 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2558 *sclk_mask = gfx_dpm_table->count - 1; 2559 *mclk_mask = mem_dpm_table->count - 1; 2560 *soc_mask = soc_dpm_table->count - 1; 2561 } 2562 2563 return 0; 2564 } 2565 2566 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, 2567 enum pp_clock_type type, uint32_t mask) 2568 { 2569 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2570 uint32_t soft_min_level, soft_max_level, hard_min_level; 2571 int ret = 0; 2572 2573 switch (type) { 2574 case PP_SCLK: 2575 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2576 soft_max_level = mask ? (fls(mask) - 1) : 0; 2577 2578 if (soft_max_level >= data->dpm_table.gfx_table.count) { 2579 pr_err("Clock level specified %d is over max allowed %d\n", 2580 soft_max_level, 2581 data->dpm_table.gfx_table.count - 1); 2582 return -EINVAL; 2583 } 2584 2585 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2586 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2587 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2588 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2589 2590 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK); 2591 PP_ASSERT_WITH_CODE(!ret, 2592 "Failed to upload boot level to lowest!", 2593 return ret); 2594 2595 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK); 2596 PP_ASSERT_WITH_CODE(!ret, 2597 "Failed to upload dpm max level to highest!", 2598 return ret); 2599 break; 2600 2601 case PP_MCLK: 2602 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2603 soft_max_level = mask ? (fls(mask) - 1) : 0; 2604 2605 if (soft_max_level >= data->dpm_table.mem_table.count) { 2606 pr_err("Clock level specified %d is over max allowed %d\n", 2607 soft_max_level, 2608 data->dpm_table.mem_table.count - 1); 2609 return -EINVAL; 2610 } 2611 2612 data->dpm_table.mem_table.dpm_state.soft_min_level = 2613 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2614 data->dpm_table.mem_table.dpm_state.soft_max_level = 2615 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2616 2617 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK); 2618 PP_ASSERT_WITH_CODE(!ret, 2619 "Failed to upload boot level to lowest!", 2620 return ret); 2621 2622 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK); 2623 PP_ASSERT_WITH_CODE(!ret, 2624 "Failed to upload dpm max level to highest!", 2625 return ret); 2626 2627 break; 2628 2629 case PP_SOCCLK: 2630 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2631 soft_max_level = mask ? (fls(mask) - 1) : 0; 2632 2633 if (soft_max_level >= data->dpm_table.soc_table.count) { 2634 pr_err("Clock level specified %d is over max allowed %d\n", 2635 soft_max_level, 2636 data->dpm_table.soc_table.count - 1); 2637 return -EINVAL; 2638 } 2639 2640 data->dpm_table.soc_table.dpm_state.soft_min_level = 2641 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2642 data->dpm_table.soc_table.dpm_state.soft_max_level = 2643 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2644 2645 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK); 2646 PP_ASSERT_WITH_CODE(!ret, 2647 "Failed to upload boot level to lowest!", 2648 return ret); 2649 2650 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK); 2651 PP_ASSERT_WITH_CODE(!ret, 2652 "Failed to upload dpm max level to highest!", 2653 return ret); 2654 2655 break; 2656 2657 case PP_FCLK: 2658 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2659 soft_max_level = mask ? (fls(mask) - 1) : 0; 2660 2661 if (soft_max_level >= data->dpm_table.fclk_table.count) { 2662 pr_err("Clock level specified %d is over max allowed %d\n", 2663 soft_max_level, 2664 data->dpm_table.fclk_table.count - 1); 2665 return -EINVAL; 2666 } 2667 2668 data->dpm_table.fclk_table.dpm_state.soft_min_level = 2669 data->dpm_table.fclk_table.dpm_levels[soft_min_level].value; 2670 data->dpm_table.fclk_table.dpm_state.soft_max_level = 2671 data->dpm_table.fclk_table.dpm_levels[soft_max_level].value; 2672 2673 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK); 2674 PP_ASSERT_WITH_CODE(!ret, 2675 "Failed to upload boot level to lowest!", 2676 return ret); 2677 2678 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK); 2679 PP_ASSERT_WITH_CODE(!ret, 2680 "Failed to upload dpm max level to highest!", 2681 return ret); 2682 2683 break; 2684 2685 case PP_DCEFCLK: 2686 hard_min_level = mask ? (ffs(mask) - 1) : 0; 2687 2688 if (hard_min_level >= data->dpm_table.dcef_table.count) { 2689 pr_err("Clock level specified %d is over max allowed %d\n", 2690 hard_min_level, 2691 data->dpm_table.dcef_table.count - 1); 2692 return -EINVAL; 2693 } 2694 2695 data->dpm_table.dcef_table.dpm_state.hard_min_level = 2696 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; 2697 2698 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK); 2699 PP_ASSERT_WITH_CODE(!ret, 2700 "Failed to upload boot level to lowest!", 2701 return ret); 2702 2703 //TODO: Setting DCEFCLK max dpm level is not supported 2704 2705 break; 2706 2707 case PP_PCIE: 2708 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2709 soft_max_level = mask ? (fls(mask) - 1) : 0; 2710 if (soft_min_level >= NUM_LINK_LEVELS || 2711 soft_max_level >= NUM_LINK_LEVELS) 2712 return -EINVAL; 2713 2714 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2715 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level, 2716 NULL); 2717 PP_ASSERT_WITH_CODE(!ret, 2718 "Failed to set min link dpm level!", 2719 return ret); 2720 2721 break; 2722 2723 default: 2724 break; 2725 } 2726 2727 return 0; 2728 } 2729 2730 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 2731 enum amd_dpm_forced_level level) 2732 { 2733 int ret = 0; 2734 uint32_t sclk_mask, mclk_mask, soc_mask; 2735 2736 switch (level) { 2737 case AMD_DPM_FORCED_LEVEL_HIGH: 2738 ret = vega20_force_dpm_highest(hwmgr); 2739 break; 2740 2741 case AMD_DPM_FORCED_LEVEL_LOW: 2742 ret = vega20_force_dpm_lowest(hwmgr); 2743 break; 2744 2745 case AMD_DPM_FORCED_LEVEL_AUTO: 2746 ret = vega20_unforce_dpm_levels(hwmgr); 2747 break; 2748 2749 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 2750 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 2751 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 2752 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 2753 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 2754 if (ret) 2755 return ret; 2756 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 2757 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); 2758 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); 2759 break; 2760 2761 case AMD_DPM_FORCED_LEVEL_MANUAL: 2762 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 2763 default: 2764 break; 2765 } 2766 2767 return ret; 2768 } 2769 2770 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr) 2771 { 2772 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2773 2774 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 2775 return AMD_FAN_CTRL_MANUAL; 2776 else 2777 return AMD_FAN_CTRL_AUTO; 2778 } 2779 2780 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 2781 { 2782 switch (mode) { 2783 case AMD_FAN_CTRL_NONE: 2784 vega20_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 2785 break; 2786 case AMD_FAN_CTRL_MANUAL: 2787 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 2788 vega20_fan_ctrl_stop_smc_fan_control(hwmgr); 2789 break; 2790 case AMD_FAN_CTRL_AUTO: 2791 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 2792 vega20_fan_ctrl_start_smc_fan_control(hwmgr); 2793 break; 2794 default: 2795 break; 2796 } 2797 } 2798 2799 static int vega20_get_sclks(struct pp_hwmgr *hwmgr, 2800 struct pp_clock_levels_with_latency *clocks) 2801 { 2802 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2803 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 2804 int i, count; 2805 2806 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 2807 return -1; 2808 2809 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2810 clocks->num_levels = count; 2811 2812 for (i = 0; i < count; i++) { 2813 clocks->data[i].clocks_in_khz = 2814 dpm_table->dpm_levels[i].value * 1000; 2815 clocks->data[i].latency_in_us = 0; 2816 } 2817 2818 return 0; 2819 } 2820 2821 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr, 2822 uint32_t clock) 2823 { 2824 return 25; 2825 } 2826 2827 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr, 2828 struct pp_clock_levels_with_latency *clocks) 2829 { 2830 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2831 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); 2832 int i, count; 2833 2834 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 2835 return -1; 2836 2837 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2838 clocks->num_levels = data->mclk_latency_table.count = count; 2839 2840 for (i = 0; i < count; i++) { 2841 clocks->data[i].clocks_in_khz = 2842 data->mclk_latency_table.entries[i].frequency = 2843 dpm_table->dpm_levels[i].value * 1000; 2844 clocks->data[i].latency_in_us = 2845 data->mclk_latency_table.entries[i].latency = 2846 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); 2847 } 2848 2849 return 0; 2850 } 2851 2852 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr, 2853 struct pp_clock_levels_with_latency *clocks) 2854 { 2855 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2856 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); 2857 int i, count; 2858 2859 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) 2860 return -1; 2861 2862 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2863 clocks->num_levels = count; 2864 2865 for (i = 0; i < count; i++) { 2866 clocks->data[i].clocks_in_khz = 2867 dpm_table->dpm_levels[i].value * 1000; 2868 clocks->data[i].latency_in_us = 0; 2869 } 2870 2871 return 0; 2872 } 2873 2874 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr, 2875 struct pp_clock_levels_with_latency *clocks) 2876 { 2877 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2878 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); 2879 int i, count; 2880 2881 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) 2882 return -1; 2883 2884 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2885 clocks->num_levels = count; 2886 2887 for (i = 0; i < count; i++) { 2888 clocks->data[i].clocks_in_khz = 2889 dpm_table->dpm_levels[i].value * 1000; 2890 clocks->data[i].latency_in_us = 0; 2891 } 2892 2893 return 0; 2894 2895 } 2896 2897 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 2898 enum amd_pp_clock_type type, 2899 struct pp_clock_levels_with_latency *clocks) 2900 { 2901 int ret; 2902 2903 switch (type) { 2904 case amd_pp_sys_clock: 2905 ret = vega20_get_sclks(hwmgr, clocks); 2906 break; 2907 case amd_pp_mem_clock: 2908 ret = vega20_get_memclocks(hwmgr, clocks); 2909 break; 2910 case amd_pp_dcef_clock: 2911 ret = vega20_get_dcefclocks(hwmgr, clocks); 2912 break; 2913 case amd_pp_soc_clock: 2914 ret = vega20_get_socclocks(hwmgr, clocks); 2915 break; 2916 default: 2917 return -EINVAL; 2918 } 2919 2920 return ret; 2921 } 2922 2923 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 2924 enum amd_pp_clock_type type, 2925 struct pp_clock_levels_with_voltage *clocks) 2926 { 2927 clocks->num_levels = 0; 2928 2929 return 0; 2930 } 2931 2932 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 2933 void *clock_ranges) 2934 { 2935 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2936 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 2937 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 2938 2939 if (!data->registry_data.disable_water_mark && 2940 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2941 data->smu_features[GNLD_DPM_SOCCLK].supported) { 2942 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 2943 data->water_marks_bitmap |= WaterMarksExist; 2944 data->water_marks_bitmap &= ~WaterMarksLoaded; 2945 } 2946 2947 return 0; 2948 } 2949 2950 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 2951 enum PP_OD_DPM_TABLE_COMMAND type, 2952 long *input, uint32_t size) 2953 { 2954 struct vega20_hwmgr *data = 2955 (struct vega20_hwmgr *)(hwmgr->backend); 2956 struct vega20_od8_single_setting *od8_settings = 2957 data->od8_settings.od8_settings_array; 2958 OverDriveTable_t *od_table = 2959 &(data->smc_state_table.overdrive_table); 2960 int32_t input_clk, input_vol, i; 2961 uint32_t input_index; 2962 int od8_id; 2963 int ret; 2964 2965 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 2966 return -EINVAL); 2967 2968 switch (type) { 2969 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2970 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && 2971 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) { 2972 pr_info("Sclk min/max frequency overdrive not supported\n"); 2973 return -EOPNOTSUPP; 2974 } 2975 2976 for (i = 0; i < size; i += 2) { 2977 if (i + 2 > size) { 2978 pr_info("invalid number of input parameters %d\n", 2979 size); 2980 return -EINVAL; 2981 } 2982 2983 input_index = input[i]; 2984 input_clk = input[i + 1]; 2985 2986 if (input_index != 0 && input_index != 1) { 2987 pr_info("Invalid index %d\n", input_index); 2988 pr_info("Support min/max sclk frequency setting only which index by 0/1\n"); 2989 return -EINVAL; 2990 } 2991 2992 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || 2993 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { 2994 pr_info("clock freq %d is not within allowed range [%d - %d]\n", 2995 input_clk, 2996 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, 2997 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); 2998 return -EINVAL; 2999 } 3000 3001 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || 3002 (input_index == 1 && od_table->GfxclkFmax != input_clk)) 3003 data->gfxclk_overdrive = true; 3004 3005 if (input_index == 0) 3006 od_table->GfxclkFmin = input_clk; 3007 else 3008 od_table->GfxclkFmax = input_clk; 3009 } 3010 3011 break; 3012 3013 case PP_OD_EDIT_MCLK_VDDC_TABLE: 3014 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { 3015 pr_info("Mclk max frequency overdrive not supported\n"); 3016 return -EOPNOTSUPP; 3017 } 3018 3019 for (i = 0; i < size; i += 2) { 3020 if (i + 2 > size) { 3021 pr_info("invalid number of input parameters %d\n", 3022 size); 3023 return -EINVAL; 3024 } 3025 3026 input_index = input[i]; 3027 input_clk = input[i + 1]; 3028 3029 if (input_index != 1) { 3030 pr_info("Invalid index %d\n", input_index); 3031 pr_info("Support max Mclk frequency setting only which index by 1\n"); 3032 return -EINVAL; 3033 } 3034 3035 if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value || 3036 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) { 3037 pr_info("clock freq %d is not within allowed range [%d - %d]\n", 3038 input_clk, 3039 od8_settings[OD8_SETTING_UCLK_FMAX].min_value, 3040 od8_settings[OD8_SETTING_UCLK_FMAX].max_value); 3041 return -EINVAL; 3042 } 3043 3044 if (input_index == 1 && od_table->UclkFmax != input_clk) 3045 data->memclk_overdrive = true; 3046 3047 od_table->UclkFmax = input_clk; 3048 } 3049 3050 break; 3051 3052 case PP_OD_EDIT_VDDC_CURVE: 3053 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && 3054 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && 3055 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && 3056 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && 3057 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && 3058 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) { 3059 pr_info("Voltage curve calibrate not supported\n"); 3060 return -EOPNOTSUPP; 3061 } 3062 3063 for (i = 0; i < size; i += 3) { 3064 if (i + 3 > size) { 3065 pr_info("invalid number of input parameters %d\n", 3066 size); 3067 return -EINVAL; 3068 } 3069 3070 input_index = input[i]; 3071 input_clk = input[i + 1]; 3072 input_vol = input[i + 2]; 3073 3074 if (input_index > 2) { 3075 pr_info("Setting for point %d is not supported\n", 3076 input_index + 1); 3077 pr_info("Three supported points index by 0, 1, 2\n"); 3078 return -EINVAL; 3079 } 3080 3081 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index; 3082 if (input_clk < od8_settings[od8_id].min_value || 3083 input_clk > od8_settings[od8_id].max_value) { 3084 pr_info("clock freq %d is not within allowed range [%d - %d]\n", 3085 input_clk, 3086 od8_settings[od8_id].min_value, 3087 od8_settings[od8_id].max_value); 3088 return -EINVAL; 3089 } 3090 3091 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index; 3092 if (input_vol < od8_settings[od8_id].min_value || 3093 input_vol > od8_settings[od8_id].max_value) { 3094 pr_info("clock voltage %d is not within allowed range [%d - %d]\n", 3095 input_vol, 3096 od8_settings[od8_id].min_value, 3097 od8_settings[od8_id].max_value); 3098 return -EINVAL; 3099 } 3100 3101 switch (input_index) { 3102 case 0: 3103 od_table->GfxclkFreq1 = input_clk; 3104 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE; 3105 break; 3106 case 1: 3107 od_table->GfxclkFreq2 = input_clk; 3108 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE; 3109 break; 3110 case 2: 3111 od_table->GfxclkFreq3 = input_clk; 3112 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE; 3113 break; 3114 } 3115 } 3116 break; 3117 3118 case PP_OD_RESTORE_DEFAULT_TABLE: 3119 data->gfxclk_overdrive = false; 3120 data->memclk_overdrive = false; 3121 3122 ret = smum_smc_table_manager(hwmgr, 3123 (uint8_t *)od_table, 3124 TABLE_OVERDRIVE, true); 3125 PP_ASSERT_WITH_CODE(!ret, 3126 "Failed to export overdrive table!", 3127 return ret); 3128 break; 3129 3130 case PP_OD_COMMIT_DPM_TABLE: 3131 ret = smum_smc_table_manager(hwmgr, 3132 (uint8_t *)od_table, 3133 TABLE_OVERDRIVE, false); 3134 PP_ASSERT_WITH_CODE(!ret, 3135 "Failed to import overdrive table!", 3136 return ret); 3137 3138 /* retrieve updated gfxclk table */ 3139 if (data->gfxclk_overdrive) { 3140 data->gfxclk_overdrive = false; 3141 3142 ret = vega20_setup_gfxclk_dpm_table(hwmgr); 3143 if (ret) 3144 return ret; 3145 } 3146 3147 /* retrieve updated memclk table */ 3148 if (data->memclk_overdrive) { 3149 data->memclk_overdrive = false; 3150 3151 ret = vega20_setup_memclk_dpm_table(hwmgr); 3152 if (ret) 3153 return ret; 3154 } 3155 break; 3156 3157 default: 3158 return -EINVAL; 3159 } 3160 3161 return 0; 3162 } 3163 3164 static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr, 3165 enum pp_mp1_state mp1_state) 3166 { 3167 uint16_t msg; 3168 int ret; 3169 3170 switch (mp1_state) { 3171 case PP_MP1_STATE_SHUTDOWN: 3172 msg = PPSMC_MSG_PrepareMp1ForShutdown; 3173 break; 3174 case PP_MP1_STATE_UNLOAD: 3175 msg = PPSMC_MSG_PrepareMp1ForUnload; 3176 break; 3177 case PP_MP1_STATE_RESET: 3178 msg = PPSMC_MSG_PrepareMp1ForReset; 3179 break; 3180 case PP_MP1_STATE_NONE: 3181 default: 3182 return 0; 3183 } 3184 3185 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 3186 "[PrepareMp1] Failed!", 3187 return ret); 3188 3189 return 0; 3190 } 3191 3192 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 3193 { 3194 static const char *ppfeature_name[] = { 3195 "DPM_PREFETCHER", 3196 "GFXCLK_DPM", 3197 "UCLK_DPM", 3198 "SOCCLK_DPM", 3199 "UVD_DPM", 3200 "VCE_DPM", 3201 "ULV", 3202 "MP0CLK_DPM", 3203 "LINK_DPM", 3204 "DCEFCLK_DPM", 3205 "GFXCLK_DS", 3206 "SOCCLK_DS", 3207 "LCLK_DS", 3208 "PPT", 3209 "TDC", 3210 "THERMAL", 3211 "GFX_PER_CU_CG", 3212 "RM", 3213 "DCEFCLK_DS", 3214 "ACDC", 3215 "VR0HOT", 3216 "VR1HOT", 3217 "FW_CTF", 3218 "LED_DISPLAY", 3219 "FAN_CONTROL", 3220 "GFX_EDC", 3221 "GFXOFF", 3222 "CG", 3223 "FCLK_DPM", 3224 "FCLK_DS", 3225 "MP1CLK_DS", 3226 "MP0CLK_DS", 3227 "XGMI", 3228 "ECC"}; 3229 static const char *output_title[] = { 3230 "FEATURES", 3231 "BITMASK", 3232 "ENABLEMENT"}; 3233 uint64_t features_enabled; 3234 int i; 3235 int ret = 0; 3236 int size = 0; 3237 3238 phm_get_sysfs_buf(&buf, &size); 3239 3240 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 3241 PP_ASSERT_WITH_CODE(!ret, 3242 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 3243 return ret); 3244 3245 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 3246 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 3247 output_title[0], 3248 output_title[1], 3249 output_title[2]); 3250 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 3251 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 3252 ppfeature_name[i], 3253 1ULL << i, 3254 (features_enabled & (1ULL << i)) ? "Y" : "N"); 3255 } 3256 3257 return size; 3258 } 3259 3260 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 3261 { 3262 struct vega20_hwmgr *data = 3263 (struct vega20_hwmgr *)(hwmgr->backend); 3264 uint64_t features_enabled, features_to_enable, features_to_disable; 3265 int i, ret = 0; 3266 bool enabled; 3267 3268 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 3269 return -EINVAL; 3270 3271 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 3272 if (ret) 3273 return ret; 3274 3275 features_to_disable = 3276 features_enabled & ~new_ppfeature_masks; 3277 features_to_enable = 3278 ~features_enabled & new_ppfeature_masks; 3279 3280 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 3281 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 3282 3283 if (features_to_disable) { 3284 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable); 3285 if (ret) 3286 return ret; 3287 } 3288 3289 if (features_to_enable) { 3290 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable); 3291 if (ret) 3292 return ret; 3293 } 3294 3295 /* Update the cached feature enablement state */ 3296 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 3297 if (ret) 3298 return ret; 3299 3300 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 3301 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? 3302 true : false; 3303 data->smu_features[i].enabled = enabled; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 3310 { 3311 struct amdgpu_device *adev = hwmgr->adev; 3312 3313 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 3314 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 3315 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 3316 } 3317 3318 static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) 3319 { 3320 uint32_t width_level; 3321 3322 width_level = vega20_get_current_pcie_link_width_level(hwmgr); 3323 if (width_level > LINK_WIDTH_MAX) 3324 width_level = 0; 3325 3326 return link_width[width_level]; 3327 } 3328 3329 static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 3330 { 3331 struct amdgpu_device *adev = hwmgr->adev; 3332 3333 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 3334 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 3335 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 3336 } 3337 3338 static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) 3339 { 3340 uint32_t speed_level; 3341 3342 speed_level = vega20_get_current_pcie_link_speed_level(hwmgr); 3343 if (speed_level > LINK_SPEED_MAX) 3344 speed_level = 0; 3345 3346 return link_speed[speed_level]; 3347 } 3348 3349 static int vega20_emit_clock_levels(struct pp_hwmgr *hwmgr, 3350 enum pp_clock_type type, char *buf, 3351 int *offset) 3352 { 3353 struct vega20_hwmgr *data = 3354 (struct vega20_hwmgr *)(hwmgr->backend); 3355 struct vega20_od8_single_setting *od8_settings = 3356 data->od8_settings.od8_settings_array; 3357 OverDriveTable_t *od_table = 3358 &(data->smc_state_table.overdrive_table); 3359 PPTable_t *pptable = &(data->smc_state_table.pp_table); 3360 struct pp_clock_levels_with_latency clocks; 3361 struct vega20_single_dpm_table *fclk_dpm_table = 3362 &(data->dpm_table.fclk_table); 3363 int i, now, size = *offset; 3364 int ret = 0; 3365 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 3366 3367 switch (type) { 3368 case PP_SCLK: 3369 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now); 3370 PP_ASSERT_WITH_CODE(!ret, 3371 "Attempt to get current gfx clk Failed!", 3372 return ret); 3373 3374 if (vega20_get_sclks(hwmgr, &clocks)) { 3375 size += sysfs_emit_at(buf, size, 3376 "0: %uMhz * (DPM disabled)\n", 3377 now / 100); 3378 break; 3379 } 3380 3381 for (i = 0; i < clocks.num_levels; i++) 3382 size += sysfs_emit_at( 3383 buf, size, "%d: %uMhz %s\n", i, 3384 clocks.data[i].clocks_in_khz / 1000, 3385 (clocks.data[i].clocks_in_khz == now * 10) ? 3386 "*" : 3387 ""); 3388 break; 3389 3390 case PP_MCLK: 3391 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now); 3392 PP_ASSERT_WITH_CODE(!ret, 3393 "Attempt to get current mclk freq Failed!", 3394 return ret); 3395 3396 if (vega20_get_memclocks(hwmgr, &clocks)) { 3397 size += sysfs_emit_at(buf, size, 3398 "0: %uMhz * (DPM disabled)\n", 3399 now / 100); 3400 break; 3401 } 3402 3403 for (i = 0; i < clocks.num_levels; i++) 3404 size += sysfs_emit_at( 3405 buf, size, "%d: %uMhz %s\n", i, 3406 clocks.data[i].clocks_in_khz / 1000, 3407 (clocks.data[i].clocks_in_khz == now * 10) ? 3408 "*" : 3409 ""); 3410 break; 3411 3412 case PP_SOCCLK: 3413 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now); 3414 PP_ASSERT_WITH_CODE(!ret, 3415 "Attempt to get current socclk freq Failed!", 3416 return ret); 3417 3418 if (vega20_get_socclocks(hwmgr, &clocks)) { 3419 size += sysfs_emit_at(buf, size, 3420 "0: %uMhz * (DPM disabled)\n", 3421 now / 100); 3422 break; 3423 } 3424 3425 for (i = 0; i < clocks.num_levels; i++) 3426 size += sysfs_emit_at( 3427 buf, size, "%d: %uMhz %s\n", i, 3428 clocks.data[i].clocks_in_khz / 1000, 3429 (clocks.data[i].clocks_in_khz == now * 10) ? 3430 "*" : 3431 ""); 3432 break; 3433 3434 case PP_FCLK: 3435 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now); 3436 PP_ASSERT_WITH_CODE(!ret, 3437 "Attempt to get current fclk freq Failed!", 3438 return ret); 3439 3440 for (i = 0; i < fclk_dpm_table->count; i++) 3441 size += sysfs_emit_at( 3442 buf, size, "%d: %uMhz %s\n", i, 3443 fclk_dpm_table->dpm_levels[i].value, 3444 fclk_dpm_table->dpm_levels[i].value == 3445 (now / 100) ? 3446 "*" : 3447 ""); 3448 break; 3449 3450 case PP_DCEFCLK: 3451 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now); 3452 PP_ASSERT_WITH_CODE(!ret, 3453 "Attempt to get current dcefclk freq Failed!", 3454 return ret); 3455 3456 if (vega20_get_dcefclocks(hwmgr, &clocks)) { 3457 size += sysfs_emit_at(buf, size, 3458 "0: %uMhz * (DPM disabled)\n", 3459 now / 100); 3460 break; 3461 } 3462 3463 for (i = 0; i < clocks.num_levels; i++) 3464 size += sysfs_emit_at( 3465 buf, size, "%d: %uMhz %s\n", i, 3466 clocks.data[i].clocks_in_khz / 1000, 3467 (clocks.data[i].clocks_in_khz == now * 10) ? 3468 "*" : 3469 ""); 3470 break; 3471 3472 case PP_PCIE: 3473 current_gen_speed = 3474 vega20_get_current_pcie_link_speed_level(hwmgr); 3475 current_lane_width = 3476 vega20_get_current_pcie_link_width_level(hwmgr); 3477 for (i = 0; i < NUM_LINK_LEVELS; i++) { 3478 gen_speed = pptable->PcieGenSpeed[i]; 3479 lane_width = pptable->PcieLaneCount[i]; 3480 3481 size += sysfs_emit_at( 3482 buf, size, "%d: %s %s %dMhz %s\n", i, 3483 (gen_speed == 0) ? "2.5GT/s," : 3484 (gen_speed == 1) ? "5.0GT/s," : 3485 (gen_speed == 2) ? "8.0GT/s," : 3486 (gen_speed == 3) ? "16.0GT/s," : 3487 "", 3488 (lane_width == 1) ? "x1" : 3489 (lane_width == 2) ? "x2" : 3490 (lane_width == 3) ? "x4" : 3491 (lane_width == 4) ? "x8" : 3492 (lane_width == 5) ? "x12" : 3493 (lane_width == 6) ? "x16" : 3494 "", 3495 pptable->LclkFreq[i], 3496 (current_gen_speed == gen_speed) && 3497 (current_lane_width == 3498 lane_width) ? 3499 "*" : 3500 ""); 3501 } 3502 break; 3503 3504 case OD_SCLK: 3505 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && 3506 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { 3507 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 3508 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 3509 od_table->GfxclkFmin); 3510 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 3511 od_table->GfxclkFmax); 3512 } 3513 break; 3514 3515 case OD_MCLK: 3516 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { 3517 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); 3518 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 3519 od_table->UclkFmax); 3520 } 3521 3522 break; 3523 3524 case OD_VDDC_CURVE: 3525 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && 3526 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && 3527 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && 3528 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && 3529 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && 3530 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { 3531 size += sysfs_emit_at(buf, size, "%s:\n", 3532 "OD_VDDC_CURVE"); 3533 size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n", 3534 od_table->GfxclkFreq1, 3535 od_table->GfxclkVolt1 / 3536 VOLTAGE_SCALE); 3537 size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n", 3538 od_table->GfxclkFreq2, 3539 od_table->GfxclkVolt2 / 3540 VOLTAGE_SCALE); 3541 size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n", 3542 od_table->GfxclkFreq3, 3543 od_table->GfxclkVolt3 / 3544 VOLTAGE_SCALE); 3545 } 3546 3547 break; 3548 3549 case OD_RANGE: 3550 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 3551 3552 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && 3553 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { 3554 size += sysfs_emit_at( 3555 buf, size, "SCLK: %7uMhz %10uMhz\n", 3556 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, 3557 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); 3558 } 3559 3560 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { 3561 size += sysfs_emit_at( 3562 buf, size, "MCLK: %7uMhz %10uMhz\n", 3563 od8_settings[OD8_SETTING_UCLK_FMAX].min_value, 3564 od8_settings[OD8_SETTING_UCLK_FMAX].max_value); 3565 } 3566 3567 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && 3568 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && 3569 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && 3570 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && 3571 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && 3572 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { 3573 size += sysfs_emit_at( 3574 buf, size, 3575 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 3576 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value, 3577 od8_settings[OD8_SETTING_GFXCLK_FREQ1] 3578 .max_value); 3579 size += sysfs_emit_at( 3580 buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 3581 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1] 3582 .min_value, 3583 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1] 3584 .max_value); 3585 size += sysfs_emit_at( 3586 buf, size, 3587 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 3588 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value, 3589 od8_settings[OD8_SETTING_GFXCLK_FREQ2] 3590 .max_value); 3591 size += sysfs_emit_at( 3592 buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 3593 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2] 3594 .min_value, 3595 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2] 3596 .max_value); 3597 size += sysfs_emit_at( 3598 buf, size, 3599 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 3600 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value, 3601 od8_settings[OD8_SETTING_GFXCLK_FREQ3] 3602 .max_value); 3603 size += sysfs_emit_at( 3604 buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 3605 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3] 3606 .min_value, 3607 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3] 3608 .max_value); 3609 } 3610 3611 break; 3612 default: 3613 break; 3614 } 3615 3616 *offset = size; 3617 3618 return 0; 3619 } 3620 3621 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, 3622 struct vega20_single_dpm_table *dpm_table) 3623 { 3624 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3625 int ret = 0; 3626 3627 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 3628 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 3629 "[SetUclkToHightestDpmLevel] Dpm table has no entry!", 3630 return -EINVAL); 3631 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, 3632 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", 3633 return -EINVAL); 3634 3635 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3636 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 3637 PPSMC_MSG_SetHardMinByFreq, 3638 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level, 3639 NULL)), 3640 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", 3641 return ret); 3642 } 3643 3644 return ret; 3645 } 3646 3647 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr) 3648 { 3649 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3650 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); 3651 int ret = 0; 3652 3653 if (data->smu_features[GNLD_DPM_FCLK].enabled) { 3654 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 3655 "[SetFclkToHightestDpmLevel] Dpm table has no entry!", 3656 return -EINVAL); 3657 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, 3658 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!", 3659 return -EINVAL); 3660 3661 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3662 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 3663 PPSMC_MSG_SetSoftMinByFreq, 3664 (PPCLK_FCLK << 16) | dpm_table->dpm_state.soft_min_level, 3665 NULL)), 3666 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!", 3667 return ret); 3668 } 3669 3670 return ret; 3671 } 3672 3673 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 3674 { 3675 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3676 int ret = 0; 3677 3678 smum_send_msg_to_smc_with_parameter(hwmgr, 3679 PPSMC_MSG_NumOfDisplays, 0, NULL); 3680 3681 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr, 3682 &data->dpm_table.mem_table); 3683 if (ret) 3684 return ret; 3685 3686 return vega20_set_fclk_to_highest_dpm_level(hwmgr); 3687 } 3688 3689 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 3690 { 3691 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3692 int result = 0; 3693 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 3694 3695 if ((data->water_marks_bitmap & WaterMarksExist) && 3696 !(data->water_marks_bitmap & WaterMarksLoaded)) { 3697 result = smum_smc_table_manager(hwmgr, 3698 (uint8_t *)wm_table, TABLE_WATERMARKS, false); 3699 PP_ASSERT_WITH_CODE(!result, 3700 "Failed to update WMTABLE!", 3701 return result); 3702 data->water_marks_bitmap |= WaterMarksLoaded; 3703 } 3704 3705 if ((data->water_marks_bitmap & WaterMarksExist) && 3706 data->smu_features[GNLD_DPM_DCEFCLK].supported && 3707 data->smu_features[GNLD_DPM_SOCCLK].supported) { 3708 result = smum_send_msg_to_smc_with_parameter(hwmgr, 3709 PPSMC_MSG_NumOfDisplays, 3710 hwmgr->display_config->num_display, 3711 NULL); 3712 } 3713 3714 return result; 3715 } 3716 3717 static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 3718 { 3719 struct vega20_hwmgr *data = 3720 (struct vega20_hwmgr *)(hwmgr->backend); 3721 int ret = 0; 3722 3723 if (data->smu_features[GNLD_DPM_UVD].supported) { 3724 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) { 3725 if (enable) 3726 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n"); 3727 else 3728 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n"); 3729 } 3730 3731 ret = vega20_enable_smc_features(hwmgr, 3732 enable, 3733 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap); 3734 PP_ASSERT_WITH_CODE(!ret, 3735 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!", 3736 return ret); 3737 data->smu_features[GNLD_DPM_UVD].enabled = enable; 3738 } 3739 3740 return 0; 3741 } 3742 3743 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 3744 { 3745 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3746 3747 if (data->vce_power_gated == bgate) 3748 return ; 3749 3750 data->vce_power_gated = bgate; 3751 if (bgate) { 3752 vega20_enable_disable_vce_dpm(hwmgr, !bgate); 3753 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 3754 AMD_IP_BLOCK_TYPE_VCE, 3755 AMD_PG_STATE_GATE); 3756 } else { 3757 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 3758 AMD_IP_BLOCK_TYPE_VCE, 3759 AMD_PG_STATE_UNGATE); 3760 vega20_enable_disable_vce_dpm(hwmgr, !bgate); 3761 } 3762 3763 } 3764 3765 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 3766 { 3767 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3768 3769 if (data->uvd_power_gated == bgate) 3770 return ; 3771 3772 data->uvd_power_gated = bgate; 3773 vega20_enable_disable_uvd_dpm(hwmgr, !bgate); 3774 } 3775 3776 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 3777 { 3778 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3779 struct vega20_single_dpm_table *dpm_table; 3780 bool vblank_too_short = false; 3781 bool disable_mclk_switching; 3782 bool disable_fclk_switching; 3783 uint32_t i, latency; 3784 3785 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 3786 !hwmgr->display_config->multi_monitor_in_sync) || 3787 vblank_too_short; 3788 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3789 3790 /* gfxclk */ 3791 dpm_table = &(data->dpm_table.gfx_table); 3792 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3793 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3794 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3795 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3796 3797 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3798 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { 3799 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 3800 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 3801 } 3802 3803 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 3804 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3805 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 3806 } 3807 3808 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3809 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3810 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3811 } 3812 } 3813 3814 /* memclk */ 3815 dpm_table = &(data->dpm_table.mem_table); 3816 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3817 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3818 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3819 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3820 3821 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3822 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { 3823 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 3824 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 3825 } 3826 3827 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 3828 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3829 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 3830 } 3831 3832 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3833 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3834 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3835 } 3836 } 3837 3838 /* honour DAL's UCLK Hardmin */ 3839 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) 3840 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; 3841 3842 /* Hardmin is dependent on displayconfig */ 3843 if (disable_mclk_switching) { 3844 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3845 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { 3846 if (data->mclk_latency_table.entries[i].latency <= latency) { 3847 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { 3848 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; 3849 break; 3850 } 3851 } 3852 } 3853 } 3854 3855 if (hwmgr->display_config->nb_pstate_switch_disable) 3856 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3857 3858 if ((disable_mclk_switching && 3859 (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) || 3860 hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value) 3861 disable_fclk_switching = true; 3862 else 3863 disable_fclk_switching = false; 3864 3865 /* fclk */ 3866 dpm_table = &(data->dpm_table.fclk_table); 3867 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3868 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3869 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3870 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3871 if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching) 3872 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3873 3874 /* vclk */ 3875 dpm_table = &(data->dpm_table.vclk_table); 3876 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3877 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3878 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3879 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3880 3881 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3882 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 3883 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3884 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3885 } 3886 3887 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3888 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3889 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3890 } 3891 } 3892 3893 /* dclk */ 3894 dpm_table = &(data->dpm_table.dclk_table); 3895 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3896 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3897 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3898 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3899 3900 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3901 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 3902 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3903 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3904 } 3905 3906 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3907 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3908 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3909 } 3910 } 3911 3912 /* socclk */ 3913 dpm_table = &(data->dpm_table.soc_table); 3914 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3915 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3916 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3917 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3918 3919 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3920 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { 3921 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value; 3922 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value; 3923 } 3924 3925 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3926 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3927 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3928 } 3929 } 3930 3931 /* eclk */ 3932 dpm_table = &(data->dpm_table.eclk_table); 3933 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3934 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3935 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3936 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3937 3938 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3939 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { 3940 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value; 3941 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value; 3942 } 3943 3944 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3945 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3946 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3947 } 3948 } 3949 3950 return 0; 3951 } 3952 3953 static bool 3954 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 3955 { 3956 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3957 bool is_update_required = false; 3958 3959 if (data->display_timing.num_existing_displays != 3960 hwmgr->display_config->num_display) 3961 is_update_required = true; 3962 3963 if (data->registry_data.gfx_clk_deep_sleep_support && 3964 (data->display_timing.min_clock_in_sr != 3965 hwmgr->display_config->min_core_set_clock_in_sr)) 3966 is_update_required = true; 3967 3968 return is_update_required; 3969 } 3970 3971 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 3972 { 3973 int ret = 0; 3974 3975 ret = vega20_disable_all_smu_features(hwmgr); 3976 PP_ASSERT_WITH_CODE(!ret, 3977 "[DisableDpmTasks] Failed to disable all smu features!", 3978 return ret); 3979 3980 return 0; 3981 } 3982 3983 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr) 3984 { 3985 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3986 int result; 3987 3988 result = vega20_disable_dpm_tasks(hwmgr); 3989 PP_ASSERT_WITH_CODE((0 == result), 3990 "[PowerOffAsic] Failed to disable DPM!", 3991 ); 3992 data->water_marks_bitmap &= ~(WaterMarksLoaded); 3993 3994 return result; 3995 } 3996 3997 static int conv_power_profile_to_pplib_workload(int power_profile) 3998 { 3999 int pplib_workload = 0; 4000 4001 switch (power_profile) { 4002 case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: 4003 pplib_workload = WORKLOAD_DEFAULT_BIT; 4004 break; 4005 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 4006 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; 4007 break; 4008 case PP_SMC_POWER_PROFILE_POWERSAVING: 4009 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; 4010 break; 4011 case PP_SMC_POWER_PROFILE_VIDEO: 4012 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; 4013 break; 4014 case PP_SMC_POWER_PROFILE_VR: 4015 pplib_workload = WORKLOAD_PPLIB_VR_BIT; 4016 break; 4017 case PP_SMC_POWER_PROFILE_COMPUTE: 4018 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; 4019 break; 4020 case PP_SMC_POWER_PROFILE_CUSTOM: 4021 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; 4022 break; 4023 } 4024 4025 return pplib_workload; 4026 } 4027 4028 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 4029 { 4030 DpmActivityMonitorCoeffInt_t activity_monitor; 4031 uint32_t i, size = 0; 4032 uint16_t workload_type = 0; 4033 static const char *title[] = { 4034 "PROFILE_INDEX(NAME)", 4035 "CLOCK_TYPE(NAME)", 4036 "FPS", 4037 "UseRlcBusy", 4038 "MinActiveFreqType", 4039 "MinActiveFreq", 4040 "BoosterFreqType", 4041 "BoosterFreq", 4042 "PD_Data_limit_c", 4043 "PD_Data_error_coeff", 4044 "PD_Data_error_rate_coeff"}; 4045 int result = 0; 4046 4047 if (!buf) 4048 return -EINVAL; 4049 4050 phm_get_sysfs_buf(&buf, &size); 4051 4052 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 4053 title[0], title[1], title[2], title[3], title[4], title[5], 4054 title[6], title[7], title[8], title[9], title[10]); 4055 4056 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 4057 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 4058 workload_type = conv_power_profile_to_pplib_workload(i); 4059 result = vega20_get_activity_monitor_coeff(hwmgr, 4060 (uint8_t *)(&activity_monitor), workload_type); 4061 PP_ASSERT_WITH_CODE(!result, 4062 "[GetPowerProfile] Failed to get activity monitor!", 4063 return result); 4064 4065 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 4066 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " "); 4067 4068 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4069 " ", 4070 0, 4071 "GFXCLK", 4072 activity_monitor.Gfx_FPS, 4073 activity_monitor.Gfx_UseRlcBusy, 4074 activity_monitor.Gfx_MinActiveFreqType, 4075 activity_monitor.Gfx_MinActiveFreq, 4076 activity_monitor.Gfx_BoosterFreqType, 4077 activity_monitor.Gfx_BoosterFreq, 4078 activity_monitor.Gfx_PD_Data_limit_c, 4079 activity_monitor.Gfx_PD_Data_error_coeff, 4080 activity_monitor.Gfx_PD_Data_error_rate_coeff); 4081 4082 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4083 " ", 4084 1, 4085 "SOCCLK", 4086 activity_monitor.Soc_FPS, 4087 activity_monitor.Soc_UseRlcBusy, 4088 activity_monitor.Soc_MinActiveFreqType, 4089 activity_monitor.Soc_MinActiveFreq, 4090 activity_monitor.Soc_BoosterFreqType, 4091 activity_monitor.Soc_BoosterFreq, 4092 activity_monitor.Soc_PD_Data_limit_c, 4093 activity_monitor.Soc_PD_Data_error_coeff, 4094 activity_monitor.Soc_PD_Data_error_rate_coeff); 4095 4096 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4097 " ", 4098 2, 4099 "UCLK", 4100 activity_monitor.Mem_FPS, 4101 activity_monitor.Mem_UseRlcBusy, 4102 activity_monitor.Mem_MinActiveFreqType, 4103 activity_monitor.Mem_MinActiveFreq, 4104 activity_monitor.Mem_BoosterFreqType, 4105 activity_monitor.Mem_BoosterFreq, 4106 activity_monitor.Mem_PD_Data_limit_c, 4107 activity_monitor.Mem_PD_Data_error_coeff, 4108 activity_monitor.Mem_PD_Data_error_rate_coeff); 4109 4110 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4111 " ", 4112 3, 4113 "FCLK", 4114 activity_monitor.Fclk_FPS, 4115 activity_monitor.Fclk_UseRlcBusy, 4116 activity_monitor.Fclk_MinActiveFreqType, 4117 activity_monitor.Fclk_MinActiveFreq, 4118 activity_monitor.Fclk_BoosterFreqType, 4119 activity_monitor.Fclk_BoosterFreq, 4120 activity_monitor.Fclk_PD_Data_limit_c, 4121 activity_monitor.Fclk_PD_Data_error_coeff, 4122 activity_monitor.Fclk_PD_Data_error_rate_coeff); 4123 } 4124 4125 return size; 4126 } 4127 4128 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 4129 { 4130 DpmActivityMonitorCoeffInt_t activity_monitor; 4131 int workload_type, result = 0; 4132 uint32_t power_profile_mode = input[size]; 4133 4134 if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 4135 pr_err("Invalid power profile mode %d\n", power_profile_mode); 4136 return -EINVAL; 4137 } 4138 4139 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 4140 struct vega20_hwmgr *data = 4141 (struct vega20_hwmgr *)(hwmgr->backend); 4142 4143 if (size != 10 && size != 0) 4144 return -EINVAL; 4145 4146 if (size == 0 && !data->is_custom_profile_set) 4147 return -EINVAL; 4148 4149 result = vega20_get_activity_monitor_coeff(hwmgr, 4150 (uint8_t *)(&activity_monitor), 4151 WORKLOAD_PPLIB_CUSTOM_BIT); 4152 PP_ASSERT_WITH_CODE(!result, 4153 "[SetPowerProfile] Failed to get activity monitor!", 4154 return result); 4155 4156 /* If size==0, then we want to apply the already-configured 4157 * CUSTOM profile again. Just apply it, since we checked its 4158 * validity above 4159 */ 4160 if (size == 0) 4161 goto out; 4162 4163 switch (input[0]) { 4164 case 0: /* Gfxclk */ 4165 activity_monitor.Gfx_FPS = input[1]; 4166 activity_monitor.Gfx_UseRlcBusy = input[2]; 4167 activity_monitor.Gfx_MinActiveFreqType = input[3]; 4168 activity_monitor.Gfx_MinActiveFreq = input[4]; 4169 activity_monitor.Gfx_BoosterFreqType = input[5]; 4170 activity_monitor.Gfx_BoosterFreq = input[6]; 4171 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 4172 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 4173 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 4174 break; 4175 case 1: /* Socclk */ 4176 activity_monitor.Soc_FPS = input[1]; 4177 activity_monitor.Soc_UseRlcBusy = input[2]; 4178 activity_monitor.Soc_MinActiveFreqType = input[3]; 4179 activity_monitor.Soc_MinActiveFreq = input[4]; 4180 activity_monitor.Soc_BoosterFreqType = input[5]; 4181 activity_monitor.Soc_BoosterFreq = input[6]; 4182 activity_monitor.Soc_PD_Data_limit_c = input[7]; 4183 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 4184 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 4185 break; 4186 case 2: /* Uclk */ 4187 activity_monitor.Mem_FPS = input[1]; 4188 activity_monitor.Mem_UseRlcBusy = input[2]; 4189 activity_monitor.Mem_MinActiveFreqType = input[3]; 4190 activity_monitor.Mem_MinActiveFreq = input[4]; 4191 activity_monitor.Mem_BoosterFreqType = input[5]; 4192 activity_monitor.Mem_BoosterFreq = input[6]; 4193 activity_monitor.Mem_PD_Data_limit_c = input[7]; 4194 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 4195 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 4196 break; 4197 case 3: /* Fclk */ 4198 activity_monitor.Fclk_FPS = input[1]; 4199 activity_monitor.Fclk_UseRlcBusy = input[2]; 4200 activity_monitor.Fclk_MinActiveFreqType = input[3]; 4201 activity_monitor.Fclk_MinActiveFreq = input[4]; 4202 activity_monitor.Fclk_BoosterFreqType = input[5]; 4203 activity_monitor.Fclk_BoosterFreq = input[6]; 4204 activity_monitor.Fclk_PD_Data_limit_c = input[7]; 4205 activity_monitor.Fclk_PD_Data_error_coeff = input[8]; 4206 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; 4207 break; 4208 default: 4209 return -EINVAL; 4210 } 4211 4212 result = vega20_set_activity_monitor_coeff(hwmgr, 4213 (uint8_t *)(&activity_monitor), 4214 WORKLOAD_PPLIB_CUSTOM_BIT); 4215 data->is_custom_profile_set = true; 4216 PP_ASSERT_WITH_CODE(!result, 4217 "[SetPowerProfile] Failed to set activity monitor!", 4218 return result); 4219 } 4220 4221 out: 4222 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 4223 workload_type = 4224 conv_power_profile_to_pplib_workload(power_profile_mode); 4225 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 4226 1 << workload_type, 4227 NULL); 4228 4229 hwmgr->power_profile_mode = power_profile_mode; 4230 4231 return 0; 4232 } 4233 4234 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 4235 uint32_t virtual_addr_low, 4236 uint32_t virtual_addr_hi, 4237 uint32_t mc_addr_low, 4238 uint32_t mc_addr_hi, 4239 uint32_t size) 4240 { 4241 smum_send_msg_to_smc_with_parameter(hwmgr, 4242 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 4243 virtual_addr_hi, 4244 NULL); 4245 smum_send_msg_to_smc_with_parameter(hwmgr, 4246 PPSMC_MSG_SetSystemVirtualDramAddrLow, 4247 virtual_addr_low, 4248 NULL); 4249 smum_send_msg_to_smc_with_parameter(hwmgr, 4250 PPSMC_MSG_DramLogSetDramAddrHigh, 4251 mc_addr_hi, 4252 NULL); 4253 4254 smum_send_msg_to_smc_with_parameter(hwmgr, 4255 PPSMC_MSG_DramLogSetDramAddrLow, 4256 mc_addr_low, 4257 NULL); 4258 4259 smum_send_msg_to_smc_with_parameter(hwmgr, 4260 PPSMC_MSG_DramLogSetDramSize, 4261 size, 4262 NULL); 4263 return 0; 4264 } 4265 4266 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 4267 struct PP_TemperatureRange *thermal_data) 4268 { 4269 struct phm_ppt_v3_information *pptable_information = 4270 (struct phm_ppt_v3_information *)hwmgr->pptable; 4271 struct vega20_hwmgr *data = 4272 (struct vega20_hwmgr *)(hwmgr->backend); 4273 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 4274 4275 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 4276 4277 thermal_data->max = pp_table->TedgeLimit * 4278 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4279 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 4280 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4281 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 4282 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4283 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 4284 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4285 thermal_data->mem_crit_max = pp_table->ThbmLimit * 4286 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4287 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 4288 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4289 thermal_data->sw_ctf_threshold = pptable_information->us_software_shutdown_temp * 4290 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4291 4292 return 0; 4293 } 4294 4295 static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire) 4296 { 4297 int res; 4298 4299 /* I2C bus access can happen very early, when SMU not loaded yet */ 4300 if (!vega20_is_smc_ram_running(hwmgr)) 4301 return 0; 4302 4303 res = smum_send_msg_to_smc_with_parameter(hwmgr, 4304 (acquire ? 4305 PPSMC_MSG_RequestI2CBus : 4306 PPSMC_MSG_ReleaseI2CBus), 4307 0, 4308 NULL); 4309 4310 PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res); 4311 return res; 4312 } 4313 4314 static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr, 4315 enum pp_df_cstate state) 4316 { 4317 int ret; 4318 4319 /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */ 4320 if (hwmgr->smu_version < 0x283200) { 4321 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n"); 4322 return -EINVAL; 4323 } 4324 4325 ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state, 4326 NULL); 4327 if (ret) 4328 pr_err("SetDfCstate failed!\n"); 4329 4330 return ret; 4331 } 4332 4333 static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr, 4334 uint32_t pstate) 4335 { 4336 int ret; 4337 4338 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4339 PPSMC_MSG_SetXgmiMode, 4340 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 4341 NULL); 4342 if (ret) 4343 pr_err("SetXgmiPstate failed!\n"); 4344 4345 return ret; 4346 } 4347 4348 static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) 4349 { 4350 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); 4351 4352 gpu_metrics->common_header.structure_size = 4353 sizeof(struct gpu_metrics_v1_0); 4354 gpu_metrics->common_header.format_revision = 1; 4355 gpu_metrics->common_header.content_revision = 0; 4356 4357 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 4358 } 4359 4360 static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr, 4361 void **table) 4362 { 4363 struct vega20_hwmgr *data = 4364 (struct vega20_hwmgr *)(hwmgr->backend); 4365 struct gpu_metrics_v1_0 *gpu_metrics = 4366 &data->gpu_metrics_table; 4367 SmuMetrics_t metrics; 4368 uint32_t fan_speed_rpm; 4369 int ret; 4370 4371 ret = vega20_get_metrics_table(hwmgr, &metrics, true); 4372 if (ret) 4373 return ret; 4374 4375 vega20_init_gpu_metrics_v1_0(gpu_metrics); 4376 4377 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 4378 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 4379 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 4380 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 4381 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 4382 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 4383 4384 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 4385 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 4386 4387 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 4388 4389 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 4390 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 4391 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 4392 4393 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 4394 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 4395 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 4396 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 4397 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 4398 4399 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 4400 4401 vega20_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); 4402 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; 4403 4404 gpu_metrics->pcie_link_width = 4405 vega20_get_current_pcie_link_width(hwmgr); 4406 gpu_metrics->pcie_link_speed = 4407 vega20_get_current_pcie_link_speed(hwmgr); 4408 4409 *table = (void *)gpu_metrics; 4410 4411 return sizeof(struct gpu_metrics_v1_0); 4412 } 4413 4414 static const struct pp_hwmgr_func vega20_hwmgr_funcs = { 4415 /* init/fini related */ 4416 .backend_init = vega20_hwmgr_backend_init, 4417 .backend_fini = vega20_hwmgr_backend_fini, 4418 .asic_setup = vega20_setup_asic_task, 4419 .power_off_asic = vega20_power_off_asic, 4420 .dynamic_state_management_enable = vega20_enable_dpm_tasks, 4421 .dynamic_state_management_disable = vega20_disable_dpm_tasks, 4422 /* power state related */ 4423 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules, 4424 .pre_display_config_changed = vega20_pre_display_configuration_changed_task, 4425 .display_config_changed = vega20_display_configuration_changed_task, 4426 .check_smc_update_required_for_display_configuration = 4427 vega20_check_smc_update_required_for_display_configuration, 4428 .notify_smc_display_config_after_ps_adjustment = 4429 vega20_notify_smc_display_config_after_ps_adjustment, 4430 /* export to DAL */ 4431 .get_sclk = vega20_dpm_get_sclk, 4432 .get_mclk = vega20_dpm_get_mclk, 4433 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency, 4434 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage, 4435 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges, 4436 .display_clock_voltage_request = vega20_display_clock_voltage_request, 4437 .get_performance_level = vega20_get_performance_level, 4438 /* UMD pstate, profile related */ 4439 .force_dpm_level = vega20_dpm_force_dpm_level, 4440 .get_power_profile_mode = vega20_get_power_profile_mode, 4441 .set_power_profile_mode = vega20_set_power_profile_mode, 4442 /* od related */ 4443 .set_power_limit = vega20_set_power_limit, 4444 .get_sclk_od = vega20_get_sclk_od, 4445 .set_sclk_od = vega20_set_sclk_od, 4446 .get_mclk_od = vega20_get_mclk_od, 4447 .set_mclk_od = vega20_set_mclk_od, 4448 .odn_edit_dpm_table = vega20_odn_edit_dpm_table, 4449 /* for sysfs to retrive/set gfxclk/memclk */ 4450 .force_clock_level = vega20_force_clock_level, 4451 .emit_clock_levels = vega20_emit_clock_levels, 4452 .read_sensor = vega20_read_sensor, 4453 .get_ppfeature_status = vega20_get_ppfeature_status, 4454 .set_ppfeature_status = vega20_set_ppfeature_status, 4455 /* powergate related */ 4456 .powergate_uvd = vega20_power_gate_uvd, 4457 .powergate_vce = vega20_power_gate_vce, 4458 /* thermal related */ 4459 .start_thermal_controller = vega20_start_thermal_controller, 4460 .stop_thermal_controller = vega20_thermal_stop_thermal_controller, 4461 .get_thermal_temperature_range = vega20_get_thermal_temperature_range, 4462 .register_irq_handlers = smu9_register_irq_handlers, 4463 .disable_smc_firmware_ctf = vega20_thermal_disable_alert, 4464 /* fan control related */ 4465 .get_fan_speed_pwm = vega20_fan_ctrl_get_fan_speed_pwm, 4466 .set_fan_speed_pwm = vega20_fan_ctrl_set_fan_speed_pwm, 4467 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info, 4468 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm, 4469 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm, 4470 .get_fan_control_mode = vega20_get_fan_control_mode, 4471 .set_fan_control_mode = vega20_set_fan_control_mode, 4472 /* smu memory related */ 4473 .notify_cac_buffer_info = vega20_notify_cac_buffer_info, 4474 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost, 4475 /* BACO related */ 4476 .get_bamaco_support = vega20_get_bamaco_support, 4477 .get_asic_baco_state = vega20_baco_get_state, 4478 .set_asic_baco_state = vega20_baco_set_state, 4479 .set_mp1_state = vega20_set_mp1_state, 4480 .smu_i2c_bus_access = vega20_smu_i2c_bus_access, 4481 .set_df_cstate = vega20_set_df_cstate, 4482 .set_xgmi_pstate = vega20_set_xgmi_pstate, 4483 .get_gpu_metrics = vega20_get_gpu_metrics, 4484 }; 4485 4486 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) 4487 { 4488 hwmgr->hwmgr_func = &vega20_hwmgr_funcs; 4489 hwmgr->pptable_func = &vega20_pptable_funcs; 4490 4491 return 0; 4492 } 4493