1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 #define ENETC_MM_VERIFY_SLEEP_US USEC_PER_MSEC 7 #define ENETC_MM_VERIFY_RETRIES 3 8 9 #define ENETC_NUM_TC 8 10 11 /* ENETC device IDs */ 12 #define ENETC_DEV_ID_PF 0xe100 13 #define ENETC_DEV_ID_VF 0xef00 14 #define ENETC_DEV_ID_PTP 0xee02 15 16 /* ENETC register block BAR */ 17 #define ENETC_BAR_REGS 0 18 19 /** SI regs, offset: 0h */ 20 #define ENETC_SIMR 0 21 #define ENETC_SIMR_EN BIT(31) 22 #define ENETC_SIMR_RSSE BIT(0) 23 #define ENETC_SICTR0 0x18 24 #define ENETC_SICTR1 0x1c 25 #define ENETC_SIPCAPR0 0x20 26 #define ENETC_SIPCAPR0_RSS BIT(8) 27 #define ENETC_SIPCAPR0_RFS BIT(2) 28 #define ENETC_SIPCAPR0_LSO BIT(1) 29 #define ENETC_SIPCAPR1 0x24 30 #define ENETC_SITGTGR 0x30 31 #define ENETC_SIRBGCR 0x38 32 /* cache attribute registers for transactions initiated by ENETC */ 33 #define ENETC_SICAR0 0x40 34 #define ENETC_SICAR1 0x44 35 #define ENETC_SICAR2 0x48 36 /* rd snoop, no alloc 37 * wr snoop, no alloc, partial cache line update for BDs and full cache line 38 * update for data 39 */ 40 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 41 #define ENETC_SICAR_WR_COHERENT 0x00006727 42 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 43 44 #define ENETC_SIPMAR0 0x80 45 #define ENETC_SIPMAR1 0x84 46 #define ENETC_SICVLANR1 0x90 47 #define ENETC_SICVLANR2 0x94 48 #define SICVLANR_ETYPE GENMASK(15, 0) 49 50 /* VF-PF Message passing */ 51 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 52 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 53 static inline u32 enetc_vsi_set_msize(u32 size) 54 { 55 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 56 } 57 58 #define ENETC_PSIMSGRR 0x204 59 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 60 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 61 62 /* Message received mask, n is the active number of VSIs. 63 * It is available for ENETC_PSIMSGRR, ENETC_PSIIER, and 64 * ENETC_PSIIDR registers. 65 */ 66 #define ENETC_PSIMR_MASK(n) \ 67 ({ typeof(n) _n = (n); (_n) ? GENMASK((_n), 1) : 0; }) 68 69 /* Message received bit, n is VSI index. It is available for 70 * ENETC_PSIMSGRR, ENETC_PSIIER, and ENETC_PSIIDR registers. 71 */ 72 #define ENETC_PSIMR_BIT(n) BIT((n) + 1) 73 74 #define ENETC_VSIMSGSR 0x204 /* RO */ 75 #define ENETC_VSIMSGSR_MB BIT(0) 76 #define ENETC_VSIMSGSR_MS BIT(1) 77 #define ENETC_VSIMSGSNDAR0 0x210 78 #define ENETC_VSIMSGSNDAR1 0x214 79 80 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 81 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 82 83 #define ENETC_PSIMSGSR 0x208 84 /* n is VF index, which is less than 15 */ 85 #define PSIMSGSR_MS(n) BIT((n) + 1) 86 #define PSIMSGSR_MC GENMASK(31, 16) 87 88 #define ENETC_VSIMSGRR 0x208 89 #define VSIMSGRR_MC GENMASK(31, 16) 90 91 /* SI statistics */ 92 #define ENETC_SIROCT 0x300 93 #define ENETC_SIRFRM 0x308 94 #define ENETC_SIRUCA 0x310 95 #define ENETC_SIRMCA 0x318 96 #define ENETC_SITOCT 0x320 97 #define ENETC_SITFRM 0x328 98 #define ENETC_SITUCA 0x330 99 #define ENETC_SITMCA 0x338 100 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 101 102 /* Control BDR regs */ 103 #define ENETC_SICBDRMR 0x800 104 #define ENETC_SICBDRSR 0x804 /* RO */ 105 #define ENETC_SICBDRBAR0 0x810 106 #define ENETC_SICBDRBAR1 0x814 107 #define ENETC_SICBDRPIR 0x818 108 #define ENETC_SICBDRCIR 0x81c 109 #define ENETC_SICBDRLENR 0x820 110 111 #define ENETC_SICAPR0 0x900 112 #define ENETC_SICAPR1 0x904 113 114 #define ENETC_VSIIER 0xa00 115 #define VSIIER_MRIE BIT(9) 116 117 #define ENETC_VSIIDR 0xa08 118 #define VSIIDR_MR BIT(9) 119 120 #define ENETC_PSIIER 0xa00 121 #define ENETC_PSIIDR 0xa08 122 123 /* VF FLR interrupt mask, n is the active number of VFs. 124 * It is available for ENETC_PSIIER and ENETC_PSIIDR registers. 125 */ 126 #define ENETC_VFFLR_MASK(n) \ 127 ({ typeof(n) _n = (n); (_n) ? GENMASK(16 + (_n), 17) : 0; }) 128 129 /* VF FLR interrupt bit, n is VF index. It is available 130 * for ENETC_PSIIER and ENETC_PSIIDR registers. 131 */ 132 #define ENETC_VFFLR_BIT(n) BIT(17 + (n)) 133 134 #define ENETC_SITXIDR 0xa18 135 #define ENETC_SIRXIDR 0xa28 136 #define ENETC_SIMSIVR 0xa30 137 138 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 139 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 140 141 #define ENETC_SIUEFDCR 0xe28 142 143 #define ENETC_SIRFSCAPR 0x1200 144 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 145 #define ENETC_SIRSSCAPR 0x1600 146 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 147 148 /** SI BDR sub-blocks, n = 0..7 */ 149 enum enetc_bdr_type {TX, RX}; 150 #define ENETC_BDR_OFF(i) ((i) * 0x200) 151 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 152 /* RX BDR reg offsets */ 153 #define ENETC_RBMR 0 154 #define ENETC_RBMR_BDS BIT(2) 155 #define ENETC_RBMR_CM BIT(4) 156 #define ENETC_RBMR_VTE BIT(5) 157 #define ENETC_RBMR_EN BIT(31) 158 #define ENETC_RBSR 0x4 159 #define ENETC_RBBSR 0x8 160 #define ENETC_RBCIR 0xc 161 #define ENETC_RBBAR0 0x10 162 #define ENETC_RBBAR1 0x14 163 #define ENETC_RBPIR 0x18 164 #define ENETC_RBLENR 0x20 165 #define ENETC_RBIER 0xa0 166 #define ENETC_RBIER_RXTIE BIT(0) 167 #define ENETC_RBIDR 0xa4 168 #define ENETC_RBICR0 0xa8 169 #define ENETC_RBICR0_ICEN BIT(31) 170 #define ENETC_RBICR0_ICPT_MASK 0x1ff 171 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 172 #define ENETC_RBICR1 0xac 173 174 /* TX BDR reg offsets */ 175 #define ENETC_TBMR 0 176 #define ENETC_TBSR_BUSY BIT(0) 177 #define ENETC_TBMR_VIH BIT(9) 178 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 179 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 180 #define ENETC_TBMR_EN BIT(31) 181 #define ENETC_TBSR 0x4 182 #define ENETC_TBBAR0 0x10 183 #define ENETC_TBBAR1 0x14 184 #define ENETC_TBPIR 0x18 185 #define ENETC_TBCIR 0x1c 186 #define ENETC_TBCIR_IDX_MASK 0xffff 187 #define ENETC_TBLENR 0x20 188 #define ENETC_TBIER 0xa0 189 #define ENETC_TBIER_TXTIE BIT(0) 190 #define ENETC_TBIDR 0xa4 191 #define ENETC_TBICR0 0xa8 192 #define ENETC_TBICR0_ICEN BIT(31) 193 #define ENETC_TBICR0_ICPT_MASK 0xf 194 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 195 #define ENETC_TBICR1 0xac 196 197 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 198 199 /* Port regs, offset: 1_0000h */ 200 #define ENETC_PORT_BASE 0x10000 201 #define ENETC_PMR 0x0000 202 #define ENETC_PMR_EN GENMASK(18, 16) 203 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 204 #define ENETC_PMR_PSPEED_10M 0 205 #define ENETC_PMR_PSPEED_100M BIT(8) 206 #define ENETC_PMR_PSPEED_1000M BIT(9) 207 #define ENETC_PMR_PSPEED_2500M BIT(10) 208 #define ENETC_PSR 0x0004 /* RO */ 209 #define ENETC_PSIPMMR 0x0018 210 #define PSIPMMR_SI_MAC_UP(n) BIT(n) /* n = SI index */ 211 #define PSIPMMR_SI_MAC_MP(n) BIT((n) + 16) 212 213 #define ENETC_PSIPVMR 0x001c 214 #define PSIPVMR_SI_VLAN_P(n) BIT(n) /* n = SI index */ 215 216 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 217 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 218 #define ENETC_PVCLCTR 0x0208 219 #define ENETC_PCVLANR1 0x0210 220 #define ENETC_PCVLANR2 0x0214 221 #define ENETC_VLAN_TYPE_C BIT(0) 222 #define ENETC_VLAN_TYPE_S BIT(1) 223 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 224 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 225 #define ENETC_PSIVLAN_EN BIT(31) 226 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 227 #define ENETC_PPAUONTR 0x0410 228 #define ENETC_PPAUOFFTR 0x0414 229 #define ENETC_PTXMBAR 0x0608 230 #define ENETC_PCAPR0 0x0900 231 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 232 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 233 #define ENETC_PCAPR0_PSFP BIT(9) 234 #define ENETC_PCAPR0_QBV BIT(4) 235 #define ENETC_PCAPR0_QBU BIT(3) 236 #define ENETC_PCAPR1 0x0904 237 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 238 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 239 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 240 #define ENETC_PSICFGR0_VTE BIT(12) 241 #define ENETC_PSICFGR0_SIVIE BIT(14) 242 #define ENETC_PSICFGR0_ASE BIT(15) 243 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 244 245 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 246 #define ENETC_CBSE BIT(31) 247 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 248 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 249 #define ENETC_RSSHASH_KEY_SIZE 40 250 #define ENETC_PRSSCAPR 0x1404 251 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 252 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 253 #define ENETC_PSIVLANFMR 0x1700 254 #define ENETC_PSIVLANFMR_VS BIT(0) 255 #define ENETC_PRFSMR 0x1800 256 #define ENETC_PRFSMR_RFSE BIT(31) 257 #define ENETC_PRFSCAPR 0x1804 258 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 259 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 260 #define ENETC_PFPMR 0x1900 261 #define ENETC_PFPMR_PMACE BIT(1) 262 #define ENETC_EMDIO_BASE 0x1c00 263 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 264 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 265 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 266 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 267 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 268 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 269 #define ENETC_MMCSR 0x1f00 270 #define ENETC_MMCSR_LINK_FAIL BIT(31) 271 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */ 272 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK) 273 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23) 274 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */ 275 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21) 276 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */ 277 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18) 278 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */ 279 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */ 280 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */ 281 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK) 282 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8) 283 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */ 284 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3) 285 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */ 286 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */ 287 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */ 288 #define ENETC_MMFAECR 0x1f08 289 #define ENETC_MMFSECR 0x1f0c 290 #define ENETC_MMFAOCR 0x1f10 291 #define ENETC_MMFCRXR 0x1f14 292 #define ENETC_MMFCTXR 0x1f18 293 #define ENETC_MMHCR 0x1f1c 294 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 295 296 #define ENETC_PMAC_OFFSET 0x1000 297 298 #define ENETC_PM0_CMD_CFG 0x8008 299 #define ENETC_PM0_TX_EN BIT(0) 300 #define ENETC_PM0_RX_EN BIT(1) 301 #define ENETC_PM0_PROMISC BIT(4) 302 #define ENETC_PM0_PAUSE_IGN BIT(8) 303 #define ENETC_PM0_CMD_XGLP BIT(10) 304 #define ENETC_PM0_CMD_TXP BIT(11) 305 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 306 #define ENETC_PM0_CMD_SFD BIT(21) 307 #define ENETC_PM0_MAXFRM 0x8014 308 #define ENETC_SET_TX_MTU(val) ((val) << 16) 309 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 310 #define ENETC_PM0_RX_FIFO 0x801c 311 #define ENETC_PM0_RX_FIFO_VAL 1 312 313 #define ENETC_PM_IMDIO_BASE 0x8030 314 315 #define ENETC_PM0_PAUSE_QUANTA 0x8054 316 #define ENETC_PM0_PAUSE_THRESH 0x8064 317 318 #define ENETC_PM0_SINGLE_STEP 0x80c0 319 #define ENETC_PM0_SINGLE_STEP_CH BIT(7) 320 #define ENETC_PM0_SINGLE_STEP_EN BIT(31) 321 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8) 322 323 #define ENETC_PM0_IF_MODE 0x8300 324 #define ENETC_PM0_IFM_RG BIT(2) 325 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 326 #define ENETC_PM0_IFM_EN_AUTO BIT(15) 327 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13) 328 #define ENETC_PM0_IFM_SSP_1000 (2 << 13) 329 #define ENETC_PM0_IFM_SSP_100 (0 << 13) 330 #define ENETC_PM0_IFM_SSP_10 (1 << 13) 331 #define ENETC_PM0_IFM_FULL_DPX BIT(12) 332 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0) 333 #define ENETC_PM0_IFM_IFMODE_XGMII 0 334 #define ENETC_PM0_IFM_IFMODE_GMII 2 335 #define ENETC_PSIDCAPR 0x1b08 336 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 337 #define ENETC_PSFCAPR 0x1b18 338 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 339 #define ENETC_PSGCAPR 0x1b28 340 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 341 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 342 #define ENETC_PFMCAPR 0x1b38 343 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 344 345 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and 346 * Port MAC 1 to the pMAC. 347 */ 348 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac)) 349 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac)) 350 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac)) 351 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac)) 352 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac)) 353 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac)) 354 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac)) 355 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac)) 356 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac)) 357 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac)) 358 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac)) 359 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac)) 360 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac)) 361 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac)) 362 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac)) 363 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac)) 364 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac)) 365 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac)) 366 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac)) 367 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac)) 368 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac)) 369 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac)) 370 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac)) 371 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac)) 372 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac)) 373 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac)) 374 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac)) 375 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac)) 376 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac)) 377 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac)) 378 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac)) 379 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac)) 380 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac)) 381 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac)) 382 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac)) 383 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac)) 384 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac)) 385 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac)) 386 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac)) 387 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac)) 388 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac)) 389 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac)) 390 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac)) 391 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac)) 392 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac)) 393 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac)) 394 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac)) 395 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac)) 396 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac)) 397 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac)) 398 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac)) 399 400 /* Port counters */ 401 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 402 #define ENETC_PBFDSIR 0x0810 403 #define ENETC_PFDMSAPR 0x0814 404 #define ENETC_UFDMF 0x1680 405 #define ENETC_MFDMF 0x1684 406 #define ENETC_PUFDVFR 0x1780 407 #define ENETC_PMFDVFR 0x1784 408 #define ENETC_PBFDVFR 0x1788 409 410 /** Global regs, offset: 2_0000h */ 411 #define ENETC_GLOBAL_BASE 0x20000 412 #define ENETC_G_EIPBRR0 0x0bf8 413 #define EIPBRR0_REVISION GENMASK(15, 0) 414 #define ENETC_REV_1_0 0x0100 415 #define ENETC_REV_4_1 0X0401 416 #define ENETC_REV_4_3 0x0403 417 418 #define ENETC_G_EIPBRR1 0x0bfc 419 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 420 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 421 422 /* PCI device info */ 423 struct enetc_hw { 424 /* SI registers, used by all PCI functions */ 425 void __iomem *reg; 426 /* Port registers, PF only */ 427 void __iomem *port; 428 /* IP global registers, PF only */ 429 void __iomem *global; 430 }; 431 432 /* ENETC register accessors */ 433 434 /* MDIO issue workaround (on LS1028A) - 435 * Due to a hardware issue, an access to MDIO registers 436 * that is concurrent with other ENETC register accesses 437 * may lead to the MDIO access being dropped or corrupted. 438 * To protect the MDIO accesses a readers-writers locking 439 * scheme is used, where the MDIO register accesses are 440 * protected by write locks to insure exclusivity, while 441 * the remaining ENETC registers are accessed under read 442 * locks since they only compete with MDIO accesses. 443 */ 444 extern rwlock_t enetc_mdio_lock; 445 446 DECLARE_STATIC_KEY_FALSE(enetc_has_err050089); 447 448 /* use this locking primitive only on the fast datapath to 449 * group together multiple non-MDIO register accesses to 450 * minimize the overhead of the lock 451 */ 452 static inline void enetc_lock_mdio(void) 453 { 454 if (static_branch_unlikely(&enetc_has_err050089)) 455 read_lock(&enetc_mdio_lock); 456 } 457 458 static inline void enetc_unlock_mdio(void) 459 { 460 if (static_branch_unlikely(&enetc_has_err050089)) 461 read_unlock(&enetc_mdio_lock); 462 } 463 464 /* use these accessors only on the fast datapath under 465 * the enetc_lock_mdio() locking primitive to minimize 466 * the overhead of the lock 467 */ 468 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 469 { 470 if (static_branch_unlikely(&enetc_has_err050089)) 471 lockdep_assert_held(&enetc_mdio_lock); 472 473 return ioread32(reg); 474 } 475 476 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 477 { 478 if (static_branch_unlikely(&enetc_has_err050089)) 479 lockdep_assert_held(&enetc_mdio_lock); 480 481 iowrite32(val, reg); 482 } 483 484 /* internal helpers for the MDIO w/a */ 485 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 486 { 487 u32 val; 488 489 enetc_lock_mdio(); 490 val = ioread32(reg); 491 enetc_unlock_mdio(); 492 493 return val; 494 } 495 496 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 497 { 498 enetc_lock_mdio(); 499 iowrite32(val, reg); 500 enetc_unlock_mdio(); 501 } 502 503 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 504 { 505 unsigned long flags; 506 u32 val; 507 508 if (static_branch_unlikely(&enetc_has_err050089)) { 509 write_lock_irqsave(&enetc_mdio_lock, flags); 510 val = ioread32(reg); 511 write_unlock_irqrestore(&enetc_mdio_lock, flags); 512 } else { 513 val = ioread32(reg); 514 } 515 516 return val; 517 } 518 519 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 520 { 521 unsigned long flags; 522 523 if (static_branch_unlikely(&enetc_has_err050089)) { 524 write_lock_irqsave(&enetc_mdio_lock, flags); 525 iowrite32(val, reg); 526 write_unlock_irqrestore(&enetc_mdio_lock, flags); 527 } else { 528 iowrite32(val, reg); 529 } 530 } 531 532 #ifdef ioread64 533 static inline u64 _enetc_rd_reg64(void __iomem *reg) 534 { 535 return ioread64(reg); 536 } 537 #else 538 /* using this to read out stats on 32b systems */ 539 static inline u64 _enetc_rd_reg64(void __iomem *reg) 540 { 541 u32 low, high, tmp; 542 543 do { 544 high = ioread32(reg + 4); 545 low = ioread32(reg); 546 tmp = ioread32(reg + 4); 547 } while (high != tmp); 548 549 return (u64)high << 32 | low; 550 } 551 #endif 552 553 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 554 { 555 u64 val; 556 557 enetc_lock_mdio(); 558 val = _enetc_rd_reg64(reg); 559 enetc_unlock_mdio(); 560 561 return val; 562 } 563 564 /* general register accessors */ 565 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 566 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 567 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 568 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 569 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off)) 570 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val) 571 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 572 /* port register accessors - PF only */ 573 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 574 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 575 #define enetc_port_rd64(hw, off) _enetc_rd_reg64_wa((hw)->port + (off)) 576 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 577 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 578 (hw)->port + (off), val) 579 /* global register accessors - PF only */ 580 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 581 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 582 /* BDR register accessors, see ENETC_BDR() */ 583 #define enetc_bdr_rd(hw, t, n, off) \ 584 enetc_rd(hw, ENETC_BDR(t, n, off)) 585 #define enetc_bdr_wr(hw, t, n, off, val) \ 586 enetc_wr(hw, ENETC_BDR(t, n, off), val) 587 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 588 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 589 #define enetc_txbdr_wr(hw, n, off, val) \ 590 enetc_bdr_wr(hw, TX, n, off, val) 591 #define enetc_rxbdr_wr(hw, n, off, val) \ 592 enetc_bdr_wr(hw, RX, n, off, val) 593 594 /* Buffer Descriptors (BD) */ 595 union enetc_tx_bd { 596 struct { 597 __le64 addr; 598 union { 599 __le16 buf_len; 600 __le16 hdr_len; /* For LSO, ENETC 4.1 and later */ 601 }; 602 __le16 frm_len; 603 union { 604 struct { 605 u8 l3_aux0; 606 #define ENETC_TX_BD_L3_START GENMASK(6, 0) 607 #define ENETC_TX_BD_IPCS BIT(7) 608 u8 l3_aux1; 609 #define ENETC_TX_BD_L3_HDR_LEN GENMASK(6, 0) 610 #define ENETC_TX_BD_L3T BIT(7) 611 u8 l4_aux; 612 #define ENETC_TX_BD_L4T GENMASK(7, 5) 613 #define ENETC_TXBD_L4T_UDP 1 614 #define ENETC_TXBD_L4T_TCP 2 615 u8 flags; 616 }; /* default layout */ 617 __le32 txstart; 618 __le32 lstatus; 619 }; 620 }; 621 struct { 622 __le32 tstamp; 623 __le16 tpid; 624 __le16 vid; 625 __le16 lso_sg_size; /* For ENETC 4.1 and later */ 626 __le16 frm_len_ext; /* For ENETC 4.1 and later */ 627 u8 reserved[2]; 628 u8 e_flags; 629 u8 flags; 630 } ext; /* Tx BD extension */ 631 struct { 632 __le32 tstamp; 633 u8 reserved[8]; 634 __le16 lso_err_count; /* For ENETC 4.1 and later */ 635 u8 status; 636 u8 flags; 637 } wb; /* writeback descriptor */ 638 }; 639 640 enum enetc_txbd_flags { 641 ENETC_TXBD_FLAGS_L4CS = BIT(0), /* For ENETC 4.1 and later */ 642 ENETC_TXBD_FLAGS_TSE = BIT(1), 643 ENETC_TXBD_FLAGS_LSO = BIT(1), /* For ENETC 4.1 and later */ 644 ENETC_TXBD_FLAGS_W = BIT(2), 645 ENETC_TXBD_FLAGS_CSUM_LSO = BIT(3), /* For ENETC 4.1 and later */ 646 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 647 ENETC_TXBD_FLAGS_EX = BIT(6), 648 ENETC_TXBD_FLAGS_F = BIT(7) 649 }; 650 #define ENETC_TXBD_STATS_WIN BIT(7) 651 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 652 #define ENETC_TXBD_FLAGS_OFFSET 24 653 #define ENETC_TXBD_TSTAMP GENMASK(29, 0) 654 655 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 656 { 657 u32 temp; 658 659 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 660 (flags << ENETC_TXBD_FLAGS_OFFSET); 661 662 return cpu_to_le32(temp); 663 } 664 665 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 666 { 667 memset(txbd, 0, sizeof(*txbd)); 668 } 669 670 /* Extension flags */ 671 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 672 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1) 673 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 674 675 union enetc_rx_bd { 676 struct { 677 __le64 addr; 678 u8 reserved[8]; 679 } w; 680 struct { 681 __le16 inet_csum; 682 __le16 parse_summary; 683 __le32 rss_hash; 684 __le16 buf_len; 685 __le16 vlan_opt; 686 union { 687 struct { 688 __le16 flags; 689 __le16 error; 690 }; 691 __le32 lstatus; 692 }; 693 } r; 694 struct { 695 __le32 tstamp; 696 u8 reserved[12]; 697 } ext; 698 }; 699 700 #define ENETC_RXBD_LSTATUS_R BIT(30) 701 #define ENETC_RXBD_LSTATUS_F BIT(31) 702 #define ENETC_RXBD_ERR_MASK 0xff 703 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 704 #define ENETC_RXBD_FLAG_VLAN BIT(9) 705 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 706 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0) 707 708 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 709 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 710 711 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 712 #define ENETC_CBD_STATUS_MASK 0xf 713 714 #define ENETC_TPID_8021Q 0 715 716 struct enetc_cmd_rfse { 717 u8 smac_h[6]; 718 u8 smac_m[6]; 719 u8 dmac_h[6]; 720 u8 dmac_m[6]; 721 __be32 sip_h[4]; 722 __be32 sip_m[4]; 723 __be32 dip_h[4]; 724 __be32 dip_m[4]; 725 u16 ethtype_h; 726 u16 ethtype_m; 727 u16 ethtype4_h; 728 u16 ethtype4_m; 729 u16 sport_h; 730 u16 sport_m; 731 u16 dport_h; 732 u16 dport_m; 733 u16 vlan_h; 734 u16 vlan_m; 735 u8 proto_h; 736 u8 proto_m; 737 u16 flags; 738 u16 result; 739 u16 mode; 740 }; 741 742 #define ENETC_RFSE_EN BIT(15) 743 #define ENETC_RFSE_MODE_BD 2 744 745 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) 746 { 747 u32 upper; 748 u16 lower; 749 750 upper = __raw_readl(hw->reg + ENETC_SIPMAR0); 751 lower = __raw_readl(hw->reg + ENETC_SIPMAR1); 752 753 put_unaligned_le32(upper, addr); 754 put_unaligned_le16(lower, addr + 4); 755 } 756 757 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw, 758 struct net_device *ndev) 759 { 760 u8 addr[ETH_ALEN]; 761 762 enetc_get_primary_mac_addr(hw, addr); 763 eth_hw_addr_set(ndev, addr); 764 } 765 766 #define ENETC_SI_INT_IDX 0 767 /* base index for Rx/Tx interrupts */ 768 #define ENETC_BDR_INT_BASE_IDX 1 769 770 /* Messaging */ 771 772 /* Command completion status */ 773 enum enetc_msg_cmd_status { 774 ENETC_MSG_CMD_STATUS_OK, 775 ENETC_MSG_CMD_STATUS_FAIL 776 }; 777 778 /* VSI-PSI command message types */ 779 enum enetc_msg_cmd_type { 780 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 781 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 782 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 783 }; 784 785 /* VSI-PSI command action types */ 786 enum enetc_msg_cmd_action_type { 787 ENETC_MSG_CMD_MNG_ADD = 1, 788 ENETC_MSG_CMD_MNG_REMOVE 789 }; 790 791 /* PSI-VSI command header format */ 792 struct enetc_msg_cmd_header { 793 u16 type; /* command class type */ 794 u16 id; /* denotes the specific required action */ 795 }; 796 797 /* Common H/W utility functions */ 798 799 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 800 bool en) 801 { 802 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 803 804 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 805 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 806 } 807 808 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 809 bool en) 810 { 811 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 812 813 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 814 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 815 } 816 817 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 818 int prio) 819 { 820 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 821 822 val &= ~ENETC_TBMR_PRIO_MASK; 823 val |= ENETC_TBMR_SET_PRIO(prio); 824 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 825 } 826 827 enum bdcr_cmd_class { 828 BDCR_CMD_UNSPEC = 0, 829 BDCR_CMD_MAC_FILTER, 830 BDCR_CMD_VLAN_FILTER, 831 BDCR_CMD_RSS, 832 BDCR_CMD_RFS, 833 BDCR_CMD_PORT_GCL, 834 BDCR_CMD_RECV_CLASSIFIER, 835 BDCR_CMD_STREAM_IDENTIFY, 836 BDCR_CMD_STREAM_FILTER, 837 BDCR_CMD_STREAM_GCL, 838 BDCR_CMD_FLOW_METER, 839 __BDCR_CMD_MAX_LEN, 840 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 841 }; 842 843 /* class 5, command 0 */ 844 struct tgs_gcl_conf { 845 u8 atc; /* init gate value */ 846 u8 res[7]; 847 struct { 848 u8 res1[4]; 849 __le16 acl_len; 850 u8 res2[2]; 851 }; 852 }; 853 854 /* gate control list entry */ 855 struct gce { 856 __le32 period; 857 u8 gate; 858 u8 res[3]; 859 }; 860 861 /* tgs_gcl_conf address point to this data space */ 862 struct tgs_gcl_data { 863 __le32 btl; 864 __le32 bth; 865 __le32 ct; 866 __le32 cte; 867 struct gce entry[]; 868 }; 869 870 /* class 7, command 0, Stream Identity Entry Configuration */ 871 struct streamid_conf { 872 __le32 stream_handle; /* init gate value */ 873 __le32 iports; 874 u8 id_type; 875 u8 oui[3]; 876 u8 res[3]; 877 u8 en; 878 }; 879 880 #define ENETC_CBDR_SID_VID_MASK 0xfff 881 #define ENETC_CBDR_SID_VIDM BIT(12) 882 #define ENETC_CBDR_SID_TG_MASK 0xc000 883 /* streamid_conf address point to this data space */ 884 struct streamid_data { 885 union { 886 u8 dmac[6]; 887 u8 smac[6]; 888 }; 889 u16 vid_vidm_tg; 890 }; 891 892 #define ENETC_CBDR_SFI_PRI_MASK 0x7 893 #define ENETC_CBDR_SFI_PRIM BIT(3) 894 #define ENETC_CBDR_SFI_BLOV BIT(4) 895 #define ENETC_CBDR_SFI_BLEN BIT(5) 896 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 897 #define ENETC_CBDR_SFI_FMITEN BIT(7) 898 #define ENETC_CBDR_SFI_ENABLE BIT(7) 899 /* class 8, command 0, Stream Filter Instance, Short Format */ 900 struct sfi_conf { 901 __le32 stream_handle; 902 u8 multi; 903 u8 res[2]; 904 u8 sthm; 905 /* Max Service Data Unit or Flow Meter Instance Table index. 906 * Depending on the value of FLT this represents either Max 907 * Service Data Unit (max frame size) allowed by the filter 908 * entry or is an index into the Flow Meter Instance table 909 * index identifying the policer which will be used to police 910 * it. 911 */ 912 __le16 fm_inst_table_index; 913 __le16 msdu; 914 __le16 sg_inst_table_index; 915 u8 res1[2]; 916 __le32 input_ports; 917 u8 res2[3]; 918 u8 en; 919 }; 920 921 /* class 8, command 2 stream Filter Instance status query short format 922 * command no need structure define 923 * Stream Filter Instance Query Statistics Response data 924 */ 925 struct sfi_counter_data { 926 u32 matchl; 927 u32 matchh; 928 u32 msdu_dropl; 929 u32 msdu_droph; 930 u32 stream_gate_dropl; 931 u32 stream_gate_droph; 932 u32 flow_meter_dropl; 933 u32 flow_meter_droph; 934 }; 935 936 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 937 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 938 #define ENETC_CBDR_SGI_CGTST BIT(6) 939 #define ENETC_CBDR_SGI_OGTST BIT(7) 940 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 941 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 942 #define ENETC_CBDR_SGI_OEX BIT(4) 943 #define ENETC_CBDR_SGI_OEXEN BIT(5) 944 #define ENETC_CBDR_SGI_IRX BIT(6) 945 #define ENETC_CBDR_SGI_IRXEN BIT(7) 946 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 947 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 948 #define ENETC_CBDR_SGI_EN BIT(7) 949 /* class 9, command 0, Stream Gate Instance Table, Short Format 950 * class 9, command 2, Stream Gate Instance Table entry query write back 951 * Short Format 952 */ 953 struct sgi_table { 954 u8 res[8]; 955 u8 oipv; 956 u8 res0[2]; 957 u8 ocgtst; 958 u8 res1[7]; 959 u8 gset; 960 u8 oacl_len; 961 u8 res2[2]; 962 u8 en; 963 }; 964 965 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 966 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 967 #define ENETC_CBDR_SGI_AGTST BIT(7) 968 969 /* class 9, command 1, Stream Gate Control List, Long Format */ 970 struct sgcl_conf { 971 u8 aipv; 972 u8 res[2]; 973 u8 agtst; 974 u8 res1[4]; 975 union { 976 struct { 977 u8 res2[4]; 978 u8 acl_len; 979 u8 res3[3]; 980 }; 981 u8 cct[8]; /* Config change time */ 982 }; 983 }; 984 985 #define ENETC_CBDR_SGL_IOMEN BIT(0) 986 #define ENETC_CBDR_SGL_IPVEN BIT(3) 987 #define ENETC_CBDR_SGL_GTST BIT(4) 988 #define ENETC_CBDR_SGL_IPV_MASK 0xe 989 /* Stream Gate Control List Entry */ 990 struct sgce { 991 u32 interval; 992 u8 msdu[3]; 993 u8 multi; 994 }; 995 996 /* stream control list class 9 , cmd 1 data buffer */ 997 struct sgcl_data { 998 u32 btl; 999 u32 bth; 1000 u32 ct; 1001 u32 cte; 1002 struct sgce sgcl[]; 1003 }; 1004 1005 #define ENETC_CBDR_FMI_MR BIT(0) 1006 #define ENETC_CBDR_FMI_MREN BIT(1) 1007 #define ENETC_CBDR_FMI_DOY BIT(2) 1008 #define ENETC_CBDR_FMI_CM BIT(3) 1009 #define ENETC_CBDR_FMI_CF BIT(4) 1010 #define ENETC_CBDR_FMI_NDOR BIT(5) 1011 #define ENETC_CBDR_FMI_OALEN BIT(6) 1012 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 1013 1014 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 1015 struct fmi_conf { 1016 __le32 cir; 1017 __le32 cbs; 1018 __le32 eir; 1019 __le32 ebs; 1020 u8 conf; 1021 u8 res1; 1022 u8 ir_fpp; 1023 u8 res2[4]; 1024 u8 en; 1025 }; 1026 1027 struct enetc_cbd { 1028 union{ 1029 struct sfi_conf sfi_conf; 1030 struct sgi_table sgi_table; 1031 struct fmi_conf fmi_conf; 1032 struct { 1033 __le32 addr[2]; 1034 union { 1035 __le32 opt[4]; 1036 struct tgs_gcl_conf gcl_conf; 1037 struct streamid_conf sid_set; 1038 struct sgcl_conf sgcl_conf; 1039 }; 1040 }; /* Long format */ 1041 __le32 data[6]; 1042 }; 1043 __le16 index; 1044 __le16 length; 1045 u8 cmd; 1046 u8 cls; 1047 u8 _res; 1048 u8 status_flags; 1049 }; 1050 1051 #define ENETC_CLK_400M 400000000ULL 1052 #define ENETC_CLK_333M 333000000ULL 1053 1054 static inline u32 enetc_cycles_to_usecs(u32 cycles, u64 clk_freq) 1055 { 1056 return (u32)div_u64(cycles * 1000000ULL, clk_freq); 1057 } 1058 1059 static inline u32 enetc_usecs_to_cycles(u32 usecs, u64 clk_freq) 1060 { 1061 return (u32)div_u64(usecs * clk_freq, 1000000ULL); 1062 } 1063 1064 /* Port traffic class frame preemption register */ 1065 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */ 1066 #define ENETC_PTCFPR_FPE BIT(31) 1067 1068 /* port time gating control register */ 1069 #define ENETC_PTGCR 0x11a00 1070 #define ENETC_PTGCR_TGE BIT(31) 1071 #define ENETC_PTGCR_TGPE BIT(30) 1072 1073 /* Port time gating capability register */ 1074 #define ENETC_PTGCAPR 0x11a08 1075 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0) 1076 1077 /* Port time specific departure */ 1078 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 1079 #define ENETC_TSDE BIT(31) 1080 1081 /* PSFP setting */ 1082 #define ENETC_PPSFPMR 0x11b00 1083 #define ENETC_PPSFPMR_PSFPEN BIT(0) 1084 #define ENETC_PPSFPMR_VS BIT(1) 1085 #define ENETC_PPSFPMR_PVC BIT(2) 1086 #define ENETC_PPSFPMR_PVZC BIT(3) 1087