1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of_address.h>
18 #include <linux/of_pci.h>
19 #include <linux/of_platform.h>
20 #include <linux/pci.h>
21 #include <linux/pci-ecam.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/irqchip/chained_irq.h>
25
26 #include "../pci.h"
27
28 /* Bridge core config registers */
29 #define BRCFG_PCIE_RX0 0x00000000
30 #define BRCFG_PCIE_RX1 0x00000004
31 #define BRCFG_INTERRUPT 0x00000010
32 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
33
34 /* Egress - Bridge translation registers */
35 #define E_BREG_CAPABILITIES 0x00000200
36 #define E_BREG_CONTROL 0x00000208
37 #define E_BREG_BASE_LO 0x00000210
38 #define E_BREG_BASE_HI 0x00000214
39 #define E_ECAM_CAPABILITIES 0x00000220
40 #define E_ECAM_CONTROL 0x00000228
41 #define E_ECAM_BASE_LO 0x00000230
42 #define E_ECAM_BASE_HI 0x00000234
43
44 /* Ingress - address translations */
45 #define I_MSII_CAPABILITIES 0x00000300
46 #define I_MSII_CONTROL 0x00000308
47 #define I_MSII_BASE_LO 0x00000310
48 #define I_MSII_BASE_HI 0x00000314
49
50 #define I_ISUB_CONTROL 0x000003E8
51 #define SET_ISUB_CONTROL BIT(0)
52 /* Rxed msg fifo - Interrupt status registers */
53 #define MSGF_MISC_STATUS 0x00000400
54 #define MSGF_MISC_MASK 0x00000404
55 #define MSGF_LEG_STATUS 0x00000420
56 #define MSGF_LEG_MASK 0x00000424
57 #define MSGF_MSI_STATUS_LO 0x00000440
58 #define MSGF_MSI_STATUS_HI 0x00000444
59 #define MSGF_MSI_MASK_LO 0x00000448
60 #define MSGF_MSI_MASK_HI 0x0000044C
61
62 /* Msg filter mask bits */
63 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
64 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
65 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
66 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
67 CFG_ENABLE_INT_MSG_FWD | \
68 CFG_ENABLE_ERR_MSG_FWD)
69
70 /* Misc interrupt status mask bits */
71 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
72 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
73 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
74 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
75 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
76 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
77 #define MSGF_MISC_SR_FATAL_AER BIT(16)
78 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
79 #define MSGF_MISC_SR_CORR_AER BIT(18)
80 #define MSGF_MISC_SR_UR_DETECT BIT(20)
81 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
82 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
83 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
84 #define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25)
85 #define MSGF_MISC_SR_LINK_BWIDTH BIT(26)
86
87 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
88 MSGF_MISC_SR_RXMSG_OVER | \
89 MSGF_MISC_SR_SLAVE_ERR | \
90 MSGF_MISC_SR_MASTER_ERR | \
91 MSGF_MISC_SR_I_ADDR_ERR | \
92 MSGF_MISC_SR_E_ADDR_ERR | \
93 MSGF_MISC_SR_FATAL_AER | \
94 MSGF_MISC_SR_NON_FATAL_AER | \
95 MSGF_MISC_SR_CORR_AER | \
96 MSGF_MISC_SR_UR_DETECT | \
97 MSGF_MISC_SR_NON_FATAL_DEV | \
98 MSGF_MISC_SR_FATAL_DEV | \
99 MSGF_MISC_SR_LINK_DOWN | \
100 MSGF_MISC_SR_LINK_AUTO_BWIDTH | \
101 MSGF_MISC_SR_LINK_BWIDTH)
102
103 /* Legacy interrupt status mask bits */
104 #define MSGF_LEG_SR_INTA BIT(0)
105 #define MSGF_LEG_SR_INTB BIT(1)
106 #define MSGF_LEG_SR_INTC BIT(2)
107 #define MSGF_LEG_SR_INTD BIT(3)
108 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
109 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
110
111 /* MSI interrupt status mask bits */
112 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
113 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
114
115 #define MSII_PRESENT BIT(0)
116 #define MSII_ENABLE BIT(0)
117 #define MSII_STATUS_ENABLE BIT(15)
118
119 /* Bridge config interrupt mask */
120 #define BRCFG_INTERRUPT_MASK BIT(0)
121 #define BREG_PRESENT BIT(0)
122 #define BREG_ENABLE BIT(0)
123 #define BREG_ENABLE_FORCE BIT(1)
124
125 /* E_ECAM status mask bits */
126 #define E_ECAM_PRESENT BIT(0)
127 #define E_ECAM_CR_ENABLE BIT(0)
128 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
129 #define E_ECAM_SIZE_SHIFT 16
130 #define NWL_ECAM_MAX_SIZE 16
131
132 #define CFG_DMA_REG_BAR GENMASK(2, 0)
133 #define CFG_PCIE_CACHE GENMASK(7, 0)
134
135 #define INT_PCI_MSI_NR (2 * 32)
136
137 /* Readin the PS_LINKUP */
138 #define PS_LINKUP_OFFSET 0x00000238
139 #define PCIE_PHY_LINKUP_BIT BIT(0)
140 #define PHY_RDY_LINKUP_BIT BIT(1)
141
142 /* Parameters for the waiting for link up routine */
143 #define LINK_WAIT_MAX_RETRIES 10
144 #define LINK_WAIT_USLEEP_MIN 90000
145 #define LINK_WAIT_USLEEP_MAX 100000
146
147 struct nwl_msi { /* MSI information */
148 struct irq_domain *msi_domain;
149 DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
150 struct irq_domain *dev_domain;
151 struct mutex lock; /* protect bitmap variable */
152 int irq_msi0;
153 int irq_msi1;
154 };
155
156 struct nwl_pcie {
157 struct device *dev;
158 void __iomem *breg_base;
159 void __iomem *pcireg_base;
160 void __iomem *ecam_base;
161 struct phy *phy[4];
162 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
164 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
165 u32 breg_size;
166 u32 pcie_reg_size;
167 u32 ecam_size;
168 int irq_intx;
169 int irq_misc;
170 struct nwl_msi msi;
171 struct irq_domain *intx_irq_domain;
172 struct clk *clk;
173 raw_spinlock_t leg_mask_lock;
174 };
175
nwl_bridge_readl(struct nwl_pcie * pcie,u32 off)176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
177 {
178 return readl(pcie->breg_base + off);
179 }
180
nwl_bridge_writel(struct nwl_pcie * pcie,u32 val,u32 off)181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
182 {
183 writel(val, pcie->breg_base + off);
184 }
185
nwl_pcie_link_up(struct nwl_pcie * pcie)186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
187 {
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
189 return true;
190 return false;
191 }
192
nwl_phy_link_up(struct nwl_pcie * pcie)193 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
194 {
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
196 return true;
197 return false;
198 }
199
nwl_wait_for_link(struct nwl_pcie * pcie)200 static int nwl_wait_for_link(struct nwl_pcie *pcie)
201 {
202 struct device *dev = pcie->dev;
203 int retries;
204
205 /* check if the link is up or not */
206 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
207 if (nwl_phy_link_up(pcie))
208 return 0;
209 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
210 }
211
212 dev_err(dev, "PHY link never came up\n");
213 return -ETIMEDOUT;
214 }
215
nwl_pcie_valid_device(struct pci_bus * bus,unsigned int devfn)216 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
217 {
218 struct nwl_pcie *pcie = bus->sysdata;
219
220 /* Check link before accessing downstream ports */
221 if (!pci_is_root_bus(bus)) {
222 if (!nwl_pcie_link_up(pcie))
223 return false;
224 } else if (devfn > 0)
225 /* Only one device down on each root port */
226 return false;
227
228 return true;
229 }
230
231 /**
232 * nwl_pcie_map_bus - Get configuration base
233 *
234 * @bus: Bus structure of current bus
235 * @devfn: Device/function
236 * @where: Offset from base
237 *
238 * Return: Base address of the configuration space needed to be
239 * accessed.
240 */
nwl_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)241 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
242 int where)
243 {
244 struct nwl_pcie *pcie = bus->sysdata;
245
246 if (!nwl_pcie_valid_device(bus, devfn))
247 return NULL;
248
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
250 }
251
252 /* PCIe operations */
253 static struct pci_ops nwl_pcie_ops = {
254 .map_bus = nwl_pcie_map_bus,
255 .read = pci_generic_config_read,
256 .write = pci_generic_config_write,
257 };
258
nwl_pcie_misc_handler(int irq,void * data)259 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
260 {
261 struct nwl_pcie *pcie = data;
262 struct device *dev = pcie->dev;
263 u32 misc_stat;
264
265 /* Checking for misc interrupts */
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
267 MSGF_MISC_SR_MASKALL;
268 if (!misc_stat)
269 return IRQ_NONE;
270
271 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
272 dev_err_ratelimited(dev, "Received Message FIFO Overflow\n");
273
274 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
275 dev_err_ratelimited(dev, "Slave error\n");
276
277 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
278 dev_err_ratelimited(dev, "Master error\n");
279
280 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
281 dev_err_ratelimited(dev, "In Misc Ingress address translation error\n");
282
283 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
284 dev_err_ratelimited(dev, "In Misc Egress address translation error\n");
285
286 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
287 dev_err_ratelimited(dev, "Fatal Error in AER Capability\n");
288
289 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
290 dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n");
291
292 if (misc_stat & MSGF_MISC_SR_CORR_AER)
293 dev_err_ratelimited(dev, "Correctable Error in AER Capability\n");
294
295 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
296 dev_err_ratelimited(dev, "Unsupported request Detected\n");
297
298 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
299 dev_err_ratelimited(dev, "Non-Fatal Error Detected\n");
300
301 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
302 dev_err_ratelimited(dev, "Fatal Error Detected\n");
303
304 if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
305 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
306
307 if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH)
308 dev_info(dev, "Link Bandwidth Management Status bit set\n");
309
310 /* Clear misc interrupt status */
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
312
313 return IRQ_HANDLED;
314 }
315
nwl_pcie_leg_handler(struct irq_desc * desc)316 static void nwl_pcie_leg_handler(struct irq_desc *desc)
317 {
318 struct irq_chip *chip = irq_desc_get_chip(desc);
319 struct nwl_pcie *pcie;
320 unsigned long status;
321 u32 bit;
322
323 chained_irq_enter(chip, desc);
324 pcie = irq_desc_get_handler_data(desc);
325
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
327 MSGF_LEG_SR_MASKALL) != 0) {
328 for_each_set_bit(bit, &status, PCI_NUM_INTX)
329 generic_handle_domain_irq(pcie->intx_irq_domain, bit);
330 }
331
332 chained_irq_exit(chip, desc);
333 }
334
nwl_pcie_handle_msi_irq(struct nwl_pcie * pcie,u32 status_reg)335 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
336 {
337 struct nwl_msi *msi = &pcie->msi;
338 unsigned long status;
339 u32 bit;
340
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
342 for_each_set_bit(bit, &status, 32) {
343 nwl_bridge_writel(pcie, 1 << bit, status_reg);
344 generic_handle_domain_irq(msi->dev_domain, bit);
345 }
346 }
347 }
348
nwl_pcie_msi_handler_high(struct irq_desc * desc)349 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
350 {
351 struct irq_chip *chip = irq_desc_get_chip(desc);
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
353
354 chained_irq_enter(chip, desc);
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
356 chained_irq_exit(chip, desc);
357 }
358
nwl_pcie_msi_handler_low(struct irq_desc * desc)359 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
360 {
361 struct irq_chip *chip = irq_desc_get_chip(desc);
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
363
364 chained_irq_enter(chip, desc);
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
366 chained_irq_exit(chip, desc);
367 }
368
nwl_mask_intx_irq(struct irq_data * data)369 static void nwl_mask_intx_irq(struct irq_data *data)
370 {
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
372 unsigned long flags;
373 u32 mask;
374 u32 val;
375
376 mask = 1 << data->hwirq;
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
381 }
382
nwl_unmask_intx_irq(struct irq_data * data)383 static void nwl_unmask_intx_irq(struct irq_data *data)
384 {
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
386 unsigned long flags;
387 u32 mask;
388 u32 val;
389
390 mask = 1 << data->hwirq;
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
395 }
396
397 static struct irq_chip nwl_intx_irq_chip = {
398 .name = "nwl_pcie:legacy",
399 .irq_enable = nwl_unmask_intx_irq,
400 .irq_disable = nwl_mask_intx_irq,
401 .irq_mask = nwl_mask_intx_irq,
402 .irq_unmask = nwl_unmask_intx_irq,
403 };
404
nwl_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)405 static int nwl_intx_map(struct irq_domain *domain, unsigned int irq,
406 irq_hw_number_t hwirq)
407 {
408 irq_set_chip_and_handler(irq, &nwl_intx_irq_chip, handle_level_irq);
409 irq_set_chip_data(irq, domain->host_data);
410 irq_set_status_flags(irq, IRQ_LEVEL);
411
412 return 0;
413 }
414
415 static const struct irq_domain_ops intx_domain_ops = {
416 .map = nwl_intx_map,
417 .xlate = pci_irqd_intx_xlate,
418 };
419
420 #ifdef CONFIG_PCI_MSI
421 static struct irq_chip nwl_msi_irq_chip = {
422 .name = "nwl_pcie:msi",
423 .irq_enable = pci_msi_unmask_irq,
424 .irq_disable = pci_msi_mask_irq,
425 .irq_mask = pci_msi_mask_irq,
426 .irq_unmask = pci_msi_unmask_irq,
427 };
428
429 static struct msi_domain_info nwl_msi_domain_info = {
430 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
431 MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI,
432 .chip = &nwl_msi_irq_chip,
433 };
434 #endif
435
nwl_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)436 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
437 {
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
440
441 msg->address_lo = lower_32_bits(msi_addr);
442 msg->address_hi = upper_32_bits(msi_addr);
443 msg->data = data->hwirq;
444 }
445
446 static struct irq_chip nwl_irq_chip = {
447 .name = "Xilinx MSI",
448 .irq_compose_msi_msg = nwl_compose_msi_msg,
449 };
450
nwl_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)451 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
452 unsigned int nr_irqs, void *args)
453 {
454 struct nwl_pcie *pcie = domain->host_data;
455 struct nwl_msi *msi = &pcie->msi;
456 int bit;
457 int i;
458
459 mutex_lock(&msi->lock);
460 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
461 get_count_order(nr_irqs));
462 if (bit < 0) {
463 mutex_unlock(&msi->lock);
464 return -ENOSPC;
465 }
466
467 for (i = 0; i < nr_irqs; i++) {
468 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
469 domain->host_data, handle_simple_irq,
470 NULL, NULL);
471 }
472 mutex_unlock(&msi->lock);
473 return 0;
474 }
475
nwl_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)476 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
477 unsigned int nr_irqs)
478 {
479 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
480 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
481 struct nwl_msi *msi = &pcie->msi;
482
483 mutex_lock(&msi->lock);
484 bitmap_release_region(msi->bitmap, data->hwirq,
485 get_count_order(nr_irqs));
486 mutex_unlock(&msi->lock);
487 }
488
489 static const struct irq_domain_ops dev_msi_domain_ops = {
490 .alloc = nwl_irq_domain_alloc,
491 .free = nwl_irq_domain_free,
492 };
493
nwl_pcie_init_msi_irq_domain(struct nwl_pcie * pcie)494 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
495 {
496 #ifdef CONFIG_PCI_MSI
497 struct device *dev = pcie->dev;
498 struct fwnode_handle *fwnode = of_fwnode_handle(dev->of_node);
499 struct nwl_msi *msi = &pcie->msi;
500
501 msi->dev_domain = irq_domain_create_linear(NULL, INT_PCI_MSI_NR, &dev_msi_domain_ops, pcie);
502 if (!msi->dev_domain) {
503 dev_err(dev, "failed to create dev IRQ domain\n");
504 return -ENOMEM;
505 }
506 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
507 &nwl_msi_domain_info,
508 msi->dev_domain);
509 if (!msi->msi_domain) {
510 dev_err(dev, "failed to create msi IRQ domain\n");
511 irq_domain_remove(msi->dev_domain);
512 return -ENOMEM;
513 }
514 #endif
515 return 0;
516 }
517
nwl_pcie_phy_power_off(struct nwl_pcie * pcie,int i)518 static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i)
519 {
520 int err = phy_power_off(pcie->phy[i]);
521
522 if (err)
523 dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i,
524 err);
525 }
526
nwl_pcie_phy_exit(struct nwl_pcie * pcie,int i)527 static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i)
528 {
529 int err = phy_exit(pcie->phy[i]);
530
531 if (err)
532 dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err);
533 }
534
nwl_pcie_phy_enable(struct nwl_pcie * pcie)535 static int nwl_pcie_phy_enable(struct nwl_pcie *pcie)
536 {
537 int i, ret;
538
539 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
540 ret = phy_init(pcie->phy[i]);
541 if (ret)
542 goto err;
543
544 ret = phy_power_on(pcie->phy[i]);
545 if (ret) {
546 nwl_pcie_phy_exit(pcie, i);
547 goto err;
548 }
549 }
550
551 return 0;
552
553 err:
554 while (i--) {
555 nwl_pcie_phy_power_off(pcie, i);
556 nwl_pcie_phy_exit(pcie, i);
557 }
558
559 return ret;
560 }
561
nwl_pcie_phy_disable(struct nwl_pcie * pcie)562 static void nwl_pcie_phy_disable(struct nwl_pcie *pcie)
563 {
564 int i;
565
566 for (i = ARRAY_SIZE(pcie->phy); i--;) {
567 nwl_pcie_phy_power_off(pcie, i);
568 nwl_pcie_phy_exit(pcie, i);
569 }
570 }
571
nwl_pcie_init_irq_domain(struct nwl_pcie * pcie)572 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
573 {
574 struct device *dev = pcie->dev;
575 struct device_node *node = dev->of_node;
576 struct device_node *intc_node;
577
578 intc_node = of_get_next_child(node, NULL);
579 if (!intc_node) {
580 dev_err(dev, "No legacy intc node found\n");
581 return -EINVAL;
582 }
583
584 pcie->intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX,
585 &intx_domain_ops, pcie);
586 of_node_put(intc_node);
587 if (!pcie->intx_irq_domain) {
588 dev_err(dev, "failed to create IRQ domain\n");
589 return -ENOMEM;
590 }
591
592 raw_spin_lock_init(&pcie->leg_mask_lock);
593 nwl_pcie_init_msi_irq_domain(pcie);
594 return 0;
595 }
596
nwl_pcie_enable_msi(struct nwl_pcie * pcie)597 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
598 {
599 struct device *dev = pcie->dev;
600 struct platform_device *pdev = to_platform_device(dev);
601 struct nwl_msi *msi = &pcie->msi;
602 unsigned long base;
603 int ret;
604
605 mutex_init(&msi->lock);
606
607 /* Get msi_1 IRQ number */
608 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
609 if (msi->irq_msi1 < 0)
610 return -EINVAL;
611
612 irq_set_chained_handler_and_data(msi->irq_msi1,
613 nwl_pcie_msi_handler_high, pcie);
614
615 /* Get msi_0 IRQ number */
616 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
617 if (msi->irq_msi0 < 0)
618 return -EINVAL;
619
620 irq_set_chained_handler_and_data(msi->irq_msi0,
621 nwl_pcie_msi_handler_low, pcie);
622
623 /* Check for msii_present bit */
624 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
625 if (!ret) {
626 dev_err(dev, "MSI not present\n");
627 return -EIO;
628 }
629
630 /* Enable MSII */
631 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
632 MSII_ENABLE, I_MSII_CONTROL);
633
634 /* Enable MSII status */
635 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
636 MSII_STATUS_ENABLE, I_MSII_CONTROL);
637
638 /* setup AFI/FPCI range */
639 base = pcie->phys_pcie_reg_base;
640 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
641 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
642
643 /*
644 * For high range MSI interrupts: disable, clear any pending,
645 * and enable
646 */
647 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
648
649 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
650 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
651
652 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
653
654 /*
655 * For low range MSI interrupts: disable, clear any pending,
656 * and enable
657 */
658 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
659
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
661 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
662
663 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
664
665 return 0;
666 }
667
nwl_pcie_bridge_init(struct nwl_pcie * pcie)668 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
669 {
670 struct device *dev = pcie->dev;
671 struct platform_device *pdev = to_platform_device(dev);
672 u32 breg_val, ecam_val;
673 int err;
674
675 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
676 if (!breg_val) {
677 dev_err(dev, "BREG is not present\n");
678 return breg_val;
679 }
680
681 /* Write bridge_off to breg base */
682 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
683 E_BREG_BASE_LO);
684 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
685 E_BREG_BASE_HI);
686
687 /* Enable BREG */
688 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
689 E_BREG_CONTROL);
690
691 /* Disable DMA channel registers */
692 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
693 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
694
695 /* Enable Ingress subtractive decode translation */
696 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
697
698 /* Enable msg filtering details */
699 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
700 BRCFG_PCIE_RX_MSG_FILTER);
701
702 /* This routes the PCIe DMA traffic to go through CCI path */
703 if (of_dma_is_coherent(dev->of_node))
704 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
705 CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
706
707 err = nwl_wait_for_link(pcie);
708 if (err)
709 return err;
710
711 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
712 if (!ecam_val) {
713 dev_err(dev, "ECAM is not present\n");
714 return ecam_val;
715 }
716
717 /* Enable ECAM */
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
719 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
720
721 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
722 (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),
723 E_ECAM_CONTROL);
724
725 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
726 E_ECAM_BASE_LO);
727 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
728 E_ECAM_BASE_HI);
729
730 if (nwl_pcie_link_up(pcie))
731 dev_info(dev, "Link is UP\n");
732 else
733 dev_info(dev, "Link is DOWN\n");
734
735 /* Get misc IRQ number */
736 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
737 if (pcie->irq_misc < 0)
738 return -EINVAL;
739
740 err = devm_request_irq(dev, pcie->irq_misc,
741 nwl_pcie_misc_handler, IRQF_SHARED,
742 "nwl_pcie:misc", pcie);
743 if (err) {
744 dev_err(dev, "fail to register misc IRQ#%d\n",
745 pcie->irq_misc);
746 return err;
747 }
748
749 /* Disable all misc interrupts */
750 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
751
752 /* Clear pending misc interrupts */
753 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
754 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
755
756 /* Enable all misc interrupts */
757 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
758
759 /* Disable all INTX interrupts */
760 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
761
762 /* Clear pending INTX interrupts */
763 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
764 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
765
766 /* Enable all INTX interrupts */
767 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
768
769 /* Enable the bridge config interrupt */
770 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
771 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
772
773 return 0;
774 }
775
nwl_pcie_parse_dt(struct nwl_pcie * pcie,struct platform_device * pdev)776 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
777 struct platform_device *pdev)
778 {
779 struct device *dev = pcie->dev;
780 struct resource *res;
781 int i;
782
783 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
784 pcie->breg_base = devm_ioremap_resource(dev, res);
785 if (IS_ERR(pcie->breg_base))
786 return PTR_ERR(pcie->breg_base);
787 pcie->phys_breg_base = res->start;
788
789 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
790 pcie->pcireg_base = devm_ioremap_resource(dev, res);
791 if (IS_ERR(pcie->pcireg_base))
792 return PTR_ERR(pcie->pcireg_base);
793 pcie->phys_pcie_reg_base = res->start;
794
795 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
796 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
797 if (IS_ERR(pcie->ecam_base))
798 return PTR_ERR(pcie->ecam_base);
799 pcie->phys_ecam_base = res->start;
800
801 /* Get intx IRQ number */
802 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
803 if (pcie->irq_intx < 0)
804 return pcie->irq_intx;
805
806 irq_set_chained_handler_and_data(pcie->irq_intx,
807 nwl_pcie_leg_handler, pcie);
808
809
810 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
811 pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i);
812 if (PTR_ERR(pcie->phy[i]) == -ENODEV) {
813 pcie->phy[i] = NULL;
814 break;
815 }
816
817 if (IS_ERR(pcie->phy[i]))
818 return PTR_ERR(pcie->phy[i]);
819 }
820
821 return 0;
822 }
823
824 static const struct of_device_id nwl_pcie_of_match[] = {
825 { .compatible = "xlnx,nwl-pcie-2.11", },
826 {}
827 };
828
nwl_pcie_probe(struct platform_device * pdev)829 static int nwl_pcie_probe(struct platform_device *pdev)
830 {
831 struct device *dev = &pdev->dev;
832 struct nwl_pcie *pcie;
833 struct pci_host_bridge *bridge;
834 int err;
835
836 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
837 if (!bridge)
838 return -ENODEV;
839
840 pcie = pci_host_bridge_priv(bridge);
841 platform_set_drvdata(pdev, pcie);
842
843 pcie->dev = dev;
844
845 err = nwl_pcie_parse_dt(pcie, pdev);
846 if (err) {
847 dev_err(dev, "Parsing DT failed\n");
848 return err;
849 }
850
851 pcie->clk = devm_clk_get(dev, NULL);
852 if (IS_ERR(pcie->clk))
853 return PTR_ERR(pcie->clk);
854
855 err = clk_prepare_enable(pcie->clk);
856 if (err) {
857 dev_err(dev, "can't enable PCIe ref clock\n");
858 return err;
859 }
860
861 err = nwl_pcie_phy_enable(pcie);
862 if (err) {
863 dev_err(dev, "could not enable PHYs\n");
864 goto err_clk;
865 }
866
867 err = nwl_pcie_bridge_init(pcie);
868 if (err) {
869 dev_err(dev, "HW Initialization failed\n");
870 goto err_phy;
871 }
872
873 err = nwl_pcie_init_irq_domain(pcie);
874 if (err) {
875 dev_err(dev, "Failed creating IRQ Domain\n");
876 goto err_phy;
877 }
878
879 bridge->sysdata = pcie;
880 bridge->ops = &nwl_pcie_ops;
881
882 if (IS_ENABLED(CONFIG_PCI_MSI)) {
883 err = nwl_pcie_enable_msi(pcie);
884 if (err < 0) {
885 dev_err(dev, "failed to enable MSI support: %d\n", err);
886 goto err_phy;
887 }
888 }
889
890 err = pci_host_probe(bridge);
891 if (!err)
892 return 0;
893
894 err_phy:
895 nwl_pcie_phy_disable(pcie);
896 err_clk:
897 clk_disable_unprepare(pcie->clk);
898 return err;
899 }
900
nwl_pcie_remove(struct platform_device * pdev)901 static void nwl_pcie_remove(struct platform_device *pdev)
902 {
903 struct nwl_pcie *pcie = platform_get_drvdata(pdev);
904
905 nwl_pcie_phy_disable(pcie);
906 clk_disable_unprepare(pcie->clk);
907 }
908
909 static struct platform_driver nwl_pcie_driver = {
910 .driver = {
911 .name = "nwl-pcie",
912 .suppress_bind_attrs = true,
913 .of_match_table = nwl_pcie_of_match,
914 },
915 .probe = nwl_pcie_probe,
916 .remove = nwl_pcie_remove,
917 };
918 builtin_platform_driver(nwl_pcie_driver);
919