1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include <core/tegra.h> 23 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 24 #include "priv.h" 25 26 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 27 #include <asm/dma-iommu.h> 28 #endif 29 30 static int 31 nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) 32 { 33 int ret; 34 35 if (tdev->vdd) { 36 ret = regulator_enable(tdev->vdd); 37 if (ret) 38 goto err_power; 39 } 40 41 ret = clk_prepare_enable(tdev->clk); 42 if (ret) 43 goto err_clk; 44 ret = clk_prepare_enable(tdev->clk_ref); 45 if (ret) 46 goto err_clk_ref; 47 ret = clk_prepare_enable(tdev->clk_pwr); 48 if (ret) 49 goto err_clk_pwr; 50 clk_set_rate(tdev->clk_pwr, 204000000); 51 udelay(10); 52 53 if (!tdev->pdev->dev.pm_domain) { 54 reset_control_assert(tdev->rst); 55 udelay(10); 56 57 ret = tegra_pmc_powergate_remove_clamping(tdev->pmc, 58 TEGRA_POWERGATE_3D); 59 if (ret) 60 goto err_clamp; 61 udelay(10); 62 63 reset_control_deassert(tdev->rst); 64 udelay(10); 65 } 66 67 return 0; 68 69 err_clamp: 70 clk_disable_unprepare(tdev->clk_pwr); 71 err_clk_pwr: 72 clk_disable_unprepare(tdev->clk_ref); 73 err_clk_ref: 74 clk_disable_unprepare(tdev->clk); 75 err_clk: 76 if (tdev->vdd) 77 regulator_disable(tdev->vdd); 78 err_power: 79 return ret; 80 } 81 82 static int 83 nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev) 84 { 85 int ret; 86 87 clk_disable_unprepare(tdev->clk_pwr); 88 clk_disable_unprepare(tdev->clk_ref); 89 clk_disable_unprepare(tdev->clk); 90 udelay(10); 91 92 if (tdev->vdd) { 93 ret = regulator_disable(tdev->vdd); 94 if (ret) 95 return ret; 96 } 97 98 return 0; 99 } 100 101 static void 102 nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) 103 { 104 #if IS_ENABLED(CONFIG_IOMMU_API) 105 struct device *dev = &tdev->pdev->dev; 106 unsigned long pgsize_bitmap; 107 int ret; 108 109 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 110 if (dev->archdata.mapping) { 111 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); 112 113 arm_iommu_detach_device(dev); 114 arm_iommu_release_mapping(mapping); 115 } 116 #endif 117 118 if (!tdev->func->iommu_bit) 119 return; 120 121 mutex_init(&tdev->iommu.mutex); 122 123 if (device_iommu_mapped(dev)) { 124 tdev->iommu.domain = iommu_paging_domain_alloc(dev); 125 if (IS_ERR(tdev->iommu.domain)) 126 goto error; 127 128 /* 129 * A IOMMU is only usable if it supports page sizes smaller 130 * or equal to the system's PAGE_SIZE, with a preference if 131 * both are equal. 132 */ 133 pgsize_bitmap = tdev->iommu.domain->pgsize_bitmap; 134 if (pgsize_bitmap & PAGE_SIZE) { 135 tdev->iommu.pgshift = PAGE_SHIFT; 136 } else { 137 tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK); 138 if (tdev->iommu.pgshift == 0) { 139 dev_warn(dev, "unsupported IOMMU page size\n"); 140 goto free_domain; 141 } 142 tdev->iommu.pgshift -= 1; 143 } 144 145 ret = iommu_attach_device(tdev->iommu.domain, dev); 146 if (ret) 147 goto free_domain; 148 149 ret = nvkm_mm_init(&tdev->iommu.mm, 0, 0, 150 (1ULL << tdev->func->iommu_bit) >> 151 tdev->iommu.pgshift, 1); 152 if (ret) 153 goto detach_device; 154 } 155 156 return; 157 158 detach_device: 159 iommu_detach_device(tdev->iommu.domain, dev); 160 161 free_domain: 162 iommu_domain_free(tdev->iommu.domain); 163 164 error: 165 tdev->iommu.domain = NULL; 166 tdev->iommu.pgshift = 0; 167 dev_err(dev, "cannot initialize IOMMU MM\n"); 168 #endif 169 } 170 171 static void 172 nvkm_device_tegra_remove_iommu(struct nvkm_device_tegra *tdev) 173 { 174 #if IS_ENABLED(CONFIG_IOMMU_API) 175 if (tdev->iommu.domain) { 176 nvkm_mm_fini(&tdev->iommu.mm); 177 iommu_detach_device(tdev->iommu.domain, tdev->device.dev); 178 iommu_domain_free(tdev->iommu.domain); 179 } 180 #endif 181 } 182 183 static struct nvkm_device_tegra * 184 nvkm_device_tegra(struct nvkm_device *device) 185 { 186 return container_of(device, struct nvkm_device_tegra, device); 187 } 188 189 static struct resource * 190 nvkm_device_tegra_resource(struct nvkm_device *device, enum nvkm_bar_id bar) 191 { 192 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); 193 int idx; 194 195 switch (bar) { 196 case NVKM_BAR0_PRI: idx = 0; break; 197 case NVKM_BAR1_FB : idx = 1; break; 198 default: 199 WARN_ON(1); 200 return NULL; 201 } 202 203 return platform_get_resource(tdev->pdev, IORESOURCE_MEM, idx); 204 } 205 206 static resource_size_t 207 nvkm_device_tegra_resource_addr(struct nvkm_device *device, enum nvkm_bar_id bar) 208 { 209 struct resource *res = nvkm_device_tegra_resource(device, bar); 210 return res ? res->start : 0; 211 } 212 213 static resource_size_t 214 nvkm_device_tegra_resource_size(struct nvkm_device *device, enum nvkm_bar_id bar) 215 { 216 struct resource *res = nvkm_device_tegra_resource(device, bar); 217 return res ? resource_size(res) : 0; 218 } 219 220 static int 221 nvkm_device_tegra_irq(struct nvkm_device *device) 222 { 223 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); 224 225 return platform_get_irq_byname(tdev->pdev, "stall"); 226 } 227 228 static void * 229 nvkm_device_tegra_dtor(struct nvkm_device *device) 230 { 231 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); 232 nvkm_device_tegra_power_down(tdev); 233 nvkm_device_tegra_remove_iommu(tdev); 234 return tdev; 235 } 236 237 static const struct nvkm_device_func 238 nvkm_device_tegra_func = { 239 .tegra = nvkm_device_tegra, 240 .dtor = nvkm_device_tegra_dtor, 241 .irq = nvkm_device_tegra_irq, 242 .resource_addr = nvkm_device_tegra_resource_addr, 243 .resource_size = nvkm_device_tegra_resource_size, 244 .cpu_coherent = false, 245 }; 246 247 int 248 nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, 249 struct platform_device *pdev, 250 const char *cfg, const char *dbg, 251 struct nvkm_device **pdevice) 252 { 253 struct nvkm_device_tegra *tdev; 254 unsigned long rate; 255 int ret; 256 257 if (!(tdev = kzalloc_obj(*tdev))) 258 return -ENOMEM; 259 260 tdev->func = func; 261 tdev->pdev = pdev; 262 263 tdev->regs = devm_platform_ioremap_resource(pdev, 0); 264 if (IS_ERR(tdev->regs)) 265 return PTR_ERR(tdev->regs); 266 267 if (func->require_vdd) { 268 tdev->vdd = devm_regulator_get(&pdev->dev, "vdd"); 269 if (IS_ERR(tdev->vdd)) { 270 ret = PTR_ERR(tdev->vdd); 271 goto free; 272 } 273 } 274 275 tdev->rst = devm_reset_control_get(&pdev->dev, "gpu"); 276 if (IS_ERR(tdev->rst)) { 277 ret = PTR_ERR(tdev->rst); 278 goto free; 279 } 280 281 tdev->clk = devm_clk_get(&pdev->dev, "gpu"); 282 if (IS_ERR(tdev->clk)) { 283 ret = PTR_ERR(tdev->clk); 284 goto free; 285 } 286 287 rate = clk_get_rate(tdev->clk); 288 if (rate == 0) { 289 ret = clk_set_rate(tdev->clk, ULONG_MAX); 290 if (ret < 0) 291 goto free; 292 293 rate = clk_get_rate(tdev->clk); 294 295 dev_dbg(&pdev->dev, "GPU clock set to %lu\n", rate); 296 } 297 298 if (func->require_ref_clk) 299 tdev->clk_ref = devm_clk_get(&pdev->dev, "ref"); 300 if (IS_ERR(tdev->clk_ref)) { 301 ret = PTR_ERR(tdev->clk_ref); 302 goto free; 303 } 304 305 tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); 306 if (IS_ERR(tdev->clk_pwr)) { 307 ret = PTR_ERR(tdev->clk_pwr); 308 goto free; 309 } 310 311 tdev->pmc = devm_tegra_pmc_get(&pdev->dev); 312 if (IS_ERR(tdev->pmc)) { 313 ret = PTR_ERR(tdev->pmc); 314 goto free; 315 } 316 317 /** 318 * The IOMMU bit defines the upper limit of the GPU-addressable space. 319 */ 320 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(tdev->func->iommu_bit)); 321 if (ret) 322 goto free; 323 324 nvkm_device_tegra_probe_iommu(tdev); 325 326 ret = nvkm_device_tegra_power_up(tdev); 327 if (ret) 328 goto remove; 329 330 tdev->gpu_speedo = tegra_sku_info.gpu_speedo_value; 331 tdev->gpu_speedo_id = tegra_sku_info.gpu_speedo_id; 332 ret = nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev, 333 NVKM_DEVICE_TEGRA, pdev->id, NULL, 334 cfg, dbg, &tdev->device); 335 if (ret) 336 goto powerdown; 337 338 *pdevice = &tdev->device; 339 340 return 0; 341 342 powerdown: 343 nvkm_device_tegra_power_down(tdev); 344 remove: 345 nvkm_device_tegra_remove_iommu(tdev); 346 free: 347 kfree(tdev); 348 return ret; 349 } 350 #else 351 int 352 nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, 353 struct platform_device *pdev, 354 const char *cfg, const char *dbg, 355 struct nvkm_device **pdevice) 356 { 357 return -ENOSYS; 358 } 359 #endif 360