xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c (revision d0034a7a4ac7fae708146ac0059b9c47a1543f0d)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 #include "regsnv04.h"
26 
27 static void
nv40_timer_init(struct nvkm_timer * tmr)28 nv40_timer_init(struct nvkm_timer *tmr)
29 {
30 	struct nvkm_subdev *subdev = &tmr->subdev;
31 	struct nvkm_device *device = subdev->device;
32 	u32 f = 0; /*XXX: figure this out */
33 	u32 n, d;
34 
35 	/* aim for 31.25MHz, which gives us nanosecond timestamps */
36 	d = 1000000 / 32;
37 	n = f;
38 
39 	if (!f) {
40 		n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR);
41 		d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR);
42 		if (!n || !d) {
43 			n = 1;
44 			d = 1;
45 		}
46 		nvkm_warn(subdev, "unknown input clock freq\n");
47 	}
48 
49 	/* reduce ratio to acceptable values */
50 	while (((n % 5) == 0) && ((d % 5) == 0)) {
51 		n /= 5;
52 		d /= 5;
53 	}
54 
55 	while (((n % 2) == 0) && ((d % 2) == 0)) {
56 		n /= 2;
57 		d /= 2;
58 	}
59 
60 	while (n > 0xffff || d > 0xffff) {
61 		n >>= 1;
62 		d >>= 1;
63 	}
64 
65 	nvkm_debug(subdev, "input frequency : %dHz\n", f);
66 	nvkm_debug(subdev, "numerator       : %08x\n", n);
67 	nvkm_debug(subdev, "denominator     : %08x\n", d);
68 	nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
69 
70 	nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n);
71 	nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d);
72 }
73 
74 static const struct nvkm_timer_func
75 nv40_timer = {
76 	.init = nv40_timer_init,
77 	.intr = nv04_timer_intr,
78 	.read = nv04_timer_read,
79 	.time = nv04_timer_time,
80 	.alarm_init = nv04_timer_alarm_init,
81 	.alarm_fini = nv04_timer_alarm_fini,
82 };
83 
84 int
nv40_timer_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_timer ** ptmr)85 nv40_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
86 	       struct nvkm_timer **ptmr)
87 {
88 	return nvkm_timer_new_(&nv40_timer, device, type, inst, ptmr);
89 }
90