1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sparc64/mm/init.c 4 * 5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #include <linux/extable.h> 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/string.h> 13 #include <linux/init.h> 14 #include <linux/memblock.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h> 17 #include <linux/initrd.h> 18 #include <linux/swap.h> 19 #include <linux/pagemap.h> 20 #include <linux/poison.h> 21 #include <linux/fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/kprobes.h> 24 #include <linux/cache.h> 25 #include <linux/sort.h> 26 #include <linux/ioport.h> 27 #include <linux/percpu.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 #include <linux/bootmem_info.h> 31 32 #include <asm/head.h> 33 #include <asm/page.h> 34 #include <asm/pgalloc.h> 35 #include <asm/oplib.h> 36 #include <asm/iommu.h> 37 #include <asm/io.h> 38 #include <linux/uaccess.h> 39 #include <asm/mmu_context.h> 40 #include <asm/tlbflush.h> 41 #include <asm/dma.h> 42 #include <asm/starfire.h> 43 #include <asm/tlb.h> 44 #include <asm/spitfire.h> 45 #include <asm/sections.h> 46 #include <asm/tsb.h> 47 #include <asm/hypervisor.h> 48 #include <asm/prom.h> 49 #include <asm/mdesc.h> 50 #include <asm/cpudata.h> 51 #include <asm/setup.h> 52 #include <asm/irq.h> 53 54 #include "init_64.h" 55 56 unsigned long kern_linear_pte_xor[4] __read_mostly; 57 static unsigned long page_cache4v_flag; 58 59 /* A bitmap, two bits for every 256MB of physical memory. These two 60 * bits determine what page size we use for kernel linear 61 * translations. They form an index into kern_linear_pte_xor[]. The 62 * value in the indexed slot is XOR'd with the TLB miss virtual 63 * address to form the resulting TTE. The mapping is: 64 * 65 * 0 ==> 4MB 66 * 1 ==> 256MB 67 * 2 ==> 2GB 68 * 3 ==> 16GB 69 * 70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 71 * support 2GB pages, and hopefully future cpus will support the 16GB 72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 73 * if these larger page sizes are not supported by the cpu. 74 * 75 * It would be nice to determine this from the machine description 76 * 'cpu' properties, but we need to have this table setup before the 77 * MDESC is initialized. 78 */ 79 80 #ifndef CONFIG_DEBUG_PAGEALLOC 81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 82 * Space is allocated for this right after the trap table in 83 * arch/sparc64/kernel/head.S 84 */ 85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 86 #endif 87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 88 89 static unsigned long cpu_pgsz_mask; 90 91 #define MAX_BANKS 1024 92 93 static struct linux_prom64_registers pavail[MAX_BANKS]; 94 static int pavail_ents; 95 96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 97 98 static int cmp_p64(const void *a, const void *b) 99 { 100 const struct linux_prom64_registers *x = a, *y = b; 101 102 if (x->phys_addr > y->phys_addr) 103 return 1; 104 if (x->phys_addr < y->phys_addr) 105 return -1; 106 return 0; 107 } 108 109 static void __init read_obp_memory(const char *property, 110 struct linux_prom64_registers *regs, 111 int *num_ents) 112 { 113 phandle node = prom_finddevice("/memory"); 114 int prop_size = prom_getproplen(node, property); 115 int ents, ret, i; 116 117 ents = prop_size / sizeof(struct linux_prom64_registers); 118 if (ents > MAX_BANKS) { 119 prom_printf("The machine has more %s property entries than " 120 "this kernel can support (%d).\n", 121 property, MAX_BANKS); 122 prom_halt(); 123 } 124 125 ret = prom_getproperty(node, property, (char *) regs, prop_size); 126 if (ret == -1) { 127 prom_printf("Couldn't get %s property from /memory.\n", 128 property); 129 prom_halt(); 130 } 131 132 /* Sanitize what we got from the firmware, by page aligning 133 * everything. 134 */ 135 for (i = 0; i < ents; i++) { 136 unsigned long base, size; 137 138 base = regs[i].phys_addr; 139 size = regs[i].reg_size; 140 141 size &= PAGE_MASK; 142 if (base & ~PAGE_MASK) { 143 unsigned long new_base = PAGE_ALIGN(base); 144 145 size -= new_base - base; 146 if ((long) size < 0L) 147 size = 0UL; 148 base = new_base; 149 } 150 if (size == 0UL) { 151 /* If it is empty, simply get rid of it. 152 * This simplifies the logic of the other 153 * functions that process these arrays. 154 */ 155 memmove(®s[i], ®s[i + 1], 156 (ents - i - 1) * sizeof(regs[0])); 157 i--; 158 ents--; 159 continue; 160 } 161 regs[i].phys_addr = base; 162 regs[i].reg_size = size; 163 } 164 165 *num_ents = ents; 166 167 sort(regs, ents, sizeof(struct linux_prom64_registers), 168 cmp_p64, NULL); 169 } 170 171 /* Kernel physical address base and size in bytes. */ 172 unsigned long kern_base __read_mostly; 173 unsigned long kern_size __read_mostly; 174 175 /* Initial ramdisk setup */ 176 extern unsigned long sparc_ramdisk_image64; 177 extern unsigned int sparc_ramdisk_image; 178 extern unsigned int sparc_ramdisk_size; 179 180 struct page *mem_map_zero __read_mostly; 181 EXPORT_SYMBOL(mem_map_zero); 182 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 184 185 unsigned long sparc64_kern_pri_context __read_mostly; 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 187 unsigned long sparc64_kern_sec_context __read_mostly; 188 189 int num_kernel_image_mappings; 190 191 #ifdef CONFIG_DEBUG_DCFLUSH 192 atomic_t dcpage_flushes = ATOMIC_INIT(0); 193 #ifdef CONFIG_SMP 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 195 #endif 196 #endif 197 198 inline void flush_dcache_folio_impl(struct folio *folio) 199 { 200 unsigned int i, nr = folio_nr_pages(folio); 201 202 BUG_ON(tlb_type == hypervisor); 203 #ifdef CONFIG_DEBUG_DCFLUSH 204 atomic_inc(&dcpage_flushes); 205 #endif 206 207 #ifdef DCACHE_ALIASING_POSSIBLE 208 for (i = 0; i < nr; i++) 209 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE, 210 ((tlb_type == spitfire) && 211 folio_flush_mapping(folio) != NULL)); 212 #else 213 if (folio_flush_mapping(folio) != NULL && 214 tlb_type == spitfire) { 215 for (i = 0; i < nr; i++) 216 __flush_icache_page((pfn + i) * PAGE_SIZE); 217 } 218 #endif 219 } 220 221 #define PG_dcache_dirty PG_arch_1 222 #define PG_dcache_cpu_shift 32UL 223 #define PG_dcache_cpu_mask \ 224 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 225 226 #define dcache_dirty_cpu(folio) \ 227 (((folio)->flags.f >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 228 229 static inline void set_dcache_dirty(struct folio *folio, int this_cpu) 230 { 231 unsigned long mask = this_cpu; 232 unsigned long non_cpu_bits; 233 234 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 235 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 236 237 __asm__ __volatile__("1:\n\t" 238 "ldx [%2], %%g7\n\t" 239 "and %%g7, %1, %%g1\n\t" 240 "or %%g1, %0, %%g1\n\t" 241 "casx [%2], %%g7, %%g1\n\t" 242 "cmp %%g7, %%g1\n\t" 243 "bne,pn %%xcc, 1b\n\t" 244 " nop" 245 : /* no outputs */ 246 : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags.f) 247 : "g1", "g7"); 248 } 249 250 static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu) 251 { 252 unsigned long mask = (1UL << PG_dcache_dirty); 253 254 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 255 "1:\n\t" 256 "ldx [%2], %%g7\n\t" 257 "srlx %%g7, %4, %%g1\n\t" 258 "and %%g1, %3, %%g1\n\t" 259 "cmp %%g1, %0\n\t" 260 "bne,pn %%icc, 2f\n\t" 261 " andn %%g7, %1, %%g1\n\t" 262 "casx [%2], %%g7, %%g1\n\t" 263 "cmp %%g7, %%g1\n\t" 264 "bne,pn %%xcc, 1b\n\t" 265 " nop\n" 266 "2:" 267 : /* no outputs */ 268 : "r" (cpu), "r" (mask), "r" (&folio->flags.f), 269 "i" (PG_dcache_cpu_mask), 270 "i" (PG_dcache_cpu_shift) 271 : "g1", "g7"); 272 } 273 274 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 275 { 276 unsigned long tsb_addr = (unsigned long) ent; 277 278 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 279 tsb_addr = __pa(tsb_addr); 280 281 __tsb_insert(tsb_addr, tag, pte); 282 } 283 284 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 285 286 static void flush_dcache(unsigned long pfn) 287 { 288 struct page *page; 289 290 page = pfn_to_page(pfn); 291 if (page) { 292 struct folio *folio = page_folio(page); 293 unsigned long pg_flags; 294 295 pg_flags = folio->flags.f; 296 if (pg_flags & (1UL << PG_dcache_dirty)) { 297 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 298 PG_dcache_cpu_mask); 299 int this_cpu = get_cpu(); 300 301 /* This is just to optimize away some function calls 302 * in the SMP case. 303 */ 304 if (cpu == this_cpu) 305 flush_dcache_folio_impl(folio); 306 else 307 smp_flush_dcache_folio_impl(folio, cpu); 308 309 clear_dcache_dirty_cpu(folio, cpu); 310 311 put_cpu(); 312 } 313 } 314 } 315 316 /* mm->context.lock must be held */ 317 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 318 unsigned long tsb_hash_shift, unsigned long address, 319 unsigned long tte) 320 { 321 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 322 unsigned long tag; 323 324 if (unlikely(!tsb)) 325 return; 326 327 tsb += ((address >> tsb_hash_shift) & 328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 329 tag = (address >> 22UL); 330 tsb_insert(tsb, tag, tte); 331 } 332 333 #ifdef CONFIG_HUGETLB_PAGE 334 static int __init hugetlbpage_init(void) 335 { 336 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT); 337 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT); 338 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT); 339 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT); 340 341 return 0; 342 } 343 344 arch_initcall(hugetlbpage_init); 345 346 static void __init pud_huge_patch(void) 347 { 348 struct pud_huge_patch_entry *p; 349 unsigned long addr; 350 351 p = &__pud_huge_patch; 352 addr = p->addr; 353 *(unsigned int *)addr = p->insn; 354 355 __asm__ __volatile__("flush %0" : : "r" (addr)); 356 } 357 358 bool __init arch_hugetlb_valid_size(unsigned long size) 359 { 360 unsigned int hugepage_shift = ilog2(size); 361 unsigned int hv_pgsz_mask; 362 363 switch (hugepage_shift) { 364 case HPAGE_16GB_SHIFT: 365 hv_pgsz_mask = HV_PGSZ_MASK_16GB; 366 pud_huge_patch(); 367 break; 368 case HPAGE_2GB_SHIFT: 369 hv_pgsz_mask = HV_PGSZ_MASK_2GB; 370 break; 371 case HPAGE_256MB_SHIFT: 372 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 373 break; 374 case HPAGE_SHIFT: 375 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 376 break; 377 case HPAGE_64K_SHIFT: 378 hv_pgsz_mask = HV_PGSZ_MASK_64K; 379 break; 380 default: 381 hv_pgsz_mask = 0; 382 } 383 384 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) 385 return false; 386 387 return true; 388 } 389 #endif /* CONFIG_HUGETLB_PAGE */ 390 391 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, 392 unsigned long address, pte_t *ptep, unsigned int nr) 393 { 394 struct mm_struct *mm; 395 unsigned long flags; 396 bool is_huge_tsb; 397 pte_t pte = *ptep; 398 unsigned int i; 399 400 if (tlb_type != hypervisor) { 401 unsigned long pfn = pte_pfn(pte); 402 403 if (pfn_valid(pfn)) 404 flush_dcache(pfn); 405 } 406 407 mm = vma->vm_mm; 408 409 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 410 if (!pte_accessible(mm, pte)) 411 return; 412 413 spin_lock_irqsave(&mm->context.lock, flags); 414 415 is_huge_tsb = false; 416 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 417 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) { 418 unsigned long hugepage_size = PAGE_SIZE; 419 420 if (is_vm_hugetlb_page(vma)) 421 hugepage_size = huge_page_size(hstate_vma(vma)); 422 423 if (hugepage_size >= PUD_SIZE) { 424 unsigned long mask = 0x1ffc00000UL; 425 426 /* Transfer bits [32:22] from address to resolve 427 * at 4M granularity. 428 */ 429 pte_val(pte) &= ~mask; 430 pte_val(pte) |= (address & mask); 431 } else if (hugepage_size >= PMD_SIZE) { 432 /* We are fabricating 8MB pages using 4MB 433 * real hw pages. 434 */ 435 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 436 } 437 438 if (hugepage_size >= PMD_SIZE) { 439 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, 440 REAL_HPAGE_SHIFT, address, pte_val(pte)); 441 is_huge_tsb = true; 442 } 443 } 444 #endif 445 if (!is_huge_tsb) { 446 for (i = 0; i < nr; i++) { 447 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 448 address, pte_val(pte)); 449 address += PAGE_SIZE; 450 pte_val(pte) += PAGE_SIZE; 451 } 452 } 453 454 spin_unlock_irqrestore(&mm->context.lock, flags); 455 } 456 457 void flush_dcache_folio(struct folio *folio) 458 { 459 unsigned long pfn = folio_pfn(folio); 460 struct address_space *mapping; 461 int this_cpu; 462 463 if (tlb_type == hypervisor) 464 return; 465 466 /* Do not bother with the expensive D-cache flush if it 467 * is merely the zero page. The 'bigcore' testcase in GDB 468 * causes this case to run millions of times. 469 */ 470 if (is_zero_pfn(pfn)) 471 return; 472 473 this_cpu = get_cpu(); 474 475 mapping = folio_flush_mapping(folio); 476 if (mapping && !mapping_mapped(mapping)) { 477 bool dirty = test_bit(PG_dcache_dirty, &folio->flags.f); 478 if (dirty) { 479 int dirty_cpu = dcache_dirty_cpu(folio); 480 481 if (dirty_cpu == this_cpu) 482 goto out; 483 smp_flush_dcache_folio_impl(folio, dirty_cpu); 484 } 485 set_dcache_dirty(folio, this_cpu); 486 } else { 487 /* We could delay the flush for the !folio_mapping 488 * case too. But that case is for exec env/arg 489 * pages and those are %99 certainly going to get 490 * faulted into the tlb (and thus flushed) anyways. 491 */ 492 flush_dcache_folio_impl(folio); 493 } 494 495 out: 496 put_cpu(); 497 } 498 EXPORT_SYMBOL(flush_dcache_folio); 499 500 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 501 { 502 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 503 if (tlb_type == spitfire) { 504 unsigned long kaddr; 505 506 /* This code only runs on Spitfire cpus so this is 507 * why we can assume _PAGE_PADDR_4U. 508 */ 509 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 510 unsigned long paddr, mask = _PAGE_PADDR_4U; 511 512 if (kaddr >= PAGE_OFFSET) 513 paddr = kaddr & mask; 514 else { 515 pte_t *ptep = virt_to_kpte(kaddr); 516 517 paddr = pte_val(*ptep) & mask; 518 } 519 __flush_icache_page(paddr); 520 } 521 } 522 } 523 EXPORT_SYMBOL(flush_icache_range); 524 525 void mmu_info(struct seq_file *m) 526 { 527 static const char *pgsz_strings[] = { 528 "8K", "64K", "512K", "4MB", "32MB", 529 "256MB", "2GB", "16GB", 530 }; 531 int i, printed; 532 533 if (tlb_type == cheetah) 534 seq_printf(m, "MMU Type\t: Cheetah\n"); 535 else if (tlb_type == cheetah_plus) 536 seq_printf(m, "MMU Type\t: Cheetah+\n"); 537 else if (tlb_type == spitfire) 538 seq_printf(m, "MMU Type\t: Spitfire\n"); 539 else if (tlb_type == hypervisor) 540 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 541 else 542 seq_printf(m, "MMU Type\t: ???\n"); 543 544 seq_printf(m, "MMU PGSZs\t: "); 545 printed = 0; 546 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 547 if (cpu_pgsz_mask & (1UL << i)) { 548 seq_printf(m, "%s%s", 549 printed ? "," : "", pgsz_strings[i]); 550 printed++; 551 } 552 } 553 seq_putc(m, '\n'); 554 555 #ifdef CONFIG_DEBUG_DCFLUSH 556 seq_printf(m, "DCPageFlushes\t: %d\n", 557 atomic_read(&dcpage_flushes)); 558 #ifdef CONFIG_SMP 559 seq_printf(m, "DCPageFlushesXC\t: %d\n", 560 atomic_read(&dcpage_flushes_xcall)); 561 #endif /* CONFIG_SMP */ 562 #endif /* CONFIG_DEBUG_DCFLUSH */ 563 } 564 565 struct linux_prom_translation prom_trans[512] __read_mostly; 566 unsigned int prom_trans_ents __read_mostly; 567 568 unsigned long kern_locked_tte_data; 569 570 /* The obp translations are saved based on 8k pagesize, since obp can 571 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 572 * HI_OBP_ADDRESS range are handled in ktlb.S. 573 */ 574 static inline int in_obp_range(unsigned long vaddr) 575 { 576 return (vaddr >= LOW_OBP_ADDRESS && 577 vaddr < HI_OBP_ADDRESS); 578 } 579 580 static int cmp_ptrans(const void *a, const void *b) 581 { 582 const struct linux_prom_translation *x = a, *y = b; 583 584 if (x->virt > y->virt) 585 return 1; 586 if (x->virt < y->virt) 587 return -1; 588 return 0; 589 } 590 591 /* Read OBP translations property into 'prom_trans[]'. */ 592 static void __init read_obp_translations(void) 593 { 594 int n, node, ents, first, last, i; 595 596 node = prom_finddevice("/virtual-memory"); 597 n = prom_getproplen(node, "translations"); 598 if (unlikely(n == 0 || n == -1)) { 599 prom_printf("prom_mappings: Couldn't get size.\n"); 600 prom_halt(); 601 } 602 if (unlikely(n > sizeof(prom_trans))) { 603 prom_printf("prom_mappings: Size %d is too big.\n", n); 604 prom_halt(); 605 } 606 607 if ((n = prom_getproperty(node, "translations", 608 (char *)&prom_trans[0], 609 sizeof(prom_trans))) == -1) { 610 prom_printf("prom_mappings: Couldn't get property.\n"); 611 prom_halt(); 612 } 613 614 n = n / sizeof(struct linux_prom_translation); 615 616 ents = n; 617 618 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 619 cmp_ptrans, NULL); 620 621 /* Now kick out all the non-OBP entries. */ 622 for (i = 0; i < ents; i++) { 623 if (in_obp_range(prom_trans[i].virt)) 624 break; 625 } 626 first = i; 627 for (; i < ents; i++) { 628 if (!in_obp_range(prom_trans[i].virt)) 629 break; 630 } 631 last = i; 632 633 for (i = 0; i < (last - first); i++) { 634 struct linux_prom_translation *src = &prom_trans[i + first]; 635 struct linux_prom_translation *dest = &prom_trans[i]; 636 637 *dest = *src; 638 } 639 for (; i < ents; i++) { 640 struct linux_prom_translation *dest = &prom_trans[i]; 641 dest->virt = dest->size = dest->data = 0x0UL; 642 } 643 644 prom_trans_ents = last - first; 645 646 if (tlb_type == spitfire) { 647 /* Clear diag TTE bits. */ 648 for (i = 0; i < prom_trans_ents; i++) 649 prom_trans[i].data &= ~0x0003fe0000000000UL; 650 } 651 652 /* Force execute bit on. */ 653 for (i = 0; i < prom_trans_ents; i++) 654 prom_trans[i].data |= (tlb_type == hypervisor ? 655 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 656 } 657 658 static void __init hypervisor_tlb_lock(unsigned long vaddr, 659 unsigned long pte, 660 unsigned long mmu) 661 { 662 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 663 664 if (ret != 0) { 665 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 666 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 667 prom_halt(); 668 } 669 } 670 671 static unsigned long kern_large_tte(unsigned long paddr); 672 673 static void __init remap_kernel(void) 674 { 675 unsigned long phys_page, tte_vaddr, tte_data; 676 int i, tlb_ent = sparc64_highest_locked_tlbent(); 677 678 tte_vaddr = (unsigned long) KERNBASE; 679 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 680 tte_data = kern_large_tte(phys_page); 681 682 kern_locked_tte_data = tte_data; 683 684 /* Now lock us into the TLBs via Hypervisor or OBP. */ 685 if (tlb_type == hypervisor) { 686 for (i = 0; i < num_kernel_image_mappings; i++) { 687 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 688 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 689 tte_vaddr += 0x400000; 690 tte_data += 0x400000; 691 } 692 } else { 693 for (i = 0; i < num_kernel_image_mappings; i++) { 694 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 695 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 696 tte_vaddr += 0x400000; 697 tte_data += 0x400000; 698 } 699 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 700 } 701 if (tlb_type == cheetah_plus) { 702 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 703 CTX_CHEETAH_PLUS_NUC); 704 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 705 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 706 } 707 } 708 709 710 static void __init inherit_prom_mappings(void) 711 { 712 /* Now fixup OBP's idea about where we really are mapped. */ 713 printk("Remapping the kernel... "); 714 remap_kernel(); 715 printk("done.\n"); 716 } 717 718 void prom_world(int enter) 719 { 720 /* 721 * No need to change the address space any more, just flush 722 * the register windows 723 */ 724 __asm__ __volatile__("flushw"); 725 } 726 727 void __flush_dcache_range(unsigned long start, unsigned long end) 728 { 729 unsigned long va; 730 731 if (tlb_type == spitfire) { 732 int n = 0; 733 734 for (va = start; va < end; va += 32) { 735 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 736 if (++n >= 512) 737 break; 738 } 739 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 740 start = __pa(start); 741 end = __pa(end); 742 for (va = start; va < end; va += 32) 743 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 744 "membar #Sync" 745 : /* no outputs */ 746 : "r" (va), 747 "i" (ASI_DCACHE_INVALIDATE)); 748 } 749 } 750 EXPORT_SYMBOL(__flush_dcache_range); 751 752 /* get_new_mmu_context() uses "cache + 1". */ 753 DEFINE_SPINLOCK(ctx_alloc_lock); 754 unsigned long tlb_context_cache = CTX_FIRST_VERSION; 755 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 756 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 757 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 758 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; 759 760 static void mmu_context_wrap(void) 761 { 762 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; 763 unsigned long new_ver, new_ctx, old_ctx; 764 struct mm_struct *mm; 765 int cpu; 766 767 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); 768 769 /* Reserve kernel context */ 770 set_bit(0, mmu_context_bmap); 771 772 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; 773 if (unlikely(new_ver == 0)) 774 new_ver = CTX_FIRST_VERSION; 775 tlb_context_cache = new_ver; 776 777 /* 778 * Make sure that any new mm that are added into per_cpu_secondary_mm, 779 * are going to go through get_new_mmu_context() path. 780 */ 781 mb(); 782 783 /* 784 * Updated versions to current on those CPUs that had valid secondary 785 * contexts 786 */ 787 for_each_online_cpu(cpu) { 788 /* 789 * If a new mm is stored after we took this mm from the array, 790 * it will go into get_new_mmu_context() path, because we 791 * already bumped the version in tlb_context_cache. 792 */ 793 mm = per_cpu(per_cpu_secondary_mm, cpu); 794 795 if (unlikely(!mm || mm == &init_mm)) 796 continue; 797 798 old_ctx = mm->context.sparc64_ctx_val; 799 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { 800 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; 801 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); 802 mm->context.sparc64_ctx_val = new_ctx; 803 } 804 } 805 } 806 807 /* Caller does TLB context flushing on local CPU if necessary. 808 * The caller also ensures that CTX_VALID(mm->context) is false. 809 * 810 * We must be careful about boundary cases so that we never 811 * let the user have CTX 0 (nucleus) or we ever use a CTX 812 * version of zero (and thus NO_CONTEXT would not be caught 813 * by version mis-match tests in mmu_context.h). 814 * 815 * Always invoked with interrupts disabled. 816 */ 817 void get_new_mmu_context(struct mm_struct *mm) 818 { 819 unsigned long ctx, new_ctx; 820 unsigned long orig_pgsz_bits; 821 822 spin_lock(&ctx_alloc_lock); 823 retry: 824 /* wrap might have happened, test again if our context became valid */ 825 if (unlikely(CTX_VALID(mm->context))) 826 goto out; 827 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 828 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 829 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 830 if (new_ctx >= (1 << CTX_NR_BITS)) { 831 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 832 if (new_ctx >= ctx) { 833 mmu_context_wrap(); 834 goto retry; 835 } 836 } 837 if (mm->context.sparc64_ctx_val) 838 cpumask_clear(mm_cpumask(mm)); 839 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 840 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 841 tlb_context_cache = new_ctx; 842 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 843 out: 844 spin_unlock(&ctx_alloc_lock); 845 } 846 847 static int numa_enabled = 1; 848 static int numa_debug; 849 850 static int __init early_numa(char *p) 851 { 852 if (!p) 853 return 0; 854 855 if (strstr(p, "off")) 856 numa_enabled = 0; 857 858 if (strstr(p, "debug")) 859 numa_debug = 1; 860 861 return 0; 862 } 863 early_param("numa", early_numa); 864 865 #define numadbg(f, a...) \ 866 do { if (numa_debug) \ 867 printk(KERN_INFO f, ## a); \ 868 } while (0) 869 870 static void __init find_ramdisk(unsigned long phys_base) 871 { 872 #ifdef CONFIG_BLK_DEV_INITRD 873 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 874 unsigned long ramdisk_image; 875 876 /* Older versions of the bootloader only supported a 877 * 32-bit physical address for the ramdisk image 878 * location, stored at sparc_ramdisk_image. Newer 879 * SILO versions set sparc_ramdisk_image to zero and 880 * provide a full 64-bit physical address at 881 * sparc_ramdisk_image64. 882 */ 883 ramdisk_image = sparc_ramdisk_image; 884 if (!ramdisk_image) 885 ramdisk_image = sparc_ramdisk_image64; 886 887 /* Another bootloader quirk. The bootloader normalizes 888 * the physical address to KERNBASE, so we have to 889 * factor that back out and add in the lowest valid 890 * physical page address to get the true physical address. 891 */ 892 ramdisk_image -= KERNBASE; 893 ramdisk_image += phys_base; 894 895 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 896 ramdisk_image, sparc_ramdisk_size); 897 898 initrd_start = ramdisk_image; 899 initrd_end = ramdisk_image + sparc_ramdisk_size; 900 901 memblock_reserve(initrd_start, sparc_ramdisk_size); 902 903 initrd_start += PAGE_OFFSET; 904 initrd_end += PAGE_OFFSET; 905 } 906 #endif 907 } 908 909 struct node_mem_mask { 910 unsigned long mask; 911 unsigned long match; 912 }; 913 static struct node_mem_mask node_masks[MAX_NUMNODES]; 914 static int num_node_masks; 915 916 #ifdef CONFIG_NUMA 917 918 struct mdesc_mlgroup { 919 u64 node; 920 u64 latency; 921 u64 match; 922 u64 mask; 923 }; 924 925 static struct mdesc_mlgroup *mlgroups; 926 static int num_mlgroups; 927 928 int numa_cpu_lookup_table[NR_CPUS]; 929 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 930 931 struct mdesc_mblock { 932 u64 base; 933 u64 size; 934 u64 offset; /* RA-to-PA */ 935 }; 936 static struct mdesc_mblock *mblocks; 937 static int num_mblocks; 938 939 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 940 { 941 struct mdesc_mblock *m = NULL; 942 int i; 943 944 for (i = 0; i < num_mblocks; i++) { 945 m = &mblocks[i]; 946 947 if (addr >= m->base && 948 addr < (m->base + m->size)) { 949 break; 950 } 951 } 952 953 return m; 954 } 955 956 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 957 { 958 int prev_nid, new_nid; 959 960 prev_nid = NUMA_NO_NODE; 961 for ( ; start < end; start += PAGE_SIZE) { 962 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 963 struct node_mem_mask *p = &node_masks[new_nid]; 964 965 if ((start & p->mask) == p->match) { 966 if (prev_nid == NUMA_NO_NODE) 967 prev_nid = new_nid; 968 break; 969 } 970 } 971 972 if (new_nid == num_node_masks) { 973 prev_nid = 0; 974 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 975 start); 976 break; 977 } 978 979 if (prev_nid != new_nid) 980 break; 981 } 982 *nid = prev_nid; 983 984 return start > end ? end : start; 985 } 986 987 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 988 { 989 u64 ret_end, pa_start, m_mask, m_match, m_end; 990 struct mdesc_mblock *mblock; 991 int _nid, i; 992 993 if (tlb_type != hypervisor) 994 return memblock_nid_range_sun4u(start, end, nid); 995 996 mblock = addr_to_mblock(start); 997 if (!mblock) { 998 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 999 start); 1000 1001 _nid = 0; 1002 ret_end = end; 1003 goto done; 1004 } 1005 1006 pa_start = start + mblock->offset; 1007 m_match = 0; 1008 m_mask = 0; 1009 1010 for (_nid = 0; _nid < num_node_masks; _nid++) { 1011 struct node_mem_mask *const m = &node_masks[_nid]; 1012 1013 if ((pa_start & m->mask) == m->match) { 1014 m_match = m->match; 1015 m_mask = m->mask; 1016 break; 1017 } 1018 } 1019 1020 if (num_node_masks == _nid) { 1021 /* We could not find NUMA group, so default to 0, but lets 1022 * search for latency group, so we could calculate the correct 1023 * end address that we return 1024 */ 1025 _nid = 0; 1026 1027 for (i = 0; i < num_mlgroups; i++) { 1028 struct mdesc_mlgroup *const m = &mlgroups[i]; 1029 1030 if ((pa_start & m->mask) == m->match) { 1031 m_match = m->match; 1032 m_mask = m->mask; 1033 break; 1034 } 1035 } 1036 1037 if (i == num_mlgroups) { 1038 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 1039 start); 1040 1041 ret_end = end; 1042 goto done; 1043 } 1044 } 1045 1046 /* 1047 * Each latency group has match and mask, and each memory block has an 1048 * offset. An address belongs to a latency group if its address matches 1049 * the following formula: ((addr + offset) & mask) == match 1050 * It is, however, slow to check every single page if it matches a 1051 * particular latency group. As optimization we calculate end value by 1052 * using bit arithmetics. 1053 */ 1054 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 1055 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 1056 ret_end = m_end > end ? end : m_end; 1057 1058 done: 1059 *nid = _nid; 1060 return ret_end; 1061 } 1062 #endif 1063 1064 /* This must be invoked after performing all of the necessary 1065 * memblock_set_node() calls for 'nid'. We need to be able to get 1066 * correct data from get_pfn_range_for_nid(). 1067 */ 1068 static void __init allocate_node_data(int nid) 1069 { 1070 struct pglist_data *p; 1071 unsigned long start_pfn, end_pfn; 1072 1073 #ifdef CONFIG_NUMA 1074 alloc_node_data(nid); 1075 1076 NODE_DATA(nid)->node_id = nid; 1077 #endif 1078 1079 p = NODE_DATA(nid); 1080 1081 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1082 p->node_start_pfn = start_pfn; 1083 p->node_spanned_pages = end_pfn - start_pfn; 1084 } 1085 1086 static void init_node_masks_nonnuma(void) 1087 { 1088 #ifdef CONFIG_NUMA 1089 int i; 1090 #endif 1091 1092 numadbg("Initializing tables for non-numa.\n"); 1093 1094 node_masks[0].mask = 0; 1095 node_masks[0].match = 0; 1096 num_node_masks = 1; 1097 1098 #ifdef CONFIG_NUMA 1099 for (i = 0; i < NR_CPUS; i++) 1100 numa_cpu_lookup_table[i] = 0; 1101 1102 cpumask_setall(&numa_cpumask_lookup_table[0]); 1103 #endif 1104 } 1105 1106 #ifdef CONFIG_NUMA 1107 1108 EXPORT_SYMBOL(numa_cpu_lookup_table); 1109 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1110 1111 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1112 u32 cfg_handle) 1113 { 1114 u64 arc; 1115 1116 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1117 u64 target = mdesc_arc_target(md, arc); 1118 const u64 *val; 1119 1120 val = mdesc_get_property(md, target, 1121 "cfg-handle", NULL); 1122 if (val && *val == cfg_handle) 1123 return 0; 1124 } 1125 return -ENODEV; 1126 } 1127 1128 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1129 u32 cfg_handle) 1130 { 1131 u64 arc, candidate, best_latency = ~(u64)0; 1132 1133 candidate = MDESC_NODE_NULL; 1134 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1135 u64 target = mdesc_arc_target(md, arc); 1136 const char *name = mdesc_node_name(md, target); 1137 const u64 *val; 1138 1139 if (strcmp(name, "pio-latency-group")) 1140 continue; 1141 1142 val = mdesc_get_property(md, target, "latency", NULL); 1143 if (!val) 1144 continue; 1145 1146 if (*val < best_latency) { 1147 candidate = target; 1148 best_latency = *val; 1149 } 1150 } 1151 1152 if (candidate == MDESC_NODE_NULL) 1153 return -ENODEV; 1154 1155 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1156 } 1157 1158 int of_node_to_nid(struct device_node *dp) 1159 { 1160 const struct linux_prom64_registers *regs; 1161 struct mdesc_handle *md; 1162 u32 cfg_handle; 1163 int count, nid; 1164 u64 grp; 1165 1166 /* This is the right thing to do on currently supported 1167 * SUN4U NUMA platforms as well, as the PCI controller does 1168 * not sit behind any particular memory controller. 1169 */ 1170 if (!mlgroups) 1171 return -1; 1172 1173 regs = of_get_property(dp, "reg", NULL); 1174 if (!regs) 1175 return -1; 1176 1177 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1178 1179 md = mdesc_grab(); 1180 1181 count = 0; 1182 nid = NUMA_NO_NODE; 1183 mdesc_for_each_node_by_name(md, grp, "group") { 1184 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1185 nid = count; 1186 break; 1187 } 1188 count++; 1189 } 1190 1191 mdesc_release(md); 1192 1193 return nid; 1194 } 1195 1196 static void __init add_node_ranges(void) 1197 { 1198 phys_addr_t start, end; 1199 unsigned long prev_max; 1200 u64 i; 1201 1202 memblock_resized: 1203 prev_max = memblock.memory.max; 1204 1205 for_each_mem_range(i, &start, &end) { 1206 while (start < end) { 1207 unsigned long this_end; 1208 int nid; 1209 1210 this_end = memblock_nid_range(start, end, &nid); 1211 1212 numadbg("Setting memblock NUMA node nid[%d] " 1213 "start[%llx] end[%lx]\n", 1214 nid, start, this_end); 1215 1216 memblock_set_node(start, this_end - start, 1217 &memblock.memory, nid); 1218 if (memblock.memory.max != prev_max) 1219 goto memblock_resized; 1220 start = this_end; 1221 } 1222 } 1223 } 1224 1225 static int __init grab_mlgroups(struct mdesc_handle *md) 1226 { 1227 unsigned long paddr; 1228 int count = 0; 1229 u64 node; 1230 1231 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1232 count++; 1233 if (!count) 1234 return -ENOENT; 1235 1236 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup), 1237 SMP_CACHE_BYTES); 1238 if (!paddr) 1239 return -ENOMEM; 1240 1241 mlgroups = __va(paddr); 1242 num_mlgroups = count; 1243 1244 count = 0; 1245 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1246 struct mdesc_mlgroup *m = &mlgroups[count++]; 1247 const u64 *val; 1248 1249 m->node = node; 1250 1251 val = mdesc_get_property(md, node, "latency", NULL); 1252 m->latency = *val; 1253 val = mdesc_get_property(md, node, "address-match", NULL); 1254 m->match = *val; 1255 val = mdesc_get_property(md, node, "address-mask", NULL); 1256 m->mask = *val; 1257 1258 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1259 "match[%llx] mask[%llx]\n", 1260 count - 1, m->node, m->latency, m->match, m->mask); 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int __init grab_mblocks(struct mdesc_handle *md) 1267 { 1268 unsigned long paddr; 1269 int count = 0; 1270 u64 node; 1271 1272 mdesc_for_each_node_by_name(md, node, "mblock") 1273 count++; 1274 if (!count) 1275 return -ENOENT; 1276 1277 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock), 1278 SMP_CACHE_BYTES); 1279 if (!paddr) 1280 return -ENOMEM; 1281 1282 mblocks = __va(paddr); 1283 num_mblocks = count; 1284 1285 count = 0; 1286 mdesc_for_each_node_by_name(md, node, "mblock") { 1287 struct mdesc_mblock *m = &mblocks[count++]; 1288 const u64 *val; 1289 1290 val = mdesc_get_property(md, node, "base", NULL); 1291 m->base = *val; 1292 val = mdesc_get_property(md, node, "size", NULL); 1293 m->size = *val; 1294 val = mdesc_get_property(md, node, 1295 "address-congruence-offset", NULL); 1296 1297 /* The address-congruence-offset property is optional. 1298 * Explicity zero it be identifty this. 1299 */ 1300 if (val) 1301 m->offset = *val; 1302 else 1303 m->offset = 0UL; 1304 1305 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1306 count - 1, m->base, m->size, m->offset); 1307 } 1308 1309 return 0; 1310 } 1311 1312 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1313 u64 grp, cpumask_t *mask) 1314 { 1315 u64 arc; 1316 1317 cpumask_clear(mask); 1318 1319 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1320 u64 target = mdesc_arc_target(md, arc); 1321 const char *name = mdesc_node_name(md, target); 1322 const u64 *id; 1323 1324 if (strcmp(name, "cpu")) 1325 continue; 1326 id = mdesc_get_property(md, target, "id", NULL); 1327 if (*id < nr_cpu_ids) 1328 cpumask_set_cpu(*id, mask); 1329 } 1330 } 1331 1332 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1333 { 1334 int i; 1335 1336 for (i = 0; i < num_mlgroups; i++) { 1337 struct mdesc_mlgroup *m = &mlgroups[i]; 1338 if (m->node == node) 1339 return m; 1340 } 1341 return NULL; 1342 } 1343 1344 int __node_distance(int from, int to) 1345 { 1346 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1347 pr_warn("Returning default NUMA distance value for %d->%d\n", 1348 from, to); 1349 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1350 } 1351 return numa_latency[from][to]; 1352 } 1353 EXPORT_SYMBOL(__node_distance); 1354 1355 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1356 { 1357 int i; 1358 1359 for (i = 0; i < MAX_NUMNODES; i++) { 1360 struct node_mem_mask *n = &node_masks[i]; 1361 1362 if ((grp->mask == n->mask) && (grp->match == n->match)) 1363 break; 1364 } 1365 return i; 1366 } 1367 1368 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1369 u64 grp, int index) 1370 { 1371 u64 arc; 1372 1373 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1374 int tnode; 1375 u64 target = mdesc_arc_target(md, arc); 1376 struct mdesc_mlgroup *m = find_mlgroup(target); 1377 1378 if (!m) 1379 continue; 1380 tnode = find_best_numa_node_for_mlgroup(m); 1381 if (tnode == MAX_NUMNODES) 1382 continue; 1383 numa_latency[index][tnode] = m->latency; 1384 } 1385 } 1386 1387 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1388 int index) 1389 { 1390 struct mdesc_mlgroup *candidate = NULL; 1391 u64 arc, best_latency = ~(u64)0; 1392 struct node_mem_mask *n; 1393 1394 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1395 u64 target = mdesc_arc_target(md, arc); 1396 struct mdesc_mlgroup *m = find_mlgroup(target); 1397 if (!m) 1398 continue; 1399 if (m->latency < best_latency) { 1400 candidate = m; 1401 best_latency = m->latency; 1402 } 1403 } 1404 if (!candidate) 1405 return -ENOENT; 1406 1407 if (num_node_masks != index) { 1408 printk(KERN_ERR "Inconsistent NUMA state, " 1409 "index[%d] != num_node_masks[%d]\n", 1410 index, num_node_masks); 1411 return -EINVAL; 1412 } 1413 1414 n = &node_masks[num_node_masks++]; 1415 1416 n->mask = candidate->mask; 1417 n->match = candidate->match; 1418 1419 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1420 index, n->mask, n->match, candidate->latency); 1421 1422 return 0; 1423 } 1424 1425 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1426 int index) 1427 { 1428 cpumask_t mask; 1429 int cpu; 1430 1431 numa_parse_mdesc_group_cpus(md, grp, &mask); 1432 1433 for_each_cpu(cpu, &mask) 1434 numa_cpu_lookup_table[cpu] = index; 1435 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1436 1437 if (numa_debug) { 1438 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1439 for_each_cpu(cpu, &mask) 1440 printk("%d ", cpu); 1441 printk("]\n"); 1442 } 1443 1444 return numa_attach_mlgroup(md, grp, index); 1445 } 1446 1447 static int __init numa_parse_mdesc(void) 1448 { 1449 struct mdesc_handle *md = mdesc_grab(); 1450 int i, j, err, count; 1451 u64 node; 1452 1453 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1454 if (node == MDESC_NODE_NULL) { 1455 mdesc_release(md); 1456 return -ENOENT; 1457 } 1458 1459 err = grab_mblocks(md); 1460 if (err < 0) 1461 goto out; 1462 1463 err = grab_mlgroups(md); 1464 if (err < 0) 1465 goto out; 1466 1467 count = 0; 1468 mdesc_for_each_node_by_name(md, node, "group") { 1469 err = numa_parse_mdesc_group(md, node, count); 1470 if (err < 0) 1471 break; 1472 count++; 1473 } 1474 1475 count = 0; 1476 mdesc_for_each_node_by_name(md, node, "group") { 1477 find_numa_latencies_for_group(md, node, count); 1478 count++; 1479 } 1480 1481 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1482 for (i = 0; i < MAX_NUMNODES; i++) { 1483 u64 self_latency = numa_latency[i][i]; 1484 1485 for (j = 0; j < MAX_NUMNODES; j++) { 1486 numa_latency[i][j] = 1487 (numa_latency[i][j] * LOCAL_DISTANCE) / 1488 self_latency; 1489 } 1490 } 1491 1492 add_node_ranges(); 1493 1494 for (i = 0; i < num_node_masks; i++) { 1495 allocate_node_data(i); 1496 node_set_online(i); 1497 } 1498 1499 err = 0; 1500 out: 1501 mdesc_release(md); 1502 return err; 1503 } 1504 1505 static int __init numa_parse_jbus(void) 1506 { 1507 unsigned long cpu, index; 1508 1509 /* NUMA node id is encoded in bits 36 and higher, and there is 1510 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1511 */ 1512 index = 0; 1513 for_each_present_cpu(cpu) { 1514 numa_cpu_lookup_table[cpu] = index; 1515 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1516 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1517 node_masks[index].match = cpu << 36UL; 1518 1519 index++; 1520 } 1521 num_node_masks = index; 1522 1523 add_node_ranges(); 1524 1525 for (index = 0; index < num_node_masks; index++) { 1526 allocate_node_data(index); 1527 node_set_online(index); 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int __init numa_parse_sun4u(void) 1534 { 1535 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1536 unsigned long ver; 1537 1538 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1539 if ((ver >> 32UL) == __JALAPENO_ID || 1540 (ver >> 32UL) == __SERRANO_ID) 1541 return numa_parse_jbus(); 1542 } 1543 return -1; 1544 } 1545 1546 static int __init bootmem_init_numa(void) 1547 { 1548 int i, j; 1549 int err = -1; 1550 1551 numadbg("bootmem_init_numa()\n"); 1552 1553 /* Some sane defaults for numa latency values */ 1554 for (i = 0; i < MAX_NUMNODES; i++) { 1555 for (j = 0; j < MAX_NUMNODES; j++) 1556 numa_latency[i][j] = (i == j) ? 1557 LOCAL_DISTANCE : REMOTE_DISTANCE; 1558 } 1559 1560 if (numa_enabled) { 1561 if (tlb_type == hypervisor) 1562 err = numa_parse_mdesc(); 1563 else 1564 err = numa_parse_sun4u(); 1565 } 1566 return err; 1567 } 1568 1569 #else 1570 1571 static int bootmem_init_numa(void) 1572 { 1573 return -1; 1574 } 1575 1576 #endif 1577 1578 static void __init bootmem_init_nonnuma(void) 1579 { 1580 unsigned long top_of_ram = memblock_end_of_DRAM(); 1581 unsigned long total_ram = memblock_phys_mem_size(); 1582 1583 numadbg("bootmem_init_nonnuma()\n"); 1584 1585 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1586 top_of_ram, total_ram); 1587 printk(KERN_INFO "Memory hole size: %ldMB\n", 1588 (top_of_ram - total_ram) >> 20); 1589 1590 init_node_masks_nonnuma(); 1591 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0); 1592 allocate_node_data(0); 1593 node_set_online(0); 1594 } 1595 1596 static unsigned long __init bootmem_init(unsigned long phys_base) 1597 { 1598 unsigned long end_pfn; 1599 1600 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1601 max_pfn = max_low_pfn = end_pfn; 1602 min_low_pfn = (phys_base >> PAGE_SHIFT); 1603 1604 if (bootmem_init_numa() < 0) 1605 bootmem_init_nonnuma(); 1606 1607 /* Dump memblock with node info. */ 1608 memblock_dump_all(); 1609 1610 /* XXX cpu notifier XXX */ 1611 1612 return end_pfn; 1613 } 1614 1615 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1616 static int pall_ents __initdata; 1617 1618 static unsigned long max_phys_bits = 40; 1619 1620 bool kern_addr_valid(unsigned long addr) 1621 { 1622 pgd_t *pgd; 1623 p4d_t *p4d; 1624 pud_t *pud; 1625 pmd_t *pmd; 1626 pte_t *pte; 1627 1628 if ((long)addr < 0L) { 1629 unsigned long pa = __pa(addr); 1630 1631 if ((pa >> max_phys_bits) != 0UL) 1632 return false; 1633 1634 return pfn_valid(pa >> PAGE_SHIFT); 1635 } 1636 1637 if (addr >= (unsigned long) KERNBASE && 1638 addr < (unsigned long)&_end) 1639 return true; 1640 1641 pgd = pgd_offset_k(addr); 1642 if (pgd_none(*pgd)) 1643 return false; 1644 1645 p4d = p4d_offset(pgd, addr); 1646 if (p4d_none(*p4d)) 1647 return false; 1648 1649 pud = pud_offset(p4d, addr); 1650 if (pud_none(*pud)) 1651 return false; 1652 1653 if (pud_leaf(*pud)) 1654 return pfn_valid(pud_pfn(*pud)); 1655 1656 pmd = pmd_offset(pud, addr); 1657 if (pmd_none(*pmd)) 1658 return false; 1659 1660 if (pmd_leaf(*pmd)) 1661 return pfn_valid(pmd_pfn(*pmd)); 1662 1663 pte = pte_offset_kernel(pmd, addr); 1664 if (pte_none(*pte)) 1665 return false; 1666 1667 return pfn_valid(pte_pfn(*pte)); 1668 } 1669 1670 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1671 unsigned long vend, 1672 pud_t *pud) 1673 { 1674 const unsigned long mask16gb = (1UL << 34) - 1UL; 1675 u64 pte_val = vstart; 1676 1677 /* Each PUD is 8GB */ 1678 if ((vstart & mask16gb) || 1679 (vend - vstart <= mask16gb)) { 1680 pte_val ^= kern_linear_pte_xor[2]; 1681 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1682 1683 return vstart + PUD_SIZE; 1684 } 1685 1686 pte_val ^= kern_linear_pte_xor[3]; 1687 pte_val |= _PAGE_PUD_HUGE; 1688 1689 vend = vstart + mask16gb + 1UL; 1690 while (vstart < vend) { 1691 pud_val(*pud) = pte_val; 1692 1693 pte_val += PUD_SIZE; 1694 vstart += PUD_SIZE; 1695 pud++; 1696 } 1697 return vstart; 1698 } 1699 1700 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1701 bool guard) 1702 { 1703 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1704 return true; 1705 1706 return false; 1707 } 1708 1709 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1710 unsigned long vend, 1711 pmd_t *pmd) 1712 { 1713 const unsigned long mask256mb = (1UL << 28) - 1UL; 1714 const unsigned long mask2gb = (1UL << 31) - 1UL; 1715 u64 pte_val = vstart; 1716 1717 /* Each PMD is 8MB */ 1718 if ((vstart & mask256mb) || 1719 (vend - vstart <= mask256mb)) { 1720 pte_val ^= kern_linear_pte_xor[0]; 1721 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1722 1723 return vstart + PMD_SIZE; 1724 } 1725 1726 if ((vstart & mask2gb) || 1727 (vend - vstart <= mask2gb)) { 1728 pte_val ^= kern_linear_pte_xor[1]; 1729 pte_val |= _PAGE_PMD_HUGE; 1730 vend = vstart + mask256mb + 1UL; 1731 } else { 1732 pte_val ^= kern_linear_pte_xor[2]; 1733 pte_val |= _PAGE_PMD_HUGE; 1734 vend = vstart + mask2gb + 1UL; 1735 } 1736 1737 while (vstart < vend) { 1738 pmd_val(*pmd) = pte_val; 1739 1740 pte_val += PMD_SIZE; 1741 vstart += PMD_SIZE; 1742 pmd++; 1743 } 1744 1745 return vstart; 1746 } 1747 1748 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1749 bool guard) 1750 { 1751 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1752 return true; 1753 1754 return false; 1755 } 1756 1757 static unsigned long __ref kernel_map_range(unsigned long pstart, 1758 unsigned long pend, pgprot_t prot, 1759 bool use_huge) 1760 { 1761 unsigned long vstart = PAGE_OFFSET + pstart; 1762 unsigned long vend = PAGE_OFFSET + pend; 1763 unsigned long alloc_bytes = 0UL; 1764 1765 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1766 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1767 vstart, vend); 1768 prom_halt(); 1769 } 1770 1771 while (vstart < vend) { 1772 unsigned long this_end, paddr = __pa(vstart); 1773 pgd_t *pgd = pgd_offset_k(vstart); 1774 p4d_t *p4d; 1775 pud_t *pud; 1776 pmd_t *pmd; 1777 pte_t *pte; 1778 1779 if (pgd_none(*pgd)) { 1780 pud_t *new; 1781 1782 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1783 PAGE_SIZE); 1784 if (!new) 1785 goto err_alloc; 1786 alloc_bytes += PAGE_SIZE; 1787 pgd_populate(&init_mm, pgd, new); 1788 } 1789 1790 p4d = p4d_offset(pgd, vstart); 1791 if (p4d_none(*p4d)) { 1792 pud_t *new; 1793 1794 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1795 PAGE_SIZE); 1796 if (!new) 1797 goto err_alloc; 1798 alloc_bytes += PAGE_SIZE; 1799 p4d_populate(&init_mm, p4d, new); 1800 } 1801 1802 pud = pud_offset(p4d, vstart); 1803 if (pud_none(*pud)) { 1804 pmd_t *new; 1805 1806 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1807 vstart = kernel_map_hugepud(vstart, vend, pud); 1808 continue; 1809 } 1810 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1811 PAGE_SIZE); 1812 if (!new) 1813 goto err_alloc; 1814 alloc_bytes += PAGE_SIZE; 1815 pud_populate(&init_mm, pud, new); 1816 } 1817 1818 pmd = pmd_offset(pud, vstart); 1819 if (pmd_none(*pmd)) { 1820 pte_t *new; 1821 1822 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1823 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1824 continue; 1825 } 1826 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1827 PAGE_SIZE); 1828 if (!new) 1829 goto err_alloc; 1830 alloc_bytes += PAGE_SIZE; 1831 pmd_populate_kernel(&init_mm, pmd, new); 1832 } 1833 1834 pte = pte_offset_kernel(pmd, vstart); 1835 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1836 if (this_end > vend) 1837 this_end = vend; 1838 1839 while (vstart < this_end) { 1840 pte_val(*pte) = (paddr | pgprot_val(prot)); 1841 1842 vstart += PAGE_SIZE; 1843 paddr += PAGE_SIZE; 1844 pte++; 1845 } 1846 } 1847 1848 return alloc_bytes; 1849 1850 err_alloc: 1851 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n", 1852 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1853 return -ENOMEM; 1854 } 1855 1856 static void __init flush_all_kernel_tsbs(void) 1857 { 1858 int i; 1859 1860 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1861 struct tsb *ent = &swapper_tsb[i]; 1862 1863 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1864 } 1865 #ifndef CONFIG_DEBUG_PAGEALLOC 1866 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1867 struct tsb *ent = &swapper_4m_tsb[i]; 1868 1869 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1870 } 1871 #endif 1872 } 1873 1874 extern unsigned int kvmap_linear_patch[1]; 1875 1876 static void __init kernel_physical_mapping_init(void) 1877 { 1878 unsigned long i, mem_alloced = 0UL; 1879 bool use_huge = true; 1880 1881 #ifdef CONFIG_DEBUG_PAGEALLOC 1882 use_huge = false; 1883 #endif 1884 for (i = 0; i < pall_ents; i++) { 1885 unsigned long phys_start, phys_end; 1886 1887 phys_start = pall[i].phys_addr; 1888 phys_end = phys_start + pall[i].reg_size; 1889 1890 mem_alloced += kernel_map_range(phys_start, phys_end, 1891 PAGE_KERNEL, use_huge); 1892 } 1893 1894 printk("Allocated %ld bytes for kernel page tables.\n", 1895 mem_alloced); 1896 1897 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1898 flushi(&kvmap_linear_patch[0]); 1899 1900 flush_all_kernel_tsbs(); 1901 1902 __flush_tlb_all(); 1903 } 1904 1905 #ifdef CONFIG_DEBUG_PAGEALLOC 1906 void __kernel_map_pages(struct page *page, int numpages, int enable) 1907 { 1908 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1909 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1910 1911 kernel_map_range(phys_start, phys_end, 1912 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1913 1914 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1915 PAGE_OFFSET + phys_end); 1916 1917 /* we should perform an IPI and flush all tlbs, 1918 * but that can deadlock->flush only current cpu. 1919 */ 1920 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1921 PAGE_OFFSET + phys_end); 1922 } 1923 #endif 1924 1925 unsigned long __init find_ecache_flush_span(unsigned long size) 1926 { 1927 int i; 1928 1929 for (i = 0; i < pavail_ents; i++) { 1930 if (pavail[i].reg_size >= size) 1931 return pavail[i].phys_addr; 1932 } 1933 1934 return ~0UL; 1935 } 1936 1937 unsigned long PAGE_OFFSET; 1938 EXPORT_SYMBOL(PAGE_OFFSET); 1939 1940 unsigned long VMALLOC_END = 0x0000010000000000UL; 1941 EXPORT_SYMBOL(VMALLOC_END); 1942 1943 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1944 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1945 1946 static void __init setup_page_offset(void) 1947 { 1948 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1949 /* Cheetah/Panther support a full 64-bit virtual 1950 * address, so we can use all that our page tables 1951 * support. 1952 */ 1953 sparc64_va_hole_top = 0xfff0000000000000UL; 1954 sparc64_va_hole_bottom = 0x0010000000000000UL; 1955 1956 max_phys_bits = 42; 1957 } else if (tlb_type == hypervisor) { 1958 switch (sun4v_chip_type) { 1959 case SUN4V_CHIP_NIAGARA1: 1960 case SUN4V_CHIP_NIAGARA2: 1961 /* T1 and T2 support 48-bit virtual addresses. */ 1962 sparc64_va_hole_top = 0xffff800000000000UL; 1963 sparc64_va_hole_bottom = 0x0000800000000000UL; 1964 1965 max_phys_bits = 39; 1966 break; 1967 case SUN4V_CHIP_NIAGARA3: 1968 /* T3 supports 48-bit virtual addresses. */ 1969 sparc64_va_hole_top = 0xffff800000000000UL; 1970 sparc64_va_hole_bottom = 0x0000800000000000UL; 1971 1972 max_phys_bits = 43; 1973 break; 1974 case SUN4V_CHIP_NIAGARA4: 1975 case SUN4V_CHIP_NIAGARA5: 1976 case SUN4V_CHIP_SPARC64X: 1977 case SUN4V_CHIP_SPARC_M6: 1978 /* T4 and later support 52-bit virtual addresses. */ 1979 sparc64_va_hole_top = 0xfff8000000000000UL; 1980 sparc64_va_hole_bottom = 0x0008000000000000UL; 1981 max_phys_bits = 47; 1982 break; 1983 case SUN4V_CHIP_SPARC_M7: 1984 case SUN4V_CHIP_SPARC_SN: 1985 /* M7 and later support 52-bit virtual addresses. */ 1986 sparc64_va_hole_top = 0xfff8000000000000UL; 1987 sparc64_va_hole_bottom = 0x0008000000000000UL; 1988 max_phys_bits = 49; 1989 break; 1990 case SUN4V_CHIP_SPARC_M8: 1991 default: 1992 /* M8 and later support 54-bit virtual addresses. 1993 * However, restricting M8 and above VA bits to 53 1994 * as 4-level page table cannot support more than 1995 * 53 VA bits. 1996 */ 1997 sparc64_va_hole_top = 0xfff0000000000000UL; 1998 sparc64_va_hole_bottom = 0x0010000000000000UL; 1999 max_phys_bits = 51; 2000 break; 2001 } 2002 } 2003 2004 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 2005 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 2006 max_phys_bits); 2007 prom_halt(); 2008 } 2009 2010 PAGE_OFFSET = sparc64_va_hole_top; 2011 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 2012 (sparc64_va_hole_bottom >> 2)); 2013 2014 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 2015 PAGE_OFFSET, max_phys_bits); 2016 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 2017 VMALLOC_START, VMALLOC_END); 2018 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 2019 VMEMMAP_BASE, VMEMMAP_BASE << 1); 2020 } 2021 2022 static void __init tsb_phys_patch(void) 2023 { 2024 struct tsb_ldquad_phys_patch_entry *pquad; 2025 struct tsb_phys_patch_entry *p; 2026 2027 pquad = &__tsb_ldquad_phys_patch; 2028 while (pquad < &__tsb_ldquad_phys_patch_end) { 2029 unsigned long addr = pquad->addr; 2030 2031 if (tlb_type == hypervisor) 2032 *(unsigned int *) addr = pquad->sun4v_insn; 2033 else 2034 *(unsigned int *) addr = pquad->sun4u_insn; 2035 wmb(); 2036 __asm__ __volatile__("flush %0" 2037 : /* no outputs */ 2038 : "r" (addr)); 2039 2040 pquad++; 2041 } 2042 2043 p = &__tsb_phys_patch; 2044 while (p < &__tsb_phys_patch_end) { 2045 unsigned long addr = p->addr; 2046 2047 *(unsigned int *) addr = p->insn; 2048 wmb(); 2049 __asm__ __volatile__("flush %0" 2050 : /* no outputs */ 2051 : "r" (addr)); 2052 2053 p++; 2054 } 2055 } 2056 2057 /* Don't mark as init, we give this to the Hypervisor. */ 2058 #ifndef CONFIG_DEBUG_PAGEALLOC 2059 #define NUM_KTSB_DESCR 2 2060 #else 2061 #define NUM_KTSB_DESCR 1 2062 #endif 2063 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 2064 2065 /* The swapper TSBs are loaded with a base sequence of: 2066 * 2067 * sethi %uhi(SYMBOL), REG1 2068 * sethi %hi(SYMBOL), REG2 2069 * or REG1, %ulo(SYMBOL), REG1 2070 * or REG2, %lo(SYMBOL), REG2 2071 * sllx REG1, 32, REG1 2072 * or REG1, REG2, REG1 2073 * 2074 * When we use physical addressing for the TSB accesses, we patch the 2075 * first four instructions in the above sequence. 2076 */ 2077 2078 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 2079 { 2080 unsigned long high_bits, low_bits; 2081 2082 high_bits = (pa >> 32) & 0xffffffff; 2083 low_bits = (pa >> 0) & 0xffffffff; 2084 2085 while (start < end) { 2086 unsigned int *ia = (unsigned int *)(unsigned long)*start; 2087 2088 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 2089 __asm__ __volatile__("flush %0" : : "r" (ia)); 2090 2091 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 2092 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 2093 2094 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 2095 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 2096 2097 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 2098 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 2099 2100 start++; 2101 } 2102 } 2103 2104 static void ktsb_phys_patch(void) 2105 { 2106 extern unsigned int __swapper_tsb_phys_patch; 2107 extern unsigned int __swapper_tsb_phys_patch_end; 2108 unsigned long ktsb_pa; 2109 2110 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2111 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2112 &__swapper_tsb_phys_patch_end, ktsb_pa); 2113 #ifndef CONFIG_DEBUG_PAGEALLOC 2114 { 2115 extern unsigned int __swapper_4m_tsb_phys_patch; 2116 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2117 ktsb_pa = (kern_base + 2118 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2119 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2120 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2121 } 2122 #endif 2123 } 2124 2125 static void __init sun4v_ktsb_init(void) 2126 { 2127 unsigned long ktsb_pa; 2128 2129 /* First KTSB for PAGE_SIZE mappings. */ 2130 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2131 2132 switch (PAGE_SIZE) { 2133 case 8 * 1024: 2134 default: 2135 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2136 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2137 break; 2138 2139 case 64 * 1024: 2140 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2141 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2142 break; 2143 2144 case 512 * 1024: 2145 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2146 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2147 break; 2148 2149 case 4 * 1024 * 1024: 2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2152 break; 2153 } 2154 2155 ktsb_descr[0].assoc = 1; 2156 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2157 ktsb_descr[0].ctx_idx = 0; 2158 ktsb_descr[0].tsb_base = ktsb_pa; 2159 ktsb_descr[0].resv = 0; 2160 2161 #ifndef CONFIG_DEBUG_PAGEALLOC 2162 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2163 ktsb_pa = (kern_base + 2164 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2165 2166 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2167 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2168 HV_PGSZ_MASK_256MB | 2169 HV_PGSZ_MASK_2GB | 2170 HV_PGSZ_MASK_16GB) & 2171 cpu_pgsz_mask); 2172 ktsb_descr[1].assoc = 1; 2173 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2174 ktsb_descr[1].ctx_idx = 0; 2175 ktsb_descr[1].tsb_base = ktsb_pa; 2176 ktsb_descr[1].resv = 0; 2177 #endif 2178 } 2179 2180 void sun4v_ktsb_register(void) 2181 { 2182 unsigned long pa, ret; 2183 2184 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2185 2186 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2187 if (ret != 0) { 2188 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2189 "errors with %lx\n", pa, ret); 2190 prom_halt(); 2191 } 2192 } 2193 2194 static void __init sun4u_linear_pte_xor_finalize(void) 2195 { 2196 #ifndef CONFIG_DEBUG_PAGEALLOC 2197 /* This is where we would add Panther support for 2198 * 32MB and 256MB pages. 2199 */ 2200 #endif 2201 } 2202 2203 static void __init sun4v_linear_pte_xor_finalize(void) 2204 { 2205 unsigned long pagecv_flag; 2206 2207 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2208 * enables MCD error. Do not set bit 9 on M7 processor. 2209 */ 2210 switch (sun4v_chip_type) { 2211 case SUN4V_CHIP_SPARC_M7: 2212 case SUN4V_CHIP_SPARC_M8: 2213 case SUN4V_CHIP_SPARC_SN: 2214 pagecv_flag = 0x00; 2215 break; 2216 default: 2217 pagecv_flag = _PAGE_CV_4V; 2218 break; 2219 } 2220 #ifndef CONFIG_DEBUG_PAGEALLOC 2221 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2222 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2223 PAGE_OFFSET; 2224 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2225 _PAGE_P_4V | _PAGE_W_4V); 2226 } else { 2227 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2228 } 2229 2230 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2231 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2232 PAGE_OFFSET; 2233 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2234 _PAGE_P_4V | _PAGE_W_4V); 2235 } else { 2236 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2237 } 2238 2239 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2240 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2241 PAGE_OFFSET; 2242 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2243 _PAGE_P_4V | _PAGE_W_4V); 2244 } else { 2245 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2246 } 2247 #endif 2248 } 2249 2250 /* paging_init() sets up the page tables */ 2251 2252 static unsigned long last_valid_pfn; 2253 2254 static void sun4u_pgprot_init(void); 2255 static void sun4v_pgprot_init(void); 2256 2257 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2258 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2259 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2260 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2261 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2262 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2263 2264 /* We need to exclude reserved regions. This exclusion will include 2265 * vmlinux and initrd. To be more precise the initrd size could be used to 2266 * compute a new lower limit because it is freed later during initialization. 2267 */ 2268 static void __init reduce_memory(phys_addr_t limit_ram) 2269 { 2270 limit_ram += memblock_reserved_size(); 2271 memblock_enforce_memory_limit(limit_ram); 2272 } 2273 2274 void __init arch_zone_limits_init(unsigned long *max_zone_pfns) 2275 { 2276 max_zone_pfns[ZONE_NORMAL] = last_valid_pfn; 2277 } 2278 2279 void __init paging_init(void) 2280 { 2281 unsigned long end_pfn, shift, phys_base; 2282 unsigned long real_end, i; 2283 2284 setup_page_offset(); 2285 2286 /* These build time checkes make sure that the dcache_dirty_cpu() 2287 * folio->flags usage will work. 2288 * 2289 * When a page gets marked as dcache-dirty, we store the 2290 * cpu number starting at bit 32 in the folio->flags. Also, 2291 * functions like clear_dcache_dirty_cpu use the cpu mask 2292 * in 13-bit signed-immediate instruction fields. 2293 */ 2294 2295 /* 2296 * Page flags must not reach into upper 32 bits that are used 2297 * for the cpu number 2298 */ 2299 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2300 2301 /* 2302 * The bit fields placed in the high range must not reach below 2303 * the 32 bit boundary. Otherwise we cannot place the cpu field 2304 * at the 32 bit boundary. 2305 */ 2306 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2307 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2308 2309 BUILD_BUG_ON(NR_CPUS > 4096); 2310 2311 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2312 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2313 2314 /* Invalidate both kernel TSBs. */ 2315 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2316 #ifndef CONFIG_DEBUG_PAGEALLOC 2317 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2318 #endif 2319 2320 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2321 * bit on M7 processor. This is a conflicting usage of the same 2322 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2323 * Detection error on all pages and this will lead to problems 2324 * later. Kernel does not run with MCD enabled and hence rest 2325 * of the required steps to fully configure memory corruption 2326 * detection are not taken. We need to ensure TTE.mcde is not 2327 * set on M7 processor. Compute the value of cacheability 2328 * flag for use later taking this into consideration. 2329 */ 2330 switch (sun4v_chip_type) { 2331 case SUN4V_CHIP_SPARC_M7: 2332 case SUN4V_CHIP_SPARC_M8: 2333 case SUN4V_CHIP_SPARC_SN: 2334 page_cache4v_flag = _PAGE_CP_4V; 2335 break; 2336 default: 2337 page_cache4v_flag = _PAGE_CACHE_4V; 2338 break; 2339 } 2340 2341 if (tlb_type == hypervisor) 2342 sun4v_pgprot_init(); 2343 else 2344 sun4u_pgprot_init(); 2345 2346 if (tlb_type == cheetah_plus || 2347 tlb_type == hypervisor) { 2348 tsb_phys_patch(); 2349 ktsb_phys_patch(); 2350 } 2351 2352 if (tlb_type == hypervisor) 2353 sun4v_patch_tlb_handlers(); 2354 2355 /* Find available physical memory... 2356 * 2357 * Read it twice in order to work around a bug in openfirmware. 2358 * The call to grab this table itself can cause openfirmware to 2359 * allocate memory, which in turn can take away some space from 2360 * the list of available memory. Reading it twice makes sure 2361 * we really do get the final value. 2362 */ 2363 read_obp_translations(); 2364 read_obp_memory("reg", &pall[0], &pall_ents); 2365 read_obp_memory("available", &pavail[0], &pavail_ents); 2366 read_obp_memory("available", &pavail[0], &pavail_ents); 2367 2368 phys_base = 0xffffffffffffffffUL; 2369 for (i = 0; i < pavail_ents; i++) { 2370 phys_base = min(phys_base, pavail[i].phys_addr); 2371 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2372 } 2373 2374 memblock_reserve(kern_base, kern_size); 2375 2376 find_ramdisk(phys_base); 2377 2378 if (cmdline_memory_size) 2379 reduce_memory(cmdline_memory_size); 2380 2381 memblock_allow_resize(); 2382 memblock_dump_all(); 2383 2384 set_bit(0, mmu_context_bmap); 2385 2386 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2387 2388 real_end = (unsigned long)_end; 2389 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2390 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2391 num_kernel_image_mappings); 2392 2393 /* Set kernel pgd to upper alias so physical page computations 2394 * work. 2395 */ 2396 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2397 2398 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2399 2400 inherit_prom_mappings(); 2401 2402 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2403 setup_tba(); 2404 2405 __flush_tlb_all(); 2406 2407 prom_build_devicetree(); 2408 of_populate_present_mask(); 2409 #ifndef CONFIG_SMP 2410 of_fill_in_cpu_data(); 2411 #endif 2412 2413 if (tlb_type == hypervisor) { 2414 sun4v_mdesc_init(); 2415 mdesc_populate_present_mask(cpu_all_mask); 2416 #ifndef CONFIG_SMP 2417 mdesc_fill_in_cpu_data(cpu_all_mask); 2418 #endif 2419 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2420 2421 sun4v_linear_pte_xor_finalize(); 2422 2423 sun4v_ktsb_init(); 2424 sun4v_ktsb_register(); 2425 } else { 2426 unsigned long impl, ver; 2427 2428 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2429 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2430 2431 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2432 impl = ((ver >> 32) & 0xffff); 2433 if (impl == PANTHER_IMPL) 2434 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2435 HV_PGSZ_MASK_256MB); 2436 2437 sun4u_linear_pte_xor_finalize(); 2438 } 2439 2440 /* Flush the TLBs and the 4M TSB so that the updated linear 2441 * pte XOR settings are realized for all mappings. 2442 */ 2443 __flush_tlb_all(); 2444 #ifndef CONFIG_DEBUG_PAGEALLOC 2445 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2446 #endif 2447 __flush_tlb_all(); 2448 2449 /* Setup bootmem... */ 2450 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2451 2452 kernel_physical_mapping_init(); 2453 2454 printk("Booting Linux...\n"); 2455 } 2456 2457 int page_in_phys_avail(unsigned long paddr) 2458 { 2459 int i; 2460 2461 paddr &= PAGE_MASK; 2462 2463 for (i = 0; i < pavail_ents; i++) { 2464 unsigned long start, end; 2465 2466 start = pavail[i].phys_addr; 2467 end = start + pavail[i].reg_size; 2468 2469 if (paddr >= start && paddr < end) 2470 return 1; 2471 } 2472 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2473 return 1; 2474 #ifdef CONFIG_BLK_DEV_INITRD 2475 if (paddr >= __pa(initrd_start) && 2476 paddr < __pa(PAGE_ALIGN(initrd_end))) 2477 return 1; 2478 #endif 2479 2480 return 0; 2481 } 2482 2483 static void __init register_page_bootmem_info(void) 2484 { 2485 #ifdef CONFIG_NUMA 2486 int i; 2487 2488 for_each_online_node(i) 2489 if (NODE_DATA(i)->node_spanned_pages) 2490 register_page_bootmem_info_node(NODE_DATA(i)); 2491 #endif 2492 } 2493 void __init mem_init(void) 2494 { 2495 /* 2496 * Must be done after boot memory is put on freelist, because here we 2497 * might set fields in deferred struct pages that have not yet been 2498 * initialized, and memblock_free_all() initializes all the reserved 2499 * deferred pages for us. 2500 */ 2501 register_page_bootmem_info(); 2502 2503 /* 2504 * Set up the zero page, mark it reserved, so that page count 2505 * is not manipulated when freeing the page from user ptes. 2506 */ 2507 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 2508 if (mem_map_zero == NULL) { 2509 prom_printf("paging_init: Cannot alloc zero page.\n"); 2510 prom_halt(); 2511 } 2512 mark_page_reserved(mem_map_zero); 2513 2514 2515 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2516 cheetah_ecache_flush_init(); 2517 } 2518 2519 void free_initmem(void) 2520 { 2521 unsigned long addr, initend; 2522 int do_free = 1; 2523 2524 /* If the physical memory maps were trimmed by kernel command 2525 * line options, don't even try freeing this initmem stuff up. 2526 * The kernel image could have been in the trimmed out region 2527 * and if so the freeing below will free invalid page structs. 2528 */ 2529 if (cmdline_memory_size) 2530 do_free = 0; 2531 2532 /* 2533 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2534 */ 2535 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2536 initend = (unsigned long)(__init_end) & PAGE_MASK; 2537 for (; addr < initend; addr += PAGE_SIZE) { 2538 unsigned long page; 2539 2540 page = (addr + 2541 ((unsigned long) __va(kern_base)) - 2542 ((unsigned long) KERNBASE)); 2543 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2544 2545 if (do_free) 2546 free_reserved_page(virt_to_page(page)); 2547 } 2548 } 2549 2550 pgprot_t PAGE_KERNEL __read_mostly; 2551 EXPORT_SYMBOL(PAGE_KERNEL); 2552 2553 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2554 pgprot_t PAGE_COPY __read_mostly; 2555 2556 pgprot_t PAGE_SHARED __read_mostly; 2557 EXPORT_SYMBOL(PAGE_SHARED); 2558 2559 unsigned long pg_iobits __read_mostly; 2560 2561 unsigned long _PAGE_IE __read_mostly; 2562 EXPORT_SYMBOL(_PAGE_IE); 2563 2564 unsigned long _PAGE_E __read_mostly; 2565 EXPORT_SYMBOL(_PAGE_E); 2566 2567 unsigned long _PAGE_CACHE __read_mostly; 2568 EXPORT_SYMBOL(_PAGE_CACHE); 2569 2570 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2571 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2572 int node, struct vmem_altmap *altmap) 2573 { 2574 unsigned long pte_base; 2575 2576 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2577 _PAGE_CP_4U | _PAGE_CV_4U | 2578 _PAGE_P_4U | _PAGE_W_4U); 2579 if (tlb_type == hypervisor) 2580 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2581 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2582 2583 pte_base |= _PAGE_PMD_HUGE; 2584 2585 vstart = vstart & PMD_MASK; 2586 vend = ALIGN(vend, PMD_SIZE); 2587 for (; vstart < vend; vstart += PMD_SIZE) { 2588 pgd_t *pgd = vmemmap_pgd_populate(vstart, node); 2589 unsigned long pte; 2590 p4d_t *p4d; 2591 pud_t *pud; 2592 pmd_t *pmd; 2593 2594 if (!pgd) 2595 return -ENOMEM; 2596 2597 p4d = vmemmap_p4d_populate(pgd, vstart, node); 2598 if (!p4d) 2599 return -ENOMEM; 2600 2601 pud = vmemmap_pud_populate(p4d, vstart, node); 2602 if (!pud) 2603 return -ENOMEM; 2604 2605 pmd = pmd_offset(pud, vstart); 2606 pte = pmd_val(*pmd); 2607 if (!(pte & _PAGE_VALID)) { 2608 void *block = vmemmap_alloc_block(PMD_SIZE, node); 2609 2610 if (!block) 2611 return -ENOMEM; 2612 2613 pmd_val(*pmd) = pte_base | __pa(block); 2614 } 2615 } 2616 2617 return 0; 2618 } 2619 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2620 2621 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 2622 static pgprot_t protection_map[16] __ro_after_init; 2623 2624 static void prot_init_common(unsigned long page_none, 2625 unsigned long page_shared, 2626 unsigned long page_copy, 2627 unsigned long page_readonly, 2628 unsigned long page_exec_bit) 2629 { 2630 PAGE_COPY = __pgprot(page_copy); 2631 PAGE_SHARED = __pgprot(page_shared); 2632 2633 protection_map[0x0] = __pgprot(page_none); 2634 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2635 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2636 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2637 protection_map[0x4] = __pgprot(page_readonly); 2638 protection_map[0x5] = __pgprot(page_readonly); 2639 protection_map[0x6] = __pgprot(page_copy); 2640 protection_map[0x7] = __pgprot(page_copy); 2641 protection_map[0x8] = __pgprot(page_none); 2642 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2643 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2644 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2645 protection_map[0xc] = __pgprot(page_readonly); 2646 protection_map[0xd] = __pgprot(page_readonly); 2647 protection_map[0xe] = __pgprot(page_shared); 2648 protection_map[0xf] = __pgprot(page_shared); 2649 } 2650 2651 static void __init sun4u_pgprot_init(void) 2652 { 2653 unsigned long page_none, page_shared, page_copy, page_readonly; 2654 unsigned long page_exec_bit; 2655 int i; 2656 2657 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2658 _PAGE_CACHE_4U | _PAGE_P_4U | 2659 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2660 _PAGE_EXEC_4U); 2661 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2662 _PAGE_CACHE_4U | _PAGE_P_4U | 2663 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2664 _PAGE_EXEC_4U | _PAGE_L_4U); 2665 2666 _PAGE_IE = _PAGE_IE_4U; 2667 _PAGE_E = _PAGE_E_4U; 2668 _PAGE_CACHE = _PAGE_CACHE_4U; 2669 2670 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2671 __ACCESS_BITS_4U | _PAGE_E_4U); 2672 2673 #ifdef CONFIG_DEBUG_PAGEALLOC 2674 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2675 #else 2676 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2677 PAGE_OFFSET; 2678 #endif 2679 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2680 _PAGE_P_4U | _PAGE_W_4U); 2681 2682 for (i = 1; i < 4; i++) 2683 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2684 2685 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2686 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2687 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2688 2689 2690 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2691 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2692 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2693 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2694 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2695 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2696 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2697 2698 page_exec_bit = _PAGE_EXEC_4U; 2699 2700 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2701 page_exec_bit); 2702 } 2703 2704 static void __init sun4v_pgprot_init(void) 2705 { 2706 unsigned long page_none, page_shared, page_copy, page_readonly; 2707 unsigned long page_exec_bit; 2708 int i; 2709 2710 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2711 page_cache4v_flag | _PAGE_P_4V | 2712 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2713 _PAGE_EXEC_4V); 2714 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2715 2716 _PAGE_IE = _PAGE_IE_4V; 2717 _PAGE_E = _PAGE_E_4V; 2718 _PAGE_CACHE = page_cache4v_flag; 2719 2720 #ifdef CONFIG_DEBUG_PAGEALLOC 2721 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2722 #else 2723 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2724 PAGE_OFFSET; 2725 #endif 2726 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2727 _PAGE_W_4V); 2728 2729 for (i = 1; i < 4; i++) 2730 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2731 2732 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2733 __ACCESS_BITS_4V | _PAGE_E_4V); 2734 2735 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2736 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2737 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2738 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2739 2740 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2741 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2742 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2743 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2744 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2745 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2746 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2747 2748 page_exec_bit = _PAGE_EXEC_4V; 2749 2750 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2751 page_exec_bit); 2752 } 2753 2754 unsigned long pte_sz_bits(unsigned long sz) 2755 { 2756 if (tlb_type == hypervisor) { 2757 switch (sz) { 2758 case 8 * 1024: 2759 default: 2760 return _PAGE_SZ8K_4V; 2761 case 64 * 1024: 2762 return _PAGE_SZ64K_4V; 2763 case 512 * 1024: 2764 return _PAGE_SZ512K_4V; 2765 case 4 * 1024 * 1024: 2766 return _PAGE_SZ4MB_4V; 2767 } 2768 } else { 2769 switch (sz) { 2770 case 8 * 1024: 2771 default: 2772 return _PAGE_SZ8K_4U; 2773 case 64 * 1024: 2774 return _PAGE_SZ64K_4U; 2775 case 512 * 1024: 2776 return _PAGE_SZ512K_4U; 2777 case 4 * 1024 * 1024: 2778 return _PAGE_SZ4MB_4U; 2779 } 2780 } 2781 } 2782 2783 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2784 { 2785 pte_t pte; 2786 2787 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2788 pte_val(pte) |= (((unsigned long)space) << 32); 2789 pte_val(pte) |= pte_sz_bits(page_size); 2790 2791 return pte; 2792 } 2793 2794 static unsigned long kern_large_tte(unsigned long paddr) 2795 { 2796 unsigned long val; 2797 2798 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2799 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2800 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2801 if (tlb_type == hypervisor) 2802 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2803 page_cache4v_flag | _PAGE_P_4V | 2804 _PAGE_EXEC_4V | _PAGE_W_4V); 2805 2806 return val | paddr; 2807 } 2808 2809 /* If not locked, zap it. */ 2810 void __flush_tlb_all(void) 2811 { 2812 unsigned long pstate; 2813 int i; 2814 2815 __asm__ __volatile__("flushw\n\t" 2816 "rdpr %%pstate, %0\n\t" 2817 "wrpr %0, %1, %%pstate" 2818 : "=r" (pstate) 2819 : "i" (PSTATE_IE)); 2820 if (tlb_type == hypervisor) { 2821 sun4v_mmu_demap_all(); 2822 } else if (tlb_type == spitfire) { 2823 for (i = 0; i < 64; i++) { 2824 /* Spitfire Errata #32 workaround */ 2825 /* NOTE: Always runs on spitfire, so no 2826 * cheetah+ page size encodings. 2827 */ 2828 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2829 "flush %%g6" 2830 : /* No outputs */ 2831 : "r" (0), 2832 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2833 2834 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2835 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2836 "membar #Sync" 2837 : /* no outputs */ 2838 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2839 spitfire_put_dtlb_data(i, 0x0UL); 2840 } 2841 2842 /* Spitfire Errata #32 workaround */ 2843 /* NOTE: Always runs on spitfire, so no 2844 * cheetah+ page size encodings. 2845 */ 2846 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2847 "flush %%g6" 2848 : /* No outputs */ 2849 : "r" (0), 2850 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2851 2852 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2853 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2854 "membar #Sync" 2855 : /* no outputs */ 2856 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2857 spitfire_put_itlb_data(i, 0x0UL); 2858 } 2859 } 2860 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2861 cheetah_flush_dtlb_all(); 2862 cheetah_flush_itlb_all(); 2863 } 2864 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2865 : : "r" (pstate)); 2866 } 2867 2868 static pte_t *__pte_alloc_one(struct mm_struct *mm) 2869 { 2870 struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0); 2871 2872 if (!ptdesc) 2873 return NULL; 2874 if (!pagetable_pte_ctor(mm, ptdesc)) { 2875 pagetable_free(ptdesc); 2876 return NULL; 2877 } 2878 return ptdesc_address(ptdesc); 2879 } 2880 2881 pte_t *pte_alloc_one_kernel(struct mm_struct *mm) 2882 { 2883 return __pte_alloc_one(mm); 2884 } 2885 2886 pgtable_t pte_alloc_one(struct mm_struct *mm) 2887 { 2888 return __pte_alloc_one(mm); 2889 } 2890 2891 static void __pte_free(pgtable_t pte) 2892 { 2893 struct ptdesc *ptdesc = virt_to_ptdesc(pte); 2894 2895 pagetable_dtor(ptdesc); 2896 pagetable_free(ptdesc); 2897 } 2898 2899 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2900 { 2901 __pte_free(pte); 2902 } 2903 2904 void pte_free(struct mm_struct *mm, pgtable_t pte) 2905 { 2906 __pte_free(pte); 2907 } 2908 2909 void pgtable_free(void *table, bool is_page) 2910 { 2911 if (is_page) 2912 __pte_free(table); 2913 else 2914 kmem_cache_free(pgtable_cache, table); 2915 } 2916 2917 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2918 static void pte_free_now(struct rcu_head *head) 2919 { 2920 struct page *page; 2921 2922 page = container_of(head, struct page, rcu_head); 2923 __pte_free((pgtable_t)page_address(page)); 2924 } 2925 2926 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable) 2927 { 2928 struct page *page; 2929 2930 page = virt_to_page(pgtable); 2931 call_rcu(&page->rcu_head, pte_free_now); 2932 } 2933 2934 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2935 pmd_t *pmd) 2936 { 2937 unsigned long pte, flags; 2938 struct mm_struct *mm; 2939 pmd_t entry = *pmd; 2940 2941 if (!pmd_leaf(entry) || !pmd_young(entry)) 2942 return; 2943 2944 pte = pmd_val(entry); 2945 2946 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2947 if (!(pte & _PAGE_VALID)) 2948 return; 2949 2950 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2951 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2952 2953 mm = vma->vm_mm; 2954 2955 spin_lock_irqsave(&mm->context.lock, flags); 2956 2957 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 2958 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 2959 addr, pte); 2960 2961 spin_unlock_irqrestore(&mm->context.lock, flags); 2962 } 2963 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 2964 2965 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 2966 static void context_reload(void *__data) 2967 { 2968 struct mm_struct *mm = __data; 2969 2970 if (mm == current->mm) 2971 load_secondary_context(mm); 2972 } 2973 2974 void hugetlb_setup(struct pt_regs *regs) 2975 { 2976 struct mm_struct *mm = current->mm; 2977 struct tsb_config *tp; 2978 2979 if (faulthandler_disabled() || !mm) { 2980 const struct exception_table_entry *entry; 2981 2982 entry = search_exception_tables(regs->tpc); 2983 if (entry) { 2984 regs->tpc = entry->fixup; 2985 regs->tnpc = regs->tpc + 4; 2986 return; 2987 } 2988 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 2989 die_if_kernel("HugeTSB in atomic", regs); 2990 } 2991 2992 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 2993 if (likely(tp->tsb == NULL)) 2994 tsb_grow(mm, MM_TSB_HUGE, 0); 2995 2996 tsb_context_switch(mm); 2997 smp_tsb_sync(mm); 2998 2999 /* On UltraSPARC-III+ and later, configure the second half of 3000 * the Data-TLB for huge pages. 3001 */ 3002 if (tlb_type == cheetah_plus) { 3003 bool need_context_reload = false; 3004 unsigned long ctx; 3005 3006 spin_lock_irq(&ctx_alloc_lock); 3007 ctx = mm->context.sparc64_ctx_val; 3008 ctx &= ~CTX_PGSZ_MASK; 3009 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 3010 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 3011 3012 if (ctx != mm->context.sparc64_ctx_val) { 3013 /* When changing the page size fields, we 3014 * must perform a context flush so that no 3015 * stale entries match. This flush must 3016 * occur with the original context register 3017 * settings. 3018 */ 3019 do_flush_tlb_mm(mm); 3020 3021 /* Reload the context register of all processors 3022 * also executing in this address space. 3023 */ 3024 mm->context.sparc64_ctx_val = ctx; 3025 need_context_reload = true; 3026 } 3027 spin_unlock_irq(&ctx_alloc_lock); 3028 3029 if (need_context_reload) 3030 on_each_cpu(context_reload, mm, 0); 3031 } 3032 } 3033 #endif 3034 3035 static struct resource code_resource = { 3036 .name = "Kernel code", 3037 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3038 }; 3039 3040 static struct resource data_resource = { 3041 .name = "Kernel data", 3042 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3043 }; 3044 3045 static struct resource bss_resource = { 3046 .name = "Kernel bss", 3047 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3048 }; 3049 3050 static inline resource_size_t compute_kern_paddr(void *addr) 3051 { 3052 return (resource_size_t) (addr - KERNBASE + kern_base); 3053 } 3054 3055 static void __init kernel_lds_init(void) 3056 { 3057 code_resource.start = compute_kern_paddr(_text); 3058 code_resource.end = compute_kern_paddr(_etext - 1); 3059 data_resource.start = compute_kern_paddr(_etext); 3060 data_resource.end = compute_kern_paddr(_edata - 1); 3061 bss_resource.start = compute_kern_paddr(__bss_start); 3062 bss_resource.end = compute_kern_paddr(_end - 1); 3063 } 3064 3065 static int __init report_memory(void) 3066 { 3067 int i; 3068 struct resource *res; 3069 3070 kernel_lds_init(); 3071 3072 for (i = 0; i < pavail_ents; i++) { 3073 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 3074 3075 if (!res) { 3076 pr_warn("Failed to allocate source.\n"); 3077 break; 3078 } 3079 3080 res->name = "System RAM"; 3081 res->start = pavail[i].phys_addr; 3082 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3083 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3084 3085 if (insert_resource(&iomem_resource, res) < 0) { 3086 pr_warn("Resource insertion failed.\n"); 3087 break; 3088 } 3089 3090 insert_resource(res, &code_resource); 3091 insert_resource(res, &data_resource); 3092 insert_resource(res, &bss_resource); 3093 } 3094 3095 return 0; 3096 } 3097 arch_initcall(report_memory); 3098 3099 #ifdef CONFIG_SMP 3100 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3101 #else 3102 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3103 #endif 3104 3105 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3106 { 3107 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3108 if (start < LOW_OBP_ADDRESS) { 3109 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3110 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3111 } 3112 if (end > HI_OBP_ADDRESS) { 3113 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3114 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3115 } 3116 } else { 3117 flush_tsb_kernel_range(start, end); 3118 do_flush_tlb_kernel_range(start, end); 3119 } 3120 } 3121 3122 void copy_user_highpage(struct page *to, struct page *from, 3123 unsigned long vaddr, struct vm_area_struct *vma) 3124 { 3125 char *vfrom, *vto; 3126 3127 vfrom = kmap_atomic(from); 3128 vto = kmap_atomic(to); 3129 copy_user_page(vto, vfrom, vaddr, to); 3130 kunmap_atomic(vto); 3131 kunmap_atomic(vfrom); 3132 3133 /* If this page has ADI enabled, copy over any ADI tags 3134 * as well 3135 */ 3136 if (vma->vm_flags & VM_SPARC_ADI) { 3137 unsigned long pfrom, pto, i, adi_tag; 3138 3139 pfrom = page_to_phys(from); 3140 pto = page_to_phys(to); 3141 3142 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3143 asm volatile("ldxa [%1] %2, %0\n\t" 3144 : "=r" (adi_tag) 3145 : "r" (i), "i" (ASI_MCD_REAL)); 3146 asm volatile("stxa %0, [%1] %2\n\t" 3147 : 3148 : "r" (adi_tag), "r" (pto), 3149 "i" (ASI_MCD_REAL)); 3150 pto += adi_blksize(); 3151 } 3152 asm volatile("membar #Sync\n\t"); 3153 } 3154 } 3155 EXPORT_SYMBOL(copy_user_highpage); 3156 3157 void copy_highpage(struct page *to, struct page *from) 3158 { 3159 char *vfrom, *vto; 3160 3161 vfrom = kmap_atomic(from); 3162 vto = kmap_atomic(to); 3163 copy_page(vto, vfrom); 3164 kunmap_atomic(vto); 3165 kunmap_atomic(vfrom); 3166 3167 /* If this platform is ADI enabled, copy any ADI tags 3168 * as well 3169 */ 3170 if (adi_capable()) { 3171 unsigned long pfrom, pto, i, adi_tag; 3172 3173 pfrom = page_to_phys(from); 3174 pto = page_to_phys(to); 3175 3176 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3177 asm volatile("ldxa [%1] %2, %0\n\t" 3178 : "=r" (adi_tag) 3179 : "r" (i), "i" (ASI_MCD_REAL)); 3180 asm volatile("stxa %0, [%1] %2\n\t" 3181 : 3182 : "r" (adi_tag), "r" (pto), 3183 "i" (ASI_MCD_REAL)); 3184 pto += adi_blksize(); 3185 } 3186 asm volatile("membar #Sync\n\t"); 3187 } 3188 } 3189 EXPORT_SYMBOL(copy_highpage); 3190 3191 pgprot_t vm_get_page_prot(vm_flags_t vm_flags) 3192 { 3193 unsigned long prot = pgprot_val(protection_map[vm_flags & 3194 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]); 3195 3196 if (vm_flags & VM_SPARC_ADI) 3197 prot |= _PAGE_MCD_4V; 3198 3199 return __pgprot(prot); 3200 } 3201 EXPORT_SYMBOL(vm_get_page_prot); 3202