1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <dt-bindings/sound/qcom,q6afe.h> 6 #include <linux/slab.h> 7 #include <linux/kernel.h> 8 #include <linux/uaccess.h> 9 #include <linux/wait.h> 10 #include <linux/jiffies.h> 11 #include <linux/sched.h> 12 #include <linux/module.h> 13 #include <linux/kref.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/spinlock.h> 17 #include <linux/delay.h> 18 #include <linux/soc/qcom/apr.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dai.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include "q6dsp-errno.h" 24 #include "q6core.h" 25 #include "q6afe.h" 26 27 /* AFE CMDs */ 28 #define AFE_PORT_CMD_DEVICE_START 0x000100E5 29 #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 30 #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF 31 #define AFE_SVC_CMD_SET_PARAM 0x000100f3 32 #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 33 #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 34 #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C 35 #define AFE_MODULE_TDM 0x0001028A 36 37 #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 38 #define AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS 0x000102A5 39 #define AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT 0x000102AA 40 41 #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 42 #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 43 44 #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 45 #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D 46 #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D 47 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 48 #define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8 49 #define AFE_PARAM_ID_USB_AUDIO_CONFIG 0x000102A4 50 #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 51 #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5 52 #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6 53 54 /* I2S config specific */ 55 #define AFE_API_VERSION_I2S_CONFIG 0x1 56 #define AFE_PORT_I2S_SD0 0x1 57 #define AFE_PORT_I2S_SD1 0x2 58 #define AFE_PORT_I2S_SD2 0x3 59 #define AFE_PORT_I2S_SD3 0x4 60 #define AFE_PORT_I2S_SD0_MASK BIT(0x0) 61 #define AFE_PORT_I2S_SD1_MASK BIT(0x1) 62 #define AFE_PORT_I2S_SD2_MASK BIT(0x2) 63 #define AFE_PORT_I2S_SD3_MASK BIT(0x3) 64 #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) 65 #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) 66 #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) 67 #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 68 #define AFE_PORT_I2S_QUAD01 0x5 69 #define AFE_PORT_I2S_QUAD23 0x6 70 #define AFE_PORT_I2S_6CHS 0x7 71 #define AFE_PORT_I2S_8CHS 0x8 72 #define AFE_PORT_I2S_MONO 0x0 73 #define AFE_PORT_I2S_STEREO 0x1 74 #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 75 #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 76 #define AFE_LINEAR_PCM_DATA 0x0 77 78 #define AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 0x1 79 80 /* Port IDs */ 81 #define AFE_API_VERSION_HDMI_CONFIG 0x1 82 #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E 83 #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 84 85 /* USB AFE port */ 86 #define AFE_PORT_ID_USB_RX 0x7000 87 88 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 89 /* Clock set API version */ 90 #define AFE_API_VERSION_CLOCK_SET 1 91 #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 92 #define AFE_MODULE_CLOCK_SET 0x0001028F 93 #define AFE_PARAM_ID_CLOCK_SET 0x00010290 94 95 /* SLIMbus Rx port on channel 0. */ 96 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 97 /* SLIMbus Tx port on channel 0. */ 98 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 99 /* SLIMbus Rx port on channel 1. */ 100 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 101 /* SLIMbus Tx port on channel 1. */ 102 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 103 /* SLIMbus Rx port on channel 2. */ 104 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 105 /* SLIMbus Tx port on channel 2. */ 106 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 107 /* SLIMbus Rx port on channel 3. */ 108 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 109 /* SLIMbus Tx port on channel 3. */ 110 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 111 /* SLIMbus Rx port on channel 4. */ 112 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 113 /* SLIMbus Tx port on channel 4. */ 114 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 115 /* SLIMbus Rx port on channel 5. */ 116 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a 117 /* SLIMbus Tx port on channel 5. */ 118 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b 119 /* SLIMbus Rx port on channel 6. */ 120 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c 121 /* SLIMbus Tx port on channel 6. */ 122 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d 123 #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 124 #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 125 #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 126 #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 127 #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 128 #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 129 #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 130 #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 131 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 132 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 133 #define AFE_PORT_ID_SENARY_MI2S_RX 0x1018 134 #define AFE_PORT_ID_SENARY_MI2S_TX 0x1019 135 136 /* Start of the range of port IDs for TDM devices. */ 137 #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 138 139 /* End of the range of port IDs for TDM devices. */ 140 #define AFE_PORT_ID_TDM_PORT_RANGE_END \ 141 (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) 142 143 /* Size of the range of port IDs for TDM ports. */ 144 #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ 145 (AFE_PORT_ID_TDM_PORT_RANGE_END - \ 146 AFE_PORT_ID_TDM_PORT_RANGE_START+1) 147 148 #define AFE_PORT_ID_PRIMARY_TDM_RX \ 149 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) 150 #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ 151 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) 152 #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ 153 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) 154 #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ 155 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) 156 #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ 157 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) 158 #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ 159 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) 160 #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ 161 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) 162 #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ 163 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) 164 165 #define AFE_PORT_ID_PRIMARY_TDM_TX \ 166 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) 167 #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ 168 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) 169 #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ 170 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) 171 #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ 172 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) 173 #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ 174 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) 175 #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ 176 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) 177 #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ 178 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) 179 #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ 180 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) 181 182 #define AFE_PORT_ID_SECONDARY_TDM_RX \ 183 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) 184 #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ 185 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) 186 #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ 187 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) 188 #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ 189 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) 190 #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ 191 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) 192 #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ 193 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) 194 #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ 195 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) 196 #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ 197 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) 198 199 #define AFE_PORT_ID_SECONDARY_TDM_TX \ 200 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) 201 #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ 202 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) 203 #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ 204 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) 205 #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ 206 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) 207 #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ 208 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) 209 #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ 210 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) 211 #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ 212 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) 213 #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ 214 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) 215 216 #define AFE_PORT_ID_TERTIARY_TDM_RX \ 217 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) 218 #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ 219 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) 220 #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ 221 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) 222 #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ 223 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) 224 #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ 225 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) 226 #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ 227 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) 228 #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ 229 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) 230 #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ 231 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) 232 233 #define AFE_PORT_ID_TERTIARY_TDM_TX \ 234 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) 235 #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ 236 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) 237 #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ 238 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) 239 #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ 240 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) 241 #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ 242 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) 243 #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ 244 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) 245 #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ 246 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) 247 #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ 248 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) 249 250 #define AFE_PORT_ID_QUATERNARY_TDM_RX \ 251 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) 252 #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ 253 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) 254 #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ 255 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) 256 #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ 257 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) 258 #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ 259 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) 260 #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ 261 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) 262 #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ 263 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) 264 #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ 265 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) 266 267 #define AFE_PORT_ID_QUATERNARY_TDM_TX \ 268 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) 269 #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ 270 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) 271 #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ 272 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) 273 #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ 274 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) 275 #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ 276 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) 277 #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ 278 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) 279 #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ 280 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) 281 #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ 282 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) 283 284 #define AFE_PORT_ID_QUINARY_TDM_RX \ 285 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) 286 #define AFE_PORT_ID_QUINARY_TDM_RX_1 \ 287 (AFE_PORT_ID_QUINARY_TDM_RX + 0x02) 288 #define AFE_PORT_ID_QUINARY_TDM_RX_2 \ 289 (AFE_PORT_ID_QUINARY_TDM_RX + 0x04) 290 #define AFE_PORT_ID_QUINARY_TDM_RX_3 \ 291 (AFE_PORT_ID_QUINARY_TDM_RX + 0x06) 292 #define AFE_PORT_ID_QUINARY_TDM_RX_4 \ 293 (AFE_PORT_ID_QUINARY_TDM_RX + 0x08) 294 #define AFE_PORT_ID_QUINARY_TDM_RX_5 \ 295 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) 296 #define AFE_PORT_ID_QUINARY_TDM_RX_6 \ 297 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) 298 #define AFE_PORT_ID_QUINARY_TDM_RX_7 \ 299 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) 300 301 #define AFE_PORT_ID_QUINARY_TDM_TX \ 302 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) 303 #define AFE_PORT_ID_QUINARY_TDM_TX_1 \ 304 (AFE_PORT_ID_QUINARY_TDM_TX + 0x02) 305 #define AFE_PORT_ID_QUINARY_TDM_TX_2 \ 306 (AFE_PORT_ID_QUINARY_TDM_TX + 0x04) 307 #define AFE_PORT_ID_QUINARY_TDM_TX_3 \ 308 (AFE_PORT_ID_QUINARY_TDM_TX + 0x06) 309 #define AFE_PORT_ID_QUINARY_TDM_TX_4 \ 310 (AFE_PORT_ID_QUINARY_TDM_TX + 0x08) 311 #define AFE_PORT_ID_QUINARY_TDM_TX_5 \ 312 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) 313 #define AFE_PORT_ID_QUINARY_TDM_TX_6 \ 314 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) 315 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \ 316 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) 317 318 /* AFE WSA Codec DMA Rx port 0 */ 319 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000 320 /* AFE WSA Codec DMA Tx port 0 */ 321 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001 322 /* AFE WSA Codec DMA Rx port 1 */ 323 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002 324 /* AFE WSA Codec DMA Tx port 1 */ 325 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003 326 /* AFE WSA Codec DMA Tx port 2 */ 327 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005 328 /* AFE VA Codec DMA Tx port 0 */ 329 #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021 330 /* AFE VA Codec DMA Tx port 1 */ 331 #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023 332 /* AFE VA Codec DMA Tx port 2 */ 333 #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025 334 /* AFE Rx Codec DMA Rx port 0 */ 335 #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030 336 /* AFE Tx Codec DMA Tx port 0 */ 337 #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031 338 /* AFE Rx Codec DMA Rx port 1 */ 339 #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032 340 /* AFE Tx Codec DMA Tx port 1 */ 341 #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033 342 /* AFE Rx Codec DMA Rx port 2 */ 343 #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034 344 /* AFE Tx Codec DMA Tx port 2 */ 345 #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035 346 /* AFE Rx Codec DMA Rx port 3 */ 347 #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036 348 /* AFE Tx Codec DMA Tx port 3 */ 349 #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037 350 /* AFE Rx Codec DMA Rx port 4 */ 351 #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038 352 /* AFE Tx Codec DMA Tx port 4 */ 353 #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039 354 /* AFE Rx Codec DMA Rx port 5 */ 355 #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A 356 /* AFE Tx Codec DMA Tx port 5 */ 357 #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B 358 /* AFE Rx Codec DMA Rx port 6 */ 359 #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C 360 /* AFE Rx Codec DMA Rx port 7 */ 361 #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E 362 363 #define Q6AFE_LPASS_MODE_CLK1_VALID 1 364 #define Q6AFE_LPASS_MODE_CLK2_VALID 2 365 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 366 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 367 #define AFE_API_VERSION_TDM_CONFIG 1 368 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 369 #define AFE_API_VERSION_CODEC_DMA_CONFIG 1 370 371 #define TIMEOUT_MS 3000 372 #define AFE_CMD_RESP_AVAIL 0 373 #define AFE_CMD_RESP_NONE 1 374 #define AFE_CLK_TOKEN 1024 375 376 struct q6afe { 377 struct apr_device *apr; 378 struct device *dev; 379 struct q6core_svc_api_info ainfo; 380 struct mutex lock; 381 struct aprv2_ibasic_rsp_result_t result; 382 wait_queue_head_t wait; 383 struct list_head port_list; 384 spinlock_t port_list_lock; 385 }; 386 387 struct afe_port_cmd_device_start { 388 u16 port_id; 389 u16 reserved; 390 } __packed; 391 392 struct afe_port_cmd_device_stop { 393 u16 port_id; 394 u16 reserved; 395 /* Reserved for 32-bit alignment. This field must be set to 0.*/ 396 } __packed; 397 398 struct afe_port_param_data_v2 { 399 u32 module_id; 400 u32 param_id; 401 u16 param_size; 402 u16 reserved; 403 } __packed; 404 405 struct afe_svc_cmd_set_param { 406 uint32_t payload_size; 407 uint32_t payload_address_lsw; 408 uint32_t payload_address_msw; 409 uint32_t mem_map_handle; 410 } __packed; 411 412 struct afe_port_cmd_set_param_v2 { 413 u16 port_id; 414 u16 payload_size; 415 u32 payload_address_lsw; 416 u32 payload_address_msw; 417 u32 mem_map_handle; 418 } __packed; 419 420 struct afe_param_id_hdmi_multi_chan_audio_cfg { 421 u32 hdmi_cfg_minor_version; 422 u16 datatype; 423 u16 channel_allocation; 424 u32 sample_rate; 425 u16 bit_width; 426 u16 reserved; 427 } __packed; 428 429 struct afe_param_id_slimbus_cfg { 430 u32 sb_cfg_minor_version; 431 /* Minor version used for tracking the version of the SLIMBUS 432 * configuration interface. 433 * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG 434 */ 435 436 u16 slimbus_dev_id; 437 /* SLIMbus hardware device ID, which is required to handle 438 * multiple SLIMbus hardware blocks. 439 * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 440 */ 441 u16 bit_width; 442 /* Bit width of the sample. 443 * Supported values: 16, 24 444 */ 445 u16 data_format; 446 /* Data format supported by the SLIMbus hardware. The default is 447 * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the 448 * hardware does not perform any format conversions before the data 449 * transfer. 450 */ 451 u16 num_channels; 452 /* Number of channels. 453 * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT 454 */ 455 u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 456 /* Mapping of shared channel IDs (128 to 255) to which the 457 * master port is to be connected. 458 * Shared_channel_mapping[i] represents the shared channel assigned 459 * for audio channel i in multichannel audio data. 460 */ 461 u32 sample_rate; 462 /* Sampling rate of the port. 463 * Supported values: 464 * - #AFE_PORT_SAMPLE_RATE_8K 465 * - #AFE_PORT_SAMPLE_RATE_16K 466 * - #AFE_PORT_SAMPLE_RATE_48K 467 * - #AFE_PORT_SAMPLE_RATE_96K 468 * - #AFE_PORT_SAMPLE_RATE_192K 469 */ 470 } __packed; 471 472 struct afe_clk_cfg { 473 u32 i2s_cfg_minor_version; 474 u32 clk_val1; 475 u32 clk_val2; 476 u16 clk_src; 477 u16 clk_root; 478 u16 clk_set_mode; 479 u16 reserved; 480 } __packed; 481 482 struct afe_digital_clk_cfg { 483 u32 i2s_cfg_minor_version; 484 u32 clk_val; 485 u16 clk_root; 486 u16 reserved; 487 } __packed; 488 489 struct afe_param_id_i2s_cfg { 490 u32 i2s_cfg_minor_version; 491 u16 bit_width; 492 u16 channel_mode; 493 u16 mono_stereo; 494 u16 ws_src; 495 u32 sample_rate; 496 u16 data_format; 497 u16 reserved; 498 } __packed; 499 500 struct afe_param_id_tdm_cfg { 501 u32 tdm_cfg_minor_version; 502 u32 num_channels; 503 u32 sample_rate; 504 u32 bit_width; 505 u16 data_format; 506 u16 sync_mode; 507 u16 sync_src; 508 u16 nslots_per_frame; 509 u16 ctrl_data_out_enable; 510 u16 ctrl_invert_sync_pulse; 511 u16 ctrl_sync_data_delay; 512 u16 slot_width; 513 u32 slot_mask; 514 } __packed; 515 516 struct afe_param_id_cdc_dma_cfg { 517 u32 cdc_dma_cfg_minor_version; 518 u32 sample_rate; 519 u16 bit_width; 520 u16 data_format; 521 u16 num_channels; 522 u16 active_channels_mask; 523 } __packed; 524 525 struct afe_param_id_usb_cfg { 526 /* Minor version used for tracking USB audio device configuration. 527 * Supported values: AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 528 */ 529 u32 cfg_minor_version; 530 /* Sampling rate of the port. 531 * Supported values: 532 * - AFE_PORT_SAMPLE_RATE_8K 533 * - AFE_PORT_SAMPLE_RATE_11025 534 * - AFE_PORT_SAMPLE_RATE_12K 535 * - AFE_PORT_SAMPLE_RATE_16K 536 * - AFE_PORT_SAMPLE_RATE_22050 537 * - AFE_PORT_SAMPLE_RATE_24K 538 * - AFE_PORT_SAMPLE_RATE_32K 539 * - AFE_PORT_SAMPLE_RATE_44P1K 540 * - AFE_PORT_SAMPLE_RATE_48K 541 * - AFE_PORT_SAMPLE_RATE_96K 542 * - AFE_PORT_SAMPLE_RATE_192K 543 */ 544 u32 sample_rate; 545 /* Bit width of the sample. 546 * Supported values: 16, 24 547 */ 548 u16 bit_width; 549 /* Number of channels. 550 * Supported values: 1 and 2 551 */ 552 u16 num_channels; 553 /* Data format supported by the USB. The supported value is 554 * 0 (#AFE_USB_AUDIO_DATA_FORMAT_LINEAR_PCM). 555 */ 556 u16 data_format; 557 /* this field must be 0 */ 558 u16 reserved; 559 /* device token of actual end USB audio device */ 560 u32 dev_token; 561 /* endianness of this interface */ 562 u32 endian; 563 /* service interval */ 564 u32 service_interval; 565 } __packed; 566 567 /** 568 * struct afe_param_id_usb_audio_dev_params 569 * @cfg_minor_version: Minor version used for tracking USB audio device 570 * configuration. 571 * Supported values: 572 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 573 * @dev_token: device token of actual end USB audio device 574 **/ 575 struct afe_param_id_usb_audio_dev_params { 576 u32 cfg_minor_version; 577 u32 dev_token; 578 } __packed; 579 580 /** 581 * struct afe_param_id_usb_audio_dev_lpcm_fmt 582 * @cfg_minor_version: Minor version used for tracking USB audio device 583 * configuration. 584 * Supported values: 585 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 586 * @endian: endianness of this interface 587 **/ 588 struct afe_param_id_usb_audio_dev_lpcm_fmt { 589 u32 cfg_minor_version; 590 u32 endian; 591 } __packed; 592 593 #define AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL 0x000102B7 594 595 /** 596 * struct afe_param_id_usb_audio_svc_interval 597 * @cfg_minor_version: Minor version used for tracking USB audio device 598 * configuration. 599 * Supported values: 600 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 601 * @svc_interval: service interval 602 **/ 603 struct afe_param_id_usb_audio_svc_interval { 604 u32 cfg_minor_version; 605 u32 svc_interval; 606 } __packed; 607 608 union afe_port_config { 609 struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; 610 struct afe_param_id_slimbus_cfg slim_cfg; 611 struct afe_param_id_i2s_cfg i2s_cfg; 612 struct afe_param_id_tdm_cfg tdm_cfg; 613 struct afe_param_id_cdc_dma_cfg dma_cfg; 614 struct afe_param_id_usb_cfg usb_cfg; 615 } __packed; 616 617 618 struct afe_clk_set { 619 uint32_t clk_set_minor_version; 620 uint32_t clk_id; 621 uint32_t clk_freq_in_hz; 622 uint16_t clk_attri; 623 uint16_t clk_root; 624 uint32_t enable; 625 }; 626 627 struct afe_param_id_slot_mapping_cfg { 628 u32 minor_version; 629 u16 num_channels; 630 u16 bitwidth; 631 u32 data_align_type; 632 u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 633 } __packed; 634 635 struct q6afe_port { 636 wait_queue_head_t wait; 637 union afe_port_config port_cfg; 638 struct afe_param_id_slot_mapping_cfg *scfg; 639 struct aprv2_ibasic_rsp_result_t result; 640 int token; 641 int id; 642 int cfg_type; 643 struct q6afe *afe; 644 struct kref refcount; 645 struct list_head node; 646 }; 647 648 struct afe_cmd_remote_lpass_core_hw_vote_request { 649 uint32_t hw_block_id; 650 char client_name[8]; 651 } __packed; 652 653 struct afe_cmd_remote_lpass_core_hw_devote_request { 654 uint32_t hw_block_id; 655 uint32_t client_handle; 656 } __packed; 657 658 659 660 struct afe_port_map { 661 int port_id; 662 int token; 663 int is_rx; 664 int is_dig_pcm; 665 }; 666 667 /* 668 * Mapping between Virtual Port IDs to DSP AFE Port ID 669 * On B Family SoCs DSP Port IDs are consistent across multiple SoCs 670 * on A Family SoCs DSP port IDs are same as virtual Port IDs. 671 */ 672 673 static struct afe_port_map port_maps[AFE_PORT_MAX] = { 674 [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, 675 [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, 676 SLIMBUS_0_RX, 1, 1}, 677 [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, 678 SLIMBUS_1_RX, 1, 1}, 679 [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, 680 SLIMBUS_2_RX, 1, 1}, 681 [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, 682 SLIMBUS_3_RX, 1, 1}, 683 [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, 684 SLIMBUS_4_RX, 1, 1}, 685 [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, 686 SLIMBUS_5_RX, 1, 1}, 687 [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, 688 SLIMBUS_6_RX, 1, 1}, 689 [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, 690 SLIMBUS_0_TX, 0, 1}, 691 [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, 692 SLIMBUS_1_TX, 0, 1}, 693 [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, 694 SLIMBUS_2_TX, 0, 1}, 695 [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, 696 SLIMBUS_3_TX, 0, 1}, 697 [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, 698 SLIMBUS_4_TX, 0, 1}, 699 [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, 700 SLIMBUS_5_TX, 0, 1}, 701 [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, 702 SLIMBUS_6_TX, 0, 1}, 703 [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, 704 PRIMARY_MI2S_RX, 1, 1}, 705 [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, 706 PRIMARY_MI2S_RX, 0, 1}, 707 [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, 708 SECONDARY_MI2S_RX, 1, 1}, 709 [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, 710 SECONDARY_MI2S_TX, 0, 1}, 711 [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, 712 TERTIARY_MI2S_RX, 1, 1}, 713 [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, 714 TERTIARY_MI2S_TX, 0, 1}, 715 [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, 716 QUATERNARY_MI2S_RX, 1, 1}, 717 [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, 718 QUATERNARY_MI2S_TX, 0, 1}, 719 [QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX, 720 QUINARY_MI2S_RX, 1, 1}, 721 [QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, 722 QUINARY_MI2S_TX, 0, 1}, 723 [SENARY_MI2S_RX] = { AFE_PORT_ID_SENARY_MI2S_RX, 724 SENARY_MI2S_RX, 1, 1}, 725 [SENARY_MI2S_TX] = { AFE_PORT_ID_SENARY_MI2S_TX, 726 SENARY_MI2S_TX, 0, 1}, 727 [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, 728 PRIMARY_TDM_RX_0, 1, 1}, 729 [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, 730 PRIMARY_TDM_TX_0, 0, 1}, 731 [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, 732 PRIMARY_TDM_RX_1, 1, 1}, 733 [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, 734 PRIMARY_TDM_TX_1, 0, 1}, 735 [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, 736 PRIMARY_TDM_RX_2, 1, 1}, 737 [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, 738 PRIMARY_TDM_TX_2, 0, 1}, 739 [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, 740 PRIMARY_TDM_RX_3, 1, 1}, 741 [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, 742 PRIMARY_TDM_TX_3, 0, 1}, 743 [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, 744 PRIMARY_TDM_RX_4, 1, 1}, 745 [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, 746 PRIMARY_TDM_TX_4, 0, 1}, 747 [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, 748 PRIMARY_TDM_RX_5, 1, 1}, 749 [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, 750 PRIMARY_TDM_TX_5, 0, 1}, 751 [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, 752 PRIMARY_TDM_RX_6, 1, 1}, 753 [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, 754 PRIMARY_TDM_TX_6, 0, 1}, 755 [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, 756 PRIMARY_TDM_RX_7, 1, 1}, 757 [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, 758 PRIMARY_TDM_TX_7, 0, 1}, 759 [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, 760 SECONDARY_TDM_RX_0, 1, 1}, 761 [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, 762 SECONDARY_TDM_TX_0, 0, 1}, 763 [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, 764 SECONDARY_TDM_RX_1, 1, 1}, 765 [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, 766 SECONDARY_TDM_TX_1, 0, 1}, 767 [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, 768 SECONDARY_TDM_RX_2, 1, 1}, 769 [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, 770 SECONDARY_TDM_TX_2, 0, 1}, 771 [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, 772 SECONDARY_TDM_RX_3, 1, 1}, 773 [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, 774 SECONDARY_TDM_TX_3, 0, 1}, 775 [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, 776 SECONDARY_TDM_RX_4, 1, 1}, 777 [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, 778 SECONDARY_TDM_TX_4, 0, 1}, 779 [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, 780 SECONDARY_TDM_RX_5, 1, 1}, 781 [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, 782 SECONDARY_TDM_TX_5, 0, 1}, 783 [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, 784 SECONDARY_TDM_RX_6, 1, 1}, 785 [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, 786 SECONDARY_TDM_TX_6, 0, 1}, 787 [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, 788 SECONDARY_TDM_RX_7, 1, 1}, 789 [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, 790 SECONDARY_TDM_TX_7, 0, 1}, 791 [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, 792 TERTIARY_TDM_RX_0, 1, 1}, 793 [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, 794 TERTIARY_TDM_TX_0, 0, 1}, 795 [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, 796 TERTIARY_TDM_RX_1, 1, 1}, 797 [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, 798 TERTIARY_TDM_TX_1, 0, 1}, 799 [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, 800 TERTIARY_TDM_RX_2, 1, 1}, 801 [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, 802 TERTIARY_TDM_TX_2, 0, 1}, 803 [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, 804 TERTIARY_TDM_RX_3, 1, 1}, 805 [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, 806 TERTIARY_TDM_TX_3, 0, 1}, 807 [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, 808 TERTIARY_TDM_RX_4, 1, 1}, 809 [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, 810 TERTIARY_TDM_TX_4, 0, 1}, 811 [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, 812 TERTIARY_TDM_RX_5, 1, 1}, 813 [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, 814 TERTIARY_TDM_TX_5, 0, 1}, 815 [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, 816 TERTIARY_TDM_RX_6, 1, 1}, 817 [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, 818 TERTIARY_TDM_TX_6, 0, 1}, 819 [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, 820 TERTIARY_TDM_RX_7, 1, 1}, 821 [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, 822 TERTIARY_TDM_TX_7, 0, 1}, 823 [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, 824 QUATERNARY_TDM_RX_0, 1, 1}, 825 [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, 826 QUATERNARY_TDM_TX_0, 0, 1}, 827 [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, 828 QUATERNARY_TDM_RX_1, 1, 1}, 829 [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, 830 QUATERNARY_TDM_TX_1, 0, 1}, 831 [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, 832 QUATERNARY_TDM_RX_2, 1, 1}, 833 [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, 834 QUATERNARY_TDM_TX_2, 0, 1}, 835 [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, 836 QUATERNARY_TDM_RX_3, 1, 1}, 837 [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, 838 QUATERNARY_TDM_TX_3, 0, 1}, 839 [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, 840 QUATERNARY_TDM_RX_4, 1, 1}, 841 [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, 842 QUATERNARY_TDM_TX_4, 0, 1}, 843 [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, 844 QUATERNARY_TDM_RX_5, 1, 1}, 845 [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, 846 QUATERNARY_TDM_TX_5, 0, 1}, 847 [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, 848 QUATERNARY_TDM_RX_6, 1, 1}, 849 [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, 850 QUATERNARY_TDM_TX_6, 0, 1}, 851 [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, 852 QUATERNARY_TDM_RX_7, 1, 1}, 853 [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, 854 QUATERNARY_TDM_TX_7, 0, 1}, 855 [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, 856 QUINARY_TDM_RX_0, 1, 1}, 857 [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, 858 QUINARY_TDM_TX_0, 0, 1}, 859 [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, 860 QUINARY_TDM_RX_1, 1, 1}, 861 [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, 862 QUINARY_TDM_TX_1, 0, 1}, 863 [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, 864 QUINARY_TDM_RX_2, 1, 1}, 865 [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, 866 QUINARY_TDM_TX_2, 0, 1}, 867 [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, 868 QUINARY_TDM_RX_3, 1, 1}, 869 [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, 870 QUINARY_TDM_TX_3, 0, 1}, 871 [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, 872 QUINARY_TDM_RX_4, 1, 1}, 873 [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, 874 QUINARY_TDM_TX_4, 0, 1}, 875 [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, 876 QUINARY_TDM_RX_5, 1, 1}, 877 [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, 878 QUINARY_TDM_TX_5, 0, 1}, 879 [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, 880 QUINARY_TDM_RX_6, 1, 1}, 881 [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, 882 QUINARY_TDM_TX_6, 0, 1}, 883 [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, 884 QUINARY_TDM_RX_7, 1, 1}, 885 [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, 886 QUINARY_TDM_TX_7, 0, 1}, 887 [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, 888 DISPLAY_PORT_RX, 1, 1}, 889 [WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0, 890 WSA_CODEC_DMA_RX_0, 1, 1}, 891 [WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0, 892 WSA_CODEC_DMA_TX_0, 0, 1}, 893 [WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1, 894 WSA_CODEC_DMA_RX_1, 1, 1}, 895 [WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1, 896 WSA_CODEC_DMA_TX_1, 0, 1}, 897 [WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2, 898 WSA_CODEC_DMA_TX_2, 0, 1}, 899 [VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0, 900 VA_CODEC_DMA_TX_0, 0, 1}, 901 [VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1, 902 VA_CODEC_DMA_TX_1, 0, 1}, 903 [VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2, 904 VA_CODEC_DMA_TX_2, 0, 1}, 905 [RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0, 906 RX_CODEC_DMA_RX_0, 1, 1}, 907 [TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0, 908 TX_CODEC_DMA_TX_0, 0, 1}, 909 [RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1, 910 RX_CODEC_DMA_RX_1, 1, 1}, 911 [TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1, 912 TX_CODEC_DMA_TX_1, 0, 1}, 913 [RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2, 914 RX_CODEC_DMA_RX_2, 1, 1}, 915 [TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2, 916 TX_CODEC_DMA_TX_2, 0, 1}, 917 [RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3, 918 RX_CODEC_DMA_RX_3, 1, 1}, 919 [TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3, 920 TX_CODEC_DMA_TX_3, 0, 1}, 921 [RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4, 922 RX_CODEC_DMA_RX_4, 1, 1}, 923 [TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4, 924 TX_CODEC_DMA_TX_4, 0, 1}, 925 [RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5, 926 RX_CODEC_DMA_RX_5, 1, 1}, 927 [TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5, 928 TX_CODEC_DMA_TX_5, 0, 1}, 929 [RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6, 930 RX_CODEC_DMA_RX_6, 1, 1}, 931 [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, 932 RX_CODEC_DMA_RX_7, 1, 1}, 933 [USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1}, 934 }; 935 936 static void q6afe_port_free(struct kref *ref) 937 { 938 struct q6afe_port *port; 939 struct q6afe *afe; 940 941 port = container_of(ref, struct q6afe_port, refcount); 942 afe = port->afe; 943 scoped_guard(spinlock_irqsave, &afe->port_list_lock) 944 list_del(&port->node); 945 kfree(port->scfg); 946 kfree(port); 947 } 948 949 static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) 950 { 951 struct q6afe_port *p; 952 struct q6afe_port *ret = NULL; 953 954 guard(spinlock_irqsave)(&afe->port_list_lock); 955 list_for_each_entry(p, &afe->port_list, node) 956 if (p->token == token) { 957 ret = p; 958 kref_get(&p->refcount); 959 break; 960 } 961 962 return ret; 963 } 964 965 static int q6afe_callback(struct apr_device *adev, const struct apr_resp_pkt *data) 966 { 967 struct q6afe *afe = dev_get_drvdata(&adev->dev); 968 const struct aprv2_ibasic_rsp_result_t *res; 969 const struct apr_hdr *hdr = &data->hdr; 970 struct q6afe_port *port; 971 972 if (!data->payload_size) 973 return 0; 974 975 res = data->payload; 976 switch (hdr->opcode) { 977 case APR_BASIC_RSP_RESULT: { 978 if (res->status) { 979 dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", 980 res->opcode, res->status); 981 } 982 switch (res->opcode) { 983 case AFE_PORT_CMD_SET_PARAM_V2: 984 case AFE_PORT_CMD_DEVICE_STOP: 985 case AFE_PORT_CMD_DEVICE_START: 986 case AFE_SVC_CMD_SET_PARAM: 987 port = q6afe_find_port(afe, hdr->token); 988 if (port) { 989 port->result = *res; 990 wake_up(&port->wait); 991 kref_put(&port->refcount, q6afe_port_free); 992 } else if (hdr->token == AFE_CLK_TOKEN) { 993 afe->result = *res; 994 wake_up(&afe->wait); 995 } 996 break; 997 default: 998 dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); 999 break; 1000 } 1001 } 1002 break; 1003 case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST: 1004 afe->result.opcode = hdr->opcode; 1005 afe->result.status = res->status; 1006 wake_up(&afe->wait); 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * q6afe_get_port_id() - Get port id from a given port index 1017 * 1018 * @index: port index 1019 * 1020 * Return: Will be an negative on error or valid port_id on success 1021 */ 1022 int q6afe_get_port_id(int index) 1023 { 1024 if (index < 0 || index >= AFE_PORT_MAX) 1025 return -EINVAL; 1026 1027 return port_maps[index].port_id; 1028 } 1029 EXPORT_SYMBOL_GPL(q6afe_get_port_id); 1030 1031 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, 1032 struct q6afe_port *port, uint32_t rsp_opcode) 1033 { 1034 wait_queue_head_t *wait; 1035 struct aprv2_ibasic_rsp_result_t *result; 1036 int ret; 1037 1038 mutex_lock(&afe->lock); 1039 if (port) { 1040 wait = &port->wait; 1041 result = &port->result; 1042 } else { 1043 result = &afe->result; 1044 wait = &afe->wait; 1045 } 1046 1047 result->opcode = 0; 1048 result->status = 0; 1049 1050 ret = apr_send_pkt(afe->apr, pkt); 1051 if (ret < 0) { 1052 dev_err(afe->dev, "packet not transmitted (%d)\n", ret); 1053 ret = -EINVAL; 1054 goto err; 1055 } 1056 1057 ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode), 1058 msecs_to_jiffies(TIMEOUT_MS)); 1059 if (!ret) { 1060 ret = -ETIMEDOUT; 1061 } else if (result->status > 0) { 1062 dev_err(afe->dev, "DSP returned error[%x]\n", 1063 result->status); 1064 ret = -EINVAL; 1065 } else { 1066 ret = 0; 1067 } 1068 1069 err: 1070 mutex_unlock(&afe->lock); 1071 1072 return ret; 1073 } 1074 1075 static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, 1076 void *data, int param_id, int module_id, int psize, 1077 int token) 1078 { 1079 struct afe_svc_cmd_set_param *param; 1080 struct afe_port_param_data_v2 *pdata; 1081 struct apr_pkt *pkt; 1082 int ret, pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1083 void *pl; 1084 1085 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1086 if (!p) 1087 return -ENOMEM; 1088 1089 pkt = p; 1090 param = p + APR_HDR_SIZE; 1091 pdata = p + APR_HDR_SIZE + sizeof(*param); 1092 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1093 memcpy(pl, data, psize); 1094 1095 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1096 APR_HDR_LEN(APR_HDR_SIZE), 1097 APR_PKT_VER); 1098 pkt->hdr.pkt_size = pkt_size; 1099 pkt->hdr.src_port = 0; 1100 pkt->hdr.dest_port = 0; 1101 pkt->hdr.token = token; 1102 pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; 1103 1104 param->payload_size = sizeof(*pdata) + psize; 1105 param->payload_address_lsw = 0x00; 1106 param->payload_address_msw = 0x00; 1107 param->mem_map_handle = 0x00; 1108 pdata->module_id = module_id; 1109 pdata->param_id = param_id; 1110 pdata->param_size = psize; 1111 1112 ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); 1113 if (ret) 1114 dev_err(afe->dev, "AFE set params failed %d\n", ret); 1115 1116 return ret; 1117 } 1118 1119 static int q6afe_port_set_param(struct q6afe_port *port, void *data, 1120 int param_id, int module_id, int psize) 1121 { 1122 return q6afe_set_param(port->afe, port, data, param_id, module_id, 1123 psize, port->token); 1124 } 1125 1126 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, 1127 int param_id, int module_id, int psize) 1128 { 1129 struct afe_port_cmd_set_param_v2 *param; 1130 struct afe_port_param_data_v2 *pdata; 1131 struct q6afe *afe = port->afe; 1132 struct apr_pkt *pkt; 1133 u16 port_id = port->id; 1134 int ret, pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1135 void *pl; 1136 1137 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1138 if (!p) 1139 return -ENOMEM; 1140 1141 pkt = p; 1142 param = p + APR_HDR_SIZE; 1143 pdata = p + APR_HDR_SIZE + sizeof(*param); 1144 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1145 memcpy(pl, data, psize); 1146 1147 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1148 APR_HDR_LEN(APR_HDR_SIZE), 1149 APR_PKT_VER); 1150 pkt->hdr.pkt_size = pkt_size; 1151 pkt->hdr.src_port = 0; 1152 pkt->hdr.dest_port = 0; 1153 pkt->hdr.token = port->token; 1154 pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; 1155 1156 param->port_id = port_id; 1157 param->payload_size = sizeof(*pdata) + psize; 1158 param->payload_address_lsw = 0x00; 1159 param->payload_address_msw = 0x00; 1160 param->mem_map_handle = 0x00; 1161 pdata->module_id = module_id; 1162 pdata->param_id = param_id; 1163 pdata->param_size = psize; 1164 1165 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2); 1166 if (ret) 1167 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1168 port_id, ret); 1169 1170 return ret; 1171 } 1172 1173 static int q6afe_port_set_lpass_clock(struct q6afe_port *port, 1174 struct afe_clk_cfg *cfg) 1175 { 1176 return q6afe_port_set_param_v2(port, cfg, 1177 AFE_PARAM_ID_LPAIF_CLK_CONFIG, 1178 AFE_MODULE_AUDIO_DEV_INTERFACE, 1179 sizeof(*cfg)); 1180 } 1181 1182 static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, 1183 struct afe_clk_set *cfg) 1184 { 1185 return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, 1186 AFE_MODULE_CLOCK_SET, sizeof(*cfg)); 1187 } 1188 1189 static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, 1190 struct afe_digital_clk_cfg *cfg) 1191 { 1192 return q6afe_port_set_param_v2(port, cfg, 1193 AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, 1194 AFE_MODULE_AUDIO_DEV_INTERFACE, 1195 sizeof(*cfg)); 1196 } 1197 1198 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 1199 int clk_root, unsigned int freq) 1200 { 1201 struct q6afe *afe = dev_get_drvdata(dev->parent); 1202 struct afe_clk_set cset = {0,}; 1203 1204 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1205 cset.clk_id = clk_id; 1206 cset.clk_freq_in_hz = freq; 1207 cset.clk_attri = attri; 1208 cset.clk_root = clk_root; 1209 cset.enable = !!freq; 1210 1211 return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET, 1212 AFE_MODULE_CLOCK_SET, sizeof(cset), 1213 AFE_CLK_TOKEN); 1214 } 1215 EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock); 1216 1217 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 1218 int clk_src, int clk_root, 1219 unsigned int freq, int dir) 1220 { 1221 struct afe_clk_cfg ccfg = {0,}; 1222 struct afe_clk_set cset = {0,}; 1223 struct afe_digital_clk_cfg dcfg = {0,}; 1224 int ret; 1225 1226 switch (clk_id) { 1227 case LPAIF_DIG_CLK: 1228 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1229 dcfg.clk_val = freq; 1230 dcfg.clk_root = clk_root; 1231 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); 1232 break; 1233 case LPAIF_BIT_CLK: 1234 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1235 ccfg.clk_val1 = freq; 1236 ccfg.clk_src = clk_src; 1237 ccfg.clk_root = clk_root; 1238 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; 1239 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1240 break; 1241 1242 case LPAIF_OSR_CLK: 1243 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1244 ccfg.clk_val2 = freq; 1245 ccfg.clk_src = clk_src; 1246 ccfg.clk_root = clk_root; 1247 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; 1248 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1249 break; 1250 case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: 1251 case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: 1252 case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: 1253 case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: 1254 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1255 cset.clk_id = clk_id; 1256 cset.clk_freq_in_hz = freq; 1257 cset.clk_attri = clk_src; 1258 cset.clk_root = clk_root; 1259 cset.enable = !!freq; 1260 ret = q6afe_set_lpass_clock_v2(port, &cset); 1261 break; 1262 default: 1263 ret = -EINVAL; 1264 break; 1265 } 1266 1267 return ret; 1268 } 1269 EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); 1270 1271 /** 1272 * q6afe_port_stop() - Stop a afe port 1273 * 1274 * @port: Instance of port to stop 1275 * 1276 * Return: Will be an negative on packet size on success. 1277 */ 1278 int q6afe_port_stop(struct q6afe_port *port) 1279 { 1280 struct afe_port_cmd_device_stop *stop; 1281 struct q6afe *afe = port->afe; 1282 struct apr_pkt *pkt; 1283 int port_id = port->id; 1284 int ret = 0; 1285 int index, pkt_size; 1286 1287 index = port->token; 1288 if (index < 0 || index >= AFE_PORT_MAX) { 1289 dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); 1290 return -EINVAL; 1291 } 1292 1293 pkt_size = APR_HDR_SIZE + sizeof(*stop); 1294 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1295 if (!p) 1296 return -ENOMEM; 1297 1298 pkt = p; 1299 stop = p + APR_HDR_SIZE; 1300 1301 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1302 APR_HDR_LEN(APR_HDR_SIZE), 1303 APR_PKT_VER); 1304 pkt->hdr.pkt_size = pkt_size; 1305 pkt->hdr.src_port = 0; 1306 pkt->hdr.dest_port = 0; 1307 pkt->hdr.token = index; 1308 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; 1309 stop->port_id = port_id; 1310 stop->reserved = 0; 1311 1312 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP); 1313 if (ret) 1314 dev_err(afe->dev, "AFE close failed %d\n", ret); 1315 1316 return ret; 1317 } 1318 EXPORT_SYMBOL_GPL(q6afe_port_stop); 1319 1320 /** 1321 * q6afe_slim_port_prepare() - Prepare slim afe port. 1322 * 1323 * @port: Instance of afe port 1324 * @cfg: SLIM configuration for the afe port 1325 * 1326 */ 1327 void q6afe_slim_port_prepare(struct q6afe_port *port, 1328 struct q6afe_slim_cfg *cfg) 1329 { 1330 union afe_port_config *pcfg = &port->port_cfg; 1331 1332 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; 1333 pcfg->slim_cfg.sample_rate = cfg->sample_rate; 1334 pcfg->slim_cfg.bit_width = cfg->bit_width; 1335 pcfg->slim_cfg.num_channels = cfg->num_channels; 1336 pcfg->slim_cfg.data_format = cfg->data_format; 1337 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; 1338 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; 1339 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; 1340 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; 1341 1342 } 1343 EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); 1344 1345 /** 1346 * q6afe_tdm_port_prepare() - Prepare tdm afe port. 1347 * 1348 * @port: Instance of afe port 1349 * @cfg: TDM configuration for the afe port 1350 * 1351 */ 1352 void q6afe_tdm_port_prepare(struct q6afe_port *port, 1353 struct q6afe_tdm_cfg *cfg) 1354 { 1355 union afe_port_config *pcfg = &port->port_cfg; 1356 1357 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; 1358 pcfg->tdm_cfg.num_channels = cfg->num_channels; 1359 pcfg->tdm_cfg.sample_rate = cfg->sample_rate; 1360 pcfg->tdm_cfg.bit_width = cfg->bit_width; 1361 pcfg->tdm_cfg.data_format = cfg->data_format; 1362 pcfg->tdm_cfg.sync_mode = cfg->sync_mode; 1363 pcfg->tdm_cfg.sync_src = cfg->sync_src; 1364 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; 1365 1366 pcfg->tdm_cfg.slot_width = cfg->slot_width; 1367 pcfg->tdm_cfg.slot_mask = cfg->slot_mask; 1368 port->scfg = kzalloc_obj(*port->scfg); 1369 if (!port->scfg) 1370 return; 1371 1372 port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; 1373 port->scfg->num_channels = cfg->num_channels; 1374 port->scfg->bitwidth = cfg->bit_width; 1375 port->scfg->data_align_type = cfg->data_align_type; 1376 memcpy(port->scfg->ch_mapping, cfg->ch_mapping, 1377 sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); 1378 } 1379 EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); 1380 1381 /** 1382 * afe_port_send_usb_dev_param() - Send USB dev token 1383 * 1384 * @port: Instance of afe port 1385 * @cardidx: USB SND card index to reference 1386 * @pcmidx: USB SND PCM device index to reference 1387 * 1388 * The USB dev token carries information about which USB SND card instance and 1389 * PCM device to execute the offload on. This information is carried through 1390 * to the stream enable QMI request, which is handled by the offload class 1391 * driver. The information is parsed to determine which USB device to query 1392 * the required resources for. 1393 */ 1394 int afe_port_send_usb_dev_param(struct q6afe_port *port, int cardidx, int pcmidx) 1395 { 1396 struct afe_param_id_usb_audio_dev_params usb_dev; 1397 int ret; 1398 1399 memset(&usb_dev, 0, sizeof(usb_dev)); 1400 1401 usb_dev.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1402 usb_dev.dev_token = (cardidx << 16) | (pcmidx << 8); 1403 ret = q6afe_port_set_param_v2(port, &usb_dev, 1404 AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS, 1405 AFE_MODULE_AUDIO_DEV_INTERFACE, 1406 sizeof(usb_dev)); 1407 if (ret) 1408 dev_err(port->afe->dev, "%s: AFE device param cmd failed %d\n", 1409 __func__, ret); 1410 1411 return ret; 1412 } 1413 EXPORT_SYMBOL_GPL(afe_port_send_usb_dev_param); 1414 1415 static int afe_port_send_usb_params(struct q6afe_port *port, struct q6afe_usb_cfg *cfg) 1416 { 1417 union afe_port_config *pcfg = &port->port_cfg; 1418 struct afe_param_id_usb_audio_dev_lpcm_fmt lpcm_fmt; 1419 struct afe_param_id_usb_audio_svc_interval svc_int; 1420 int ret; 1421 1422 if (!pcfg) { 1423 dev_err(port->afe->dev, "%s: Error, no configuration data\n", __func__); 1424 return -EINVAL; 1425 } 1426 1427 memset(&lpcm_fmt, 0, sizeof(lpcm_fmt)); 1428 memset(&svc_int, 0, sizeof(svc_int)); 1429 1430 lpcm_fmt.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1431 lpcm_fmt.endian = pcfg->usb_cfg.endian; 1432 ret = q6afe_port_set_param_v2(port, &lpcm_fmt, 1433 AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT, 1434 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(lpcm_fmt)); 1435 if (ret) { 1436 dev_err(port->afe->dev, "%s: AFE device param cmd LPCM_FMT failed %d\n", 1437 __func__, ret); 1438 return ret; 1439 } 1440 1441 svc_int.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1442 svc_int.svc_interval = pcfg->usb_cfg.service_interval; 1443 ret = q6afe_port_set_param_v2(port, &svc_int, 1444 AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL, 1445 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(svc_int)); 1446 if (ret) 1447 dev_err(port->afe->dev, "%s: AFE device param cmd svc_interval failed %d\n", 1448 __func__, ret); 1449 1450 return ret; 1451 } 1452 1453 /** 1454 * q6afe_usb_port_prepare() - Prepare usb afe port. 1455 * 1456 * @port: Instance of afe port 1457 * @cfg: USB configuration for the afe port 1458 * 1459 */ 1460 void q6afe_usb_port_prepare(struct q6afe_port *port, 1461 struct q6afe_usb_cfg *cfg) 1462 { 1463 union afe_port_config *pcfg = &port->port_cfg; 1464 1465 pcfg->usb_cfg.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1466 pcfg->usb_cfg.sample_rate = cfg->sample_rate; 1467 pcfg->usb_cfg.num_channels = cfg->num_channels; 1468 pcfg->usb_cfg.bit_width = cfg->bit_width; 1469 1470 afe_port_send_usb_params(port, cfg); 1471 } 1472 EXPORT_SYMBOL_GPL(q6afe_usb_port_prepare); 1473 1474 /** 1475 * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. 1476 * 1477 * @port: Instance of afe port 1478 * @cfg: HDMI configuration for the afe port 1479 * 1480 */ 1481 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 1482 struct q6afe_hdmi_cfg *cfg) 1483 { 1484 union afe_port_config *pcfg = &port->port_cfg; 1485 1486 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = 1487 AFE_API_VERSION_HDMI_CONFIG; 1488 pcfg->hdmi_multi_ch.datatype = cfg->datatype; 1489 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; 1490 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; 1491 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; 1492 } 1493 EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); 1494 1495 /** 1496 * q6afe_i2s_port_prepare() - Prepare i2s afe port. 1497 * 1498 * @port: Instance of afe port 1499 * @cfg: I2S configuration for the afe port 1500 * Return: Will be an negative on error and zero on success. 1501 */ 1502 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) 1503 { 1504 union afe_port_config *pcfg = &port->port_cfg; 1505 struct device *dev = port->afe->dev; 1506 int num_sd_lines; 1507 1508 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1509 pcfg->i2s_cfg.sample_rate = cfg->sample_rate; 1510 pcfg->i2s_cfg.bit_width = cfg->bit_width; 1511 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; 1512 1513 switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1514 case SND_SOC_DAIFMT_BP_FP: 1515 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; 1516 break; 1517 case SND_SOC_DAIFMT_BC_FC: 1518 /* CPU is slave */ 1519 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; 1520 break; 1521 default: 1522 break; 1523 } 1524 1525 num_sd_lines = hweight_long(cfg->sd_line_mask); 1526 1527 switch (num_sd_lines) { 1528 case 0: 1529 dev_err(dev, "no line is assigned\n"); 1530 return -EINVAL; 1531 case 1: 1532 switch (cfg->sd_line_mask) { 1533 case AFE_PORT_I2S_SD0_MASK: 1534 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1535 break; 1536 case AFE_PORT_I2S_SD1_MASK: 1537 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; 1538 break; 1539 case AFE_PORT_I2S_SD2_MASK: 1540 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1541 break; 1542 case AFE_PORT_I2S_SD3_MASK: 1543 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; 1544 break; 1545 default: 1546 dev_err(dev, "Invalid SD lines\n"); 1547 return -EINVAL; 1548 } 1549 break; 1550 case 2: 1551 switch (cfg->sd_line_mask) { 1552 case AFE_PORT_I2S_SD0_1_MASK: 1553 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; 1554 break; 1555 case AFE_PORT_I2S_SD2_3_MASK: 1556 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; 1557 break; 1558 default: 1559 dev_err(dev, "Invalid SD lines\n"); 1560 return -EINVAL; 1561 } 1562 break; 1563 case 3: 1564 switch (cfg->sd_line_mask) { 1565 case AFE_PORT_I2S_SD0_1_2_MASK: 1566 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; 1567 break; 1568 default: 1569 dev_err(dev, "Invalid SD lines\n"); 1570 return -EINVAL; 1571 } 1572 break; 1573 case 4: 1574 switch (cfg->sd_line_mask) { 1575 case AFE_PORT_I2S_SD0_1_2_3_MASK: 1576 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; 1577 1578 break; 1579 default: 1580 dev_err(dev, "Invalid SD lines\n"); 1581 return -EINVAL; 1582 } 1583 break; 1584 default: 1585 dev_err(dev, "Invalid SD lines\n"); 1586 return -EINVAL; 1587 } 1588 1589 switch (cfg->num_channels) { 1590 case 1: 1591 case 2: 1592 switch (pcfg->i2s_cfg.channel_mode) { 1593 case AFE_PORT_I2S_QUAD01: 1594 case AFE_PORT_I2S_6CHS: 1595 case AFE_PORT_I2S_8CHS: 1596 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1597 break; 1598 case AFE_PORT_I2S_QUAD23: 1599 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1600 break; 1601 } 1602 1603 if (cfg->num_channels == 2) 1604 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; 1605 else 1606 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; 1607 1608 break; 1609 case 3: 1610 case 4: 1611 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { 1612 dev_err(dev, "Invalid Channel mode\n"); 1613 return -EINVAL; 1614 } 1615 break; 1616 case 5: 1617 case 6: 1618 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { 1619 dev_err(dev, "Invalid Channel mode\n"); 1620 return -EINVAL; 1621 } 1622 break; 1623 case 7: 1624 case 8: 1625 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { 1626 dev_err(dev, "Invalid Channel mode\n"); 1627 return -EINVAL; 1628 } 1629 break; 1630 default: 1631 break; 1632 } 1633 1634 return 0; 1635 } 1636 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); 1637 1638 /** 1639 * q6afe_cdc_dma_port_prepare() - Prepare dma afe port. 1640 * 1641 * @port: Instance of afe port 1642 * @cfg: DMA configuration for the afe port 1643 * 1644 */ 1645 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 1646 struct q6afe_cdc_dma_cfg *cfg) 1647 { 1648 union afe_port_config *pcfg = &port->port_cfg; 1649 struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg; 1650 1651 dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG; 1652 dma_cfg->sample_rate = cfg->sample_rate; 1653 dma_cfg->bit_width = cfg->bit_width; 1654 dma_cfg->data_format = cfg->data_format; 1655 dma_cfg->num_channels = cfg->num_channels; 1656 if (!cfg->active_channels_mask) 1657 dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1; 1658 } 1659 EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare); 1660 /** 1661 * q6afe_port_start() - Start a afe port 1662 * 1663 * @port: Instance of port to start 1664 * 1665 * Return: Will be an negative on packet size on success. 1666 */ 1667 int q6afe_port_start(struct q6afe_port *port) 1668 { 1669 struct afe_port_cmd_device_start *start; 1670 struct q6afe *afe = port->afe; 1671 int port_id = port->id; 1672 int ret, param_id = port->cfg_type; 1673 struct apr_pkt *pkt; 1674 int pkt_size; 1675 1676 ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, 1677 AFE_MODULE_AUDIO_DEV_INTERFACE, 1678 sizeof(port->port_cfg)); 1679 if (ret) { 1680 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1681 port_id, ret); 1682 return ret; 1683 } 1684 1685 if (port->scfg) { 1686 ret = q6afe_port_set_param_v2(port, port->scfg, 1687 AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, 1688 AFE_MODULE_TDM, sizeof(*port->scfg)); 1689 if (ret) { 1690 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1691 port_id, ret); 1692 return ret; 1693 } 1694 } 1695 1696 pkt_size = APR_HDR_SIZE + sizeof(*start); 1697 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1698 if (!p) 1699 return -ENOMEM; 1700 1701 pkt = p; 1702 start = p + APR_HDR_SIZE; 1703 1704 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1705 APR_HDR_LEN(APR_HDR_SIZE), 1706 APR_PKT_VER); 1707 pkt->hdr.pkt_size = pkt_size; 1708 pkt->hdr.src_port = 0; 1709 pkt->hdr.dest_port = 0; 1710 pkt->hdr.token = port->token; 1711 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; 1712 1713 start->port_id = port_id; 1714 1715 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START); 1716 if (ret) 1717 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1718 port_id, ret); 1719 1720 return ret; 1721 } 1722 EXPORT_SYMBOL_GPL(q6afe_port_start); 1723 1724 /** 1725 * q6afe_port_get_from_id() - Get port instance from a port id 1726 * 1727 * @dev: Pointer to afe child device. 1728 * @id: port id 1729 * 1730 * Return: Will be an error pointer on error or a valid afe port 1731 * on success. 1732 */ 1733 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) 1734 { 1735 int port_id; 1736 struct q6afe *afe = dev_get_drvdata(dev->parent); 1737 struct q6afe_port *port; 1738 int cfg_type; 1739 1740 if (id < 0 || id >= AFE_PORT_MAX) { 1741 dev_err(dev, "AFE port token[%d] invalid!\n", id); 1742 return ERR_PTR(-EINVAL); 1743 } 1744 1745 /* if port is multiple times bind/unbind before callback finishes */ 1746 port = q6afe_find_port(afe, id); 1747 if (port) { 1748 dev_err(dev, "AFE Port already open\n"); 1749 return port; 1750 } 1751 1752 port_id = port_maps[id].port_id; 1753 1754 switch (port_id) { 1755 case AFE_PORT_ID_MULTICHAN_HDMI_RX: 1756 case AFE_PORT_ID_HDMI_OVER_DP_RX: 1757 cfg_type = AFE_PARAM_ID_HDMI_CONFIG; 1758 break; 1759 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: 1760 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: 1761 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: 1762 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: 1763 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: 1764 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: 1765 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: 1766 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: 1767 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: 1768 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: 1769 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: 1770 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: 1771 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: 1772 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: 1773 cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; 1774 break; 1775 1776 case AFE_PORT_ID_PRIMARY_MI2S_RX: 1777 case AFE_PORT_ID_PRIMARY_MI2S_TX: 1778 case AFE_PORT_ID_SECONDARY_MI2S_RX: 1779 case AFE_PORT_ID_SECONDARY_MI2S_TX: 1780 case AFE_PORT_ID_TERTIARY_MI2S_RX: 1781 case AFE_PORT_ID_TERTIARY_MI2S_TX: 1782 case AFE_PORT_ID_QUATERNARY_MI2S_RX: 1783 case AFE_PORT_ID_QUATERNARY_MI2S_TX: 1784 case AFE_PORT_ID_QUINARY_MI2S_RX: 1785 case AFE_PORT_ID_QUINARY_MI2S_TX: 1786 case AFE_PORT_ID_SENARY_MI2S_RX: 1787 case AFE_PORT_ID_SENARY_MI2S_TX: 1788 cfg_type = AFE_PARAM_ID_I2S_CONFIG; 1789 break; 1790 case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: 1791 cfg_type = AFE_PARAM_ID_TDM_CONFIG; 1792 break; 1793 case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7: 1794 cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG; 1795 break; 1796 case AFE_PORT_ID_USB_RX: 1797 cfg_type = AFE_PARAM_ID_USB_AUDIO_CONFIG; 1798 break; 1799 default: 1800 dev_err(dev, "Invalid port id 0x%x\n", port_id); 1801 return ERR_PTR(-EINVAL); 1802 } 1803 1804 port = kzalloc(sizeof(*port), GFP_KERNEL); 1805 if (!port) 1806 return ERR_PTR(-ENOMEM); 1807 1808 init_waitqueue_head(&port->wait); 1809 1810 port->token = id; 1811 port->id = port_id; 1812 port->afe = afe; 1813 port->cfg_type = cfg_type; 1814 kref_init(&port->refcount); 1815 1816 scoped_guard(spinlock_irqsave, &afe->port_list_lock) 1817 list_add_tail(&port->node, &afe->port_list); 1818 1819 return port; 1820 1821 } 1822 EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); 1823 1824 /** 1825 * q6afe_port_put() - Release port reference 1826 * 1827 * @port: Instance of port to put 1828 */ 1829 void q6afe_port_put(struct q6afe_port *port) 1830 { 1831 kref_put(&port->refcount, q6afe_port_free); 1832 } 1833 EXPORT_SYMBOL_GPL(q6afe_port_put); 1834 1835 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1836 uint32_t client_handle) 1837 { 1838 struct q6afe *afe = dev_get_drvdata(dev->parent); 1839 struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg; 1840 struct apr_pkt *pkt; 1841 int ret = 0; 1842 int pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1843 1844 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1845 if (!p) 1846 return -ENOMEM; 1847 1848 pkt = p; 1849 vote_cfg = p + APR_HDR_SIZE; 1850 1851 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1852 APR_HDR_LEN(APR_HDR_SIZE), 1853 APR_PKT_VER); 1854 pkt->hdr.pkt_size = pkt_size; 1855 pkt->hdr.src_port = 0; 1856 pkt->hdr.dest_port = 0; 1857 pkt->hdr.token = hw_block_id; 1858 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST; 1859 vote_cfg->hw_block_id = hw_block_id; 1860 vote_cfg->client_handle = client_handle; 1861 1862 ret = apr_send_pkt(afe->apr, pkt); 1863 if (ret < 0) 1864 dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id); 1865 1866 return ret; 1867 } 1868 EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw); 1869 1870 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1871 const char *client_name, uint32_t *client_handle) 1872 { 1873 struct q6afe *afe = dev_get_drvdata(dev->parent); 1874 struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg; 1875 struct apr_pkt *pkt; 1876 int ret = 0; 1877 int pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1878 1879 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1880 if (!p) 1881 return -ENOMEM; 1882 1883 pkt = p; 1884 vote_cfg = p + APR_HDR_SIZE; 1885 1886 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1887 APR_HDR_LEN(APR_HDR_SIZE), 1888 APR_PKT_VER); 1889 pkt->hdr.pkt_size = pkt_size; 1890 pkt->hdr.src_port = 0; 1891 pkt->hdr.dest_port = 0; 1892 pkt->hdr.token = hw_block_id; 1893 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST; 1894 vote_cfg->hw_block_id = hw_block_id; 1895 strscpy(vote_cfg->client_name, client_name, 1896 sizeof(vote_cfg->client_name)); 1897 1898 ret = afe_apr_send_pkt(afe, pkt, NULL, 1899 AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST); 1900 if (ret) 1901 dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id); 1902 1903 return ret; 1904 } 1905 EXPORT_SYMBOL(q6afe_vote_lpass_core_hw); 1906 1907 static int q6afe_probe(struct apr_device *adev) 1908 { 1909 struct q6afe *afe; 1910 struct device *dev = &adev->dev; 1911 1912 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 1913 if (!afe) 1914 return -ENOMEM; 1915 1916 q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); 1917 afe->apr = adev; 1918 mutex_init(&afe->lock); 1919 init_waitqueue_head(&afe->wait); 1920 afe->dev = dev; 1921 INIT_LIST_HEAD(&afe->port_list); 1922 spin_lock_init(&afe->port_list_lock); 1923 1924 dev_set_drvdata(dev, afe); 1925 1926 return devm_of_platform_populate(dev); 1927 } 1928 1929 #ifdef CONFIG_OF 1930 static const struct of_device_id q6afe_device_id[] = { 1931 { .compatible = "qcom,q6afe" }, 1932 {}, 1933 }; 1934 MODULE_DEVICE_TABLE(of, q6afe_device_id); 1935 #endif 1936 1937 static struct apr_driver qcom_q6afe_driver = { 1938 .probe = q6afe_probe, 1939 .callback = q6afe_callback, 1940 .driver = { 1941 .name = "qcom-q6afe", 1942 .of_match_table = of_match_ptr(q6afe_device_id), 1943 1944 }, 1945 }; 1946 1947 module_apr_driver(qcom_q6afe_driver); 1948 MODULE_DESCRIPTION("Q6 Audio Front End"); 1949 MODULE_LICENSE("GPL v2"); 1950