1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * BRIEF MODULE DESCRIPTION
4 * Au1100 LCD Driver.
5 *
6 * Rewritten for 2.6 by Embedded Alley Solutions
7 * <source@embeddedalley.com>, based on submissions by
8 * Karl Lessard <klessard@sunrisetelecom.com>
9 * <c.pellegrin@exadron.com>
10 *
11 * PM support added by Rodolfo Giometti <giometti@linux.it>
12 * Cursor enable/disable by Rodolfo Giometti <giometti@linux.it>
13 *
14 * Copyright 2002 MontaVista Software
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * Copyright 2002 Alchemy Semiconductor
19 * Author: Alchemy Semiconductor
20 *
21 * Based on:
22 * linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
23 * Created 28 Dec 1997 by Geert Uytterhoeven
24 */
25
26 #define pr_fmt(fmt) "au1100fb:" fmt "\n"
27
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/io.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mm.h>
36 #include <linux/fb.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/ctype.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
43
44 #if defined(__BIG_ENDIAN)
45 #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
46 #else
47 #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
48 #endif
49 #define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
50
51 /********************************************************************/
52
53 /* LCD controller restrictions */
54 #define AU1100_LCD_MAX_XRES 800
55 #define AU1100_LCD_MAX_YRES 600
56 #define AU1100_LCD_MAX_BPP 16
57 #define AU1100_LCD_MAX_CLK 48000000
58 #define AU1100_LCD_NBR_PALETTE_ENTRIES 256
59
60 /* Default number of visible screen buffer to allocate */
61 #define AU1100FB_NBR_VIDEO_BUFFERS 4
62
63 /********************************************************************/
64
65 struct au1100fb_panel
66 {
67 const char name[25]; /* Full name <vendor>_<model> */
68
69 u32 control_base; /* Mode-independent control values */
70 u32 clkcontrol_base; /* Panel pixclock preferences */
71
72 u32 horztiming;
73 u32 verttiming;
74
75 u32 xres; /* Maximum horizontal resolution */
76 u32 yres; /* Maximum vertical resolution */
77 u32 bpp; /* Maximum depth supported */
78 };
79
80 struct au1100fb_regs
81 {
82 u32 lcd_control;
83 u32 lcd_intstatus;
84 u32 lcd_intenable;
85 u32 lcd_horztiming;
86 u32 lcd_verttiming;
87 u32 lcd_clkcontrol;
88 u32 lcd_dmaaddr0;
89 u32 lcd_dmaaddr1;
90 u32 lcd_words;
91 u32 lcd_pwmdiv;
92 u32 lcd_pwmhi;
93 u32 reserved[(0x0400-0x002C)/4];
94 u32 lcd_palettebase[256];
95 };
96
97 struct au1100fb_device {
98
99 struct fb_info info; /* FB driver info record */
100
101 struct au1100fb_panel *panel; /* Panel connected to this device */
102
103 struct au1100fb_regs* regs; /* Registers memory map */
104 size_t regs_len;
105 unsigned int regs_phys;
106
107 #ifdef CONFIG_PM
108 /* stores the register values during suspend */
109 struct au1100fb_regs pm_regs;
110 #endif
111
112 unsigned char* fb_mem; /* FrameBuffer memory map */
113 size_t fb_len;
114 dma_addr_t fb_phys;
115 int panel_idx;
116 struct clk *lcdclk;
117 struct device *dev;
118 };
119
120 /********************************************************************/
121
122 #define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
123 #define LCD_CONTROL_SBB_BIT 21
124 #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
125 #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
126 #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
127 #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
128 #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
129 #define LCD_CONTROL_SBPPF_BIT 18
130 #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
131 #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
132 #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
133 #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
134 #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
135 #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
136 #define LCD_CONTROL_WP (1<<17)
137 #define LCD_CONTROL_WD (1<<16)
138 #define LCD_CONTROL_C (1<<15)
139 #define LCD_CONTROL_SM_BIT 13
140 #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
141 #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
142 #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
143 #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
144 #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
145 #define LCD_CONTROL_DB (1<<12)
146 #define LCD_CONTROL_CCO (1<<11)
147 #define LCD_CONTROL_DP (1<<10)
148 #define LCD_CONTROL_PO_BIT 8
149 #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
150 #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
151 #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
152 #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
153 #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
154 #define LCD_CONTROL_MPI (1<<7)
155 #define LCD_CONTROL_PT (1<<6)
156 #define LCD_CONTROL_PC (1<<5)
157 #define LCD_CONTROL_BPP_BIT 1
158 #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
159 #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
160 #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
161 #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
162 #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
163 #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
164 #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
165 #define LCD_CONTROL_GO (1<<0)
166
167 #define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
168 #define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
169 #define LCD_INT_SD (1<<7)
170 #define LCD_INT_OF (1<<6)
171 #define LCD_INT_UF (1<<5)
172 #define LCD_INT_SA (1<<3)
173 #define LCD_INT_SS (1<<2)
174 #define LCD_INT_S1 (1<<1)
175 #define LCD_INT_S0 (1<<0)
176
177 #define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
178 #define LCD_HORZTIMING_HN2_BIT 24
179 #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
180 #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
181 #define LCD_HORZTIMING_HN1_BIT 16
182 #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
183 #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
184 #define LCD_HORZTIMING_HPW_BIT 10
185 #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
186 #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
187 #define LCD_HORZTIMING_PPL_BIT 0
188 #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
189 #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
190
191 #define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
192 #define LCD_VERTTIMING_VN2_BIT 24
193 #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
194 #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
195 #define LCD_VERTTIMING_VN1_BIT 16
196 #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
197 #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
198 #define LCD_VERTTIMING_VPW_BIT 10
199 #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
200 #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
201 #define LCD_VERTTIMING_LPP_BIT 0
202 #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
203 #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
204
205 #define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
206 #define LCD_CLKCONTROL_IB (1<<18)
207 #define LCD_CLKCONTROL_IC (1<<17)
208 #define LCD_CLKCONTROL_IH (1<<16)
209 #define LCD_CLKCONTROL_IV (1<<15)
210 #define LCD_CLKCONTROL_BF_BIT 10
211 #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
212 #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
213 #define LCD_CLKCONTROL_PCD_BIT 0
214 #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
215 #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
216
217 #define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
218 #define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
219 #define LCD_DMA_SA_BIT 5
220 #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
221 #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
222
223 #define LCD_WORDS (AU1100_LCD_BASE + 0x20)
224 #define LCD_WRD_WRDS_BIT 0
225 #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
226 #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
227
228 #define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
229 #define LCD_PWMDIV_EN (1<<12)
230 #define LCD_PWMDIV_PWMDIV_BIT 0
231 #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
232 #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
233
234 #define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
235 #define LCD_PWMHI_PWMHI1_BIT 12
236 #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
237 #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
238 #define LCD_PWMHI_PWMHI0_BIT 0
239 #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
240 #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
241
242 #define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
243 #define LCD_PALLETTE_MONO_MI_BIT 0
244 #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
245 #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
246
247 #define LCD_PALLETTE_COLOR_RI_BIT 8
248 #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
249 #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
250 #define LCD_PALLETTE_COLOR_GI_BIT 4
251 #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
252 #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
253 #define LCD_PALLETTE_COLOR_BI_BIT 0
254 #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
255 #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
256
257 #define LCD_PALLETTE_TFT_DC_BIT 0
258 #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
259 #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
260
261 /********************************************************************/
262
263 /* List of panels known to work with the AU1100 LCD controller.
264 * To add a new panel, enter the same specifications as the
265 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
266 * with the controller restrictions. Restrictions are:
267 *
268 * STN color panels: max_bpp <= 12
269 * STN mono panels: max_bpp <= 4
270 * TFT panels: max_bpp <= 16
271 * max_xres <= 800
272 * max_yres <= 600
273 */
274 static struct au1100fb_panel known_lcd_panels[] =
275 {
276 /* 800x600x16bpp CRT */
277 [0] = {
278 .name = "CRT_800x600_16",
279 .xres = 800,
280 .yres = 600,
281 .bpp = 16,
282 .control_base = 0x0004886A |
283 LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
284 LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
285 .clkcontrol_base = 0x00020000,
286 .horztiming = 0x005aff1f,
287 .verttiming = 0x16000e57,
288 },
289 /* just the standard LCD */
290 [1] = {
291 .name = "WWPC LCD",
292 .xres = 240,
293 .yres = 320,
294 .bpp = 16,
295 .control_base = 0x0006806A,
296 .horztiming = 0x0A1010EF,
297 .verttiming = 0x0301013F,
298 .clkcontrol_base = 0x00018001,
299 },
300 /* Sharp 320x240 TFT panel */
301 [2] = {
302 .name = "Sharp_LQ038Q5DR01",
303 .xres = 320,
304 .yres = 240,
305 .bpp = 16,
306 .control_base =
307 ( LCD_CONTROL_SBPPF_565
308 | LCD_CONTROL_C
309 | LCD_CONTROL_SM_0
310 | LCD_CONTROL_DEFAULT_PO
311 | LCD_CONTROL_PT
312 | LCD_CONTROL_PC
313 | LCD_CONTROL_BPP_16 ),
314 .horztiming =
315 ( LCD_HORZTIMING_HN2_N(8)
316 | LCD_HORZTIMING_HN1_N(60)
317 | LCD_HORZTIMING_HPW_N(12)
318 | LCD_HORZTIMING_PPL_N(320) ),
319 .verttiming =
320 ( LCD_VERTTIMING_VN2_N(5)
321 | LCD_VERTTIMING_VN1_N(17)
322 | LCD_VERTTIMING_VPW_N(1)
323 | LCD_VERTTIMING_LPP_N(240) ),
324 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
325 },
326
327 /* Hitachi SP14Q005 and possibly others */
328 [3] = {
329 .name = "Hitachi_SP14Qxxx",
330 .xres = 320,
331 .yres = 240,
332 .bpp = 4,
333 .control_base =
334 ( LCD_CONTROL_C
335 | LCD_CONTROL_BPP_4 ),
336 .horztiming =
337 ( LCD_HORZTIMING_HN2_N(1)
338 | LCD_HORZTIMING_HN1_N(1)
339 | LCD_HORZTIMING_HPW_N(1)
340 | LCD_HORZTIMING_PPL_N(320) ),
341 .verttiming =
342 ( LCD_VERTTIMING_VN2_N(1)
343 | LCD_VERTTIMING_VN1_N(1)
344 | LCD_VERTTIMING_VPW_N(1)
345 | LCD_VERTTIMING_LPP_N(240) ),
346 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
347 },
348
349 /* Generic 640x480 TFT panel */
350 [4] = {
351 .name = "TFT_640x480_16",
352 .xres = 640,
353 .yres = 480,
354 .bpp = 16,
355 .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
356 .horztiming = 0x3434d67f,
357 .verttiming = 0x0e0e39df,
358 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
359 },
360
361 /* Pb1100 LCDB 640x480 PrimeView TFT panel */
362 [5] = {
363 .name = "PrimeView_640x480_16",
364 .xres = 640,
365 .yres = 480,
366 .bpp = 16,
367 .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
368 .horztiming = 0x0e4bfe7f,
369 .verttiming = 0x210805df,
370 .clkcontrol_base = 0x00038001,
371 },
372 };
373
374 /********************************************************************/
375
376 /* Inline helpers */
377
378 #define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
379 #define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
380 #define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
381 #define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
382
383 #if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_MIPS)
384 /* This is only defined to be able to compile this driver on non-mips platforms */
385 #define KSEG1ADDR(x) (x)
386 #endif
387
388 #define DRIVER_NAME "au1100fb"
389 #define DRIVER_DESC "LCD controller driver for AU1100 processors"
390
391 #define to_au1100fb_device(_info) \
392 (_info ? container_of(_info, struct au1100fb_device, info) : NULL);
393
394 /* Bitfields format supported by the controller. Note that the order of formats
395 * SHOULD be the same as in the LCD_CONTROL_SBPPF field, so we can retrieve the
396 * right pixel format by doing rgb_bitfields[LCD_CONTROL_SBPPF_XXX >> LCD_CONTROL_SBPPF]
397 */
398 struct fb_bitfield rgb_bitfields[][4] =
399 {
400 /* Red, Green, Blue, Transp */
401 { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
402 { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
403 { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
404 { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
405 { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
406
407 /* The last is used to describe 12bpp format */
408 { { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
409 };
410
411 /* fb_blank
412 * Blank the screen. Depending on the mode, the screen will be
413 * activated with the backlight color, or desactivated
414 */
au1100fb_fb_blank(int blank_mode,struct fb_info * fbi)415 static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
416 {
417 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
418
419 pr_devel("fb_blank %d %p", blank_mode, fbi);
420
421 switch (blank_mode) {
422
423 case VESA_NO_BLANKING:
424 /* Turn on panel */
425 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
426 wmb(); /* drain writebuffer */
427 break;
428
429 case VESA_VSYNC_SUSPEND:
430 case VESA_HSYNC_SUSPEND:
431 case VESA_POWERDOWN:
432 /* Turn off panel */
433 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
434 wmb(); /* drain writebuffer */
435 break;
436 default:
437 break;
438
439 }
440 return 0;
441 }
442
443 /*
444 * Set hardware with var settings. This will enable the controller with a specific
445 * mode, normally validated with the fb_check_var method
446 */
au1100fb_setmode(struct au1100fb_device * fbdev)447 static int au1100fb_setmode(struct au1100fb_device *fbdev)
448 {
449 struct fb_info *info;
450 u32 words;
451 int index;
452
453 if (!fbdev)
454 return -EINVAL;
455
456 info = &fbdev->info;
457
458 /* Update var-dependent FB info */
459 if (panel_is_active(fbdev->panel) || panel_is_color(fbdev->panel)) {
460 if (info->var.bits_per_pixel <= 8) {
461 /* palettized */
462 info->var.red.offset = 0;
463 info->var.red.length = info->var.bits_per_pixel;
464 info->var.red.msb_right = 0;
465
466 info->var.green.offset = 0;
467 info->var.green.length = info->var.bits_per_pixel;
468 info->var.green.msb_right = 0;
469
470 info->var.blue.offset = 0;
471 info->var.blue.length = info->var.bits_per_pixel;
472 info->var.blue.msb_right = 0;
473
474 info->var.transp.offset = 0;
475 info->var.transp.length = 0;
476 info->var.transp.msb_right = 0;
477
478 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
479 info->fix.line_length = info->var.xres_virtual /
480 (8/info->var.bits_per_pixel);
481 } else {
482 /* non-palettized */
483 index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT;
484 info->var.red = rgb_bitfields[index][0];
485 info->var.green = rgb_bitfields[index][1];
486 info->var.blue = rgb_bitfields[index][2];
487 info->var.transp = rgb_bitfields[index][3];
488
489 info->fix.visual = FB_VISUAL_TRUECOLOR;
490 info->fix.line_length = info->var.xres_virtual << 1; /* depth=16 */
491 }
492 } else {
493 /* mono */
494 info->fix.visual = FB_VISUAL_MONO10;
495 info->fix.line_length = info->var.xres_virtual / 8;
496 }
497
498 info->screen_size = info->fix.line_length * info->var.yres_virtual;
499 info->var.rotate = ((fbdev->panel->control_base&LCD_CONTROL_SM_MASK) \
500 >> LCD_CONTROL_SM_BIT) * 90;
501
502 /* Determine BPP mode and format */
503 fbdev->regs->lcd_control = fbdev->panel->control_base;
504 fbdev->regs->lcd_horztiming = fbdev->panel->horztiming;
505 fbdev->regs->lcd_verttiming = fbdev->panel->verttiming;
506 fbdev->regs->lcd_clkcontrol = fbdev->panel->clkcontrol_base;
507 fbdev->regs->lcd_intenable = 0;
508 fbdev->regs->lcd_intstatus = 0;
509 fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(fbdev->fb_phys);
510
511 if (panel_is_dual(fbdev->panel)) {
512 /* Second panel display seconf half of screen if possible,
513 * otherwise display the same as the first panel */
514 if (info->var.yres_virtual >= (info->var.yres << 1)) {
515 fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys +
516 (info->fix.line_length *
517 (info->var.yres_virtual >> 1)));
518 } else {
519 fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys);
520 }
521 }
522
523 words = info->fix.line_length / sizeof(u32);
524 if (!info->var.rotate || (info->var.rotate == 180)) {
525 words *= info->var.yres_virtual;
526 if (info->var.rotate /* 180 */) {
527 words -= (words % 8); /* should be divisable by 8 */
528 }
529 }
530 fbdev->regs->lcd_words = LCD_WRD_WRDS_N(words);
531
532 fbdev->regs->lcd_pwmdiv = 0;
533 fbdev->regs->lcd_pwmhi = 0;
534
535 /* Resume controller */
536 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
537 mdelay(10);
538 au1100fb_fb_blank(VESA_NO_BLANKING, info);
539
540 return 0;
541 }
542
543 /* fb_setcolreg
544 * Set color in LCD palette.
545 */
au1100fb_fb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * fbi)546 static int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
547 unsigned transp, struct fb_info *fbi)
548 {
549 struct au1100fb_device *fbdev;
550 u32 *palette;
551 u32 value;
552
553 fbdev = to_au1100fb_device(fbi);
554 palette = fbdev->regs->lcd_palettebase;
555
556 if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1))
557 return -EINVAL;
558
559 if (fbi->var.grayscale) {
560 /* Convert color to grayscale */
561 red = green = blue =
562 (19595 * red + 38470 * green + 7471 * blue) >> 16;
563 }
564
565 if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
566 /* Place color in the pseudopalette */
567 if (regno > 16)
568 return -EINVAL;
569
570 palette = (u32*)fbi->pseudo_palette;
571
572 red >>= (16 - fbi->var.red.length);
573 green >>= (16 - fbi->var.green.length);
574 blue >>= (16 - fbi->var.blue.length);
575
576 value = (red << fbi->var.red.offset) |
577 (green << fbi->var.green.offset)|
578 (blue << fbi->var.blue.offset);
579 value &= 0xFFFF;
580
581 } else if (panel_is_active(fbdev->panel)) {
582 /* COLOR TFT PALLETTIZED (use RGB 565) */
583 value = (red & 0xF800)|((green >> 5) & 0x07E0)|((blue >> 11) & 0x001F);
584 value &= 0xFFFF;
585
586 } else if (panel_is_color(fbdev->panel)) {
587 /* COLOR STN MODE */
588 value = (((panel_swap_rgb(fbdev->panel) ? blue : red) >> 12) & 0x000F) |
589 ((green >> 8) & 0x00F0) |
590 (((panel_swap_rgb(fbdev->panel) ? red : blue) >> 4) & 0x0F00);
591 value &= 0xFFF;
592 } else {
593 /* MONOCHROME MODE */
594 value = (green >> 12) & 0x000F;
595 value &= 0xF;
596 }
597
598 palette[regno] = value;
599
600 return 0;
601 }
602
603 /* fb_pan_display
604 * Pan display in x and/or y as specified
605 */
au1100fb_fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * fbi)606 static int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
607 {
608 struct au1100fb_device *fbdev;
609 int dy;
610
611 fbdev = to_au1100fb_device(fbi);
612
613 pr_devel("fb_pan_display %p %p", var, fbi);
614
615 if (!var || !fbdev) {
616 return -EINVAL;
617 }
618
619 if (var->xoffset - fbi->var.xoffset) {
620 /* No support for X panning for now! */
621 return -EINVAL;
622 }
623
624 pr_devel("fb_pan_display 2 %p %p", var, fbi);
625 dy = var->yoffset - fbi->var.yoffset;
626 if (dy) {
627
628 u32 dmaaddr;
629
630 pr_devel("Panning screen of %d lines", dy);
631
632 dmaaddr = fbdev->regs->lcd_dmaaddr0;
633 dmaaddr += (fbi->fix.line_length * dy);
634
635 /* TODO: Wait for current frame to finished */
636 fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
637
638 if (panel_is_dual(fbdev->panel)) {
639 dmaaddr = fbdev->regs->lcd_dmaaddr1;
640 dmaaddr += (fbi->fix.line_length * dy);
641 fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
642 }
643 }
644 pr_devel("fb_pan_display 3 %p %p", var, fbi);
645
646 return 0;
647 }
648
649 /* fb_mmap
650 * Map video memory in user space. We don't use the generic fb_mmap method mainly
651 * to allow the use of the TLB streaming flag (CCA=6)
652 */
au1100fb_fb_mmap(struct fb_info * fbi,struct vm_area_struct * vma)653 static int au1100fb_fb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
654 {
655 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
656
657 vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
658
659 #ifndef CONFIG_S390
660 /* On s390 pgprot_val() is a function and thus not a lvalue */
661 pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
662 #endif
663
664 return dma_mmap_coherent(fbdev->dev, vma, fbdev->fb_mem, fbdev->fb_phys,
665 fbdev->fb_len);
666 }
667
668 static const struct fb_ops au1100fb_ops = {
669 .owner = THIS_MODULE,
670 __FB_DEFAULT_IOMEM_OPS_RDWR,
671 .fb_setcolreg = au1100fb_fb_setcolreg,
672 .fb_blank = au1100fb_fb_blank,
673 .fb_pan_display = au1100fb_fb_pan_display,
674 __FB_DEFAULT_IOMEM_OPS_DRAW,
675 .fb_mmap = au1100fb_fb_mmap,
676 };
677
678
679 /*-------------------------------------------------------------------------*/
680
au1100fb_setup(struct au1100fb_device * fbdev)681 static int au1100fb_setup(struct au1100fb_device *fbdev)
682 {
683 char *this_opt, *options;
684 int num_panels = ARRAY_SIZE(known_lcd_panels);
685
686 if (num_panels <= 0) {
687 pr_err("No LCD panels supported by driver!");
688 return -ENODEV;
689 }
690
691 if (fb_get_options(DRIVER_NAME, &options))
692 return -ENODEV;
693 if (!options)
694 return -ENODEV;
695
696 while ((this_opt = strsep(&options, ",")) != NULL) {
697 /* Panel option */
698 if (!strncmp(this_opt, "panel:", 6)) {
699 int i;
700 this_opt += 6;
701 for (i = 0; i < num_panels; i++) {
702 if (!strncmp(this_opt, known_lcd_panels[i].name,
703 strlen(this_opt))) {
704 fbdev->panel = &known_lcd_panels[i];
705 fbdev->panel_idx = i;
706 break;
707 }
708 }
709 if (i >= num_panels) {
710 pr_warn("Panel '%s' not supported!", this_opt);
711 return -ENODEV;
712 }
713 }
714 /* Unsupported option */
715 else
716 pr_warn("Unsupported option \"%s\"", this_opt);
717 }
718
719 pr_info("Panel=%s", fbdev->panel->name);
720
721 return 0;
722 }
723
au1100fb_drv_probe(struct platform_device * dev)724 static int au1100fb_drv_probe(struct platform_device *dev)
725 {
726 struct au1100fb_device *fbdev;
727 struct resource *regs_res;
728 struct clk *c;
729
730 /* Allocate new device private */
731 fbdev = devm_kzalloc(&dev->dev, sizeof(*fbdev), GFP_KERNEL);
732 if (!fbdev)
733 return -ENOMEM;
734
735 if (au1100fb_setup(fbdev))
736 goto failed;
737
738 platform_set_drvdata(dev, (void *)fbdev);
739 fbdev->dev = &dev->dev;
740
741 /* Allocate region for our registers and map them */
742 regs_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
743 if (!regs_res) {
744 pr_err("fail to retrieve registers resource");
745 return -EFAULT;
746 }
747
748 fbdev->info.fix = (struct fb_fix_screeninfo) {
749 .mmio_start = regs_res->start,
750 .mmio_len = resource_size(regs_res),
751 .id = "AU1100 FB",
752 .xpanstep = 1,
753 .ypanstep = 1,
754 .type = FB_TYPE_PACKED_PIXELS,
755 .accel = FB_ACCEL_NONE,
756 };
757
758 if (!devm_request_mem_region(&dev->dev,
759 fbdev->info.fix.mmio_start,
760 fbdev->info.fix.mmio_len,
761 DRIVER_NAME)) {
762 pr_err("fail to lock memory region at 0x%08lx",
763 fbdev->info.fix.mmio_start);
764 return -EBUSY;
765 }
766
767 fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(fbdev->info.fix.mmio_start);
768
769 pr_devel("Register memory map at %p", fbdev->regs);
770 pr_devel("phys=0x%08x, size=%zu", fbdev->regs_phys, fbdev->regs_len);
771
772 c = clk_get(NULL, "lcd_intclk");
773 if (!IS_ERR(c)) {
774 fbdev->lcdclk = c;
775 clk_set_rate(c, 48000000);
776 clk_prepare_enable(c);
777 }
778
779 /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */
780 fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
781 (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
782
783 fbdev->fb_mem = dmam_alloc_coherent(&dev->dev,
784 PAGE_ALIGN(fbdev->fb_len),
785 &fbdev->fb_phys, GFP_KERNEL);
786 if (!fbdev->fb_mem) {
787 pr_err("fail to allocate framebuffer (size: %zuK))",
788 fbdev->fb_len / 1024);
789 return -ENOMEM;
790 }
791
792 fbdev->info.fix.smem_start = fbdev->fb_phys;
793 fbdev->info.fix.smem_len = fbdev->fb_len;
794
795 pr_devel("Framebuffer memory map at %p", fbdev->fb_mem);
796 pr_devel("phys=0x%pad, size=%zuK", &fbdev->fb_phys, fbdev->fb_len / 1024);
797
798 /* load the panel info into the var struct */
799 fbdev->info.var = (struct fb_var_screeninfo) {
800 .activate = FB_ACTIVATE_NOW,
801 .height = -1,
802 .width = -1,
803 .vmode = FB_VMODE_NONINTERLACED,
804 .bits_per_pixel = fbdev->panel->bpp,
805 .xres = fbdev->panel->xres,
806 .xres_virtual = fbdev->panel->xres,
807 .yres = fbdev->panel->yres,
808 .yres_virtual = fbdev->panel->yres,
809 };
810
811 fbdev->info.screen_base = fbdev->fb_mem;
812 fbdev->info.fbops = &au1100fb_ops;
813
814 fbdev->info.pseudo_palette =
815 devm_kcalloc(&dev->dev, 16, sizeof(u32), GFP_KERNEL);
816 if (!fbdev->info.pseudo_palette)
817 return -ENOMEM;
818
819 if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
820 pr_err("Fail to allocate colormap (%d entries)",
821 AU1100_LCD_NBR_PALETTE_ENTRIES);
822 return -EFAULT;
823 }
824
825 /* Set h/w registers */
826 au1100fb_setmode(fbdev);
827
828 /* Register new framebuffer */
829 if (register_framebuffer(&fbdev->info) < 0) {
830 pr_err("cannot register new framebuffer");
831 goto failed;
832 }
833
834 return 0;
835
836 failed:
837 if (fbdev->lcdclk) {
838 clk_disable_unprepare(fbdev->lcdclk);
839 clk_put(fbdev->lcdclk);
840 }
841 if (fbdev->info.cmap.len != 0) {
842 fb_dealloc_cmap(&fbdev->info.cmap);
843 }
844
845 return -ENODEV;
846 }
847
au1100fb_drv_remove(struct platform_device * dev)848 static void au1100fb_drv_remove(struct platform_device *dev)
849 {
850 struct au1100fb_device *fbdev = NULL;
851
852 fbdev = platform_get_drvdata(dev);
853
854 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
855 au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
856 #endif
857 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
858
859 /* Clean up all probe data */
860 unregister_framebuffer(&fbdev->info);
861
862 fb_dealloc_cmap(&fbdev->info.cmap);
863
864 if (fbdev->lcdclk) {
865 clk_disable_unprepare(fbdev->lcdclk);
866 clk_put(fbdev->lcdclk);
867 }
868 }
869
870 #ifdef CONFIG_PM
au1100fb_drv_suspend(struct platform_device * dev,pm_message_t state)871 static int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
872 {
873 struct au1100fb_device *fbdev = platform_get_drvdata(dev);
874
875 if (!fbdev)
876 return 0;
877
878 /* Blank the LCD */
879 au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
880
881 clk_disable(fbdev->lcdclk);
882
883 memcpy(&fbdev->pm_regs, fbdev->regs, sizeof(struct au1100fb_regs));
884
885 return 0;
886 }
887
au1100fb_drv_resume(struct platform_device * dev)888 static int au1100fb_drv_resume(struct platform_device *dev)
889 {
890 struct au1100fb_device *fbdev = platform_get_drvdata(dev);
891 int ret;
892
893 if (!fbdev)
894 return 0;
895
896 memcpy(fbdev->regs, &fbdev->pm_regs, sizeof(struct au1100fb_regs));
897
898 ret = clk_enable(fbdev->lcdclk);
899 if (ret)
900 return ret;
901
902 /* Unblank the LCD */
903 au1100fb_fb_blank(VESA_NO_BLANKING, &fbdev->info);
904
905 return 0;
906 }
907 #else
908 #define au1100fb_drv_suspend NULL
909 #define au1100fb_drv_resume NULL
910 #endif
911
912 static struct platform_driver au1100fb_driver = {
913 .driver = {
914 .name = "au1100-lcd",
915 },
916 .probe = au1100fb_drv_probe,
917 .remove = au1100fb_drv_remove,
918 .suspend = au1100fb_drv_suspend,
919 .resume = au1100fb_drv_resume,
920 };
921 module_platform_driver(au1100fb_driver);
922
923 MODULE_DESCRIPTION(DRIVER_DESC);
924 MODULE_LICENSE("GPL");
925