1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/iopoll.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irq.h> 31 #include <linux/irq_work.h> 32 #include <linux/kernel.h> 33 #include <linux/of_address.h> 34 #include <linux/of_clk.h> 35 #include <linux/of.h> 36 #include <linux/of_irq.h> 37 #include <linux/of_platform.h> 38 #include <linux/pinctrl/pinconf-generic.h> 39 #include <linux/pinctrl/pinconf.h> 40 #include <linux/pinctrl/pinctrl.h> 41 #include <linux/platform_device.h> 42 #include <linux/pm_domain.h> 43 #include <linux/pm_opp.h> 44 #include <linux/power_supply.h> 45 #include <linux/reboot.h> 46 #include <linux/regmap.h> 47 #include <linux/reset.h> 48 #include <linux/seq_file.h> 49 #include <linux/slab.h> 50 #include <linux/spinlock.h> 51 #include <linux/string_choices.h> 52 #include <linux/syscore_ops.h> 53 54 #include <soc/tegra/common.h> 55 #include <soc/tegra/fuse.h> 56 #include <soc/tegra/pmc.h> 57 58 #include <dt-bindings/interrupt-controller/arm-gic.h> 59 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 60 #include <dt-bindings/gpio/tegra186-gpio.h> 61 #include <dt-bindings/gpio/tegra194-gpio.h> 62 #include <dt-bindings/gpio/tegra234-gpio.h> 63 #include <dt-bindings/soc/tegra-pmc.h> 64 65 #define PMC_CNTRL 0x0 66 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 67 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 68 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 69 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 70 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 71 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 72 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 73 #define PMC_CNTRL_BLINK_EN 7 74 #define PMC_CNTRL_MAIN_RST BIT(4) 75 76 #define PMC_WAKE_MASK 0x0c 77 #define PMC_WAKE_LEVEL 0x10 78 #define PMC_WAKE_STATUS 0x14 79 #define PMC_SW_WAKE_STATUS 0x18 80 #define PMC_DPD_PADS_ORIDE 0x1c 81 #define PMC_DPD_PADS_ORIDE_BLINK 20 82 83 #define DPD_SAMPLE 0x020 84 #define DPD_SAMPLE_ENABLE BIT(0) 85 #define DPD_SAMPLE_DISABLE (0 << 0) 86 87 #define PWRGATE_TOGGLE 0x30 88 #define PWRGATE_TOGGLE_START BIT(8) 89 90 #define REMOVE_CLAMPING 0x34 91 92 #define PWRGATE_STATUS 0x38 93 94 #define PMC_BLINK_TIMER 0x40 95 #define PMC_IMPL_E_33V_PWR 0x40 96 97 #define PMC_PWR_DET 0x48 98 99 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 100 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 101 #define PMC_SCRATCH0_MODE_RCM BIT(1) 102 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 103 PMC_SCRATCH0_MODE_BOOTLOADER | \ 104 PMC_SCRATCH0_MODE_RCM) 105 106 #define PMC_CPUPWRGOOD_TIMER 0xc8 107 #define PMC_CPUPWROFF_TIMER 0xcc 108 #define PMC_COREPWRGOOD_TIMER 0x3c 109 #define PMC_COREPWROFF_TIMER 0xe0 110 111 #define PMC_PWR_DET_VALUE 0xe4 112 113 #define PMC_USB_DEBOUNCE_DEL 0xec 114 #define PMC_USB_AO 0xf0 115 116 #define PMC_SCRATCH37 0x130 117 #define PMC_SCRATCH41 0x140 118 119 #define PMC_WAKE2_MASK 0x160 120 #define PMC_WAKE2_LEVEL 0x164 121 #define PMC_WAKE2_STATUS 0x168 122 #define PMC_SW_WAKE2_STATUS 0x16c 123 124 #define PMC_CLK_OUT_CNTRL 0x1a8 125 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 126 #define PMC_SENSOR_CTRL 0x1b0 127 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 128 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 129 130 #define PMC_RST_STATUS_POR 0 131 #define PMC_RST_STATUS_WATCHDOG 1 132 #define PMC_RST_STATUS_SENSOR 2 133 #define PMC_RST_STATUS_SW_MAIN 3 134 #define PMC_RST_STATUS_LP0 4 135 #define PMC_RST_STATUS_AOTAG 5 136 137 #define IO_DPD_REQ 0x1b8 138 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 139 #define IO_DPD_REQ_CODE_OFF (1U << 30) 140 #define IO_DPD_REQ_CODE_ON (2U << 30) 141 #define IO_DPD_REQ_CODE_MASK (3U << 30) 142 143 #define IO_DPD_STATUS 0x1bc 144 #define IO_DPD2_REQ 0x1c0 145 #define IO_DPD2_STATUS 0x1c4 146 #define SEL_DPD_TIM 0x1c8 147 148 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 149 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 150 151 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 152 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 153 #define PMC_UTMIP_UHSIC_FAKE 0x218 154 155 #define PMC_SCRATCH54 0x258 156 #define PMC_SCRATCH54_DATA_SHIFT 8 157 #define PMC_SCRATCH54_ADDR_SHIFT 0 158 159 #define PMC_SCRATCH55 0x25c 160 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 161 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 162 #define PMC_SCRATCH55_PINMUX_SHIFT 24 163 #define PMC_SCRATCH55_16BITOP BIT(15) 164 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 165 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 166 167 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 168 169 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 170 #define PMC_UTMIP_MASTER_CONFIG 0x274 171 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 172 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 173 174 #define GPU_RG_CNTRL 0x2d4 175 176 #define PMC_UTMIP_PAD_CFG0 0x4c0 177 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 178 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 179 /* Tegra186 and later */ 180 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 181 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 182 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 183 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 184 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 185 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 186 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 187 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 188 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 189 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 190 #define WAKE_AOWAKE_SW_STATUS_W_0 0x49c 191 #define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2)) 192 #define WAKE_LATCH_SW 0x498 193 194 #define WAKE_AOWAKE_CTRL 0x4f4 195 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 196 197 #define SW_WAKE_ID 83 /* wake83 */ 198 199 /* for secure PMC */ 200 #define TEGRA_SMC_PMC 0xc2fffe00 201 #define TEGRA_SMC_PMC_READ 0xaa 202 #define TEGRA_SMC_PMC_WRITE 0xbb 203 204 struct pmc_clk { 205 struct clk_hw hw; 206 struct tegra_pmc *pmc; 207 unsigned long offs; 208 u32 mux_shift; 209 u32 force_en_shift; 210 }; 211 212 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 213 214 struct pmc_clk_gate { 215 struct clk_hw hw; 216 struct tegra_pmc *pmc; 217 unsigned long offs; 218 u32 shift; 219 }; 220 221 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 222 223 struct pmc_clk_init_data { 224 char *name; 225 const char *const *parents; 226 int num_parents; 227 int clk_id; 228 u8 mux_shift; 229 u8 force_en_shift; 230 }; 231 232 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 233 "osc_div4", "extern1", 234 }; 235 236 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 237 "osc_div4", "extern2", 238 }; 239 240 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 241 "osc_div4", "extern3", 242 }; 243 244 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 245 { 246 .name = "pmc_clk_out_1", 247 .parents = clk_out1_parents, 248 .num_parents = ARRAY_SIZE(clk_out1_parents), 249 .clk_id = TEGRA_PMC_CLK_OUT_1, 250 .mux_shift = 6, 251 .force_en_shift = 2, 252 }, 253 { 254 .name = "pmc_clk_out_2", 255 .parents = clk_out2_parents, 256 .num_parents = ARRAY_SIZE(clk_out2_parents), 257 .clk_id = TEGRA_PMC_CLK_OUT_2, 258 .mux_shift = 14, 259 .force_en_shift = 10, 260 }, 261 { 262 .name = "pmc_clk_out_3", 263 .parents = clk_out3_parents, 264 .num_parents = ARRAY_SIZE(clk_out3_parents), 265 .clk_id = TEGRA_PMC_CLK_OUT_3, 266 .mux_shift = 22, 267 .force_en_shift = 18, 268 }, 269 }; 270 271 struct tegra_pmc_core_pd { 272 struct generic_pm_domain genpd; 273 struct tegra_pmc *pmc; 274 }; 275 276 static inline struct tegra_pmc_core_pd * 277 to_core_pd(struct generic_pm_domain *genpd) 278 { 279 return container_of(genpd, struct tegra_pmc_core_pd, genpd); 280 } 281 282 struct tegra_powergate { 283 struct generic_pm_domain genpd; 284 struct tegra_pmc *pmc; 285 unsigned int id; 286 struct clk **clks; 287 unsigned int num_clks; 288 unsigned long *clk_rates; 289 struct reset_control *reset; 290 }; 291 292 struct tegra_io_pad_soc { 293 enum tegra_io_pad id; 294 unsigned int dpd; 295 unsigned int request; 296 unsigned int status; 297 unsigned int voltage; 298 const char *name; 299 }; 300 301 struct tegra_pmc_regs { 302 unsigned int scratch0; 303 unsigned int rst_status; 304 unsigned int rst_source_shift; 305 unsigned int rst_source_mask; 306 unsigned int rst_level_shift; 307 unsigned int rst_level_mask; 308 }; 309 310 struct tegra_wake_event { 311 const char *name; 312 unsigned int id; 313 unsigned int irq; 314 struct { 315 unsigned int instance; 316 unsigned int pin; 317 } gpio; 318 }; 319 320 #define TEGRA_WAKE_SIMPLE(_name, _id) \ 321 { \ 322 .name = _name, \ 323 .id = _id, \ 324 .irq = 0, \ 325 .gpio = { \ 326 .instance = UINT_MAX, \ 327 .pin = UINT_MAX, \ 328 }, \ 329 } 330 331 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 332 { \ 333 .name = _name, \ 334 .id = _id, \ 335 .irq = _irq, \ 336 .gpio = { \ 337 .instance = UINT_MAX, \ 338 .pin = UINT_MAX, \ 339 }, \ 340 } 341 342 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 343 { \ 344 .name = _name, \ 345 .id = _id, \ 346 .irq = 0, \ 347 .gpio = { \ 348 .instance = _instance, \ 349 .pin = _pin, \ 350 }, \ 351 } 352 353 struct tegra_pmc_soc { 354 unsigned int num_powergates; 355 const char *const *powergates; 356 unsigned int num_cpu_powergates; 357 const u8 *cpu_powergates; 358 359 bool has_tsense_reset; 360 bool has_gpu_clamps; 361 bool needs_mbist_war; 362 bool has_impl_33v_pwr; 363 bool maybe_tz_only; 364 365 const struct tegra_io_pad_soc *io_pads; 366 unsigned int num_io_pads; 367 368 const struct pinctrl_pin_desc *pin_descs; 369 unsigned int num_pin_descs; 370 371 const struct tegra_pmc_regs *regs; 372 void (*init)(struct tegra_pmc *pmc); 373 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 374 struct device_node *np, 375 bool invert); 376 void (*set_wake_filters)(struct tegra_pmc *pmc); 377 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 378 int (*irq_set_type)(struct irq_data *data, unsigned int type); 379 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 380 bool new_state); 381 382 const char * const *reset_sources; 383 unsigned int num_reset_sources; 384 const char * const *reset_levels; 385 unsigned int num_reset_levels; 386 387 /* 388 * These describe events that can wake the system from sleep (i.e. 389 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 390 * are dealt with in the LIC. 391 */ 392 const struct tegra_wake_event *wake_events; 393 unsigned int num_wake_events; 394 unsigned int max_wake_events; 395 unsigned int max_wake_vectors; 396 397 const struct pmc_clk_init_data *pmc_clks_data; 398 unsigned int num_pmc_clks; 399 bool has_blink_output; 400 bool has_usb_sleepwalk; 401 bool supports_core_domain; 402 bool has_single_mmio_aperture; 403 }; 404 405 /** 406 * struct tegra_pmc - NVIDIA Tegra PMC 407 * @dev: pointer to PMC device structure 408 * @base: pointer to I/O remapped register region 409 * @wake: pointer to I/O remapped region for WAKE registers 410 * @aotag: pointer to I/O remapped region for AOTAG registers 411 * @scratch: pointer to I/O remapped region for scratch registers 412 * @clk: pointer to pclk clock 413 * @soc: pointer to SoC data structure 414 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 415 * @rate: currently configured rate of pclk 416 * @suspend_mode: lowest suspend mode available 417 * @cpu_good_time: CPU power good time (in microseconds) 418 * @cpu_off_time: CPU power off time (in microsecends) 419 * @core_osc_time: core power good OSC time (in microseconds) 420 * @core_pmu_time: core power good PMU time (in microseconds) 421 * @core_off_time: core power off time (in microseconds) 422 * @corereq_high: core power request is active-high 423 * @sysclkreq_high: system clock request is active-high 424 * @combined_req: combined power request for CPU & core 425 * @cpu_pwr_good_en: CPU power good signal is enabled 426 * @lp0_vec_phys: physical base address of the LP0 warm boot code 427 * @lp0_vec_size: size of the LP0 warm boot code 428 * @powergates_available: Bitmap of available power gates 429 * @powergates_lock: mutex for power gate register access 430 * @pctl_dev: pin controller exposed by the PMC 431 * @domain: IRQ domain provided by the PMC 432 * @irq: chip implementation for the IRQ domain 433 * @clk_nb: pclk clock changes handler 434 * @core_domain_state_synced: flag marking the core domain's state as synced 435 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 436 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 437 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 438 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 439 * cntrl register associated with each wake during system suspend. 440 * @syscore: syscore suspend/resume callbacks 441 */ 442 struct tegra_pmc { 443 struct device *dev; 444 void __iomem *base; 445 void __iomem *wake; 446 void __iomem *aotag; 447 void __iomem *scratch; 448 struct clk *clk; 449 450 const struct tegra_pmc_soc *soc; 451 bool tz_only; 452 453 unsigned long rate; 454 455 enum tegra_suspend_mode suspend_mode; 456 u32 cpu_good_time; 457 u32 cpu_off_time; 458 u32 core_osc_time; 459 u32 core_pmu_time; 460 u32 core_off_time; 461 bool corereq_high; 462 bool sysclkreq_high; 463 bool combined_req; 464 bool cpu_pwr_good_en; 465 u32 lp0_vec_phys; 466 u32 lp0_vec_size; 467 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 468 469 struct mutex powergates_lock; 470 471 struct pinctrl_dev *pctl_dev; 472 473 struct irq_domain *domain; 474 struct irq_chip irq; 475 476 struct notifier_block clk_nb; 477 478 bool core_domain_state_synced; 479 480 unsigned long *wake_type_level_map; 481 unsigned long *wake_type_dual_edge_map; 482 unsigned long *wake_sw_status_map; 483 unsigned long *wake_cntrl_level_map; 484 485 struct notifier_block reboot_notifier; 486 struct syscore syscore; 487 488 /* Pending wake IRQ processing */ 489 struct irq_work wake_work; 490 u32 *wake_status; 491 }; 492 493 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 494 .base = NULL, 495 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 496 }; 497 498 static inline struct tegra_powergate * 499 to_powergate(struct generic_pm_domain *domain) 500 { 501 return container_of(domain, struct tegra_powergate, genpd); 502 } 503 504 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 505 { 506 struct arm_smccc_res res; 507 508 if (pmc->tz_only) { 509 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 510 0, 0, 0, &res); 511 if (res.a0) { 512 if (pmc->dev) 513 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 514 __func__, res.a0); 515 else 516 pr_warn("%s(): SMC failed: %lu\n", __func__, 517 res.a0); 518 } 519 520 return res.a1; 521 } 522 523 return readl(pmc->base + offset); 524 } 525 526 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 527 unsigned long offset) 528 { 529 struct arm_smccc_res res; 530 531 if (pmc->tz_only) { 532 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 533 value, 0, 0, 0, 0, &res); 534 if (res.a0) { 535 if (pmc->dev) 536 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 537 __func__, res.a0); 538 else 539 pr_warn("%s(): SMC failed: %lu\n", __func__, 540 res.a0); 541 } 542 } else { 543 writel(value, pmc->base + offset); 544 } 545 } 546 547 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 548 { 549 if (pmc->tz_only) 550 return tegra_pmc_readl(pmc, offset); 551 552 return readl(pmc->scratch + offset); 553 } 554 555 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 556 unsigned long offset) 557 { 558 if (pmc->tz_only) 559 tegra_pmc_writel(pmc, value, offset); 560 else 561 writel(value, pmc->scratch + offset); 562 } 563 564 static inline bool tegra_powergate_state(struct tegra_pmc *pmc, int id) 565 { 566 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 567 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 568 else 569 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 570 } 571 572 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 573 { 574 return (pmc->soc && pmc->soc->powergates[id]); 575 } 576 577 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 578 { 579 return test_bit(id, pmc->powergates_available); 580 } 581 582 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 583 { 584 unsigned int i; 585 586 if (!pmc || !pmc->soc || !name) 587 return -EINVAL; 588 589 for (i = 0; i < pmc->soc->num_powergates; i++) { 590 if (!tegra_powergate_is_valid(pmc, i)) 591 continue; 592 593 if (!strcmp(name, pmc->soc->powergates[i])) 594 return i; 595 } 596 597 return -ENODEV; 598 } 599 600 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 601 bool new_state) 602 { 603 unsigned int retries = 100; 604 bool status; 605 int ret; 606 607 /* 608 * As per TRM documentation, the toggle command will be dropped by PMC 609 * if there is contention with a HW-initiated toggling (i.e. CPU core 610 * power-gated), the command should be retried in that case. 611 */ 612 do { 613 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 614 615 /* wait for PMC to execute the command */ 616 ret = read_poll_timeout(tegra_powergate_state, status, 617 status == new_state, 1, 10, false, 618 pmc, id); 619 } while (ret == -ETIMEDOUT && retries--); 620 621 return ret; 622 } 623 624 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 625 { 626 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 627 } 628 629 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 630 bool new_state) 631 { 632 bool status; 633 int err; 634 635 /* wait while PMC power gating is contended */ 636 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 637 status == true, 1, 100); 638 if (err) 639 return err; 640 641 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 642 643 /* wait for PMC to accept the command */ 644 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 645 status == true, 1, 100); 646 if (err) 647 return err; 648 649 /* wait for PMC to execute the command */ 650 err = read_poll_timeout(tegra_powergate_state, status, 651 status == new_state, 10, 100000, false, 652 pmc, id); 653 if (err) 654 return err; 655 656 return 0; 657 } 658 659 /** 660 * tegra_powergate_set() - set the state of a partition 661 * @pmc: power management controller 662 * @id: partition ID 663 * @new_state: new state of the partition 664 */ 665 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 666 bool new_state) 667 { 668 int err; 669 670 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 671 return -EINVAL; 672 673 mutex_lock(&pmc->powergates_lock); 674 675 if (tegra_powergate_state(pmc, id) == new_state) { 676 mutex_unlock(&pmc->powergates_lock); 677 return 0; 678 } 679 680 err = pmc->soc->powergate_set(pmc, id, new_state); 681 682 mutex_unlock(&pmc->powergates_lock); 683 684 return err; 685 } 686 687 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 688 unsigned int id) 689 { 690 u32 mask; 691 692 mutex_lock(&pmc->powergates_lock); 693 694 /* 695 * On Tegra124 and later, the clamps for the GPU are controlled by a 696 * separate register (with different semantics). 697 */ 698 if (id == TEGRA_POWERGATE_3D) { 699 if (pmc->soc->has_gpu_clamps) { 700 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 701 goto out; 702 } 703 } 704 705 /* 706 * Tegra 2 has a bug where PCIE and VDE clamping masks are 707 * swapped relatively to the partition ids 708 */ 709 if (id == TEGRA_POWERGATE_VDEC) 710 mask = (1 << TEGRA_POWERGATE_PCIE); 711 else if (id == TEGRA_POWERGATE_PCIE) 712 mask = (1 << TEGRA_POWERGATE_VDEC); 713 else 714 mask = (1 << id); 715 716 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 717 718 out: 719 mutex_unlock(&pmc->powergates_lock); 720 721 return 0; 722 } 723 724 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 725 { 726 unsigned long safe_rate = 100 * 1000 * 1000; 727 unsigned int i; 728 int err; 729 730 for (i = 0; i < pg->num_clks; i++) { 731 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 732 733 if (!pg->clk_rates[i]) { 734 err = -EINVAL; 735 goto out; 736 } 737 738 if (pg->clk_rates[i] <= safe_rate) 739 continue; 740 741 /* 742 * We don't know whether voltage state is okay for the 743 * current clock rate, hence it's better to temporally 744 * switch clock to a safe rate which is suitable for 745 * all voltages, before enabling the clock. 746 */ 747 err = clk_set_rate(pg->clks[i], safe_rate); 748 if (err) 749 goto out; 750 } 751 752 return 0; 753 754 out: 755 while (i--) 756 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 757 758 return err; 759 } 760 761 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 762 { 763 unsigned int i; 764 int err; 765 766 for (i = 0; i < pg->num_clks; i++) { 767 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 768 if (err) 769 return err; 770 } 771 772 return 0; 773 } 774 775 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 776 { 777 unsigned int i; 778 779 for (i = 0; i < pg->num_clks; i++) 780 clk_disable_unprepare(pg->clks[i]); 781 } 782 783 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 784 { 785 unsigned int i; 786 int err; 787 788 for (i = 0; i < pg->num_clks; i++) { 789 err = clk_prepare_enable(pg->clks[i]); 790 if (err) 791 goto out; 792 } 793 794 return 0; 795 796 out: 797 while (i--) 798 clk_disable_unprepare(pg->clks[i]); 799 800 return err; 801 } 802 803 static int tegra_powergate_power_up(struct tegra_powergate *pg, 804 bool disable_clocks) 805 { 806 int err; 807 808 err = reset_control_assert(pg->reset); 809 if (err) 810 return err; 811 812 usleep_range(10, 20); 813 814 err = tegra_powergate_set(pg->pmc, pg->id, true); 815 if (err < 0) 816 return err; 817 818 usleep_range(10, 20); 819 820 err = tegra_powergate_prepare_clocks(pg); 821 if (err) 822 goto powergate_off; 823 824 err = tegra_powergate_enable_clocks(pg); 825 if (err) 826 goto unprepare_clks; 827 828 usleep_range(10, 20); 829 830 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 831 if (err) 832 goto disable_clks; 833 834 usleep_range(10, 20); 835 836 err = reset_control_deassert(pg->reset); 837 if (err) 838 goto disable_clks; 839 840 usleep_range(10, 20); 841 842 if (pg->pmc->soc->needs_mbist_war) 843 err = tegra210_clk_handle_mbist_war(pg->id); 844 if (err) 845 goto disable_clks; 846 847 if (disable_clocks) 848 tegra_powergate_disable_clocks(pg); 849 850 err = tegra_powergate_unprepare_clocks(pg); 851 if (err) 852 return err; 853 854 return 0; 855 856 disable_clks: 857 tegra_powergate_disable_clocks(pg); 858 usleep_range(10, 20); 859 860 unprepare_clks: 861 tegra_powergate_unprepare_clocks(pg); 862 863 powergate_off: 864 tegra_powergate_set(pg->pmc, pg->id, false); 865 866 return err; 867 } 868 869 static int tegra_powergate_power_down(struct tegra_powergate *pg) 870 { 871 int err; 872 873 err = tegra_powergate_prepare_clocks(pg); 874 if (err) 875 return err; 876 877 err = tegra_powergate_enable_clocks(pg); 878 if (err) 879 goto unprepare_clks; 880 881 usleep_range(10, 20); 882 883 err = reset_control_assert(pg->reset); 884 if (err) 885 goto disable_clks; 886 887 usleep_range(10, 20); 888 889 tegra_powergate_disable_clocks(pg); 890 891 usleep_range(10, 20); 892 893 err = tegra_powergate_set(pg->pmc, pg->id, false); 894 if (err) 895 goto assert_resets; 896 897 err = tegra_powergate_unprepare_clocks(pg); 898 if (err) 899 return err; 900 901 return 0; 902 903 assert_resets: 904 tegra_powergate_enable_clocks(pg); 905 usleep_range(10, 20); 906 reset_control_deassert(pg->reset); 907 usleep_range(10, 20); 908 909 disable_clks: 910 tegra_powergate_disable_clocks(pg); 911 912 unprepare_clks: 913 tegra_powergate_unprepare_clocks(pg); 914 915 return err; 916 } 917 918 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 919 { 920 struct tegra_powergate *pg = to_powergate(domain); 921 struct device *dev = pg->pmc->dev; 922 int err; 923 924 err = tegra_powergate_power_up(pg, true); 925 if (err) { 926 dev_err(dev, "failed to turn on PM domain %s: %d\n", 927 pg->genpd.name, err); 928 goto out; 929 } 930 931 reset_control_release(pg->reset); 932 933 out: 934 return err; 935 } 936 937 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 938 { 939 struct tegra_powergate *pg = to_powergate(domain); 940 struct device *dev = pg->pmc->dev; 941 int err; 942 943 err = reset_control_acquire(pg->reset); 944 if (err < 0) { 945 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 946 pg->genpd.name, err); 947 return err; 948 } 949 950 err = tegra_powergate_power_down(pg); 951 if (err) { 952 dev_err(dev, "failed to turn off PM domain %s: %d\n", 953 pg->genpd.name, err); 954 reset_control_release(pg->reset); 955 } 956 957 return err; 958 } 959 960 static void tegra_pmc_put_device(void *data) 961 { 962 struct tegra_pmc *pmc = data; 963 964 put_device(pmc->dev); 965 } 966 967 static const struct of_device_id tegra_pmc_match[]; 968 969 static struct tegra_pmc *tegra_pmc_get(struct device *dev) 970 { 971 struct platform_device *pdev; 972 struct device_node *np; 973 struct tegra_pmc *pmc; 974 975 np = of_parse_phandle(dev->of_node, "nvidia,pmc", 0); 976 if (!np) { 977 struct device_node *parent = of_node_get(dev->of_node); 978 979 while ((parent = of_get_next_parent(parent)) != NULL) { 980 np = of_find_matching_node(parent, tegra_pmc_match); 981 if (np) 982 break; 983 } 984 985 of_node_put(parent); 986 987 if (!np) 988 return ERR_PTR(-ENODEV); 989 } 990 991 pdev = of_find_device_by_node(np); 992 of_node_put(np); 993 994 if (!pdev) 995 return ERR_PTR(-ENODEV); 996 997 pmc = platform_get_drvdata(pdev); 998 if (!pmc) { 999 put_device(&pdev->dev); 1000 return ERR_PTR(-EPROBE_DEFER); 1001 } 1002 1003 return pmc; 1004 } 1005 1006 /** 1007 * tegra_pmc_get() - find the PMC for a given device 1008 * @dev: device for which to find the PMC 1009 * 1010 * Returns a pointer to the PMC on success or an ERR_PTR()-encoded error code 1011 * otherwise. 1012 */ 1013 struct tegra_pmc *devm_tegra_pmc_get(struct device *dev) 1014 { 1015 struct tegra_pmc *pmc; 1016 int err; 1017 1018 pmc = tegra_pmc_get(dev); 1019 if (IS_ERR(pmc)) 1020 return pmc; 1021 1022 err = devm_add_action_or_reset(dev, tegra_pmc_put_device, pmc); 1023 if (err < 0) 1024 return ERR_PTR(err); 1025 1026 return pmc; 1027 } 1028 EXPORT_SYMBOL(devm_tegra_pmc_get); 1029 1030 /** 1031 * tegra_pmc_powergate_power_on() - power on partition 1032 * @pmc: power management controller 1033 * @id: partition ID 1034 */ 1035 int tegra_pmc_powergate_power_on(struct tegra_pmc *pmc, unsigned int id) 1036 { 1037 if (!tegra_powergate_is_available(pmc, id)) 1038 return -EINVAL; 1039 1040 return tegra_powergate_set(pmc, id, true); 1041 } 1042 EXPORT_SYMBOL(tegra_pmc_powergate_power_on); 1043 1044 /** 1045 * tegra_powergate_power_on() - power on partition 1046 * @id: partition ID 1047 */ 1048 int tegra_powergate_power_on(unsigned int id) 1049 { 1050 return tegra_pmc_powergate_power_on(pmc, id); 1051 } 1052 EXPORT_SYMBOL(tegra_powergate_power_on); 1053 1054 /** 1055 * tegra_pmc_powergate_power_off() - power off partition 1056 * @pmc: power management controller 1057 * @id: partition ID 1058 */ 1059 int tegra_pmc_powergate_power_off(struct tegra_pmc *pmc, unsigned int id) 1060 { 1061 if (!tegra_powergate_is_available(pmc, id)) 1062 return -EINVAL; 1063 1064 return tegra_powergate_set(pmc, id, false); 1065 } 1066 EXPORT_SYMBOL(tegra_pmc_powergate_power_off); 1067 1068 /** 1069 * tegra_powergate_power_off() - power off partition 1070 * @id: partition ID 1071 */ 1072 int tegra_powergate_power_off(unsigned int id) 1073 { 1074 return tegra_pmc_powergate_power_off(pmc, id); 1075 } 1076 EXPORT_SYMBOL(tegra_powergate_power_off); 1077 1078 /** 1079 * tegra_powergate_is_powered() - check if partition is powered 1080 * @pmc: power management controller 1081 * @id: partition ID 1082 */ 1083 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 1084 { 1085 if (!tegra_powergate_is_valid(pmc, id)) 1086 return -EINVAL; 1087 1088 return tegra_powergate_state(pmc, id); 1089 } 1090 1091 /** 1092 * tegra_pmc_powergate_remove_clamping() - remove power clamps for partition 1093 * @pmc: power management controller 1094 * @id: partition ID 1095 */ 1096 int tegra_pmc_powergate_remove_clamping(struct tegra_pmc *pmc, unsigned int id) 1097 { 1098 if (!tegra_powergate_is_available(pmc, id)) 1099 return -EINVAL; 1100 1101 return __tegra_powergate_remove_clamping(pmc, id); 1102 } 1103 EXPORT_SYMBOL(tegra_pmc_powergate_remove_clamping); 1104 1105 /** 1106 * tegra_powergate_remove_clamping() - remove power clamps for partition 1107 * @id: partition ID 1108 */ 1109 int tegra_powergate_remove_clamping(unsigned int id) 1110 { 1111 return tegra_pmc_powergate_remove_clamping(pmc, id); 1112 } 1113 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 1114 1115 /** 1116 * tegra_pmc_powergate_sequence_power_up() - power up partition 1117 * @pmc: power management controller 1118 * @id: partition ID 1119 * @clk: clock for partition 1120 * @rst: reset for partition 1121 * 1122 * Must be called with clk disabled, and returns with clk enabled. 1123 */ 1124 int tegra_pmc_powergate_sequence_power_up(struct tegra_pmc *pmc, 1125 unsigned int id, struct clk *clk, 1126 struct reset_control *rst) 1127 { 1128 struct tegra_powergate *pg; 1129 int err; 1130 1131 if (!tegra_powergate_is_available(pmc, id)) 1132 return -EINVAL; 1133 1134 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1135 if (!pg) 1136 return -ENOMEM; 1137 1138 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 1139 if (!pg->clk_rates) { 1140 kfree(pg->clks); 1141 return -ENOMEM; 1142 } 1143 1144 pg->id = id; 1145 pg->clks = &clk; 1146 pg->num_clks = 1; 1147 pg->reset = rst; 1148 pg->pmc = pmc; 1149 1150 err = tegra_powergate_power_up(pg, false); 1151 if (err) 1152 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1153 err); 1154 1155 kfree(pg->clk_rates); 1156 kfree(pg); 1157 1158 return err; 1159 } 1160 EXPORT_SYMBOL(tegra_pmc_powergate_sequence_power_up); 1161 1162 /** 1163 * tegra_powergate_sequence_power_up() - power up partition 1164 * @id: partition ID 1165 * @clk: clock for partition 1166 * @rst: reset for partition 1167 * 1168 * Must be called with clk disabled, and returns with clk enabled. 1169 */ 1170 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 1171 struct reset_control *rst) 1172 { 1173 return tegra_pmc_powergate_sequence_power_up(pmc, id, clk, rst); 1174 } 1175 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1176 1177 /** 1178 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1179 * @pmc: power management controller 1180 * @cpuid: CPU partition ID 1181 * 1182 * Returns the partition ID corresponding to the CPU partition ID or a 1183 * negative error code on failure. 1184 */ 1185 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1186 unsigned int cpuid) 1187 { 1188 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1189 return pmc->soc->cpu_powergates[cpuid]; 1190 1191 return -EINVAL; 1192 } 1193 1194 /** 1195 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1196 * @cpuid: CPU partition ID 1197 */ 1198 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1199 { 1200 int id; 1201 1202 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1203 if (id < 0) 1204 return false; 1205 1206 return tegra_powergate_is_powered(pmc, id); 1207 } 1208 1209 /** 1210 * tegra_pmc_cpu_power_on() - power on CPU partition 1211 * @cpuid: CPU partition ID 1212 */ 1213 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1214 { 1215 int id; 1216 1217 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1218 if (id < 0) 1219 return id; 1220 1221 return tegra_powergate_set(pmc, id, true); 1222 } 1223 1224 /** 1225 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1226 * @cpuid: CPU partition ID 1227 */ 1228 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1229 { 1230 int id; 1231 1232 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1233 if (id < 0) 1234 return id; 1235 1236 return tegra_powergate_remove_clamping(id); 1237 } 1238 1239 static void tegra_pmc_program_reboot_reason(struct tegra_pmc *pmc, 1240 const char *cmd) 1241 { 1242 u32 value; 1243 1244 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1245 value &= ~PMC_SCRATCH0_MODE_MASK; 1246 1247 if (cmd) { 1248 if (strcmp(cmd, "recovery") == 0) 1249 value |= PMC_SCRATCH0_MODE_RECOVERY; 1250 1251 if (strcmp(cmd, "bootloader") == 0) 1252 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1253 1254 if (strcmp(cmd, "forced-recovery") == 0) 1255 value |= PMC_SCRATCH0_MODE_RCM; 1256 } 1257 1258 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1259 } 1260 1261 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1262 unsigned long action, void *data) 1263 { 1264 struct tegra_pmc *pmc = container_of(this, struct tegra_pmc, 1265 reboot_notifier); 1266 if (action == SYS_RESTART) 1267 tegra_pmc_program_reboot_reason(pmc, data); 1268 1269 return NOTIFY_DONE; 1270 } 1271 1272 static void tegra_pmc_restart(struct tegra_pmc *pmc) 1273 { 1274 u32 value; 1275 1276 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1277 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1278 value |= PMC_CNTRL_MAIN_RST; 1279 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1280 } 1281 1282 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1283 { 1284 struct tegra_pmc *pmc = data->cb_data; 1285 1286 tegra_pmc_restart(pmc); 1287 1288 return NOTIFY_DONE; 1289 } 1290 1291 static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1292 { 1293 struct tegra_pmc *pmc = data->cb_data; 1294 1295 /* 1296 * Reboot Nexus 7 into special bootloader mode if USB cable is 1297 * connected in order to display battery status and power off. 1298 */ 1299 if (of_machine_is_compatible("asus,grouper") && 1300 power_supply_is_system_supplied()) { 1301 const u32 go_to_charger_mode = 0xa5a55a5a; 1302 1303 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1304 tegra_pmc_restart(pmc); 1305 } 1306 1307 return NOTIFY_DONE; 1308 } 1309 1310 static int powergate_show(struct seq_file *s, void *data) 1311 { 1312 struct tegra_pmc *pmc = data; 1313 unsigned int i; 1314 int status; 1315 1316 seq_printf(s, " powergate powered\n"); 1317 seq_printf(s, "------------------\n"); 1318 1319 for (i = 0; i < pmc->soc->num_powergates; i++) { 1320 status = tegra_powergate_is_powered(pmc, i); 1321 if (status < 0) 1322 continue; 1323 1324 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1325 str_yes_no(status)); 1326 } 1327 1328 return 0; 1329 } 1330 1331 DEFINE_SHOW_ATTRIBUTE(powergate); 1332 1333 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1334 struct device_node *np) 1335 { 1336 struct clk *clk; 1337 unsigned int i, count; 1338 int err; 1339 1340 count = of_clk_get_parent_count(np); 1341 if (count == 0) 1342 return -ENODEV; 1343 1344 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1345 if (!pg->clks) 1346 return -ENOMEM; 1347 1348 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1349 if (!pg->clk_rates) { 1350 kfree(pg->clks); 1351 return -ENOMEM; 1352 } 1353 1354 for (i = 0; i < count; i++) { 1355 pg->clks[i] = of_clk_get(np, i); 1356 if (IS_ERR(pg->clks[i])) { 1357 err = PTR_ERR(pg->clks[i]); 1358 goto err; 1359 } 1360 } 1361 1362 pg->num_clks = count; 1363 1364 return 0; 1365 1366 err: 1367 while (i--) 1368 clk_put(pg->clks[i]); 1369 1370 kfree(pg->clk_rates); 1371 kfree(pg->clks); 1372 1373 return err; 1374 } 1375 1376 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1377 struct device_node *np) 1378 { 1379 struct device *dev = pg->pmc->dev; 1380 int err; 1381 1382 pg->reset = of_reset_control_array_get_exclusive_released(np); 1383 if (IS_ERR(pg->reset)) { 1384 err = PTR_ERR(pg->reset); 1385 dev_err(dev, "failed to get device resets: %d\n", err); 1386 return err; 1387 } 1388 1389 err = reset_control_acquire(pg->reset); 1390 if (err < 0) { 1391 pr_err("failed to acquire resets: %d\n", err); 1392 reset_control_put(pg->reset); 1393 } 1394 1395 return err; 1396 } 1397 1398 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1399 { 1400 struct device *dev = pmc->dev; 1401 struct tegra_powergate *pg; 1402 int id, err = 0; 1403 bool off; 1404 1405 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1406 if (!pg) 1407 return -ENOMEM; 1408 1409 id = tegra_powergate_lookup(pmc, np->name); 1410 if (id < 0) { 1411 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1412 err = -ENODEV; 1413 goto free_mem; 1414 } 1415 1416 /* 1417 * Clear the bit for this powergate so it cannot be managed 1418 * directly via the legacy APIs for controlling powergates. 1419 */ 1420 clear_bit(id, pmc->powergates_available); 1421 1422 pg->id = id; 1423 pg->genpd.name = np->name; 1424 pg->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1425 pg->genpd.power_off = tegra_genpd_power_off; 1426 pg->genpd.power_on = tegra_genpd_power_on; 1427 pg->pmc = pmc; 1428 1429 off = !tegra_powergate_is_powered(pmc, pg->id); 1430 1431 err = tegra_powergate_of_get_clks(pg, np); 1432 if (err < 0) { 1433 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1434 goto set_available; 1435 } 1436 1437 err = tegra_powergate_of_get_resets(pg, np); 1438 if (err < 0) { 1439 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1440 goto remove_clks; 1441 } 1442 1443 /* 1444 * If the power-domain is off, then ensure the resets are asserted. 1445 * If the power-domain is on, then power down to ensure that when is 1446 * it turned on the power-domain, clocks and resets are all in the 1447 * expected state. 1448 */ 1449 if (off) { 1450 err = reset_control_assert(pg->reset); 1451 if (err) { 1452 pr_err("failed to assert resets: %d\n", err); 1453 goto remove_resets; 1454 } 1455 } else { 1456 err = tegra_powergate_power_down(pg); 1457 if (err) { 1458 dev_err(dev, "failed to turn off PM domain %s: %d\n", 1459 pg->genpd.name, err); 1460 goto remove_resets; 1461 } 1462 } 1463 1464 /* 1465 * If PM_GENERIC_DOMAINS is not enabled, power-on 1466 * the domain and skip the genpd registration. 1467 */ 1468 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1469 WARN_ON(tegra_powergate_power_up(pg, true)); 1470 goto remove_resets; 1471 } 1472 1473 err = pm_genpd_init(&pg->genpd, NULL, true); 1474 if (err < 0) { 1475 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1476 err); 1477 goto remove_resets; 1478 } 1479 1480 err = of_genpd_add_provider_simple(np, &pg->genpd); 1481 if (err < 0) { 1482 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1483 np, err); 1484 goto remove_genpd; 1485 } 1486 1487 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1488 1489 return 0; 1490 1491 remove_genpd: 1492 pm_genpd_remove(&pg->genpd); 1493 1494 remove_resets: 1495 reset_control_put(pg->reset); 1496 1497 remove_clks: 1498 while (pg->num_clks--) 1499 clk_put(pg->clks[pg->num_clks]); 1500 1501 kfree(pg->clks); 1502 1503 set_available: 1504 set_bit(id, pmc->powergates_available); 1505 1506 free_mem: 1507 kfree(pg); 1508 1509 return err; 1510 } 1511 1512 bool tegra_pmc_core_domain_state_synced(void) 1513 { 1514 return pmc->core_domain_state_synced; 1515 } 1516 1517 static int 1518 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1519 unsigned int level) 1520 { 1521 struct tegra_pmc_core_pd *pd = to_core_pd(genpd); 1522 struct tegra_pmc *pmc = pd->pmc; 1523 struct dev_pm_opp *opp; 1524 int err; 1525 1526 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1527 if (IS_ERR(opp)) { 1528 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1529 level, opp); 1530 return PTR_ERR(opp); 1531 } 1532 1533 mutex_lock(&pmc->powergates_lock); 1534 err = dev_pm_opp_set_opp(pmc->dev, opp); 1535 mutex_unlock(&pmc->powergates_lock); 1536 1537 dev_pm_opp_put(opp); 1538 1539 if (err) { 1540 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1541 level, err); 1542 return err; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1549 { 1550 const char *rname[] = { "core", NULL}; 1551 struct tegra_pmc_core_pd *pd; 1552 int err; 1553 1554 pd = devm_kzalloc(pmc->dev, sizeof(*pd), GFP_KERNEL); 1555 if (!pd) 1556 return -ENOMEM; 1557 1558 pd->genpd.name = "core"; 1559 pd->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1560 pd->genpd.set_performance_state = tegra_pmc_core_pd_set_performance_state; 1561 pd->pmc = pmc; 1562 1563 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1564 if (err) 1565 return dev_err_probe(pmc->dev, err, 1566 "failed to set core OPP regulator\n"); 1567 1568 err = pm_genpd_init(&pd->genpd, NULL, false); 1569 if (err) { 1570 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1571 return err; 1572 } 1573 1574 err = of_genpd_add_provider_simple(np, &pd->genpd); 1575 if (err) { 1576 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1577 goto remove_genpd; 1578 } 1579 1580 return 0; 1581 1582 remove_genpd: 1583 pm_genpd_remove(&pd->genpd); 1584 1585 return err; 1586 } 1587 1588 static int tegra_powergate_init(struct tegra_pmc *pmc, 1589 struct device_node *parent) 1590 { 1591 struct of_phandle_args child_args, parent_args; 1592 struct device_node *np; 1593 int err = 0; 1594 1595 /* 1596 * Core power domain is the parent of powergate domains, hence it 1597 * should be registered first. 1598 */ 1599 np = of_get_child_by_name(parent, "core-domain"); 1600 if (np) { 1601 err = tegra_pmc_core_pd_add(pmc, np); 1602 of_node_put(np); 1603 if (err) 1604 return err; 1605 } 1606 1607 np = of_get_child_by_name(parent, "powergates"); 1608 if (!np) 1609 return 0; 1610 1611 for_each_child_of_node_scoped(np, child) { 1612 err = tegra_powergate_add(pmc, child); 1613 if (err < 0) 1614 break; 1615 1616 if (of_parse_phandle_with_args(child, "power-domains", 1617 "#power-domain-cells", 1618 0, &parent_args)) 1619 continue; 1620 1621 child_args.np = child; 1622 child_args.args_count = 0; 1623 1624 err = of_genpd_add_subdomain(&parent_args, &child_args); 1625 of_node_put(parent_args.np); 1626 if (err) 1627 break; 1628 } 1629 1630 of_node_put(np); 1631 1632 return err; 1633 } 1634 1635 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1636 { 1637 struct tegra_powergate *pg = to_powergate(genpd); 1638 1639 reset_control_put(pg->reset); 1640 1641 while (pg->num_clks--) 1642 clk_put(pg->clks[pg->num_clks]); 1643 1644 kfree(pg->clks); 1645 1646 set_bit(pg->id, pg->pmc->powergates_available); 1647 1648 kfree(pg); 1649 } 1650 1651 static void tegra_powergate_remove_all(struct device_node *parent) 1652 { 1653 struct generic_pm_domain *genpd; 1654 struct device_node *np, *child; 1655 1656 np = of_get_child_by_name(parent, "powergates"); 1657 if (!np) 1658 return; 1659 1660 for_each_child_of_node(np, child) { 1661 of_genpd_del_provider(child); 1662 1663 genpd = of_genpd_remove_last(child); 1664 if (IS_ERR(genpd)) 1665 continue; 1666 1667 tegra_powergate_remove(genpd); 1668 } 1669 1670 of_node_put(np); 1671 1672 np = of_get_child_by_name(parent, "core-domain"); 1673 if (np) { 1674 of_genpd_del_provider(np); 1675 of_genpd_remove_last(np); 1676 } 1677 } 1678 1679 static const struct tegra_io_pad_soc * 1680 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1681 { 1682 unsigned int i; 1683 1684 for (i = 0; i < pmc->soc->num_io_pads; i++) 1685 if (pmc->soc->io_pads[i].id == id) 1686 return &pmc->soc->io_pads[i]; 1687 1688 return NULL; 1689 } 1690 1691 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1692 const struct tegra_io_pad_soc *pad, 1693 unsigned long *request, 1694 unsigned long *status, 1695 u32 *mask) 1696 { 1697 unsigned long rate, value; 1698 1699 if (pad->dpd == UINT_MAX) 1700 return -EINVAL; 1701 1702 *request = pad->request; 1703 *status = pad->status; 1704 *mask = BIT(pad->dpd); 1705 1706 if (pmc->clk) { 1707 rate = pmc->rate; 1708 if (!rate) { 1709 dev_err(pmc->dev, "failed to get clock rate\n"); 1710 return -ENODEV; 1711 } 1712 1713 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1714 1715 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1716 value = DIV_ROUND_UP(1000000000, rate); 1717 value = DIV_ROUND_UP(200, value); 1718 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1719 } 1720 1721 return 0; 1722 } 1723 1724 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1725 u32 mask, u32 val, unsigned long timeout) 1726 { 1727 u32 value; 1728 1729 timeout = jiffies + msecs_to_jiffies(timeout); 1730 1731 while (time_after(timeout, jiffies)) { 1732 value = tegra_pmc_readl(pmc, offset); 1733 if ((value & mask) == val) 1734 return 0; 1735 1736 usleep_range(250, 1000); 1737 } 1738 1739 return -ETIMEDOUT; 1740 } 1741 1742 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1743 { 1744 if (pmc->clk) 1745 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1746 } 1747 1748 /** 1749 * tegra_io_pad_power_enable() - enable power to I/O pad 1750 * @pmc: power management controller 1751 * @id: Tegra I/O pad ID for which to enable power 1752 * 1753 * Returns: 0 on success or a negative error code on failure. 1754 */ 1755 int tegra_pmc_io_pad_power_enable(struct tegra_pmc *pmc, enum tegra_io_pad id) 1756 { 1757 const struct tegra_io_pad_soc *pad; 1758 unsigned long request, status; 1759 u32 mask; 1760 int err; 1761 1762 pad = tegra_io_pad_find(pmc, id); 1763 if (!pad) { 1764 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1765 return -ENOENT; 1766 } 1767 1768 mutex_lock(&pmc->powergates_lock); 1769 1770 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1771 if (err < 0) { 1772 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1773 goto unlock; 1774 } 1775 1776 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1777 1778 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1779 if (err < 0) { 1780 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1781 goto unlock; 1782 } 1783 1784 tegra_io_pad_unprepare(pmc); 1785 1786 unlock: 1787 mutex_unlock(&pmc->powergates_lock); 1788 return err; 1789 } 1790 EXPORT_SYMBOL(tegra_pmc_io_pad_power_enable); 1791 1792 /** 1793 * tegra_io_pad_power_enable() - enable power to I/O pad 1794 * @id: Tegra I/O pad ID for which to enable power 1795 * 1796 * Returns: 0 on success or a negative error code on failure. 1797 */ 1798 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1799 { 1800 return tegra_pmc_io_pad_power_enable(pmc, id); 1801 } 1802 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1803 1804 /** 1805 * tegra_pmc_io_pad_power_disable() - disable power to I/O pad 1806 * @pmc: power management controller 1807 * @id: Tegra I/O pad ID for which to disable power 1808 * 1809 * Returns: 0 on success or a negative error code on failure. 1810 */ 1811 int tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id) 1812 { 1813 const struct tegra_io_pad_soc *pad; 1814 unsigned long request, status; 1815 u32 mask; 1816 int err; 1817 1818 pad = tegra_io_pad_find(pmc, id); 1819 if (!pad) { 1820 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1821 return -ENOENT; 1822 } 1823 1824 mutex_lock(&pmc->powergates_lock); 1825 1826 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1827 if (err < 0) { 1828 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1829 goto unlock; 1830 } 1831 1832 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1833 1834 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1835 if (err < 0) { 1836 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1837 goto unlock; 1838 } 1839 1840 tegra_io_pad_unprepare(pmc); 1841 1842 unlock: 1843 mutex_unlock(&pmc->powergates_lock); 1844 return err; 1845 } 1846 EXPORT_SYMBOL(tegra_pmc_io_pad_power_disable); 1847 1848 /** 1849 * tegra_io_pad_power_disable() - disable power to I/O pad 1850 * @id: Tegra I/O pad ID for which to disable power 1851 * 1852 * Returns: 0 on success or a negative error code on failure. 1853 */ 1854 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1855 { 1856 return tegra_pmc_io_pad_power_disable(pmc, id); 1857 } 1858 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1859 1860 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1861 { 1862 const struct tegra_io_pad_soc *pad; 1863 unsigned long status; 1864 u32 mask, value; 1865 1866 pad = tegra_io_pad_find(pmc, id); 1867 if (!pad) { 1868 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1869 return -ENOENT; 1870 } 1871 1872 if (pad->dpd == UINT_MAX) 1873 return -EINVAL; 1874 1875 status = pad->status; 1876 mask = BIT(pad->dpd); 1877 1878 value = tegra_pmc_readl(pmc, status); 1879 1880 return !(value & mask); 1881 } 1882 1883 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1884 int voltage) 1885 { 1886 const struct tegra_io_pad_soc *pad; 1887 u32 value; 1888 1889 pad = tegra_io_pad_find(pmc, id); 1890 if (!pad) 1891 return -ENOENT; 1892 1893 if (pad->voltage == UINT_MAX) 1894 return -ENOTSUPP; 1895 1896 mutex_lock(&pmc->powergates_lock); 1897 1898 if (pmc->soc->has_impl_33v_pwr) { 1899 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1900 1901 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1902 value &= ~BIT(pad->voltage); 1903 else 1904 value |= BIT(pad->voltage); 1905 1906 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1907 } else { 1908 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1909 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1910 value |= BIT(pad->voltage); 1911 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1912 1913 /* update I/O voltage */ 1914 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1915 1916 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1917 value &= ~BIT(pad->voltage); 1918 else 1919 value |= BIT(pad->voltage); 1920 1921 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1922 } 1923 1924 mutex_unlock(&pmc->powergates_lock); 1925 1926 usleep_range(100, 250); 1927 1928 return 0; 1929 } 1930 1931 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1932 { 1933 const struct tegra_io_pad_soc *pad; 1934 u32 value; 1935 1936 pad = tegra_io_pad_find(pmc, id); 1937 if (!pad) 1938 return -ENOENT; 1939 1940 if (pad->voltage == UINT_MAX) 1941 return -ENOTSUPP; 1942 1943 if (pmc->soc->has_impl_33v_pwr) 1944 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1945 else 1946 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1947 1948 if ((value & BIT(pad->voltage)) == 0) 1949 return TEGRA_IO_PAD_VOLTAGE_1V8; 1950 1951 return TEGRA_IO_PAD_VOLTAGE_3V3; 1952 } 1953 1954 #ifdef CONFIG_PM_SLEEP 1955 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1956 { 1957 return pmc->suspend_mode; 1958 } 1959 1960 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1961 { 1962 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1963 return; 1964 1965 pmc->suspend_mode = mode; 1966 } 1967 1968 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1969 { 1970 unsigned long long rate = 0; 1971 u64 ticks; 1972 u32 value; 1973 1974 switch (mode) { 1975 case TEGRA_SUSPEND_LP1: 1976 rate = 32768; 1977 break; 1978 1979 case TEGRA_SUSPEND_LP2: 1980 rate = pmc->rate; 1981 break; 1982 1983 default: 1984 break; 1985 } 1986 1987 if (WARN_ON_ONCE(rate == 0)) 1988 rate = 100000000; 1989 1990 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1991 do_div(ticks, USEC_PER_SEC); 1992 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1993 1994 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1995 do_div(ticks, USEC_PER_SEC); 1996 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1997 1998 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1999 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 2000 value |= PMC_CNTRL_CPU_PWRREQ_OE; 2001 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2002 } 2003 #endif 2004 2005 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 2006 { 2007 u32 value, values[2]; 2008 2009 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 2010 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2011 } else { 2012 switch (value) { 2013 case 0: 2014 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 2015 break; 2016 2017 case 1: 2018 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 2019 break; 2020 2021 case 2: 2022 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 2023 break; 2024 2025 default: 2026 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2027 break; 2028 } 2029 } 2030 2031 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 2032 2033 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 2034 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2035 2036 pmc->cpu_good_time = value; 2037 2038 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 2039 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2040 2041 pmc->cpu_off_time = value; 2042 2043 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 2044 values, ARRAY_SIZE(values))) 2045 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2046 2047 pmc->core_osc_time = values[0]; 2048 pmc->core_pmu_time = values[1]; 2049 2050 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 2051 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2052 2053 pmc->core_off_time = value; 2054 2055 pmc->corereq_high = of_property_read_bool(np, 2056 "nvidia,core-power-req-active-high"); 2057 2058 pmc->sysclkreq_high = of_property_read_bool(np, 2059 "nvidia,sys-clock-req-active-high"); 2060 2061 pmc->combined_req = of_property_read_bool(np, 2062 "nvidia,combined-power-req"); 2063 2064 pmc->cpu_pwr_good_en = of_property_read_bool(np, 2065 "nvidia,cpu-pwr-good-en"); 2066 2067 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 2068 ARRAY_SIZE(values))) 2069 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 2070 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 2071 2072 pmc->lp0_vec_phys = values[0]; 2073 pmc->lp0_vec_size = values[1]; 2074 2075 return 0; 2076 } 2077 2078 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 2079 static void tegra186_pmc_wake_handler(struct irq_work *work) 2080 { 2081 struct tegra_pmc *pmc = container_of(work, struct tegra_pmc, wake_work); 2082 unsigned int i, wake; 2083 2084 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 2085 unsigned long status = pmc->wake_status[i]; 2086 2087 for_each_set_bit(wake, &status, 32) { 2088 irq_hw_number_t hwirq = wake + (i * 32); 2089 struct irq_desc *desc; 2090 unsigned int irq; 2091 2092 irq = irq_find_mapping(pmc->domain, hwirq); 2093 if (!irq) { 2094 dev_warn(pmc->dev, 2095 "No IRQ found for WAKE#%lu!\n", 2096 hwirq); 2097 continue; 2098 } 2099 2100 dev_dbg(pmc->dev, 2101 "Resume caused by WAKE#%lu mapped to IRQ#%u\n", 2102 hwirq, irq); 2103 2104 desc = irq_to_desc(irq); 2105 if (!desc) { 2106 dev_warn(pmc->dev, 2107 "No descriptor found for IRQ#%u\n", 2108 irq); 2109 continue; 2110 } 2111 2112 if (!desc->action || !desc->action->name) 2113 continue; 2114 2115 generic_handle_irq(irq); 2116 } 2117 2118 pmc->wake_status[i] = 0; 2119 } 2120 } 2121 2122 static int tegra_pmc_init(struct tegra_pmc *pmc) 2123 { 2124 if (pmc->soc->max_wake_events > 0) { 2125 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2126 if (!pmc->wake_type_level_map) 2127 return -ENOMEM; 2128 2129 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2130 if (!pmc->wake_type_dual_edge_map) 2131 return -ENOMEM; 2132 2133 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2134 if (!pmc->wake_sw_status_map) 2135 return -ENOMEM; 2136 2137 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2138 if (!pmc->wake_cntrl_level_map) 2139 return -ENOMEM; 2140 2141 pmc->wake_status = kcalloc(pmc->soc->max_wake_vectors, sizeof(u32), GFP_KERNEL); 2142 if (!pmc->wake_status) 2143 return -ENOMEM; 2144 2145 /* 2146 * Initialize IRQ work for processing wake IRQs. Must use 2147 * HARD_IRQ variant to run in hard IRQ context on PREEMPT_RT 2148 * because we call generic_handle_irq() which requires hard 2149 * IRQ context. 2150 */ 2151 pmc->wake_work = IRQ_WORK_INIT_HARD(tegra186_pmc_wake_handler); 2152 } 2153 2154 if (pmc->soc->init) 2155 pmc->soc->init(pmc); 2156 2157 return 0; 2158 } 2159 2160 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 2161 { 2162 static const char disabled[] = "emergency thermal reset disabled"; 2163 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 2164 struct device *dev = pmc->dev; 2165 struct device_node *np; 2166 u32 value, checksum; 2167 2168 if (!pmc->soc->has_tsense_reset) 2169 return; 2170 2171 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 2172 if (!np) { 2173 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 2174 return; 2175 } 2176 2177 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 2178 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 2179 goto out; 2180 } 2181 2182 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 2183 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 2184 goto out; 2185 } 2186 2187 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 2188 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 2189 goto out; 2190 } 2191 2192 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 2193 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 2194 goto out; 2195 } 2196 2197 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 2198 pinmux = 0; 2199 2200 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2201 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 2202 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2203 2204 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 2205 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 2206 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 2207 2208 value = PMC_SCRATCH55_RESET_TEGRA; 2209 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 2210 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 2211 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 2212 2213 /* 2214 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 2215 * contain the checksum and are currently zero, so they are not added. 2216 */ 2217 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 2218 + ((value >> 24) & 0xff); 2219 checksum &= 0xff; 2220 checksum = 0x100 - checksum; 2221 2222 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 2223 2224 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 2225 2226 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2227 value |= PMC_SENSOR_CTRL_ENABLE_RST; 2228 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2229 2230 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 2231 2232 out: 2233 of_node_put(np); 2234 } 2235 2236 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2237 { 2238 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2239 2240 return pmc->soc->num_io_pads; 2241 } 2242 2243 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2244 unsigned int group) 2245 { 2246 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2247 2248 return pmc->soc->io_pads[group].name; 2249 } 2250 2251 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2252 unsigned int group, 2253 const unsigned int **pins, 2254 unsigned int *num_pins) 2255 { 2256 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2257 2258 *pins = &pmc->soc->io_pads[group].id; 2259 *num_pins = 1; 2260 2261 return 0; 2262 } 2263 2264 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2265 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2266 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2267 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2268 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2269 .dt_free_map = pinconf_generic_dt_free_map, 2270 }; 2271 2272 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2273 unsigned int pin, unsigned long *config) 2274 { 2275 enum pin_config_param param = pinconf_to_config_param(*config); 2276 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2277 const struct tegra_io_pad_soc *pad; 2278 int ret; 2279 u32 arg; 2280 2281 pad = tegra_io_pad_find(pmc, pin); 2282 if (!pad) 2283 return -EINVAL; 2284 2285 switch (param) { 2286 case PIN_CONFIG_POWER_SOURCE: 2287 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2288 if (ret < 0) 2289 return ret; 2290 2291 arg = ret; 2292 break; 2293 2294 case PIN_CONFIG_MODE_LOW_POWER: 2295 ret = tegra_io_pad_is_powered(pmc, pad->id); 2296 if (ret < 0) 2297 return ret; 2298 2299 arg = !ret; 2300 break; 2301 2302 default: 2303 return -EINVAL; 2304 } 2305 2306 *config = pinconf_to_config_packed(param, arg); 2307 2308 return 0; 2309 } 2310 2311 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2312 unsigned int pin, unsigned long *configs, 2313 unsigned int num_configs) 2314 { 2315 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2316 const struct tegra_io_pad_soc *pad; 2317 enum pin_config_param param; 2318 unsigned int i; 2319 int err; 2320 u32 arg; 2321 2322 pad = tegra_io_pad_find(pmc, pin); 2323 if (!pad) 2324 return -EINVAL; 2325 2326 for (i = 0; i < num_configs; ++i) { 2327 param = pinconf_to_config_param(configs[i]); 2328 arg = pinconf_to_config_argument(configs[i]); 2329 2330 switch (param) { 2331 case PIN_CONFIG_MODE_LOW_POWER: 2332 if (arg) 2333 err = tegra_pmc_io_pad_power_disable(pmc, pad->id); 2334 else 2335 err = tegra_pmc_io_pad_power_enable(pmc, pad->id); 2336 if (err) 2337 return err; 2338 break; 2339 case PIN_CONFIG_POWER_SOURCE: 2340 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2341 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2342 return -EINVAL; 2343 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2344 if (err) 2345 return err; 2346 break; 2347 default: 2348 return -EINVAL; 2349 } 2350 } 2351 2352 return 0; 2353 } 2354 2355 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2356 .pin_config_get = tegra_io_pad_pinconf_get, 2357 .pin_config_set = tegra_io_pad_pinconf_set, 2358 .is_generic = true, 2359 }; 2360 2361 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2362 .pctlops = &tegra_io_pad_pinctrl_ops, 2363 .confops = &tegra_io_pad_pinconf_ops, 2364 }; 2365 2366 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2367 { 2368 int err; 2369 2370 if (!pmc->soc->num_pin_descs) 2371 return 0; 2372 2373 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2374 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2375 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2376 2377 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2378 pmc); 2379 if (IS_ERR(pmc->pctl_dev)) { 2380 err = PTR_ERR(pmc->pctl_dev); 2381 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2382 err); 2383 return err; 2384 } 2385 2386 return 0; 2387 } 2388 2389 static ssize_t reset_reason_show(struct device *dev, 2390 struct device_attribute *attr, char *buf) 2391 { 2392 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2393 u32 value; 2394 2395 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2396 value &= pmc->soc->regs->rst_source_mask; 2397 value >>= pmc->soc->regs->rst_source_shift; 2398 2399 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2400 return sprintf(buf, "%s\n", "UNKNOWN"); 2401 2402 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2403 } 2404 2405 static DEVICE_ATTR_RO(reset_reason); 2406 2407 static ssize_t reset_level_show(struct device *dev, 2408 struct device_attribute *attr, char *buf) 2409 { 2410 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2411 u32 value; 2412 2413 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2414 value &= pmc->soc->regs->rst_level_mask; 2415 value >>= pmc->soc->regs->rst_level_shift; 2416 2417 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2418 return sprintf(buf, "%s\n", "UNKNOWN"); 2419 2420 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2421 } 2422 2423 static DEVICE_ATTR_RO(reset_level); 2424 2425 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2426 { 2427 struct device *dev = pmc->dev; 2428 int err = 0; 2429 2430 if (pmc->soc->reset_sources) { 2431 err = device_create_file(dev, &dev_attr_reset_reason); 2432 if (err < 0) 2433 dev_warn(dev, 2434 "failed to create attr \"reset_reason\": %d\n", 2435 err); 2436 } 2437 2438 if (pmc->soc->reset_levels) { 2439 err = device_create_file(dev, &dev_attr_reset_level); 2440 if (err < 0) 2441 dev_warn(dev, 2442 "failed to create attr \"reset_level\": %d\n", 2443 err); 2444 } 2445 } 2446 2447 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2448 struct irq_fwspec *fwspec, 2449 unsigned long *hwirq, 2450 unsigned int *type) 2451 { 2452 if (WARN_ON(fwspec->param_count < 2)) 2453 return -EINVAL; 2454 2455 *hwirq = fwspec->param[0]; 2456 *type = fwspec->param[1]; 2457 2458 return 0; 2459 } 2460 2461 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2462 unsigned int num_irqs, void *data) 2463 { 2464 struct tegra_pmc *pmc = domain->host_data; 2465 const struct tegra_pmc_soc *soc = pmc->soc; 2466 struct irq_fwspec *fwspec = data; 2467 unsigned int i; 2468 int err = 0; 2469 2470 if (WARN_ON(num_irqs > 1)) 2471 return -EINVAL; 2472 2473 for (i = 0; i < soc->num_wake_events; i++) { 2474 const struct tegra_wake_event *event = &soc->wake_events[i]; 2475 2476 /* IRQ and simple wake events */ 2477 if (fwspec->param_count == 2) { 2478 struct irq_fwspec spec; 2479 2480 if (event->id != fwspec->param[0]) 2481 continue; 2482 2483 err = irq_domain_set_hwirq_and_chip(domain, virq, 2484 event->id, 2485 &pmc->irq, pmc); 2486 if (err < 0) 2487 break; 2488 2489 /* simple hierarchies stop at the PMC level */ 2490 if (event->irq == 0) { 2491 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2492 break; 2493 } 2494 2495 spec.fwnode = &pmc->dev->of_node->fwnode; 2496 spec.param_count = 3; 2497 spec.param[0] = GIC_SPI; 2498 spec.param[1] = event->irq; 2499 spec.param[2] = fwspec->param[1]; 2500 2501 err = irq_domain_alloc_irqs_parent(domain, virq, 2502 num_irqs, &spec); 2503 2504 break; 2505 } 2506 2507 /* GPIO wake events */ 2508 if (fwspec->param_count == 3) { 2509 if (event->gpio.instance != fwspec->param[0] || 2510 event->gpio.pin != fwspec->param[1]) 2511 continue; 2512 2513 err = irq_domain_set_hwirq_and_chip(domain, virq, 2514 event->id, 2515 &pmc->irq, pmc); 2516 2517 /* GPIO hierarchies stop at the PMC level */ 2518 if (!err && domain->parent) 2519 err = irq_domain_disconnect_hierarchy(domain->parent, 2520 virq); 2521 break; 2522 } 2523 } 2524 2525 /* If there is no wake-up event, there is no PMC mapping */ 2526 if (i == soc->num_wake_events) 2527 err = irq_domain_disconnect_hierarchy(domain, virq); 2528 2529 return err; 2530 } 2531 2532 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2533 .translate = tegra_pmc_irq_translate, 2534 .alloc = tegra_pmc_irq_alloc, 2535 }; 2536 2537 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2538 { 2539 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2540 unsigned int offset, bit; 2541 u32 value; 2542 2543 offset = data->hwirq / 32; 2544 bit = data->hwirq % 32; 2545 2546 /* clear wake status */ 2547 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2548 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2549 2550 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2551 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2552 2553 /* enable PMC wake */ 2554 if (data->hwirq >= 32) 2555 offset = PMC_WAKE2_MASK; 2556 else 2557 offset = PMC_WAKE_MASK; 2558 2559 value = tegra_pmc_readl(pmc, offset); 2560 2561 if (on) 2562 value |= BIT(bit); 2563 else 2564 value &= ~BIT(bit); 2565 2566 tegra_pmc_writel(pmc, value, offset); 2567 2568 return 0; 2569 } 2570 2571 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2572 { 2573 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2574 unsigned int offset, bit; 2575 u32 value; 2576 2577 offset = data->hwirq / 32; 2578 bit = data->hwirq % 32; 2579 2580 if (data->hwirq >= 32) 2581 offset = PMC_WAKE2_LEVEL; 2582 else 2583 offset = PMC_WAKE_LEVEL; 2584 2585 value = tegra_pmc_readl(pmc, offset); 2586 2587 switch (type) { 2588 case IRQ_TYPE_EDGE_RISING: 2589 case IRQ_TYPE_LEVEL_HIGH: 2590 value |= BIT(bit); 2591 break; 2592 2593 case IRQ_TYPE_EDGE_FALLING: 2594 case IRQ_TYPE_LEVEL_LOW: 2595 value &= ~BIT(bit); 2596 break; 2597 2598 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2599 value ^= BIT(bit); 2600 break; 2601 2602 default: 2603 return -EINVAL; 2604 } 2605 2606 tegra_pmc_writel(pmc, value, offset); 2607 2608 return 0; 2609 } 2610 2611 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2612 { 2613 u32 value; 2614 2615 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2616 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2617 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2618 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2619 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2620 } 2621 2622 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2623 { 2624 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2625 unsigned int offset, bit; 2626 u32 value; 2627 2628 offset = data->hwirq / 32; 2629 bit = data->hwirq % 32; 2630 2631 /* clear wake status */ 2632 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2633 2634 /* route wake to tier 2 */ 2635 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2636 2637 if (!on) 2638 value &= ~(1 << bit); 2639 else 2640 value |= 1 << bit; 2641 2642 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2643 2644 /* enable wakeup event */ 2645 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2646 2647 return 0; 2648 } 2649 2650 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2651 { 2652 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2653 u32 value; 2654 2655 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2656 2657 switch (type) { 2658 case IRQ_TYPE_EDGE_RISING: 2659 case IRQ_TYPE_LEVEL_HIGH: 2660 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2661 set_bit(data->hwirq, pmc->wake_type_level_map); 2662 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2663 break; 2664 2665 case IRQ_TYPE_EDGE_FALLING: 2666 case IRQ_TYPE_LEVEL_LOW: 2667 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2668 clear_bit(data->hwirq, pmc->wake_type_level_map); 2669 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2670 break; 2671 2672 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2673 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2674 clear_bit(data->hwirq, pmc->wake_type_level_map); 2675 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2676 break; 2677 2678 default: 2679 return -EINVAL; 2680 } 2681 2682 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2683 2684 return 0; 2685 } 2686 2687 static void tegra_irq_mask_parent(struct irq_data *data) 2688 { 2689 if (data->parent_data) 2690 irq_chip_mask_parent(data); 2691 } 2692 2693 static void tegra_irq_unmask_parent(struct irq_data *data) 2694 { 2695 if (data->parent_data) 2696 irq_chip_unmask_parent(data); 2697 } 2698 2699 static void tegra_irq_eoi_parent(struct irq_data *data) 2700 { 2701 if (data->parent_data) 2702 irq_chip_eoi_parent(data); 2703 } 2704 2705 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2706 const struct cpumask *dest, 2707 bool force) 2708 { 2709 if (data->parent_data) 2710 return irq_chip_set_affinity_parent(data, dest, force); 2711 2712 return -EINVAL; 2713 } 2714 2715 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2716 { 2717 struct irq_domain *parent = NULL; 2718 struct device_node *np; 2719 2720 np = of_irq_find_parent(pmc->dev->of_node); 2721 if (np) { 2722 parent = irq_find_host(np); 2723 of_node_put(np); 2724 } 2725 2726 if (!parent) 2727 return 0; 2728 2729 pmc->irq.name = dev_name(pmc->dev); 2730 pmc->irq.irq_mask = tegra_irq_mask_parent; 2731 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2732 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2733 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2734 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2735 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2736 2737 pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, dev_fwnode(pmc->dev), 2738 &tegra_pmc_irq_domain_ops, pmc); 2739 if (!pmc->domain) { 2740 dev_err(pmc->dev, "failed to allocate domain\n"); 2741 return -ENOMEM; 2742 } 2743 2744 return 0; 2745 } 2746 2747 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2748 unsigned long action, void *ptr) 2749 { 2750 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2751 struct clk_notifier_data *data = ptr; 2752 2753 switch (action) { 2754 case PRE_RATE_CHANGE: 2755 mutex_lock(&pmc->powergates_lock); 2756 break; 2757 2758 case POST_RATE_CHANGE: 2759 pmc->rate = data->new_rate; 2760 fallthrough; 2761 2762 case ABORT_RATE_CHANGE: 2763 mutex_unlock(&pmc->powergates_lock); 2764 break; 2765 2766 default: 2767 WARN_ON_ONCE(1); 2768 return notifier_from_errno(-EINVAL); 2769 } 2770 2771 return NOTIFY_OK; 2772 } 2773 2774 static void pmc_clk_fence_udelay(struct tegra_pmc *pmc, u32 offset) 2775 { 2776 tegra_pmc_readl(pmc, offset); 2777 /* pmc clk propagation delay 2 us */ 2778 udelay(2); 2779 } 2780 2781 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2782 { 2783 struct pmc_clk *clk = to_pmc_clk(hw); 2784 u32 val; 2785 2786 val = tegra_pmc_readl(clk->pmc, clk->offs) >> clk->mux_shift; 2787 val &= PMC_CLK_OUT_MUX_MASK; 2788 2789 return val; 2790 } 2791 2792 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2793 { 2794 struct pmc_clk *clk = to_pmc_clk(hw); 2795 u32 val; 2796 2797 val = tegra_pmc_readl(clk->pmc, clk->offs); 2798 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2799 val |= index << clk->mux_shift; 2800 tegra_pmc_writel(clk->pmc, val, clk->offs); 2801 pmc_clk_fence_udelay(clk->pmc, clk->offs); 2802 2803 return 0; 2804 } 2805 2806 static int pmc_clk_is_enabled(struct clk_hw *hw) 2807 { 2808 struct pmc_clk *clk = to_pmc_clk(hw); 2809 u32 val; 2810 2811 val = tegra_pmc_readl(clk->pmc, clk->offs) & BIT(clk->force_en_shift); 2812 2813 return val ? 1 : 0; 2814 } 2815 2816 static void pmc_clk_set_state(struct tegra_pmc *pmc, unsigned long offs, 2817 u32 shift, int state) 2818 { 2819 u32 val; 2820 2821 val = tegra_pmc_readl(pmc, offs); 2822 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2823 tegra_pmc_writel(pmc, val, offs); 2824 pmc_clk_fence_udelay(pmc, offs); 2825 } 2826 2827 static int pmc_clk_enable(struct clk_hw *hw) 2828 { 2829 struct pmc_clk *clk = to_pmc_clk(hw); 2830 2831 pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 1); 2832 2833 return 0; 2834 } 2835 2836 static void pmc_clk_disable(struct clk_hw *hw) 2837 { 2838 struct pmc_clk *clk = to_pmc_clk(hw); 2839 2840 pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 0); 2841 } 2842 2843 static const struct clk_ops pmc_clk_ops = { 2844 .get_parent = pmc_clk_mux_get_parent, 2845 .set_parent = pmc_clk_mux_set_parent, 2846 .determine_rate = __clk_mux_determine_rate, 2847 .is_enabled = pmc_clk_is_enabled, 2848 .enable = pmc_clk_enable, 2849 .disable = pmc_clk_disable, 2850 }; 2851 2852 static struct clk * 2853 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2854 const struct pmc_clk_init_data *data, 2855 unsigned long offset) 2856 { 2857 struct clk_init_data init; 2858 struct pmc_clk *pmc_clk; 2859 2860 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2861 if (!pmc_clk) 2862 return ERR_PTR(-ENOMEM); 2863 2864 init.name = data->name; 2865 init.ops = &pmc_clk_ops; 2866 init.parent_names = data->parents; 2867 init.num_parents = data->num_parents; 2868 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2869 CLK_SET_PARENT_GATE; 2870 2871 pmc_clk->hw.init = &init; 2872 pmc_clk->pmc = pmc; 2873 pmc_clk->offs = offset; 2874 pmc_clk->mux_shift = data->mux_shift; 2875 pmc_clk->force_en_shift = data->force_en_shift; 2876 2877 return clk_register(NULL, &pmc_clk->hw); 2878 } 2879 2880 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2881 { 2882 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2883 u32 value = tegra_pmc_readl(gate->pmc, gate->offs); 2884 2885 return value & BIT(gate->shift) ? 1 : 0; 2886 } 2887 2888 static int pmc_clk_gate_enable(struct clk_hw *hw) 2889 { 2890 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2891 2892 pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 1); 2893 2894 return 0; 2895 } 2896 2897 static void pmc_clk_gate_disable(struct clk_hw *hw) 2898 { 2899 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2900 2901 pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 0); 2902 } 2903 2904 static const struct clk_ops pmc_clk_gate_ops = { 2905 .is_enabled = pmc_clk_gate_is_enabled, 2906 .enable = pmc_clk_gate_enable, 2907 .disable = pmc_clk_gate_disable, 2908 }; 2909 2910 static struct clk * 2911 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2912 const char *parent_name, unsigned long offset, 2913 u32 shift) 2914 { 2915 struct clk_init_data init; 2916 struct pmc_clk_gate *gate; 2917 2918 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2919 if (!gate) 2920 return ERR_PTR(-ENOMEM); 2921 2922 init.name = name; 2923 init.ops = &pmc_clk_gate_ops; 2924 init.parent_names = &parent_name; 2925 init.num_parents = 1; 2926 init.flags = 0; 2927 2928 gate->hw.init = &init; 2929 gate->pmc = pmc; 2930 gate->offs = offset; 2931 gate->shift = shift; 2932 2933 return clk_register(NULL, &gate->hw); 2934 } 2935 2936 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2937 struct device_node *np) 2938 { 2939 struct clk *clk; 2940 struct clk_onecell_data *clk_data; 2941 unsigned int num_clks; 2942 int i, err; 2943 2944 num_clks = pmc->soc->num_pmc_clks; 2945 if (pmc->soc->has_blink_output) 2946 num_clks += 1; 2947 2948 if (!num_clks) 2949 return; 2950 2951 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2952 if (!clk_data) 2953 return; 2954 2955 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2956 sizeof(*clk_data->clks), GFP_KERNEL); 2957 if (!clk_data->clks) 2958 return; 2959 2960 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2961 2962 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2963 clk_data->clks[i] = ERR_PTR(-ENOENT); 2964 2965 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2966 const struct pmc_clk_init_data *data; 2967 2968 data = pmc->soc->pmc_clks_data + i; 2969 2970 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2971 if (IS_ERR(clk)) { 2972 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2973 data->name, PTR_ERR_OR_ZERO(clk)); 2974 return; 2975 } 2976 2977 err = clk_register_clkdev(clk, data->name, NULL); 2978 if (err) { 2979 dev_warn(pmc->dev, 2980 "unable to register %s clock lookup: %d\n", 2981 data->name, err); 2982 return; 2983 } 2984 2985 clk_data->clks[data->clk_id] = clk; 2986 } 2987 2988 if (pmc->soc->has_blink_output) { 2989 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2990 clk = tegra_pmc_clk_gate_register(pmc, 2991 "pmc_blink_override", 2992 "clk_32k", 2993 PMC_DPD_PADS_ORIDE, 2994 PMC_DPD_PADS_ORIDE_BLINK); 2995 if (IS_ERR(clk)) { 2996 dev_warn(pmc->dev, 2997 "unable to register pmc_blink_override: %d\n", 2998 PTR_ERR_OR_ZERO(clk)); 2999 return; 3000 } 3001 3002 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 3003 "pmc_blink_override", 3004 PMC_CNTRL, 3005 PMC_CNTRL_BLINK_EN); 3006 if (IS_ERR(clk)) { 3007 dev_warn(pmc->dev, 3008 "unable to register pmc_blink: %d\n", 3009 PTR_ERR_OR_ZERO(clk)); 3010 return; 3011 } 3012 3013 err = clk_register_clkdev(clk, "pmc_blink", NULL); 3014 if (err) { 3015 dev_warn(pmc->dev, 3016 "unable to register pmc_blink lookup: %d\n", 3017 err); 3018 return; 3019 } 3020 3021 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 3022 } 3023 3024 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 3025 if (err) 3026 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 3027 err); 3028 } 3029 3030 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 3031 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 3032 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 3033 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 3034 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 3035 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 3036 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 3037 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 3038 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 3039 }; 3040 3041 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 3042 .yes_ranges = pmc_usb_sleepwalk_ranges, 3043 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 3044 }; 3045 3046 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 3047 { 3048 struct tegra_pmc *pmc = context; 3049 3050 *value = tegra_pmc_readl(pmc, offset); 3051 return 0; 3052 } 3053 3054 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 3055 { 3056 struct tegra_pmc *pmc = context; 3057 3058 tegra_pmc_writel(pmc, value, offset); 3059 return 0; 3060 } 3061 3062 static const struct regmap_config usb_sleepwalk_regmap_config = { 3063 .name = "usb_sleepwalk", 3064 .reg_bits = 32, 3065 .val_bits = 32, 3066 .reg_stride = 4, 3067 .fast_io = true, 3068 .rd_table = &pmc_usb_sleepwalk_table, 3069 .wr_table = &pmc_usb_sleepwalk_table, 3070 .reg_read = tegra_pmc_regmap_readl, 3071 .reg_write = tegra_pmc_regmap_writel, 3072 }; 3073 3074 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 3075 { 3076 struct regmap *regmap; 3077 int err; 3078 3079 if (pmc->soc->has_usb_sleepwalk) { 3080 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 3081 if (IS_ERR(regmap)) { 3082 err = PTR_ERR(regmap); 3083 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 3084 return err; 3085 } 3086 } 3087 3088 return 0; 3089 } 3090 3091 static void tegra_pmc_reset_suspend_mode(void *data) 3092 { 3093 struct tegra_pmc *pmc = data; 3094 3095 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 3096 } 3097 3098 static int tegra_pmc_probe(struct platform_device *pdev) 3099 { 3100 void __iomem *base; 3101 struct resource *res; 3102 int err; 3103 3104 /* 3105 * Early initialisation should have configured an initial 3106 * register mapping and setup the soc data pointer. If these 3107 * are not valid then something went badly wrong! 3108 */ 3109 if (WARN_ON(!pmc->base || !pmc->soc)) 3110 return -ENODEV; 3111 3112 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 3113 if (err < 0) 3114 return err; 3115 3116 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 3117 pmc); 3118 if (err) 3119 return err; 3120 3121 /* take over the memory region from the early initialization */ 3122 base = devm_platform_ioremap_resource(pdev, 0); 3123 if (IS_ERR(base)) 3124 return PTR_ERR(base); 3125 3126 if (pmc->soc->has_single_mmio_aperture) { 3127 pmc->wake = base; 3128 pmc->aotag = base; 3129 pmc->scratch = base; 3130 } else { 3131 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); 3132 if (IS_ERR(pmc->wake)) 3133 return PTR_ERR(pmc->wake); 3134 3135 /* "aotag" is an optional aperture */ 3136 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3137 "aotag"); 3138 if (res) { 3139 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 3140 if (IS_ERR(pmc->aotag)) 3141 return PTR_ERR(pmc->aotag); 3142 } else { 3143 pmc->aotag = NULL; 3144 } 3145 3146 /* "scratch" is an optional aperture */ 3147 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3148 "scratch"); 3149 if (res) { 3150 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 3151 if (IS_ERR(pmc->scratch)) 3152 return PTR_ERR(pmc->scratch); 3153 } else { 3154 pmc->scratch = NULL; 3155 } 3156 } 3157 3158 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 3159 if (IS_ERR(pmc->clk)) 3160 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 3161 "failed to get pclk\n"); 3162 3163 /* 3164 * PMC should be last resort for restarting since it soft-resets 3165 * CPU without resetting everything else. 3166 */ 3167 if (pmc->scratch) { 3168 pmc->reboot_notifier.notifier_call = tegra_pmc_reboot_notify; 3169 3170 err = devm_register_reboot_notifier(&pdev->dev, 3171 &pmc->reboot_notifier); 3172 if (err) { 3173 dev_err(&pdev->dev, 3174 "unable to register reboot notifier, %d\n", 3175 err); 3176 return err; 3177 } 3178 } 3179 3180 err = devm_register_sys_off_handler(&pdev->dev, 3181 SYS_OFF_MODE_RESTART, 3182 SYS_OFF_PRIO_LOW, 3183 tegra_pmc_restart_handler, 3184 pmc); 3185 if (err) { 3186 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3187 err); 3188 return err; 3189 } 3190 3191 /* 3192 * PMC should be primary power-off method if it soft-resets CPU, 3193 * asking bootloader to shutdown hardware. 3194 */ 3195 err = devm_register_sys_off_handler(&pdev->dev, 3196 SYS_OFF_MODE_POWER_OFF, 3197 SYS_OFF_PRIO_FIRMWARE, 3198 tegra_pmc_power_off_handler, 3199 pmc); 3200 if (err) { 3201 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3202 err); 3203 return err; 3204 } 3205 3206 /* 3207 * PCLK clock rate can't be retrieved using CLK API because it 3208 * causes lockup if CPU enters LP2 idle state from some other 3209 * CLK notifier, hence we're caching the rate's value locally. 3210 */ 3211 if (pmc->clk) { 3212 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 3213 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 3214 &pmc->clk_nb); 3215 if (err) { 3216 dev_err(&pdev->dev, 3217 "failed to register clk notifier\n"); 3218 return err; 3219 } 3220 3221 pmc->rate = clk_get_rate(pmc->clk); 3222 } 3223 3224 pmc->dev = &pdev->dev; 3225 3226 err = tegra_pmc_init(pmc); 3227 if (err < 0) { 3228 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 3229 return err; 3230 } 3231 3232 tegra_pmc_init_tsense_reset(pmc); 3233 3234 tegra_pmc_reset_sysfs_init(pmc); 3235 3236 err = tegra_pmc_pinctrl_init(pmc); 3237 if (err) 3238 goto cleanup_sysfs; 3239 3240 err = tegra_pmc_regmap_init(pmc); 3241 if (err < 0) 3242 goto cleanup_sysfs; 3243 3244 err = tegra_powergate_init(pmc, pdev->dev.of_node); 3245 if (err < 0) 3246 goto cleanup_powergates; 3247 3248 err = tegra_pmc_irq_init(pmc); 3249 if (err < 0) 3250 goto cleanup_powergates; 3251 3252 mutex_lock(&pmc->powergates_lock); 3253 iounmap(pmc->base); 3254 pmc->base = base; 3255 mutex_unlock(&pmc->powergates_lock); 3256 3257 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3258 platform_set_drvdata(pdev, pmc); 3259 tegra_pm_init_suspend(); 3260 3261 /* Some wakes require specific filter configuration */ 3262 if (pmc->soc->set_wake_filters) 3263 pmc->soc->set_wake_filters(pmc); 3264 3265 debugfs_create_file("powergate", 0444, NULL, pmc, &powergate_fops); 3266 3267 return 0; 3268 3269 cleanup_powergates: 3270 tegra_powergate_remove_all(pdev->dev.of_node); 3271 cleanup_sysfs: 3272 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3273 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3274 3275 return err; 3276 } 3277 3278 /* 3279 * Ensures that sufficient time is passed for a register write to 3280 * serialize into the 32KHz domain. 3281 */ 3282 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3283 { 3284 writel(value, pmc->wake + offset); 3285 udelay(130); 3286 } 3287 3288 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3289 { 3290 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3291 u32 value; 3292 3293 value = readl(pmc->wake + offset); 3294 if (level) 3295 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3296 else 3297 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3298 3299 writel(value, pmc->wake + offset); 3300 } 3301 3302 static void wke_write_wake_levels(struct tegra_pmc *pmc) 3303 { 3304 unsigned int i; 3305 3306 for (i = 0; i < pmc->soc->max_wake_events; i++) 3307 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3308 } 3309 3310 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3311 { 3312 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); 3313 } 3314 3315 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3316 { 3317 unsigned long status; 3318 unsigned int wake, i; 3319 3320 for (i = 0; i < pmc->soc->max_wake_events; i++) 3321 wke_write_wake_level(pmc, i, 0); 3322 3323 wke_clear_sw_wake_status(pmc); 3324 3325 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); 3326 3327 /* 3328 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3329 * obtain the current status of the input wake signals, change 3330 * the polarity of the wake level from 0->1 while latching to force 3331 * a positive edge if the sampled signal is '1'. 3332 */ 3333 for (i = 0; i < pmc->soc->max_wake_events; i++) 3334 wke_write_wake_level(pmc, i, 1); 3335 3336 /* 3337 * Wait for the update to be synced into the 32kHz domain, 3338 * and let enough time lapse, so that the wake signals have time to 3339 * be sampled. 3340 */ 3341 udelay(300); 3342 3343 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); 3344 3345 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3346 3347 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3348 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); 3349 3350 for_each_set_bit(wake, &status, 32) 3351 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3352 } 3353 } 3354 3355 static void wke_clear_wake_status(struct tegra_pmc *pmc) 3356 { 3357 unsigned long status; 3358 unsigned int i, wake; 3359 u32 mask; 3360 3361 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3362 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3363 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3364 3365 for_each_set_bit(wake, &status, 32) 3366 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); 3367 } 3368 } 3369 3370 static void tegra186_pmc_wake_syscore_resume(void *data) 3371 { 3372 struct tegra_pmc *pmc = data; 3373 unsigned int i; 3374 u32 mask; 3375 3376 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3377 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3378 pmc->wake_status[i] = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3379 } 3380 3381 /* Schedule IRQ work to process wake IRQs (if any) */ 3382 irq_work_queue(&pmc->wake_work); 3383 } 3384 3385 static int tegra186_pmc_wake_syscore_suspend(void *data) 3386 { 3387 struct tegra_pmc *pmc = data; 3388 unsigned int i; 3389 3390 /* Check if there are unhandled wake IRQs */ 3391 for (i = 0; i < pmc->soc->max_wake_vectors; i++) 3392 if (pmc->wake_status[i]) 3393 dev_warn(pmc->dev, 3394 "Unhandled wake IRQs pending vector[%u]: 0x%x\n", 3395 i, pmc->wake_status[i]); 3396 3397 wke_read_sw_wake_status(pmc); 3398 3399 /* flip the wakeup trigger for dual-edge triggered pads 3400 * which are currently asserting as wakeups 3401 */ 3402 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3403 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3404 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3405 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3406 3407 /* Clear PMC Wake Status registers while going to suspend */ 3408 wke_clear_wake_status(pmc); 3409 wke_write_wake_levels(pmc); 3410 3411 return 0; 3412 } 3413 3414 static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { 3415 .suspend = tegra186_pmc_wake_syscore_suspend, 3416 .resume = tegra186_pmc_wake_syscore_resume, 3417 }; 3418 3419 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3420 static int tegra_pmc_suspend(struct device *dev) 3421 { 3422 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3423 3424 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3425 3426 return 0; 3427 } 3428 3429 static int tegra_pmc_resume(struct device *dev) 3430 { 3431 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3432 3433 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3434 3435 return 0; 3436 } 3437 3438 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3439 3440 #endif 3441 3442 static const char * const tegra20_powergates[] = { 3443 [TEGRA_POWERGATE_CPU] = "cpu", 3444 [TEGRA_POWERGATE_3D] = "td", 3445 [TEGRA_POWERGATE_VENC] = "venc", 3446 [TEGRA_POWERGATE_VDEC] = "vdec", 3447 [TEGRA_POWERGATE_PCIE] = "pcie", 3448 [TEGRA_POWERGATE_L2] = "l2", 3449 [TEGRA_POWERGATE_MPE] = "mpe", 3450 }; 3451 3452 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3453 .scratch0 = 0x50, 3454 .rst_status = 0x1b4, 3455 .rst_source_shift = 0x0, 3456 .rst_source_mask = 0x7, 3457 .rst_level_shift = 0x0, 3458 .rst_level_mask = 0x0, 3459 }; 3460 3461 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3462 { 3463 u32 value, osc, pmu, off; 3464 3465 /* Always enable CPU power request */ 3466 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3467 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3468 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3469 3470 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3471 3472 if (pmc->sysclkreq_high) 3473 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3474 else 3475 value |= PMC_CNTRL_SYSCLK_POLARITY; 3476 3477 if (pmc->corereq_high) 3478 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3479 else 3480 value |= PMC_CNTRL_PWRREQ_POLARITY; 3481 3482 /* configure the output polarity while the request is tristated */ 3483 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3484 3485 /* now enable the request */ 3486 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3487 value |= PMC_CNTRL_SYSCLK_OE; 3488 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3489 3490 /* program core timings which are applicable only for suspend state */ 3491 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3492 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3493 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3494 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3495 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3496 PMC_COREPWRGOOD_TIMER); 3497 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3498 } 3499 } 3500 3501 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3502 struct device_node *np, 3503 bool invert) 3504 { 3505 u32 value; 3506 3507 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3508 3509 if (invert) 3510 value |= PMC_CNTRL_INTR_POLARITY; 3511 else 3512 value &= ~PMC_CNTRL_INTR_POLARITY; 3513 3514 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3515 } 3516 3517 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3518 .supports_core_domain = true, 3519 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3520 .powergates = tegra20_powergates, 3521 .num_cpu_powergates = 0, 3522 .cpu_powergates = NULL, 3523 .has_tsense_reset = false, 3524 .has_gpu_clamps = false, 3525 .needs_mbist_war = false, 3526 .has_impl_33v_pwr = false, 3527 .maybe_tz_only = false, 3528 .num_io_pads = 0, 3529 .io_pads = NULL, 3530 .num_pin_descs = 0, 3531 .pin_descs = NULL, 3532 .regs = &tegra20_pmc_regs, 3533 .init = tegra20_pmc_init, 3534 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3535 .powergate_set = tegra20_powergate_set, 3536 .reset_sources = NULL, 3537 .num_reset_sources = 0, 3538 .reset_levels = NULL, 3539 .num_reset_levels = 0, 3540 .pmc_clks_data = NULL, 3541 .num_pmc_clks = 0, 3542 .has_blink_output = true, 3543 .has_usb_sleepwalk = true, 3544 .has_single_mmio_aperture = true, 3545 }; 3546 3547 static const char * const tegra30_powergates[] = { 3548 [TEGRA_POWERGATE_CPU] = "cpu0", 3549 [TEGRA_POWERGATE_3D] = "td", 3550 [TEGRA_POWERGATE_VENC] = "venc", 3551 [TEGRA_POWERGATE_VDEC] = "vdec", 3552 [TEGRA_POWERGATE_PCIE] = "pcie", 3553 [TEGRA_POWERGATE_L2] = "l2", 3554 [TEGRA_POWERGATE_MPE] = "mpe", 3555 [TEGRA_POWERGATE_HEG] = "heg", 3556 [TEGRA_POWERGATE_SATA] = "sata", 3557 [TEGRA_POWERGATE_CPU1] = "cpu1", 3558 [TEGRA_POWERGATE_CPU2] = "cpu2", 3559 [TEGRA_POWERGATE_CPU3] = "cpu3", 3560 [TEGRA_POWERGATE_CELP] = "celp", 3561 [TEGRA_POWERGATE_3D1] = "td2", 3562 }; 3563 3564 static const u8 tegra30_cpu_powergates[] = { 3565 TEGRA_POWERGATE_CPU, 3566 TEGRA_POWERGATE_CPU1, 3567 TEGRA_POWERGATE_CPU2, 3568 TEGRA_POWERGATE_CPU3, 3569 }; 3570 3571 static const char * const tegra30_reset_sources[] = { 3572 "POWER_ON_RESET", 3573 "WATCHDOG", 3574 "SENSOR", 3575 "SW_MAIN", 3576 "LP0" 3577 }; 3578 3579 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3580 .supports_core_domain = true, 3581 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3582 .powergates = tegra30_powergates, 3583 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3584 .cpu_powergates = tegra30_cpu_powergates, 3585 .has_tsense_reset = true, 3586 .has_gpu_clamps = false, 3587 .needs_mbist_war = false, 3588 .has_impl_33v_pwr = false, 3589 .maybe_tz_only = false, 3590 .num_io_pads = 0, 3591 .io_pads = NULL, 3592 .num_pin_descs = 0, 3593 .pin_descs = NULL, 3594 .regs = &tegra20_pmc_regs, 3595 .init = tegra20_pmc_init, 3596 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3597 .powergate_set = tegra20_powergate_set, 3598 .reset_sources = tegra30_reset_sources, 3599 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3600 .reset_levels = NULL, 3601 .num_reset_levels = 0, 3602 .pmc_clks_data = tegra_pmc_clks_data, 3603 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3604 .has_blink_output = true, 3605 .has_usb_sleepwalk = true, 3606 .has_single_mmio_aperture = true, 3607 }; 3608 3609 static const char * const tegra114_powergates[] = { 3610 [TEGRA_POWERGATE_CPU] = "crail", 3611 [TEGRA_POWERGATE_3D] = "td", 3612 [TEGRA_POWERGATE_VENC] = "venc", 3613 [TEGRA_POWERGATE_VDEC] = "vdec", 3614 [TEGRA_POWERGATE_MPE] = "mpe", 3615 [TEGRA_POWERGATE_HEG] = "heg", 3616 [TEGRA_POWERGATE_CPU1] = "cpu1", 3617 [TEGRA_POWERGATE_CPU2] = "cpu2", 3618 [TEGRA_POWERGATE_CPU3] = "cpu3", 3619 [TEGRA_POWERGATE_CELP] = "celp", 3620 [TEGRA_POWERGATE_CPU0] = "cpu0", 3621 [TEGRA_POWERGATE_C0NC] = "c0nc", 3622 [TEGRA_POWERGATE_C1NC] = "c1nc", 3623 [TEGRA_POWERGATE_DIS] = "dis", 3624 [TEGRA_POWERGATE_DISB] = "disb", 3625 [TEGRA_POWERGATE_XUSBA] = "xusba", 3626 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3627 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3628 }; 3629 3630 static const u8 tegra114_cpu_powergates[] = { 3631 TEGRA_POWERGATE_CPU0, 3632 TEGRA_POWERGATE_CPU1, 3633 TEGRA_POWERGATE_CPU2, 3634 TEGRA_POWERGATE_CPU3, 3635 }; 3636 3637 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3638 .supports_core_domain = false, 3639 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3640 .powergates = tegra114_powergates, 3641 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3642 .cpu_powergates = tegra114_cpu_powergates, 3643 .has_tsense_reset = true, 3644 .has_gpu_clamps = false, 3645 .needs_mbist_war = false, 3646 .has_impl_33v_pwr = false, 3647 .maybe_tz_only = false, 3648 .num_io_pads = 0, 3649 .io_pads = NULL, 3650 .num_pin_descs = 0, 3651 .pin_descs = NULL, 3652 .regs = &tegra20_pmc_regs, 3653 .init = tegra20_pmc_init, 3654 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3655 .powergate_set = tegra114_powergate_set, 3656 .reset_sources = tegra30_reset_sources, 3657 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3658 .reset_levels = NULL, 3659 .num_reset_levels = 0, 3660 .pmc_clks_data = tegra_pmc_clks_data, 3661 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3662 .has_blink_output = true, 3663 .has_usb_sleepwalk = true, 3664 .has_single_mmio_aperture = true, 3665 }; 3666 3667 static const char * const tegra124_powergates[] = { 3668 [TEGRA_POWERGATE_CPU] = "crail", 3669 [TEGRA_POWERGATE_3D] = "3d", 3670 [TEGRA_POWERGATE_VENC] = "venc", 3671 [TEGRA_POWERGATE_PCIE] = "pcie", 3672 [TEGRA_POWERGATE_VDEC] = "vdec", 3673 [TEGRA_POWERGATE_MPE] = "mpe", 3674 [TEGRA_POWERGATE_HEG] = "heg", 3675 [TEGRA_POWERGATE_SATA] = "sata", 3676 [TEGRA_POWERGATE_CPU1] = "cpu1", 3677 [TEGRA_POWERGATE_CPU2] = "cpu2", 3678 [TEGRA_POWERGATE_CPU3] = "cpu3", 3679 [TEGRA_POWERGATE_CELP] = "celp", 3680 [TEGRA_POWERGATE_CPU0] = "cpu0", 3681 [TEGRA_POWERGATE_C0NC] = "c0nc", 3682 [TEGRA_POWERGATE_C1NC] = "c1nc", 3683 [TEGRA_POWERGATE_SOR] = "sor", 3684 [TEGRA_POWERGATE_DIS] = "dis", 3685 [TEGRA_POWERGATE_DISB] = "disb", 3686 [TEGRA_POWERGATE_XUSBA] = "xusba", 3687 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3688 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3689 [TEGRA_POWERGATE_VIC] = "vic", 3690 [TEGRA_POWERGATE_IRAM] = "iram", 3691 }; 3692 3693 static const u8 tegra124_cpu_powergates[] = { 3694 TEGRA_POWERGATE_CPU0, 3695 TEGRA_POWERGATE_CPU1, 3696 TEGRA_POWERGATE_CPU2, 3697 TEGRA_POWERGATE_CPU3, 3698 }; 3699 3700 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \ 3701 ((struct tegra_io_pad_soc) { \ 3702 .id = (_id), \ 3703 .dpd = (_dpd), \ 3704 .request = (_request), \ 3705 .status = (_status), \ 3706 .voltage = (_voltage), \ 3707 .name = (_name), \ 3708 }) 3709 3710 #define TEGRA_IO_PIN_DESC(_id, _name) \ 3711 ((struct pinctrl_pin_desc) { \ 3712 .number = (_id), \ 3713 .name = (_name), \ 3714 }) 3715 3716 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3717 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"), 3718 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"), 3719 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"), 3720 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"), 3721 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3722 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3723 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3724 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3725 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3726 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3727 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3728 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3729 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3730 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"), 3731 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3732 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3733 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"), 3734 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3735 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3736 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3737 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"), 3738 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"), 3739 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"), 3740 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"), 3741 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"), 3742 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"), 3743 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3744 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3745 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3746 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"), 3747 }; 3748 3749 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3750 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3751 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3752 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3753 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3754 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3755 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3756 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3757 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3758 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3759 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3760 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3761 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3762 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3763 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3764 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3765 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3766 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3767 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3768 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3769 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3770 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3771 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3772 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3773 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3774 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3775 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3776 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3777 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3778 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3779 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3780 }; 3781 3782 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3783 .supports_core_domain = false, 3784 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3785 .powergates = tegra124_powergates, 3786 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3787 .cpu_powergates = tegra124_cpu_powergates, 3788 .has_tsense_reset = true, 3789 .has_gpu_clamps = true, 3790 .needs_mbist_war = false, 3791 .has_impl_33v_pwr = false, 3792 .maybe_tz_only = false, 3793 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3794 .io_pads = tegra124_io_pads, 3795 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3796 .pin_descs = tegra124_pin_descs, 3797 .regs = &tegra20_pmc_regs, 3798 .init = tegra20_pmc_init, 3799 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3800 .powergate_set = tegra114_powergate_set, 3801 .reset_sources = tegra30_reset_sources, 3802 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3803 .reset_levels = NULL, 3804 .num_reset_levels = 0, 3805 .pmc_clks_data = tegra_pmc_clks_data, 3806 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3807 .has_blink_output = true, 3808 .has_usb_sleepwalk = true, 3809 .has_single_mmio_aperture = true, 3810 }; 3811 3812 static const char * const tegra210_powergates[] = { 3813 [TEGRA_POWERGATE_CPU] = "crail", 3814 [TEGRA_POWERGATE_3D] = "3d", 3815 [TEGRA_POWERGATE_VENC] = "venc", 3816 [TEGRA_POWERGATE_PCIE] = "pcie", 3817 [TEGRA_POWERGATE_MPE] = "mpe", 3818 [TEGRA_POWERGATE_SATA] = "sata", 3819 [TEGRA_POWERGATE_CPU1] = "cpu1", 3820 [TEGRA_POWERGATE_CPU2] = "cpu2", 3821 [TEGRA_POWERGATE_CPU3] = "cpu3", 3822 [TEGRA_POWERGATE_CPU0] = "cpu0", 3823 [TEGRA_POWERGATE_C0NC] = "c0nc", 3824 [TEGRA_POWERGATE_SOR] = "sor", 3825 [TEGRA_POWERGATE_DIS] = "dis", 3826 [TEGRA_POWERGATE_DISB] = "disb", 3827 [TEGRA_POWERGATE_XUSBA] = "xusba", 3828 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3829 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3830 [TEGRA_POWERGATE_VIC] = "vic", 3831 [TEGRA_POWERGATE_IRAM] = "iram", 3832 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3833 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3834 [TEGRA_POWERGATE_AUD] = "aud", 3835 [TEGRA_POWERGATE_DFD] = "dfd", 3836 [TEGRA_POWERGATE_VE2] = "ve2", 3837 }; 3838 3839 static const u8 tegra210_cpu_powergates[] = { 3840 TEGRA_POWERGATE_CPU0, 3841 TEGRA_POWERGATE_CPU1, 3842 TEGRA_POWERGATE_CPU2, 3843 TEGRA_POWERGATE_CPU3, 3844 }; 3845 3846 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3847 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"), 3848 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"), 3849 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"), 3850 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3851 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3852 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"), 3853 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"), 3854 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3855 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"), 3856 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"), 3857 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"), 3858 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"), 3859 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"), 3860 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3861 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3862 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3863 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3864 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"), 3865 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"), 3866 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"), 3867 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3868 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3869 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3870 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3871 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3872 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3873 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3874 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"), 3875 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"), 3876 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"), 3877 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"), 3878 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"), 3879 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"), 3880 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3881 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3882 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3883 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"), 3884 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"), 3885 }; 3886 3887 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3888 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3889 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3890 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3891 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3892 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3893 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3894 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3895 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3896 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3897 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3898 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3899 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3900 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3901 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3902 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3903 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3904 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3905 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3906 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3907 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3908 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3909 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3910 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3911 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3912 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3913 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3914 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3915 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3916 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3917 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3918 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3919 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3920 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3921 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3922 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3923 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3924 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3925 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3926 }; 3927 3928 static const char * const tegra210_reset_sources[] = { 3929 "POWER_ON_RESET", 3930 "WATCHDOG", 3931 "SENSOR", 3932 "SW_MAIN", 3933 "LP0", 3934 "AOTAG" 3935 }; 3936 3937 static const struct tegra_wake_event tegra210_wake_events[] = { 3938 TEGRA_WAKE_IRQ("rtc", 16, 2), 3939 TEGRA_WAKE_IRQ("pmu", 51, 86), 3940 }; 3941 3942 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3943 .supports_core_domain = false, 3944 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3945 .powergates = tegra210_powergates, 3946 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3947 .cpu_powergates = tegra210_cpu_powergates, 3948 .has_tsense_reset = true, 3949 .has_gpu_clamps = true, 3950 .needs_mbist_war = true, 3951 .has_impl_33v_pwr = false, 3952 .maybe_tz_only = true, 3953 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3954 .io_pads = tegra210_io_pads, 3955 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3956 .pin_descs = tegra210_pin_descs, 3957 .regs = &tegra20_pmc_regs, 3958 .init = tegra20_pmc_init, 3959 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3960 .powergate_set = tegra114_powergate_set, 3961 .irq_set_wake = tegra210_pmc_irq_set_wake, 3962 .irq_set_type = tegra210_pmc_irq_set_type, 3963 .reset_sources = tegra210_reset_sources, 3964 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3965 .reset_levels = NULL, 3966 .num_reset_levels = 0, 3967 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3968 .wake_events = tegra210_wake_events, 3969 .pmc_clks_data = tegra_pmc_clks_data, 3970 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3971 .has_blink_output = true, 3972 .has_usb_sleepwalk = true, 3973 .has_single_mmio_aperture = true, 3974 }; 3975 3976 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3977 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3978 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3979 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"), 3980 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3981 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3982 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3983 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3984 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3985 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"), 3986 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"), 3987 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"), 3988 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"), 3989 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3990 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3991 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"), 3992 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3993 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3994 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3995 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3996 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"), 3997 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3998 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3999 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"), 4000 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"), 4001 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"), 4002 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 4003 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 4004 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 4005 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 4006 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 4007 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 4008 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"), 4009 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 4010 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 4011 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 4012 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 4013 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 4014 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4015 }; 4016 4017 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 4041 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 4042 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 4043 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4044 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4045 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4046 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4047 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 4050 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4051 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4052 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4053 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4054 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4055 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4056 }; 4057 4058 static const struct tegra_pmc_regs tegra186_pmc_regs = { 4059 .scratch0 = 0x2000, 4060 .rst_status = 0x70, 4061 .rst_source_shift = 0x2, 4062 .rst_source_mask = 0x3c, 4063 .rst_level_shift = 0x0, 4064 .rst_level_mask = 0x3, 4065 }; 4066 4067 static void tegra186_pmc_init(struct tegra_pmc *pmc) 4068 { 4069 pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; 4070 pmc->syscore.data = pmc; 4071 register_syscore(&pmc->syscore); 4072 } 4073 4074 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 4075 struct device_node *np, 4076 bool invert) 4077 { 4078 struct resource regs; 4079 void __iomem *wake; 4080 u32 value; 4081 int index; 4082 4083 index = of_property_match_string(np, "reg-names", "wake"); 4084 if (index < 0) { 4085 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 4086 return; 4087 } 4088 4089 of_address_to_resource(np, index, ®s); 4090 4091 wake = ioremap(regs.start, resource_size(®s)); 4092 if (!wake) { 4093 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 4094 return; 4095 } 4096 4097 value = readl(wake + WAKE_AOWAKE_CTRL); 4098 4099 if (invert) 4100 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 4101 else 4102 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 4103 4104 writel(value, wake + WAKE_AOWAKE_CTRL); 4105 4106 iounmap(wake); 4107 } 4108 4109 static const char * const tegra186_reset_sources[] = { 4110 "SYS_RESET", 4111 "AOWDT", 4112 "MCCPLEXWDT", 4113 "BPMPWDT", 4114 "SCEWDT", 4115 "SPEWDT", 4116 "APEWDT", 4117 "BCCPLEXWDT", 4118 "SENSOR", 4119 "AOTAG", 4120 "VFSENSOR", 4121 "SWREST", 4122 "SC7", 4123 "HSM", 4124 "CORESIGHT" 4125 }; 4126 4127 static const char * const tegra186_reset_levels[] = { 4128 "L0", "L1", "L2", "WARM" 4129 }; 4130 4131 static const struct tegra_wake_event tegra186_wake_events[] = { 4132 TEGRA_WAKE_IRQ("pmu", 24, 209), 4133 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 4134 TEGRA_WAKE_IRQ("rtc", 73, 10), 4135 }; 4136 4137 static const struct tegra_pmc_soc tegra186_pmc_soc = { 4138 .supports_core_domain = false, 4139 .num_powergates = 0, 4140 .powergates = NULL, 4141 .num_cpu_powergates = 0, 4142 .cpu_powergates = NULL, 4143 .has_tsense_reset = false, 4144 .has_gpu_clamps = false, 4145 .needs_mbist_war = false, 4146 .has_impl_33v_pwr = true, 4147 .maybe_tz_only = false, 4148 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 4149 .io_pads = tegra186_io_pads, 4150 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 4151 .pin_descs = tegra186_pin_descs, 4152 .regs = &tegra186_pmc_regs, 4153 .init = tegra186_pmc_init, 4154 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4155 .set_wake_filters = tegra186_pmc_set_wake_filters, 4156 .irq_set_wake = tegra186_pmc_irq_set_wake, 4157 .irq_set_type = tegra186_pmc_irq_set_type, 4158 .reset_sources = tegra186_reset_sources, 4159 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 4160 .reset_levels = tegra186_reset_levels, 4161 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4162 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 4163 .wake_events = tegra186_wake_events, 4164 .max_wake_events = 96, 4165 .max_wake_vectors = 3, 4166 .pmc_clks_data = NULL, 4167 .num_pmc_clks = 0, 4168 .has_blink_output = false, 4169 .has_usb_sleepwalk = false, 4170 .has_single_mmio_aperture = false, 4171 }; 4172 4173 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 4174 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 4175 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 4176 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 4177 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 4178 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 4179 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 4180 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 4181 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"), 4182 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"), 4183 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"), 4184 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"), 4185 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"), 4186 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 4187 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"), 4188 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"), 4189 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 4190 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"), 4191 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"), 4192 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"), 4193 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"), 4194 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"), 4195 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"), 4196 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"), 4197 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 4198 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"), 4199 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"), 4200 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 4201 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 4202 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 4203 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"), 4204 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"), 4205 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"), 4206 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 4207 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"), 4208 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 4209 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 4210 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 4211 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 4212 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 4213 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 4214 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 4215 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"), 4216 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"), 4217 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 4218 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 4219 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 4220 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 4221 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 4222 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4223 }; 4224 4225 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 4226 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4227 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4228 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4229 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4230 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4231 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4232 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4233 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 4234 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 4235 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 4236 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 4237 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 4238 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4239 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 4240 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 4241 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4242 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4243 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4244 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4245 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4246 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4247 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4248 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4249 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4250 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4251 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4252 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4253 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4254 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4255 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4256 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4257 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4258 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4259 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4260 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4261 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4262 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4263 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4264 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4265 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4266 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4267 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4268 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4269 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4270 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4271 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4272 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4273 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4274 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4275 }; 4276 4277 static const struct tegra_pmc_regs tegra194_pmc_regs = { 4278 .scratch0 = 0x2000, 4279 .rst_status = 0x70, 4280 .rst_source_shift = 0x2, 4281 .rst_source_mask = 0x7c, 4282 .rst_level_shift = 0x0, 4283 .rst_level_mask = 0x3, 4284 }; 4285 4286 static const char * const tegra194_reset_sources[] = { 4287 "SYS_RESET_N", 4288 "AOWDT", 4289 "BCCPLEXWDT", 4290 "BPMPWDT", 4291 "SCEWDT", 4292 "SPEWDT", 4293 "APEWDT", 4294 "LCCPLEXWDT", 4295 "SENSOR", 4296 "AOTAG", 4297 "VFSENSOR", 4298 "MAINSWRST", 4299 "SC7", 4300 "HSM", 4301 "CSITE", 4302 "RCEWDT", 4303 "PVA0WDT", 4304 "PVA1WDT", 4305 "L1A_ASYNC", 4306 "BPMPBOOT", 4307 "FUSECRC", 4308 }; 4309 4310 static const struct tegra_wake_event tegra194_wake_events[] = { 4311 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), 4312 TEGRA_WAKE_IRQ("pmu", 24, 209), 4313 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4314 TEGRA_WAKE_IRQ("rtc", 73, 10), 4315 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4316 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4317 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4318 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4319 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4320 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4321 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4322 }; 4323 4324 static const struct tegra_pmc_soc tegra194_pmc_soc = { 4325 .supports_core_domain = false, 4326 .num_powergates = 0, 4327 .powergates = NULL, 4328 .num_cpu_powergates = 0, 4329 .cpu_powergates = NULL, 4330 .has_tsense_reset = false, 4331 .has_gpu_clamps = false, 4332 .needs_mbist_war = false, 4333 .has_impl_33v_pwr = true, 4334 .maybe_tz_only = false, 4335 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4336 .io_pads = tegra194_io_pads, 4337 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4338 .pin_descs = tegra194_pin_descs, 4339 .regs = &tegra194_pmc_regs, 4340 .init = tegra186_pmc_init, 4341 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4342 .set_wake_filters = tegra186_pmc_set_wake_filters, 4343 .irq_set_wake = tegra186_pmc_irq_set_wake, 4344 .irq_set_type = tegra186_pmc_irq_set_type, 4345 .reset_sources = tegra194_reset_sources, 4346 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4347 .reset_levels = tegra186_reset_levels, 4348 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4349 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4350 .wake_events = tegra194_wake_events, 4351 .max_wake_events = 96, 4352 .max_wake_vectors = 3, 4353 .pmc_clks_data = NULL, 4354 .num_pmc_clks = 0, 4355 .has_blink_output = false, 4356 .has_usb_sleepwalk = false, 4357 .has_single_mmio_aperture = false, 4358 }; 4359 4360 static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4361 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"), 4362 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"), 4363 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"), 4364 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"), 4365 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"), 4366 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"), 4367 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"), 4368 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"), 4369 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"), 4370 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"), 4371 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"), 4372 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"), 4373 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4374 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"), 4375 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"), 4376 }; 4377 4378 static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4379 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4380 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4381 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4382 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4383 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4384 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4385 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4386 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4387 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4388 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4389 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4390 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4391 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4392 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4393 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4394 }; 4395 4396 static const struct tegra_pmc_regs tegra234_pmc_regs = { 4397 .scratch0 = 0x2000, 4398 .rst_status = 0x70, 4399 .rst_source_shift = 0x2, 4400 .rst_source_mask = 0xfc, 4401 .rst_level_shift = 0x0, 4402 .rst_level_mask = 0x3, 4403 }; 4404 4405 static const char * const tegra234_reset_sources[] = { 4406 "SYS_RESET_N", /* 0x0 */ 4407 "AOWDT", 4408 "BCCPLEXWDT", 4409 "BPMPWDT", 4410 "SCEWDT", 4411 "SPEWDT", 4412 "APEWDT", 4413 "LCCPLEXWDT", 4414 "SENSOR", /* 0x8 */ 4415 NULL, 4416 NULL, 4417 "MAINSWRST", 4418 "SC7", 4419 "HSM", 4420 NULL, 4421 "RCEWDT", 4422 NULL, /* 0x10 */ 4423 NULL, 4424 NULL, 4425 "BPMPBOOT", 4426 "FUSECRC", 4427 "DCEWDT", 4428 "PSCWDT", 4429 "PSC", 4430 "CSITE_SW", /* 0x18 */ 4431 "POD", 4432 "SCPM", 4433 "VREFRO_POWERBAD", 4434 "VMON", 4435 "FMON", 4436 "FSI_R5WDT", 4437 "FSI_THERM", 4438 "FSI_R52C0WDT", /* 0x20 */ 4439 "FSI_R52C1WDT", 4440 "FSI_R52C2WDT", 4441 "FSI_R52C3WDT", 4442 "FSI_FMON", 4443 "FSI_VMON", /* 0x25 */ 4444 }; 4445 4446 static const struct tegra_wake_event tegra234_wake_events[] = { 4447 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4448 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), 4449 TEGRA_WAKE_IRQ("pmu", 24, 209), 4450 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4451 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4452 TEGRA_WAKE_IRQ("rtc", 73, 10), 4453 TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), 4454 TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), 4455 TEGRA_WAKE_IRQ("usb3-port-2-3", 78, 167), 4456 TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), 4457 TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), 4458 TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), 4459 TEGRA_WAKE_IRQ("usb2-port-3", 82, 167), 4460 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4461 }; 4462 4463 static const struct tegra_pmc_soc tegra234_pmc_soc = { 4464 .supports_core_domain = false, 4465 .num_powergates = 0, 4466 .powergates = NULL, 4467 .num_cpu_powergates = 0, 4468 .cpu_powergates = NULL, 4469 .has_tsense_reset = false, 4470 .has_gpu_clamps = false, 4471 .needs_mbist_war = false, 4472 .has_impl_33v_pwr = true, 4473 .maybe_tz_only = false, 4474 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4475 .io_pads = tegra234_io_pads, 4476 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4477 .pin_descs = tegra234_pin_descs, 4478 .regs = &tegra234_pmc_regs, 4479 .init = tegra186_pmc_init, 4480 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4481 .set_wake_filters = tegra186_pmc_set_wake_filters, 4482 .irq_set_wake = tegra186_pmc_irq_set_wake, 4483 .irq_set_type = tegra186_pmc_irq_set_type, 4484 .reset_sources = tegra234_reset_sources, 4485 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4486 .reset_levels = tegra186_reset_levels, 4487 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4488 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4489 .wake_events = tegra234_wake_events, 4490 .max_wake_events = 96, 4491 .max_wake_vectors = 3, 4492 .pmc_clks_data = NULL, 4493 .num_pmc_clks = 0, 4494 .has_blink_output = false, 4495 .has_single_mmio_aperture = false, 4496 }; 4497 4498 static const struct tegra_pmc_regs tegra264_pmc_regs = { 4499 .scratch0 = 0x684, 4500 .rst_status = 0x4, 4501 .rst_source_shift = 0x2, 4502 .rst_source_mask = 0x1fc, 4503 .rst_level_shift = 0x0, 4504 .rst_level_mask = 0x3, 4505 }; 4506 4507 static const char * const tegra264_reset_sources[] = { 4508 "SYS_RESET_N", /* 0x0 */ 4509 "CSDC_RTC_XTAL", 4510 "VREFRO_POWER_BAD", 4511 "SCPM_SOC_XTAL", 4512 "SCPM_RTC_XTAL", 4513 "FMON_32K", 4514 "FMON_OSC", 4515 "POD_RTC", 4516 "POD_IO", /* 0x8 */ 4517 "POD_PLUS_IO_SPLL", 4518 "POD_PLUS_SOC", 4519 "VMON_PLUS_UV", 4520 "VMON_PLUS_OV", 4521 "FUSECRC_FAULT", 4522 "OSC_FAULT", 4523 "BPMP_BOOT_FAULT", 4524 "SCPM_BPMP_CORE_CLK", /* 0x10 */ 4525 "SCPM_PSC_SE_CLK", 4526 "VMON_SOC_MIN", 4527 "VMON_SOC_MAX", 4528 "VMON_MSS_MIN", 4529 "VMON_MSS_MAX", 4530 "POD_PLUS_IO_VMON", 4531 "NVJTAG_SEL_MONITOR", 4532 "NV_THERM_FAULT", /* 0x18 */ 4533 "FSI_THERM_FAULT", 4534 "PSC_SW", 4535 "SCPM_OESP_SE_CLK", 4536 "SCPM_SB_SE_CLK", 4537 "POD_CPU", 4538 "POD_GPU", 4539 "DCLS_GPU", 4540 "POD_MSS", /* 0x20 */ 4541 "FMON_FSI", 4542 "POD_FSI", 4543 "VMON_FSI_MIN", 4544 "VMON_FSI_MAX", 4545 "VMON_CPU0_MIN", 4546 "VMON_CPU0_MAX", 4547 "BPMP_FMON", 4548 "AO_WDT_POR", /* 0x28 */ 4549 "BPMP_WDT_POR", 4550 "AO_TKE_WDT_POR", 4551 "RCE0_WDT_POR", 4552 "RCE1_WDT_POR", 4553 "DCE_WDT_POR", 4554 "FSI_R5_WDT_POR", 4555 "FSI_R52_0_WDT_POR", 4556 "FSI_R52_1_WDT_POR", /* 0x30 */ 4557 "FSI_R52_2_WDT_POR", 4558 "FSI_R52_3_WDT_POR", 4559 "TOP_0_WDT_POR", 4560 "TOP_1_WDT_POR", 4561 "TOP_2_WDT_POR", 4562 "APE_C0_WDT_POR", 4563 "APE_C1_WDT_POR", 4564 "GPU_TKE_WDT_POR", /* 0x38 */ 4565 "PSC_WDT_POR", 4566 "OESP_WDT_POR", 4567 "SB_WDT_POR", 4568 "SW_MAIN", 4569 "L0L1_RST_OUT_N", 4570 "FSI_HSM", 4571 "CSITE_SW", 4572 "AO_WDT_DBG", /* 0x40 */ 4573 "BPMP_WDT_DBG", 4574 "AO_TKE_WDT_DBG", 4575 "RCE0_WDT_DBG", 4576 "RCE1_WDT_DBG", 4577 "DCE_WDT_DBG", 4578 "FSI_R5_WDT_DBG", 4579 "FSI_R52_0_WDT_DBG", 4580 "FSI_R52_1_WDT_DBG", /* 0x48 */ 4581 "FSI_R52_2_WDT_DBG", 4582 "FSI_R52_3_WDT_DBG", 4583 "TOP_0_WDT_DBG", 4584 "TOP_1_WDT_DBG", 4585 "TOP_2_WDT_DBG", 4586 "APE_C0_WDT_DBG", 4587 "APE_C1_WDT_DBG", 4588 "PSC_WDT_DBG", /* 0x50 */ 4589 "OESP_WDT_DBG", 4590 "SB_WDT_DBG", 4591 "TSC_0_WDT_DBG", 4592 "TSC_1_WDT_DBG", 4593 "L2_RST_OUT_N", 4594 "SC7" 4595 }; 4596 4597 static const struct tegra_wake_event tegra264_wake_events[] = { 4598 }; 4599 4600 static const struct tegra_pmc_soc tegra264_pmc_soc = { 4601 .has_impl_33v_pwr = true, 4602 .regs = &tegra264_pmc_regs, 4603 .init = tegra186_pmc_init, 4604 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4605 .set_wake_filters = tegra186_pmc_set_wake_filters, 4606 .irq_set_wake = tegra186_pmc_irq_set_wake, 4607 .irq_set_type = tegra186_pmc_irq_set_type, 4608 .reset_sources = tegra264_reset_sources, 4609 .num_reset_sources = ARRAY_SIZE(tegra264_reset_sources), 4610 .reset_levels = tegra186_reset_levels, 4611 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4612 .wake_events = tegra264_wake_events, 4613 .num_wake_events = ARRAY_SIZE(tegra264_wake_events), 4614 .max_wake_events = 128, 4615 .max_wake_vectors = 4, 4616 }; 4617 4618 static const struct of_device_id tegra_pmc_match[] = { 4619 { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, 4620 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4621 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4622 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4623 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4624 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4625 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4626 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4627 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4628 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4629 { } 4630 }; 4631 4632 static void tegra_pmc_sync_state(struct device *dev) 4633 { 4634 struct device_node *np, *child; 4635 int err; 4636 4637 np = of_get_child_by_name(dev->of_node, "powergates"); 4638 if (!np) 4639 return; 4640 4641 for_each_child_of_node(np, child) 4642 of_genpd_sync_state(child); 4643 4644 of_node_put(np); 4645 4646 np = of_get_child_by_name(dev->of_node, "core-domain"); 4647 if (!np) 4648 return; 4649 4650 of_genpd_sync_state(np); 4651 of_node_put(np); 4652 4653 /* 4654 * Newer device-trees have power domains, but we need to prepare all 4655 * device drivers with runtime PM and OPP support first, otherwise 4656 * state syncing is unsafe. 4657 */ 4658 if (!pmc->soc->supports_core_domain) 4659 return; 4660 4661 /* 4662 * Older device-trees don't have core PD, and thus, there are 4663 * no dependencies that will block the state syncing. We shouldn't 4664 * mark the domain as synced in this case. 4665 */ 4666 pmc->core_domain_state_synced = true; 4667 4668 /* this is a no-op if core regulator isn't used */ 4669 mutex_lock(&pmc->powergates_lock); 4670 err = dev_pm_opp_sync_regulators(dev); 4671 mutex_unlock(&pmc->powergates_lock); 4672 4673 if (err) 4674 dev_err(dev, "failed to sync regulators: %d\n", err); 4675 } 4676 4677 static struct platform_driver tegra_pmc_driver = { 4678 .driver = { 4679 .name = "tegra-pmc", 4680 .suppress_bind_attrs = true, 4681 .of_match_table = tegra_pmc_match, 4682 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 4683 .pm = &tegra_pmc_pm_ops, 4684 #endif 4685 .sync_state = tegra_pmc_sync_state, 4686 }, 4687 .probe = tegra_pmc_probe, 4688 }; 4689 builtin_platform_driver(tegra_pmc_driver); 4690 4691 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 4692 { 4693 u32 value, saved; 4694 4695 saved = readl(pmc->base + pmc->soc->regs->scratch0); 4696 value = saved ^ 0xffffffff; 4697 4698 if (value == 0xffffffff) 4699 value = 0xdeadbeef; 4700 4701 /* write pattern and read it back */ 4702 writel(value, pmc->base + pmc->soc->regs->scratch0); 4703 value = readl(pmc->base + pmc->soc->regs->scratch0); 4704 4705 /* if we read all-zeroes, access is restricted to TZ only */ 4706 if (value == 0) { 4707 pr_info("access to PMC is restricted to TZ\n"); 4708 return true; 4709 } 4710 4711 /* restore original value */ 4712 writel(saved, pmc->base + pmc->soc->regs->scratch0); 4713 4714 return false; 4715 } 4716 4717 /* 4718 * Early initialization to allow access to registers in the very early boot 4719 * process. 4720 */ 4721 static int __init tegra_pmc_early_init(void) 4722 { 4723 const struct of_device_id *match; 4724 struct device_node *np; 4725 struct resource regs; 4726 unsigned int i; 4727 bool invert; 4728 4729 mutex_init(&pmc->powergates_lock); 4730 4731 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 4732 if (!np) { 4733 /* 4734 * Fall back to legacy initialization for 32-bit ARM only. All 4735 * 64-bit ARM device tree files for Tegra are required to have 4736 * a PMC node. 4737 * 4738 * This is for backwards-compatibility with old device trees 4739 * that didn't contain a PMC node. Note that in this case the 4740 * SoC data can't be matched and therefore powergating is 4741 * disabled. 4742 */ 4743 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4744 pr_warn("DT node not found, powergating disabled\n"); 4745 4746 regs.start = 0x7000e400; 4747 regs.end = 0x7000e7ff; 4748 regs.flags = IORESOURCE_MEM; 4749 4750 pr_warn("Using memory region %pR\n", ®s); 4751 } else { 4752 /* 4753 * At this point we're not running on Tegra, so play 4754 * nice with multi-platform kernels. 4755 */ 4756 return 0; 4757 } 4758 } else { 4759 /* 4760 * Extract information from the device tree if we've found a 4761 * matching node. 4762 */ 4763 if (of_address_to_resource(np, 0, ®s) < 0) { 4764 pr_err("failed to get PMC registers\n"); 4765 of_node_put(np); 4766 return -ENXIO; 4767 } 4768 } 4769 4770 pmc->base = ioremap(regs.start, resource_size(®s)); 4771 if (!pmc->base) { 4772 pr_err("failed to map PMC registers\n"); 4773 of_node_put(np); 4774 return -ENXIO; 4775 } 4776 4777 if (of_device_is_available(np)) { 4778 pmc->soc = match->data; 4779 4780 if (pmc->soc->maybe_tz_only) 4781 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4782 4783 /* Create a bitmap of the available and valid partitions */ 4784 for (i = 0; i < pmc->soc->num_powergates; i++) 4785 if (pmc->soc->powergates[i]) 4786 set_bit(i, pmc->powergates_available); 4787 4788 /* 4789 * Invert the interrupt polarity if a PMC device tree node 4790 * exists and contains the nvidia,invert-interrupt property. 4791 */ 4792 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4793 4794 pmc->soc->setup_irq_polarity(pmc, np, invert); 4795 4796 of_node_put(np); 4797 } 4798 4799 return 0; 4800 } 4801 early_initcall(tegra_pmc_early_init); 4802