1 /*
2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_discovery.h"
28 #include "soc15_hw_ip.h"
29 #include "discovery.h"
30 #include "amdgpu_ras.h"
31
32 #include "soc15.h"
33 #include "gfx_v9_0.h"
34 #include "gfx_v9_4_3.h"
35 #include "gmc_v9_0.h"
36 #include "df_v1_7.h"
37 #include "df_v3_6.h"
38 #include "df_v4_3.h"
39 #include "df_v4_6_2.h"
40 #include "df_v4_15.h"
41 #include "nbio_v6_1.h"
42 #include "nbio_v7_0.h"
43 #include "nbio_v7_4.h"
44 #include "nbio_v7_9.h"
45 #include "nbio_v7_11.h"
46 #include "hdp_v4_0.h"
47 #include "vega10_ih.h"
48 #include "vega20_ih.h"
49 #include "sdma_v4_0.h"
50 #include "sdma_v4_4_2.h"
51 #include "uvd_v7_0.h"
52 #include "vce_v4_0.h"
53 #include "vcn_v1_0.h"
54 #include "vcn_v2_5.h"
55 #include "jpeg_v2_5.h"
56 #include "smuio_v9_0.h"
57 #include "gmc_v10_0.h"
58 #include "gmc_v11_0.h"
59 #include "gmc_v12_0.h"
60 #include "gfxhub_v2_0.h"
61 #include "mmhub_v2_0.h"
62 #include "nbio_v2_3.h"
63 #include "nbio_v4_3.h"
64 #include "nbio_v7_2.h"
65 #include "nbio_v7_7.h"
66 #include "nbif_v6_3_1.h"
67 #include "nbio_v6_3_2.h"
68 #include "hdp_v5_0.h"
69 #include "hdp_v5_2.h"
70 #include "hdp_v6_0.h"
71 #include "hdp_v7_0.h"
72 #include "nv.h"
73 #include "soc21.h"
74 #include "soc24.h"
75 #include "soc_v1_0.h"
76 #include "navi10_ih.h"
77 #include "ih_v6_0.h"
78 #include "ih_v6_1.h"
79 #include "ih_v7_0.h"
80 #include "gfx_v10_0.h"
81 #include "gfx_v11_0.h"
82 #include "gfx_v12_0.h"
83 #include "gfx_v12_1.h"
84 #include "sdma_v5_0.h"
85 #include "sdma_v5_2.h"
86 #include "sdma_v6_0.h"
87 #include "sdma_v7_0.h"
88 #include "sdma_v7_1.h"
89 #include "lsdma_v6_0.h"
90 #include "lsdma_v7_0.h"
91 #include "lsdma_v7_1.h"
92 #include "vcn_v2_0.h"
93 #include "jpeg_v2_0.h"
94 #include "vcn_v3_0.h"
95 #include "jpeg_v3_0.h"
96 #include "vcn_v4_0.h"
97 #include "jpeg_v4_0.h"
98 #include "vcn_v4_0_3.h"
99 #include "jpeg_v4_0_3.h"
100 #include "vcn_v4_0_5.h"
101 #include "jpeg_v4_0_5.h"
102 #include "amdgpu_vkms.h"
103 #include "mes_v11_0.h"
104 #include "mes_v12_0.h"
105 #include "mes_v12_1.h"
106 #include "smuio_v11_0.h"
107 #include "smuio_v11_0_6.h"
108 #include "smuio_v13_0.h"
109 #include "smuio_v13_0_3.h"
110 #include "smuio_v13_0_6.h"
111 #include "smuio_v14_0_2.h"
112 #include "smuio_v15_0_0.h"
113 #include "smuio_v15_0_8.h"
114 #include "vcn_v5_0_0.h"
115 #include "vcn_v5_0_1.h"
116 #include "vcn_v5_0_2.h"
117 #include "jpeg_v5_0_0.h"
118 #include "jpeg_v5_0_1.h"
119 #include "jpeg_v5_0_2.h"
120 #include "jpeg_v5_3_0.h"
121
122 #include "amdgpu_ras_mgr.h"
123
124 #include "amdgpu_vpe.h"
125 #if defined(CONFIG_DRM_AMD_ISP)
126 #include "amdgpu_isp.h"
127 #endif
128
129 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
130 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin");
131 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin");
132 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin");
133 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");
134 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");
135 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");
136 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");
137 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");
138
139 /* Note: These registers are consistent across all the SOCs */
140 #define mmIP_DISCOVERY_VERSION 0x16A00
141 #define mmRCC_CONFIG_MEMSIZE 0xde3
142 #define mmMP0_SMN_C2PMSG_33 0x16061
143 #define mmMM_INDEX 0x0
144 #define mmMM_INDEX_HI 0x6
145 #define mmMM_DATA 0x1
146
147 #define mmDRIVER_SCRATCH_0 0x94
148 #define mmDRIVER_SCRATCH_1 0x95
149 #define mmDRIVER_SCRATCH_2 0x96
150
151 static const char *hw_id_names[HW_ID_MAX] = {
152 [MP1_HWID] = "MP1",
153 [MP2_HWID] = "MP2",
154 [THM_HWID] = "THM",
155 [SMUIO_HWID] = "SMUIO",
156 [FUSE_HWID] = "FUSE",
157 [CLKA_HWID] = "CLKA",
158 [PWR_HWID] = "PWR",
159 [GC_HWID] = "GC",
160 [UVD_HWID] = "UVD",
161 [AUDIO_AZ_HWID] = "AUDIO_AZ",
162 [ACP_HWID] = "ACP",
163 [DCI_HWID] = "DCI",
164 [DMU_HWID] = "DMU",
165 [DCO_HWID] = "DCO",
166 [DIO_HWID] = "DIO",
167 [XDMA_HWID] = "XDMA",
168 [DCEAZ_HWID] = "DCEAZ",
169 [DAZ_HWID] = "DAZ",
170 [SDPMUX_HWID] = "SDPMUX",
171 [NTB_HWID] = "NTB",
172 [IOHC_HWID] = "IOHC",
173 [L2IMU_HWID] = "L2IMU",
174 [VCE_HWID] = "VCE",
175 [MMHUB_HWID] = "MMHUB",
176 [ATHUB_HWID] = "ATHUB",
177 [DBGU_NBIO_HWID] = "DBGU_NBIO",
178 [DFX_HWID] = "DFX",
179 [DBGU0_HWID] = "DBGU0",
180 [DBGU1_HWID] = "DBGU1",
181 [OSSSYS_HWID] = "OSSSYS",
182 [HDP_HWID] = "HDP",
183 [SDMA0_HWID] = "SDMA0",
184 [SDMA1_HWID] = "SDMA1",
185 [SDMA2_HWID] = "SDMA2",
186 [SDMA3_HWID] = "SDMA3",
187 [LSDMA_HWID] = "LSDMA",
188 [ISP_HWID] = "ISP",
189 [DBGU_IO_HWID] = "DBGU_IO",
190 [DF_HWID] = "DF",
191 [CLKB_HWID] = "CLKB",
192 [FCH_HWID] = "FCH",
193 [DFX_DAP_HWID] = "DFX_DAP",
194 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
195 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
196 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
197 [L1IMU3_HWID] = "L1IMU3",
198 [L1IMU4_HWID] = "L1IMU4",
199 [L1IMU5_HWID] = "L1IMU5",
200 [L1IMU6_HWID] = "L1IMU6",
201 [L1IMU7_HWID] = "L1IMU7",
202 [L1IMU8_HWID] = "L1IMU8",
203 [L1IMU9_HWID] = "L1IMU9",
204 [L1IMU10_HWID] = "L1IMU10",
205 [L1IMU11_HWID] = "L1IMU11",
206 [L1IMU12_HWID] = "L1IMU12",
207 [L1IMU13_HWID] = "L1IMU13",
208 [L1IMU14_HWID] = "L1IMU14",
209 [L1IMU15_HWID] = "L1IMU15",
210 [WAFLC_HWID] = "WAFLC",
211 [FCH_USB_PD_HWID] = "FCH_USB_PD",
212 [PCIE_HWID] = "PCIE",
213 [PCS_HWID] = "PCS",
214 [DDCL_HWID] = "DDCL",
215 [SST_HWID] = "SST",
216 [IOAGR_HWID] = "IOAGR",
217 [NBIF_HWID] = "NBIF",
218 [IOAPIC_HWID] = "IOAPIC",
219 [SYSTEMHUB_HWID] = "SYSTEMHUB",
220 [NTBCCP_HWID] = "NTBCCP",
221 [UMC_HWID] = "UMC",
222 [SATA_HWID] = "SATA",
223 [USB_HWID] = "USB",
224 [CCXSEC_HWID] = "CCXSEC",
225 [XGMI_HWID] = "XGMI",
226 [XGBE_HWID] = "XGBE",
227 [MP0_HWID] = "MP0",
228 [VPE_HWID] = "VPE",
229 [ATU_HWID] = "ATU",
230 [AIGC_HWID] = "AIGC",
231 };
232
233 static int hw_id_map[MAX_HWIP] = {
234 [GC_HWIP] = GC_HWID,
235 [HDP_HWIP] = HDP_HWID,
236 [SDMA0_HWIP] = SDMA0_HWID,
237 [SDMA1_HWIP] = SDMA1_HWID,
238 [SDMA2_HWIP] = SDMA2_HWID,
239 [SDMA3_HWIP] = SDMA3_HWID,
240 [LSDMA_HWIP] = LSDMA_HWID,
241 [MMHUB_HWIP] = MMHUB_HWID,
242 [ATHUB_HWIP] = ATHUB_HWID,
243 [NBIO_HWIP] = NBIF_HWID,
244 [MP0_HWIP] = MP0_HWID,
245 [MP1_HWIP] = MP1_HWID,
246 [UVD_HWIP] = UVD_HWID,
247 [VCE_HWIP] = VCE_HWID,
248 [DF_HWIP] = DF_HWID,
249 [DCE_HWIP] = DMU_HWID,
250 [OSSSYS_HWIP] = OSSSYS_HWID,
251 [SMUIO_HWIP] = SMUIO_HWID,
252 [PWR_HWIP] = PWR_HWID,
253 [NBIF_HWIP] = NBIF_HWID,
254 [THM_HWIP] = THM_HWID,
255 [CLK_HWIP] = CLKA_HWID,
256 [UMC_HWIP] = UMC_HWID,
257 [XGMI_HWIP] = XGMI_HWID,
258 [DCI_HWIP] = DCI_HWID,
259 [PCIE_HWIP] = PCIE_HWID,
260 [VPE_HWIP] = VPE_HWID,
261 [ISP_HWIP] = ISP_HWID,
262 [ATU_HWIP] = ATU_HWID,
263 };
264
amdgpu_discovery_get_tmr_info(struct amdgpu_device * adev,bool * is_tmr_in_sysmem)265 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev,
266 bool *is_tmr_in_sysmem)
267 {
268 u64 vram_size, tmr_offset, tmr_size;
269 u32 msg, tmr_offset_lo, tmr_offset_hi;
270 int i, ret;
271
272 if (!amdgpu_sriov_vf(adev)) {
273 /* It can take up to two second for IFWI init to complete on some dGPUs,
274 * but generally it should be in the 60-100ms range. Normally this starts
275 * as soon as the device gets power so by the time the OS loads this has long
276 * completed. However, when a card is hotplugged via e.g., USB4, we need to
277 * wait for this to complete. Once the C2PMSG is updated, we can
278 * continue.
279 */
280
281 for (i = 0; i < 2000; i++) {
282 msg = RREG32(mmMP0_SMN_C2PMSG_33);
283 if (msg & 0x80000000)
284 break;
285 msleep(1);
286 }
287 }
288
289 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);
290 if (vram_size == U32_MAX)
291 return -ENXIO;
292 else if (!vram_size)
293 *is_tmr_in_sysmem = true;
294 else
295 *is_tmr_in_sysmem = false;
296
297 /* init the default tmr size and offset */
298 adev->discovery.size = DISCOVERY_TMR_SIZE;
299 if (vram_size)
300 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET;
301
302 if (amdgpu_sriov_vf(adev)) {
303 if (adev->virt.is_dynamic_crit_regn_enabled) {
304 adev->discovery.offset =
305 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset;
306 adev->discovery.size =
307 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10;
308 if (!adev->discovery.size)
309 return -EINVAL;
310 } else {
311 goto out;
312 }
313 } else {
314 if (adev->discovery.offset) {
315 u32 signature;
316
317 /* If VRAM holds a valid discovery signature at the default
318 * discovery offset, use it as-is.
319 */
320 amdgpu_device_vram_access(adev, adev->discovery.offset,
321 &signature, sizeof(signature),
322 false);
323 if (le32_to_cpu(signature) == BINARY_SIGNATURE)
324 goto out;
325 }
326
327 tmr_size = RREG32(mmDRIVER_SCRATCH_2);
328 if (tmr_size) {
329 /* It's preferred to transition to PSP mailbox reg interface
330 * for both bare-metal and passthrough if available */
331 adev->discovery.size = (u32)tmr_size;
332 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0);
333 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1);
334 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 |
335 le32_to_cpu(tmr_offset_lo));
336 } else if (!vram_size) {
337 /* fall back to apci approach to query tmr offset if vram_size is 0 */
338 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
339 if (ret)
340 return ret;
341 adev->discovery.size = DISCOVERY_TMR_SIZE;
342 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
343 }
344 }
345 out:
346 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL);
347 if (!adev->discovery.bin)
348 return -ENOMEM;
349 adev->discovery.debugfs_blob.data = adev->discovery.bin;
350 adev->discovery.debugfs_blob.size = adev->discovery.size;
351
352 return 0;
353 }
354
amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device * adev,uint8_t * binary)355 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
356 {
357 void *discv_regn;
358
359 /* This region is read-only and reserved from system use */
360 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC);
361 if (discv_regn) {
362 memcpy(binary, discv_regn, adev->discovery.size);
363 memunmap(discv_regn);
364 return 0;
365 }
366
367 return -ENOENT;
368 }
369
370 #define IP_DISCOVERY_V2 2
371 #define IP_DISCOVERY_V4 4
372
amdgpu_discovery_read_binary_from_mem(struct amdgpu_device * adev,uint8_t * binary,bool is_tmr_in_sysmem)373 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
374 uint8_t *binary,
375 bool is_tmr_in_sysmem)
376 {
377 int ret = 0;
378
379 if (!is_tmr_in_sysmem) {
380 if (amdgpu_sriov_vf(adev) &&
381 amdgpu_sriov_xgmi_connected_to_cpu(adev)) {
382 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
383 } else {
384 amdgpu_device_vram_access(adev, adev->discovery.offset,
385 (uint32_t *)binary,
386 adev->discovery.size, false);
387 adev->discovery.reserve_tmr = true;
388 }
389 } else {
390 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
391 }
392
393 return ret;
394 }
395
amdgpu_discovery_read_binary_from_file(struct amdgpu_device * adev,uint8_t * binary,const char * fw_name)396 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
397 uint8_t *binary,
398 const char *fw_name)
399 {
400 const struct firmware *fw;
401 int r;
402
403 r = firmware_request_nowarn(&fw, fw_name, adev->dev);
404 if (r) {
405 if (amdgpu_discovery == 2)
406 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name);
407 else
408 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name);
409 return r;
410 }
411
412 if (fw->size > adev->discovery.size) {
413 dev_err(adev->dev,
414 "ip discovery firmware \"%s\" too large (%zu > %u)\n",
415 fw_name, fw->size, adev->discovery.size);
416 release_firmware(fw);
417 return -EINVAL;
418 }
419
420 /* Ensure the firmware is at least large enough to contain the
421 * binary header fields.
422 */
423 if (fw->size < offsetof(struct binary_header, binary_size) +
424 sizeof(((struct binary_header *)0)->binary_size)) {
425 dev_err(adev->dev,
426 "ip discovery firmware \"%s\" too small (%zu)\n",
427 fw_name, fw->size);
428 release_firmware(fw);
429 return -EINVAL;
430 }
431
432 memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
433 release_firmware(fw);
434
435 return 0;
436 }
437
amdgpu_discovery_calculate_checksum(uint8_t * data,uint32_t size)438 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
439 {
440 uint16_t checksum = 0;
441 int i;
442
443 for (i = 0; i < size; i++)
444 checksum += data[i];
445
446 return checksum;
447 }
448
amdgpu_discovery_verify_checksum(struct amdgpu_device * adev,uint8_t * data,uint32_t size,uint16_t expected)449 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev,
450 uint8_t *data, uint32_t size,
451 uint16_t expected)
452 {
453 uint16_t calculated;
454
455 calculated = amdgpu_discovery_calculate_checksum(data, size);
456
457 if (calculated != expected) {
458 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n",
459 calculated, expected, size);
460 return false;
461 }
462
463 return true;
464 }
465
amdgpu_discovery_verify_binary_signature(uint8_t * binary)466 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
467 {
468 struct binary_header *bhdr;
469 bhdr = (struct binary_header *)binary;
470
471 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
472 }
473
amdgpu_discovery_harvest_config_quirk(struct amdgpu_device * adev)474 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
475 {
476 /*
477 * So far, apply this quirk only on those Navy Flounder boards which
478 * have a bad harvest table of VCN config.
479 */
480 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
481 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
482 switch (adev->pdev->revision) {
483 case 0xC1:
484 case 0xC2:
485 case 0xC3:
486 case 0xC5:
487 case 0xC7:
488 case 0xCF:
489 case 0xDF:
490 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
491 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
492 break;
493 default:
494 break;
495 }
496 }
497 }
498
amdgpu_discovery_verify_npsinfo(struct amdgpu_device * adev,struct table_info * info)499 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
500 struct table_info *info)
501 {
502 uint8_t *discovery_bin = adev->discovery.bin;
503 uint16_t checksum;
504 uint16_t offset;
505
506 offset = le16_to_cpu(info->offset);
507 checksum = le16_to_cpu(info->checksum);
508
509 struct nps_info_header *nhdr =
510 (struct nps_info_header *)(discovery_bin + offset);
511
512 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
513 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
514 return -EINVAL;
515 }
516
517 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
518 le32_to_cpu(nhdr->size_bytes),
519 checksum)) {
520 dev_dbg(adev->dev, "invalid nps info data table checksum\n");
521 return -EINVAL;
522 }
523
524 return 0;
525 }
526
amdgpu_discovery_get_fw_name(struct amdgpu_device * adev)527 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev)
528 {
529 if (amdgpu_discovery == 2) {
530 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */
531 adev->discovery.reserve_tmr = true;
532 return "amdgpu/ip_discovery.bin";
533 }
534
535 switch (adev->asic_type) {
536 case CHIP_VEGA10:
537 return "amdgpu/vega10_ip_discovery.bin";
538 case CHIP_VEGA12:
539 return "amdgpu/vega12_ip_discovery.bin";
540 case CHIP_RAVEN:
541 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
542 return "amdgpu/raven2_ip_discovery.bin";
543 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
544 return "amdgpu/picasso_ip_discovery.bin";
545 else
546 return "amdgpu/raven_ip_discovery.bin";
547 case CHIP_VEGA20:
548 return "amdgpu/vega20_ip_discovery.bin";
549 case CHIP_ARCTURUS:
550 return "amdgpu/arcturus_ip_discovery.bin";
551 case CHIP_ALDEBARAN:
552 return "amdgpu/aldebaran_ip_discovery.bin";
553 default:
554 return NULL;
555 }
556 }
557
amdgpu_discovery_get_table_info(struct amdgpu_device * adev,struct table_info ** info,uint16_t table_id)558 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev,
559 struct table_info **info,
560 uint16_t table_id)
561 {
562 struct binary_header *bhdr =
563 (struct binary_header *)adev->discovery.bin;
564 struct binary_header_v2 *bhdrv2;
565
566 switch (bhdr->version_major) {
567 case 2:
568 bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin;
569 *info = &bhdrv2->table_list[table_id];
570 break;
571 case 1:
572 case 0:
573 *info = &bhdr->table_list[table_id];
574 break;
575 default:
576 dev_err(adev->dev, "Invalid ip discovery table version %d\n",bhdr->version_major);
577 return -EINVAL;
578 }
579
580 return 0;
581 }
582
amdgpu_discovery_table_check(struct amdgpu_device * adev,uint8_t * discovery_bin,uint16_t table_id)583 static int amdgpu_discovery_table_check(struct amdgpu_device *adev,
584 uint8_t *discovery_bin,
585 uint16_t table_id)
586 {
587 int r, act_val, exp_val, table_size;
588 uint16_t offset, checksum;
589 struct table_info *info;
590 bool check_table = true;
591 char *table_name;
592
593 r = amdgpu_discovery_get_table_info(adev, &info, table_id);
594 if (r)
595 return r;
596 offset = le16_to_cpu(info->offset);
597 checksum = le16_to_cpu(info->checksum);
598
599 switch (table_id) {
600 case IP_DISCOVERY: {
601 struct ip_discovery_header *ihdr =
602 (struct ip_discovery_header *)(discovery_bin + offset);
603 act_val = le32_to_cpu(ihdr->signature);
604 exp_val = DISCOVERY_TABLE_SIGNATURE;
605 table_size = le16_to_cpu(ihdr->size);
606 table_name = "data table";
607 break;
608 }
609 case GC: {
610 struct gpu_info_header *ghdr =
611 (struct gpu_info_header *)(discovery_bin + offset);
612 act_val = le32_to_cpu(ghdr->table_id);
613 exp_val = GC_TABLE_ID;
614 table_size = le16_to_cpu(ghdr->size);
615 table_name = "gc table";
616 break;
617 }
618 case HARVEST_INFO: {
619 struct harvest_info_header *hhdr =
620 (struct harvest_info_header *)(discovery_bin + offset);
621 act_val = le32_to_cpu(hhdr->signature);
622 exp_val = HARVEST_TABLE_SIGNATURE;
623 table_size = sizeof(struct harvest_table);
624 table_name = "harvest table";
625 break;
626 }
627 case VCN_INFO: {
628 struct vcn_info_header *vhdr =
629 (struct vcn_info_header *)(discovery_bin + offset);
630 act_val = le32_to_cpu(vhdr->table_id);
631 exp_val = VCN_INFO_TABLE_ID;
632 table_size = le32_to_cpu(vhdr->size_bytes);
633 table_name = "vcn table";
634 break;
635 }
636 case MALL_INFO: {
637 struct mall_info_header *mhdr =
638 (struct mall_info_header *)(discovery_bin + offset);
639 act_val = le32_to_cpu(mhdr->table_id);
640 exp_val = MALL_INFO_TABLE_ID;
641 table_size = le32_to_cpu(mhdr->size_bytes);
642 table_name = "mall table";
643 check_table = false;
644 break;
645 }
646 default:
647 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id);
648 check_table = false;
649 break;
650 }
651
652 if (check_table && offset) {
653 if (act_val != exp_val) {
654 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name);
655 return -EINVAL;
656 }
657
658 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
659 table_size, checksum)) {
660 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name);
661 return -EINVAL;
662 }
663 }
664
665 return 0;
666 }
667
amdgpu_discovery_init(struct amdgpu_device * adev)668 static int amdgpu_discovery_init(struct amdgpu_device *adev)
669 {
670 struct binary_header *bhdr;
671 uint8_t *discovery_bin;
672 const char *fw_name;
673 uint16_t offset;
674 uint16_t size;
675 uint16_t checksum;
676 uint16_t table_id;
677 bool is_tmr_in_sysmem;
678 int r;
679
680 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem);
681 if (r)
682 return r;
683
684 discovery_bin = adev->discovery.bin;
685 /* Read from file if it is the preferred option */
686 fw_name = amdgpu_discovery_get_fw_name(adev);
687 if (fw_name != NULL) {
688 drm_dbg(&adev->ddev, "use ip discovery information from file");
689 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin,
690 fw_name);
691 if (r)
692 goto out;
693 } else {
694 drm_dbg(&adev->ddev, "use ip discovery information from memory");
695 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin,
696 is_tmr_in_sysmem);
697 if (r)
698 goto out;
699 }
700
701 /* check the ip discovery binary signature */
702 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) {
703 dev_err(adev->dev,
704 "get invalid ip discovery binary signature\n");
705 r = -EINVAL;
706 goto out;
707 }
708
709 bhdr = (struct binary_header *)discovery_bin;
710
711 offset = offsetof(struct binary_header, binary_checksum) +
712 sizeof(bhdr->binary_checksum);
713 size = le16_to_cpu(bhdr->binary_size) - offset;
714 checksum = le16_to_cpu(bhdr->binary_checksum);
715
716 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size,
717 checksum)) {
718 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
719 r = -EINVAL;
720 goto out;
721 }
722
723 for (table_id = 0; table_id <= MALL_INFO; table_id++) {
724 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id);
725 if (r)
726 goto out;
727 }
728
729 return 0;
730
731 out:
732 kfree(adev->discovery.bin);
733 adev->discovery.bin = NULL;
734 if ((amdgpu_discovery != 2) &&
735 (RREG32(mmIP_DISCOVERY_VERSION) == 4))
736 amdgpu_ras_query_boot_status(adev, 4);
737 return r;
738 }
739
740 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
741
amdgpu_discovery_fini(struct amdgpu_device * adev)742 void amdgpu_discovery_fini(struct amdgpu_device *adev)
743 {
744 amdgpu_discovery_sysfs_fini(adev);
745 kfree(adev->discovery.bin);
746 adev->discovery.bin = NULL;
747 }
748
amdgpu_discovery_validate_ip(struct amdgpu_device * adev,uint8_t instance,uint16_t hw_id)749 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev,
750 uint8_t instance, uint16_t hw_id)
751 {
752 if (instance >= HWIP_MAX_INSTANCE) {
753 dev_err(adev->dev,
754 "Unexpected instance_number (%d) from ip discovery blob\n",
755 instance);
756 return -EINVAL;
757 }
758 if (hw_id >= HW_ID_MAX) {
759 dev_err(adev->dev,
760 "Unexpected hw_id (%d) from ip discovery blob\n",
761 hw_id);
762 return -EINVAL;
763 }
764
765 return 0;
766 }
767
amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device * adev,uint32_t * vcn_harvest_count)768 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
769 uint32_t *vcn_harvest_count)
770 {
771 uint8_t *discovery_bin = adev->discovery.bin;
772 struct binary_header *bhdr;
773 struct ip_discovery_header *ihdr;
774 struct die_header *dhdr;
775 struct ip *ip;
776 uint16_t die_offset, ip_offset, num_dies, num_ips;
777 uint16_t hw_id;
778 uint8_t inst;
779 int i, j;
780
781 bhdr = (struct binary_header *)discovery_bin;
782 ihdr = (struct ip_discovery_header
783 *)(discovery_bin +
784 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
785 num_dies = le16_to_cpu(ihdr->num_dies);
786
787 /* scan harvest bit of all IP data structures */
788 for (i = 0; i < num_dies; i++) {
789 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
790 dhdr = (struct die_header *)(discovery_bin + die_offset);
791 num_ips = le16_to_cpu(dhdr->num_ips);
792 ip_offset = die_offset + sizeof(*dhdr);
793
794 for (j = 0; j < num_ips; j++) {
795 ip = (struct ip *)(discovery_bin + ip_offset);
796 inst = ip->number_instance;
797 hw_id = le16_to_cpu(ip->hw_id);
798 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
799 goto next_ip;
800
801 if (ip->harvest == 1) {
802 switch (hw_id) {
803 case VCN_HWID:
804 (*vcn_harvest_count)++;
805 if (inst == 0) {
806 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
807 adev->vcn.inst_mask &=
808 ~AMDGPU_VCN_HARVEST_VCN0;
809 adev->jpeg.inst_mask &=
810 ~AMDGPU_VCN_HARVEST_VCN0;
811 } else {
812 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
813 adev->vcn.inst_mask &=
814 ~AMDGPU_VCN_HARVEST_VCN1;
815 adev->jpeg.inst_mask &=
816 ~AMDGPU_VCN_HARVEST_VCN1;
817 }
818 break;
819 case DMU_HWID:
820 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
821 break;
822 default:
823 break;
824 }
825 }
826 next_ip:
827 ip_offset += struct_size(ip, base_address,
828 ip->num_base_address);
829 }
830 }
831 }
832
amdgpu_discovery_read_from_harvest_table(struct amdgpu_device * adev,uint32_t * vcn_harvest_count,uint32_t * umc_harvest_count)833 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
834 uint32_t *vcn_harvest_count,
835 uint32_t *umc_harvest_count)
836 {
837 uint8_t *discovery_bin = adev->discovery.bin;
838 struct table_info *info;
839 struct harvest_table *harvest_info;
840 u16 offset;
841 int i;
842 u64 umc_harvest_config = 0;
843
844 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO))
845 return;
846 offset = le16_to_cpu(info->offset);
847
848 if (!offset) {
849 dev_err(adev->dev, "invalid harvest table offset\n");
850 return;
851 }
852
853 harvest_info = (struct harvest_table *)(discovery_bin + offset);
854
855 for (i = 0; i < 32; i++) {
856 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id);
857 u8 inst = harvest_info->list[i].number_instance;
858
859 if (hw_id == 0)
860 break;
861
862 if (inst >= 32) {
863 dev_warn(adev->dev,
864 "bogus harvest instance %u for hw_id %u\n",
865 inst, hw_id);
866 continue;
867 }
868
869 switch (hw_id) {
870 case VCN_HWID:
871 (*vcn_harvest_count)++;
872 adev->vcn.harvest_config |= BIT(inst);
873 adev->jpeg.harvest_config |= BIT(inst);
874
875 adev->vcn.inst_mask &= ~BIT(inst);
876 adev->jpeg.inst_mask &= ~BIT(inst);
877 break;
878 case DMU_HWID:
879 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
880 break;
881 case UMC_HWID:
882 umc_harvest_config |= BIT_ULL(inst);
883 (*umc_harvest_count)++;
884 break;
885 case GC_HWID:
886 adev->gfx.xcc_mask &= ~BIT(inst);
887 break;
888 case SDMA0_HWID:
889 adev->sdma.sdma_mask &= ~BIT(inst);
890 break;
891 #if defined(CONFIG_DRM_AMD_ISP)
892 case ISP_HWID:
893 adev->isp.harvest_config |= ~BIT(inst);
894 break;
895 #endif
896 default:
897 break;
898 }
899 }
900
901 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) &
902 ~umc_harvest_config;
903 }
904
905 /* ================================================== */
906
907 struct ip_hw_instance {
908 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
909
910 int hw_id;
911 u8 num_instance;
912 u8 major, minor, revision;
913 u8 harvest;
914
915 int num_base_addresses;
916 u32 base_addr[] __counted_by(num_base_addresses);
917 };
918
919 struct ip_hw_id {
920 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
921 int hw_id;
922 };
923
924 struct ip_die_entry {
925 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
926 u16 num_ips;
927 };
928
929 /* -------------------------------------------------- */
930
931 struct ip_hw_instance_attr {
932 struct attribute attr;
933 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
934 };
935
hw_id_show(struct ip_hw_instance * ip_hw_instance,char * buf)936 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
937 {
938 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
939 }
940
num_instance_show(struct ip_hw_instance * ip_hw_instance,char * buf)941 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
942 {
943 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
944 }
945
major_show(struct ip_hw_instance * ip_hw_instance,char * buf)946 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
947 {
948 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
949 }
950
minor_show(struct ip_hw_instance * ip_hw_instance,char * buf)951 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
952 {
953 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
954 }
955
revision_show(struct ip_hw_instance * ip_hw_instance,char * buf)956 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
957 {
958 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
959 }
960
harvest_show(struct ip_hw_instance * ip_hw_instance,char * buf)961 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
962 {
963 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
964 }
965
num_base_addresses_show(struct ip_hw_instance * ip_hw_instance,char * buf)966 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
967 {
968 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
969 }
970
base_addr_show(struct ip_hw_instance * ip_hw_instance,char * buf)971 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
972 {
973 ssize_t at;
974 int ii;
975
976 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
977 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
978 */
979 if (at + 12 > PAGE_SIZE)
980 break;
981 at += sysfs_emit_at(buf, at, "0x%08X\n",
982 ip_hw_instance->base_addr[ii]);
983 }
984
985 return at;
986 }
987
988 static struct ip_hw_instance_attr ip_hw_attr[] = {
989 __ATTR_RO(hw_id),
990 __ATTR_RO(num_instance),
991 __ATTR_RO(major),
992 __ATTR_RO(minor),
993 __ATTR_RO(revision),
994 __ATTR_RO(harvest),
995 __ATTR_RO(num_base_addresses),
996 __ATTR_RO(base_addr),
997 };
998
999 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
1000 ATTRIBUTE_GROUPS(ip_hw_instance);
1001
1002 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
1003 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
1004
ip_hw_instance_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1005 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
1006 struct attribute *attr,
1007 char *buf)
1008 {
1009 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1010 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
1011
1012 if (!ip_hw_attr->show)
1013 return -EIO;
1014
1015 return ip_hw_attr->show(ip_hw_instance, buf);
1016 }
1017
1018 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
1019 .show = ip_hw_instance_attr_show,
1020 };
1021
ip_hw_instance_release(struct kobject * kobj)1022 static void ip_hw_instance_release(struct kobject *kobj)
1023 {
1024 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1025
1026 kfree(ip_hw_instance);
1027 }
1028
1029 static const struct kobj_type ip_hw_instance_ktype = {
1030 .release = ip_hw_instance_release,
1031 .sysfs_ops = &ip_hw_instance_sysfs_ops,
1032 .default_groups = ip_hw_instance_groups,
1033 };
1034
1035 /* -------------------------------------------------- */
1036
1037 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
1038
ip_hw_id_release(struct kobject * kobj)1039 static void ip_hw_id_release(struct kobject *kobj)
1040 {
1041 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
1042
1043 if (!list_empty(&ip_hw_id->hw_id_kset.list))
1044 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
1045 kfree(ip_hw_id);
1046 }
1047
1048 static const struct kobj_type ip_hw_id_ktype = {
1049 .release = ip_hw_id_release,
1050 .sysfs_ops = &kobj_sysfs_ops,
1051 };
1052
1053 /* -------------------------------------------------- */
1054
1055 static void die_kobj_release(struct kobject *kobj);
1056 static void ip_disc_release(struct kobject *kobj);
1057
1058 struct ip_die_entry_attribute {
1059 struct attribute attr;
1060 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
1061 };
1062
1063 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
1064
num_ips_show(struct ip_die_entry * ip_die_entry,char * buf)1065 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
1066 {
1067 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
1068 }
1069
1070 /* If there are more ip_die_entry attrs, other than the number of IPs,
1071 * we can make this intro an array of attrs, and then initialize
1072 * ip_die_entry_attrs in a loop.
1073 */
1074 static struct ip_die_entry_attribute num_ips_attr =
1075 __ATTR_RO(num_ips);
1076
1077 static struct attribute *ip_die_entry_attrs[] = {
1078 &num_ips_attr.attr,
1079 NULL,
1080 };
1081 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
1082
1083 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
1084
ip_die_entry_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1085 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
1086 struct attribute *attr,
1087 char *buf)
1088 {
1089 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
1090 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1091
1092 if (!ip_die_entry_attr->show)
1093 return -EIO;
1094
1095 return ip_die_entry_attr->show(ip_die_entry, buf);
1096 }
1097
ip_die_entry_release(struct kobject * kobj)1098 static void ip_die_entry_release(struct kobject *kobj)
1099 {
1100 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1101
1102 if (!list_empty(&ip_die_entry->ip_kset.list))
1103 DRM_ERROR("ip_die_entry->ip_kset is not empty");
1104 kfree(ip_die_entry);
1105 }
1106
1107 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
1108 .show = ip_die_entry_attr_show,
1109 };
1110
1111 static const struct kobj_type ip_die_entry_ktype = {
1112 .release = ip_die_entry_release,
1113 .sysfs_ops = &ip_die_entry_sysfs_ops,
1114 .default_groups = ip_die_entry_groups,
1115 };
1116
1117 static const struct kobj_type die_kobj_ktype = {
1118 .release = die_kobj_release,
1119 .sysfs_ops = &kobj_sysfs_ops,
1120 };
1121
1122 static const struct kobj_type ip_discovery_ktype = {
1123 .release = ip_disc_release,
1124 .sysfs_ops = &kobj_sysfs_ops,
1125 };
1126
1127 struct ip_discovery_top {
1128 struct kobject kobj; /* ip_discovery/ */
1129 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */
1130 struct amdgpu_device *adev;
1131 };
1132
die_kobj_release(struct kobject * kobj)1133 static void die_kobj_release(struct kobject *kobj)
1134 {
1135 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
1136 struct ip_discovery_top,
1137 die_kset);
1138 if (!list_empty(&ip_top->die_kset.list))
1139 DRM_ERROR("ip_top->die_kset is not empty");
1140 }
1141
ip_disc_release(struct kobject * kobj)1142 static void ip_disc_release(struct kobject *kobj)
1143 {
1144 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
1145 kobj);
1146 struct amdgpu_device *adev = ip_top->adev;
1147
1148 kfree(ip_top);
1149 adev->discovery.ip_top = NULL;
1150 }
1151
amdgpu_discovery_get_harvest_info(struct amdgpu_device * adev,uint16_t hw_id,uint8_t inst)1152 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
1153 uint16_t hw_id, uint8_t inst)
1154 {
1155 uint8_t harvest = 0;
1156
1157 /* Until a uniform way is figured, get mask based on hwid */
1158 switch (hw_id) {
1159 case VCN_HWID:
1160 /* VCN vs UVD+VCE */
1161 if (!amdgpu_ip_version(adev, VCE_HWIP, 0))
1162 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
1163 break;
1164 case DMU_HWID:
1165 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
1166 harvest = 0x1;
1167 break;
1168 case UMC_HWID:
1169 /* TODO: It needs another parsing; for now, ignore.*/
1170 break;
1171 case GC_HWID:
1172 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1173 break;
1174 case SDMA0_HWID:
1175 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
1176 break;
1177 default:
1178 break;
1179 }
1180
1181 return harvest;
1182 }
1183
amdgpu_discovery_sysfs_ips(struct amdgpu_device * adev,struct ip_die_entry * ip_die_entry,const size_t _ip_offset,const int num_ips,bool reg_base_64)1184 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
1185 struct ip_die_entry *ip_die_entry,
1186 const size_t _ip_offset, const int num_ips,
1187 bool reg_base_64)
1188 {
1189 uint8_t *discovery_bin = adev->discovery.bin;
1190 int ii, jj, kk, res;
1191 uint16_t hw_id;
1192 uint8_t inst;
1193
1194 DRM_DEBUG("num_ips:%d", num_ips);
1195
1196 /* Find all IPs of a given HW ID, and add their instance to
1197 * #die/#hw_id/#instance/<attributes>
1198 */
1199 for (ii = 0; ii < HW_ID_MAX; ii++) {
1200 struct ip_hw_id *ip_hw_id = NULL;
1201 size_t ip_offset = _ip_offset;
1202
1203 for (jj = 0; jj < num_ips; jj++) {
1204 struct ip_v4 *ip;
1205 struct ip_hw_instance *ip_hw_instance;
1206
1207 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1208 inst = ip->instance_number;
1209 hw_id = le16_to_cpu(ip->hw_id);
1210 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||
1211 hw_id != ii)
1212 goto next_ip;
1213
1214 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
1215
1216 /* We have a hw_id match; register the hw
1217 * block if not yet registered.
1218 */
1219 if (!ip_hw_id) {
1220 ip_hw_id = kzalloc_obj(*ip_hw_id);
1221 if (!ip_hw_id)
1222 return -ENOMEM;
1223 ip_hw_id->hw_id = ii;
1224
1225 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
1226 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
1227 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
1228 res = kset_register(&ip_hw_id->hw_id_kset);
1229 if (res) {
1230 DRM_ERROR("Couldn't register ip_hw_id kset");
1231 kfree(ip_hw_id);
1232 return res;
1233 }
1234 if (hw_id_names[ii]) {
1235 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
1236 &ip_hw_id->hw_id_kset.kobj,
1237 hw_id_names[ii]);
1238 if (res) {
1239 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
1240 hw_id_names[ii],
1241 kobject_name(&ip_die_entry->ip_kset.kobj));
1242 }
1243 }
1244 }
1245
1246 /* Now register its instance.
1247 */
1248 ip_hw_instance = kzalloc_flex(*ip_hw_instance,
1249 base_addr,
1250 ip->num_base_address);
1251 if (!ip_hw_instance) {
1252 DRM_ERROR("no memory for ip_hw_instance");
1253 return -ENOMEM;
1254 }
1255 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1256 ip_hw_instance->num_instance = ip->instance_number;
1257 ip_hw_instance->major = ip->major;
1258 ip_hw_instance->minor = ip->minor;
1259 ip_hw_instance->revision = ip->revision;
1260 ip_hw_instance->harvest =
1261 amdgpu_discovery_get_harvest_info(
1262 adev, ip_hw_instance->hw_id,
1263 ip_hw_instance->num_instance);
1264 ip_hw_instance->num_base_addresses = ip->num_base_address;
1265
1266 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
1267 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1268
1269 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1270 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1271 res = kobject_add(&ip_hw_instance->kobj, NULL,
1272 "%d", ip_hw_instance->num_instance);
1273 next_ip:
1274 if (reg_base_64)
1275 ip_offset += struct_size(ip, base_address_64,
1276 ip->num_base_address);
1277 else
1278 ip_offset += struct_size(ip, base_address,
1279 ip->num_base_address);
1280 }
1281 }
1282
1283 return 0;
1284 }
1285
amdgpu_discovery_sysfs_recurse(struct amdgpu_device * adev)1286 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
1287 {
1288 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1289 uint8_t *discovery_bin = adev->discovery.bin;
1290 struct table_info *info;
1291 struct ip_discovery_header *ihdr;
1292 struct die_header *dhdr;
1293 struct kset *die_kset = &ip_top->die_kset;
1294 u16 num_dies, die_offset, num_ips;
1295 size_t ip_offset;
1296 int ii, res;
1297
1298 res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY);
1299 if (res)
1300 return res;
1301 ihdr = (struct ip_discovery_header
1302 *)(discovery_bin +
1303 le16_to_cpu(info->offset));
1304 num_dies = le16_to_cpu(ihdr->num_dies);
1305
1306 DRM_DEBUG("number of dies: %d\n", num_dies);
1307
1308 for (ii = 0; ii < num_dies; ii++) {
1309 struct ip_die_entry *ip_die_entry;
1310
1311 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1312 dhdr = (struct die_header *)(discovery_bin + die_offset);
1313 num_ips = le16_to_cpu(dhdr->num_ips);
1314 ip_offset = die_offset + sizeof(*dhdr);
1315
1316 /* Add the die to the kset.
1317 *
1318 * dhdr->die_id == ii, which was checked in
1319 * amdgpu_discovery_reg_base_init().
1320 */
1321
1322 ip_die_entry = kzalloc_obj(*ip_die_entry);
1323 if (!ip_die_entry)
1324 return -ENOMEM;
1325
1326 ip_die_entry->num_ips = num_ips;
1327
1328 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1329 ip_die_entry->ip_kset.kobj.kset = die_kset;
1330 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1331 res = kset_register(&ip_die_entry->ip_kset);
1332 if (res) {
1333 DRM_ERROR("Couldn't register ip_die_entry kset");
1334 kfree(ip_die_entry);
1335 return res;
1336 }
1337
1338 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit);
1339 }
1340
1341 return 0;
1342 }
1343
amdgpu_discovery_sysfs_init(struct amdgpu_device * adev)1344 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1345 {
1346 uint8_t *discovery_bin = adev->discovery.bin;
1347 struct ip_discovery_top *ip_top;
1348 struct kset *die_kset;
1349 int res, ii;
1350
1351 if (!discovery_bin)
1352 return -EINVAL;
1353
1354 ip_top = kzalloc_obj(*ip_top);
1355 if (!ip_top)
1356 return -ENOMEM;
1357
1358 ip_top->adev = adev;
1359 adev->discovery.ip_top = ip_top;
1360 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1361 &adev->dev->kobj, "ip_discovery");
1362 if (res) {
1363 DRM_ERROR("Couldn't init and add ip_discovery/");
1364 goto Err;
1365 }
1366
1367 die_kset = &ip_top->die_kset;
1368 kobject_set_name(&die_kset->kobj, "%s", "die");
1369 die_kset->kobj.parent = &ip_top->kobj;
1370 die_kset->kobj.ktype = &die_kobj_ktype;
1371 res = kset_register(&ip_top->die_kset);
1372 if (res) {
1373 DRM_ERROR("Couldn't register die_kset");
1374 goto Err;
1375 }
1376
1377 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1378 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1379 ip_hw_instance_attrs[ii] = NULL;
1380
1381 res = amdgpu_discovery_sysfs_recurse(adev);
1382
1383 return res;
1384 Err:
1385 kobject_put(&ip_top->kobj);
1386 return res;
1387 }
1388
1389 /* -------------------------------------------------- */
1390
1391 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1392
amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id * ip_hw_id)1393 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1394 {
1395 struct list_head *el, *tmp;
1396 struct kset *hw_id_kset;
1397
1398 hw_id_kset = &ip_hw_id->hw_id_kset;
1399 spin_lock(&hw_id_kset->list_lock);
1400 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1401 list_del_init(el);
1402 spin_unlock(&hw_id_kset->list_lock);
1403 /* kobject is embedded in ip_hw_instance */
1404 kobject_put(list_to_kobj(el));
1405 spin_lock(&hw_id_kset->list_lock);
1406 }
1407 spin_unlock(&hw_id_kset->list_lock);
1408 kobject_put(&ip_hw_id->hw_id_kset.kobj);
1409 }
1410
amdgpu_discovery_sysfs_die_free(struct ip_die_entry * ip_die_entry)1411 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1412 {
1413 struct list_head *el, *tmp;
1414 struct kset *ip_kset;
1415
1416 ip_kset = &ip_die_entry->ip_kset;
1417 spin_lock(&ip_kset->list_lock);
1418 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1419 list_del_init(el);
1420 spin_unlock(&ip_kset->list_lock);
1421 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1422 spin_lock(&ip_kset->list_lock);
1423 }
1424 spin_unlock(&ip_kset->list_lock);
1425 kobject_put(&ip_die_entry->ip_kset.kobj);
1426 }
1427
amdgpu_discovery_sysfs_fini(struct amdgpu_device * adev)1428 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1429 {
1430 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1431 struct list_head *el, *tmp;
1432 struct kset *die_kset;
1433
1434 if (!ip_top)
1435 return;
1436
1437 die_kset = &ip_top->die_kset;
1438 spin_lock(&die_kset->list_lock);
1439 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1440 list_del_init(el);
1441 spin_unlock(&die_kset->list_lock);
1442 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1443 spin_lock(&die_kset->list_lock);
1444 }
1445 spin_unlock(&die_kset->list_lock);
1446 kobject_put(&ip_top->die_kset.kobj);
1447 kobject_put(&ip_top->kobj);
1448 }
1449
1450 /* devcoredump support */
amdgpu_discovery_dump(struct amdgpu_device * adev,struct drm_printer * p)1451 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p)
1452 {
1453 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1454 struct ip_die_entry *ip_die_entry;
1455 struct list_head *el_die, *el_hw_id, *el_hw_inst;
1456 struct ip_hw_id *hw_id;
1457 struct kset *die_kset;
1458 struct ip_hw_instance *ip_inst;
1459 int i = 0, j;
1460
1461 if (!ip_top)
1462 return;
1463
1464 die_kset = &ip_top->die_kset;
1465
1466 drm_printf(p, "\nHW IP Discovery\n");
1467
1468 spin_lock(&die_kset->list_lock);
1469 list_for_each(el_die, &die_kset->list) {
1470 drm_printf(p, "die %d\n", i++);
1471 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die));
1472
1473 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) {
1474 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id));
1475 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]);
1476
1477 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) {
1478 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst));
1479 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance);
1480 drm_printf(p, "\tmajor %d\n", ip_inst->major);
1481 drm_printf(p, "\tminor %d\n", ip_inst->minor);
1482 drm_printf(p, "\trevision %d\n", ip_inst->revision);
1483 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest);
1484 drm_printf(p, "\tnum_base_addresses %d\n",
1485 ip_inst->num_base_addresses);
1486 for (j = 0; j < ip_inst->num_base_addresses; j++)
1487 drm_printf(p, "\tbase_addr[%d] 0x%08X\n",
1488 j, ip_inst->base_addr[j]);
1489 }
1490 }
1491 }
1492 spin_unlock(&die_kset->list_lock);
1493 }
1494
1495
1496 /* ================================================== */
1497
amdgpu_discovery_reg_base_init(struct amdgpu_device * adev)1498 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1499 {
1500 uint8_t num_base_address, subrev, variant;
1501 struct table_info *info;
1502 struct ip_discovery_header *ihdr;
1503 struct die_header *dhdr;
1504 uint8_t *discovery_bin;
1505 struct ip_v4 *ip;
1506 uint16_t die_offset;
1507 uint16_t ip_offset;
1508 uint16_t num_dies;
1509 uint32_t wafl_ver;
1510 uint16_t num_ips;
1511 uint16_t hw_id;
1512 uint8_t inst;
1513 int hw_ip;
1514 int i, j, k;
1515 int r;
1516
1517 r = amdgpu_discovery_init(adev);
1518 if (r)
1519 return r;
1520 discovery_bin = adev->discovery.bin;
1521 wafl_ver = 0;
1522 adev->gfx.xcc_mask = 0;
1523 adev->sdma.sdma_mask = 0;
1524 adev->vcn.inst_mask = 0;
1525 adev->jpeg.inst_mask = 0;
1526 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY);
1527 if (r)
1528 return r;
1529 ihdr = (struct ip_discovery_header
1530 *)(discovery_bin +
1531 le16_to_cpu(info->offset));
1532 num_dies = le16_to_cpu(ihdr->num_dies);
1533
1534 DRM_DEBUG("number of dies: %d\n", num_dies);
1535
1536 for (i = 0; i < num_dies; i++) {
1537 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1538 dhdr = (struct die_header *)(discovery_bin + die_offset);
1539 num_ips = le16_to_cpu(dhdr->num_ips);
1540 ip_offset = die_offset + sizeof(*dhdr);
1541
1542 if (le16_to_cpu(dhdr->die_id) != i) {
1543 DRM_ERROR("invalid die id %d, expected %d\n",
1544 le16_to_cpu(dhdr->die_id), i);
1545 return -EINVAL;
1546 }
1547
1548 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1549 le16_to_cpu(dhdr->die_id), num_ips);
1550
1551 for (j = 0; j < num_ips; j++) {
1552 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1553
1554 inst = ip->instance_number;
1555 hw_id = le16_to_cpu(ip->hw_id);
1556 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
1557 goto next_ip;
1558
1559 num_base_address = ip->num_base_address;
1560
1561 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1562 hw_id_names[le16_to_cpu(ip->hw_id)],
1563 le16_to_cpu(ip->hw_id),
1564 ip->instance_number,
1565 ip->major, ip->minor,
1566 ip->revision);
1567
1568 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1569 /* Bit [5:0]: original revision value
1570 * Bit [7:6]: en/decode capability:
1571 * 0b00 : VCN function normally
1572 * 0b10 : encode is disabled
1573 * 0b01 : decode is disabled
1574 */
1575 if (adev->vcn.num_vcn_inst <
1576 AMDGPU_MAX_VCN_INSTANCES) {
1577 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
1578 ip->revision & 0xc0;
1579 adev->vcn.num_vcn_inst++;
1580 adev->vcn.inst_mask |=
1581 (1U << ip->instance_number);
1582 adev->jpeg.inst_mask |=
1583 (1U << ip->instance_number);
1584 } else {
1585 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1586 adev->vcn.num_vcn_inst + 1,
1587 AMDGPU_MAX_VCN_INSTANCES);
1588 }
1589 ip->revision &= ~0xc0;
1590 }
1591 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1592 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1593 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1594 le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1595 if (adev->sdma.num_instances <
1596 AMDGPU_MAX_SDMA_INSTANCES) {
1597 adev->sdma.num_instances++;
1598 adev->sdma.sdma_mask |=
1599 (1U << ip->instance_number);
1600 } else {
1601 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1602 adev->sdma.num_instances + 1,
1603 AMDGPU_MAX_SDMA_INSTANCES);
1604 }
1605 }
1606
1607 if (le16_to_cpu(ip->hw_id) == VPE_HWID) {
1608 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)
1609 adev->vpe.num_instances++;
1610 else
1611 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n",
1612 adev->vpe.num_instances + 1,
1613 AMDGPU_MAX_VPE_INSTANCES);
1614 }
1615
1616 if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1617 adev->gmc.num_umc++;
1618 adev->umc.node_inst_num++;
1619 }
1620
1621 if (le16_to_cpu(ip->hw_id) == GC_HWID)
1622 adev->gfx.xcc_mask |=
1623 (1U << ip->instance_number);
1624
1625 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID)
1626 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor,
1627 ip->revision, 0, 0);
1628
1629 for (k = 0; k < num_base_address; k++) {
1630 /*
1631 * convert the endianness of base addresses in place,
1632 * so that we don't need to convert them when accessing adev->reg_offset.
1633 */
1634 if (ihdr->base_addr_64_bit)
1635 /* Truncate the 64bit base address from ip discovery
1636 * and only store lower 32bit ip base in reg_offset[].
1637 * Bits > 32 follows ASIC specific format, thus just
1638 * discard them and handle it within specific ASIC.
1639 * By this way reg_offset[] and related helpers can
1640 * stay unchanged.
1641 * The base address is in dwords, thus clear the
1642 * highest 2 bits to store.
1643 */
1644 ip->base_address[k] =
1645 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1646 else
1647 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1648 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1649 }
1650
1651 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1652 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1653 hw_id_map[hw_ip] != 0) {
1654 DRM_DEBUG("set register base offset for %s\n",
1655 hw_id_names[le16_to_cpu(ip->hw_id)]);
1656 adev->reg_offset[hw_ip][ip->instance_number] =
1657 ip->base_address;
1658 /* Instance support is somewhat inconsistent.
1659 * SDMA is a good example. Sienna cichlid has 4 total
1660 * SDMA instances, each enumerated separately (HWIDs
1661 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1662 * but they are enumerated as multiple instances of the
1663 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1664 * example. On most chips there are multiple instances
1665 * with the same HWID.
1666 */
1667
1668 if (ihdr->version < 3) {
1669 subrev = 0;
1670 variant = 0;
1671 } else {
1672 subrev = ip->sub_revision;
1673 variant = ip->variant;
1674 }
1675
1676 adev->ip_versions[hw_ip]
1677 [ip->instance_number] =
1678 IP_VERSION_FULL(ip->major,
1679 ip->minor,
1680 ip->revision,
1681 variant,
1682 subrev);
1683 }
1684 }
1685
1686 next_ip:
1687 if (ihdr->base_addr_64_bit)
1688 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1689 else
1690 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1691 }
1692 }
1693
1694 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0])
1695 adev->ip_versions[XGMI_HWIP][0] = wafl_ver;
1696
1697 return 0;
1698 }
1699
amdgpu_discovery_harvest_ip(struct amdgpu_device * adev)1700 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1701 {
1702 uint8_t *discovery_bin = adev->discovery.bin;
1703 struct ip_discovery_header *ihdr;
1704 struct table_info *info;
1705 int vcn_harvest_count = 0;
1706 int umc_harvest_count = 0;
1707 uint16_t ihdr_ver;
1708
1709 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY))
1710 return;
1711 ihdr = (struct ip_discovery_header *)(discovery_bin +
1712 le16_to_cpu(info->offset));
1713 ihdr_ver = le16_to_cpu(ihdr->version);
1714 /*
1715 * Harvest table does not fit Navi1x and legacy GPUs,
1716 * so read harvest bit per IP data structure to set
1717 * harvest configuration.
1718 */
1719 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1720 ihdr_ver <= 2) {
1721 if ((adev->pdev->device == 0x731E &&
1722 (adev->pdev->revision == 0xC6 ||
1723 adev->pdev->revision == 0xC7)) ||
1724 (adev->pdev->device == 0x7340 &&
1725 adev->pdev->revision == 0xC9) ||
1726 (adev->pdev->device == 0x7360 &&
1727 adev->pdev->revision == 0xC7))
1728 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1729 &vcn_harvest_count);
1730 } else {
1731 amdgpu_discovery_read_from_harvest_table(adev,
1732 &vcn_harvest_count,
1733 &umc_harvest_count);
1734 }
1735
1736 amdgpu_discovery_harvest_config_quirk(adev);
1737
1738 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1739 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1740 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1741 }
1742
1743 if (umc_harvest_count < adev->gmc.num_umc) {
1744 adev->gmc.num_umc -= umc_harvest_count;
1745 }
1746 }
1747
1748 union gc_info {
1749 struct gc_info_v1_0 v1;
1750 struct gc_info_v1_1 v1_1;
1751 struct gc_info_v1_2 v1_2;
1752 struct gc_info_v1_3 v1_3;
1753 struct gc_info_v2_0 v2;
1754 struct gc_info_v2_1 v2_1;
1755 };
1756
amdgpu_discovery_get_gfx_info(struct amdgpu_device * adev)1757 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1758 {
1759 uint8_t *discovery_bin = adev->discovery.bin;
1760 struct table_info *info;
1761 union gc_info *gc_info;
1762 u16 offset;
1763
1764 if (!discovery_bin) {
1765 DRM_ERROR("ip discovery uninitialized\n");
1766 return -EINVAL;
1767 }
1768
1769 if (amdgpu_discovery_get_table_info(adev, &info, GC))
1770 return -EINVAL;
1771 offset = le16_to_cpu(info->offset);
1772
1773 if (!offset)
1774 return 0;
1775
1776 gc_info = (union gc_info *)(discovery_bin + offset);
1777
1778 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1779 case 1:
1780 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1781 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1782 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1783 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1784 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1785 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1786 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1787 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1788 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1789 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1790 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1791 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1792 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1793 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1794 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1795 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1796 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1797 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1798 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
1799 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1800 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1801 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1802 }
1803 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
1804 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1805 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1806 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1807 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1808 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1809 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1810 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1811 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1812 }
1813 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
1814 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
1815 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
1816 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
1817 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
1818 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
1819 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
1820 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
1821 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
1822 }
1823 break;
1824 case 2:
1825 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1826 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1827 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1828 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1829 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1830 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1831 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1832 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1833 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1834 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1835 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1836 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1837 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1838 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1839 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1840 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1841 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1842 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) {
1843 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
1844 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
1845 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
1846 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
1847 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
1848 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
1849 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
1850 }
1851 break;
1852 default:
1853 dev_err(adev->dev,
1854 "Unhandled GC info table %d.%d\n",
1855 le16_to_cpu(gc_info->v1.header.version_major),
1856 le16_to_cpu(gc_info->v1.header.version_minor));
1857 return -EINVAL;
1858 }
1859 return 0;
1860 }
1861
1862 union mall_info {
1863 struct mall_info_v1_0 v1;
1864 struct mall_info_v2_0 v2;
1865 };
1866
amdgpu_discovery_get_mall_info(struct amdgpu_device * adev)1867 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1868 {
1869 uint8_t *discovery_bin = adev->discovery.bin;
1870 struct table_info *info;
1871 union mall_info *mall_info;
1872 u32 u, mall_size_per_umc, m_s_present, half_use;
1873 u64 mall_size;
1874 u16 offset;
1875
1876 if (!discovery_bin) {
1877 DRM_ERROR("ip discovery uninitialized\n");
1878 return -EINVAL;
1879 }
1880
1881 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO))
1882 return -EINVAL;
1883 offset = le16_to_cpu(info->offset);
1884
1885 if (!offset)
1886 return 0;
1887
1888 mall_info = (union mall_info *)(discovery_bin + offset);
1889
1890 switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1891 case 1:
1892 mall_size = 0;
1893 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1894 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1895 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1896 for (u = 0; u < adev->gmc.num_umc; u++) {
1897 if (m_s_present & (1 << u))
1898 mall_size += mall_size_per_umc * 2;
1899 else if (half_use & (1 << u))
1900 mall_size += mall_size_per_umc / 2;
1901 else
1902 mall_size += mall_size_per_umc;
1903 }
1904 adev->gmc.mall_size = mall_size;
1905 adev->gmc.m_half_use = half_use;
1906 break;
1907 case 2:
1908 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
1909 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc;
1910 break;
1911 default:
1912 dev_err(adev->dev,
1913 "Unhandled MALL info table %d.%d\n",
1914 le16_to_cpu(mall_info->v1.header.version_major),
1915 le16_to_cpu(mall_info->v1.header.version_minor));
1916 return -EINVAL;
1917 }
1918 return 0;
1919 }
1920
1921 union vcn_info {
1922 struct vcn_info_v1_0 v1;
1923 };
1924
amdgpu_discovery_get_vcn_info(struct amdgpu_device * adev)1925 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1926 {
1927 uint8_t *discovery_bin = adev->discovery.bin;
1928 struct table_info *info;
1929 union vcn_info *vcn_info;
1930 u16 offset;
1931 int v;
1932
1933 if (!discovery_bin) {
1934 DRM_ERROR("ip discovery uninitialized\n");
1935 return -EINVAL;
1936 }
1937
1938 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1939 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
1940 * but that may change in the future with new GPUs so keep this
1941 * check for defensive purposes.
1942 */
1943 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1944 dev_err(adev->dev, "invalid vcn instances\n");
1945 return -EINVAL;
1946 }
1947
1948 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO))
1949 return -EINVAL;
1950 offset = le16_to_cpu(info->offset);
1951
1952 if (!offset)
1953 return 0;
1954
1955 vcn_info = (union vcn_info *)(discovery_bin + offset);
1956
1957 switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1958 case 1:
1959 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1960 * so this won't overflow.
1961 */
1962 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1963 adev->vcn.inst[v].vcn_codec_disable_mask =
1964 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1965 }
1966 break;
1967 default:
1968 dev_err(adev->dev,
1969 "Unhandled VCN info table %d.%d\n",
1970 le16_to_cpu(vcn_info->v1.header.version_major),
1971 le16_to_cpu(vcn_info->v1.header.version_minor));
1972 return -EINVAL;
1973 }
1974 return 0;
1975 }
1976
1977 union nps_info {
1978 struct nps_info_v1_0 v1;
1979 };
1980
amdgpu_discovery_refresh_nps_info(struct amdgpu_device * adev,union nps_info * nps_data)1981 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev,
1982 union nps_info *nps_data)
1983 {
1984 uint64_t vram_size, pos, offset;
1985 struct nps_info_header *nhdr;
1986 struct binary_header bhdr;
1987 struct binary_header_v2 bhdrv2;
1988 uint16_t checksum;
1989
1990 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
1991 pos = vram_size - DISCOVERY_TMR_OFFSET;
1992 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
1993
1994 switch (bhdr.version_major) {
1995 case 2:
1996 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false);
1997 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset);
1998 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum);
1999 break;
2000 case 1:
2001 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset);
2002 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum);
2003 break;
2004 default:
2005 return -EINVAL;
2006 }
2007
2008 amdgpu_device_vram_access(adev, (pos + offset), nps_data,
2009 sizeof(*nps_data), false);
2010
2011 nhdr = (struct nps_info_header *)(nps_data);
2012 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data,
2013 le32_to_cpu(nhdr->size_bytes),
2014 checksum)) {
2015 dev_err(adev->dev, "nps data refresh, checksum mismatch\n");
2016 return -EINVAL;
2017 }
2018
2019 return 0;
2020 }
2021
amdgpu_discovery_get_nps_info(struct amdgpu_device * adev,uint32_t * nps_type,struct amdgpu_gmc_memrange * ranges,int * range_cnt,bool refresh)2022 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
2023 uint32_t *nps_type,
2024 struct amdgpu_gmc_memrange *ranges,
2025 int *range_cnt, bool refresh)
2026 {
2027 uint8_t *discovery_bin = adev->discovery.bin;
2028 struct table_info *info;
2029 union nps_info *nps_info;
2030 union nps_info nps_data;
2031 u16 offset;
2032 int i, r;
2033
2034 if (!nps_type || !range_cnt || !ranges)
2035 return -EINVAL;
2036
2037 if (refresh) {
2038 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data);
2039 if (r)
2040 return r;
2041 nps_info = &nps_data;
2042 } else {
2043 if (!discovery_bin) {
2044 dev_err(adev->dev,
2045 "fetch mem range failed, ip discovery uninitialized\n");
2046 return -EINVAL;
2047 }
2048
2049 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO))
2050 return -EINVAL;
2051 offset = le16_to_cpu(info->offset);
2052
2053 if (!offset)
2054 return -ENOENT;
2055
2056 /* If verification fails, return as if NPS table doesn't exist */
2057 if (amdgpu_discovery_verify_npsinfo(adev, info))
2058 return -ENOENT;
2059
2060 nps_info = (union nps_info *)(discovery_bin + offset);
2061 }
2062
2063 switch (le16_to_cpu(nps_info->v1.header.version_major)) {
2064 case 1:
2065 *nps_type = nps_info->v1.nps_type;
2066 if (*range_cnt < nps_info->v1.count) {
2067 dev_dbg(adev->dev,
2068 "not enough space for nps ranges: %d < %d\n",
2069 *range_cnt, nps_info->v1.count);
2070 return -ENOSPC;
2071 }
2072 *range_cnt = nps_info->v1.count;
2073 for (i = 0; i < *range_cnt; i++) {
2074 ranges[i].base_address =
2075 nps_info->v1.instance_info[i].base_address;
2076 ranges[i].limit_address =
2077 nps_info->v1.instance_info[i].limit_address;
2078 ranges[i].nid_mask = -1;
2079 ranges[i].flags = 0;
2080 }
2081 break;
2082 default:
2083 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
2084 le16_to_cpu(nps_info->v1.header.version_major),
2085 le16_to_cpu(nps_info->v1.header.version_minor));
2086 return -EINVAL;
2087 }
2088
2089 return 0;
2090 }
2091
amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device * adev)2092 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
2093 {
2094 /* what IP to use for this? */
2095 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2096 case IP_VERSION(9, 0, 1):
2097 case IP_VERSION(9, 1, 0):
2098 case IP_VERSION(9, 2, 1):
2099 case IP_VERSION(9, 2, 2):
2100 case IP_VERSION(9, 3, 0):
2101 case IP_VERSION(9, 4, 0):
2102 case IP_VERSION(9, 4, 1):
2103 case IP_VERSION(9, 4, 2):
2104 case IP_VERSION(9, 4, 3):
2105 case IP_VERSION(9, 4, 4):
2106 case IP_VERSION(9, 5, 0):
2107 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
2108 break;
2109 case IP_VERSION(10, 1, 10):
2110 case IP_VERSION(10, 1, 1):
2111 case IP_VERSION(10, 1, 2):
2112 case IP_VERSION(10, 1, 3):
2113 case IP_VERSION(10, 1, 4):
2114 case IP_VERSION(10, 3, 0):
2115 case IP_VERSION(10, 3, 1):
2116 case IP_VERSION(10, 3, 2):
2117 case IP_VERSION(10, 3, 3):
2118 case IP_VERSION(10, 3, 4):
2119 case IP_VERSION(10, 3, 5):
2120 case IP_VERSION(10, 3, 6):
2121 case IP_VERSION(10, 3, 7):
2122 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
2123 break;
2124 case IP_VERSION(11, 0, 0):
2125 case IP_VERSION(11, 0, 1):
2126 case IP_VERSION(11, 0, 2):
2127 case IP_VERSION(11, 0, 3):
2128 case IP_VERSION(11, 0, 4):
2129 case IP_VERSION(11, 5, 0):
2130 case IP_VERSION(11, 5, 1):
2131 case IP_VERSION(11, 5, 2):
2132 case IP_VERSION(11, 5, 3):
2133 case IP_VERSION(11, 5, 4):
2134 case IP_VERSION(11, 5, 6):
2135 case IP_VERSION(11, 7, 0):
2136 case IP_VERSION(11, 7, 1):
2137 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
2138 break;
2139 case IP_VERSION(12, 0, 0):
2140 case IP_VERSION(12, 0, 1):
2141 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block);
2142 break;
2143 case IP_VERSION(12, 1, 0):
2144 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block);
2145 break;
2146 default:
2147 dev_err(adev->dev,
2148 "Failed to add common ip block(GC_HWIP:0x%x)\n",
2149 amdgpu_ip_version(adev, GC_HWIP, 0));
2150 return -EINVAL;
2151 }
2152 return 0;
2153 }
2154
amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device * adev)2155 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
2156 {
2157 /* use GC or MMHUB IP version */
2158 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2159 case IP_VERSION(9, 0, 1):
2160 case IP_VERSION(9, 1, 0):
2161 case IP_VERSION(9, 2, 1):
2162 case IP_VERSION(9, 2, 2):
2163 case IP_VERSION(9, 3, 0):
2164 case IP_VERSION(9, 4, 0):
2165 case IP_VERSION(9, 4, 1):
2166 case IP_VERSION(9, 4, 2):
2167 case IP_VERSION(9, 4, 3):
2168 case IP_VERSION(9, 4, 4):
2169 case IP_VERSION(9, 5, 0):
2170 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2171 break;
2172 case IP_VERSION(10, 1, 10):
2173 case IP_VERSION(10, 1, 1):
2174 case IP_VERSION(10, 1, 2):
2175 case IP_VERSION(10, 1, 3):
2176 case IP_VERSION(10, 1, 4):
2177 case IP_VERSION(10, 3, 0):
2178 case IP_VERSION(10, 3, 1):
2179 case IP_VERSION(10, 3, 2):
2180 case IP_VERSION(10, 3, 3):
2181 case IP_VERSION(10, 3, 4):
2182 case IP_VERSION(10, 3, 5):
2183 case IP_VERSION(10, 3, 6):
2184 case IP_VERSION(10, 3, 7):
2185 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
2186 break;
2187 case IP_VERSION(11, 0, 0):
2188 case IP_VERSION(11, 0, 1):
2189 case IP_VERSION(11, 0, 2):
2190 case IP_VERSION(11, 0, 3):
2191 case IP_VERSION(11, 0, 4):
2192 case IP_VERSION(11, 5, 0):
2193 case IP_VERSION(11, 5, 1):
2194 case IP_VERSION(11, 5, 2):
2195 case IP_VERSION(11, 5, 3):
2196 case IP_VERSION(11, 5, 4):
2197 case IP_VERSION(11, 5, 6):
2198 case IP_VERSION(11, 7, 0):
2199 case IP_VERSION(11, 7, 1):
2200 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
2201 break;
2202 case IP_VERSION(12, 0, 0):
2203 case IP_VERSION(12, 0, 1):
2204 case IP_VERSION(12, 1, 0):
2205 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block);
2206 break;
2207 default:
2208 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
2209 amdgpu_ip_version(adev, GC_HWIP, 0));
2210 return -EINVAL;
2211 }
2212 return 0;
2213 }
2214
amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device * adev)2215 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
2216 {
2217 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
2218 case IP_VERSION(4, 0, 0):
2219 case IP_VERSION(4, 0, 1):
2220 case IP_VERSION(4, 1, 0):
2221 case IP_VERSION(4, 1, 1):
2222 case IP_VERSION(4, 3, 0):
2223 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
2224 break;
2225 case IP_VERSION(4, 2, 0):
2226 case IP_VERSION(4, 2, 1):
2227 case IP_VERSION(4, 4, 0):
2228 case IP_VERSION(4, 4, 2):
2229 case IP_VERSION(4, 4, 5):
2230 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
2231 break;
2232 case IP_VERSION(5, 0, 0):
2233 case IP_VERSION(5, 0, 1):
2234 case IP_VERSION(5, 0, 2):
2235 case IP_VERSION(5, 0, 3):
2236 case IP_VERSION(5, 2, 0):
2237 case IP_VERSION(5, 2, 1):
2238 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
2239 break;
2240 case IP_VERSION(6, 0, 0):
2241 case IP_VERSION(6, 0, 1):
2242 case IP_VERSION(6, 0, 2):
2243 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
2244 break;
2245 case IP_VERSION(6, 1, 0):
2246 case IP_VERSION(6, 1, 1):
2247 case IP_VERSION(6, 4, 0):
2248 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
2249 break;
2250 case IP_VERSION(7, 0, 0):
2251 case IP_VERSION(7, 1, 0):
2252 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block);
2253 break;
2254 default:
2255 dev_err(adev->dev,
2256 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
2257 amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
2258 return -EINVAL;
2259 }
2260 return 0;
2261 }
2262
amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device * adev)2263 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
2264 {
2265 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2266 case IP_VERSION(9, 0, 0):
2267 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
2268 break;
2269 case IP_VERSION(10, 0, 0):
2270 case IP_VERSION(10, 0, 1):
2271 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
2272 break;
2273 case IP_VERSION(11, 0, 0):
2274 case IP_VERSION(11, 0, 2):
2275 case IP_VERSION(11, 0, 4):
2276 case IP_VERSION(11, 0, 5):
2277 case IP_VERSION(11, 0, 9):
2278 case IP_VERSION(11, 0, 7):
2279 case IP_VERSION(11, 0, 11):
2280 case IP_VERSION(11, 0, 12):
2281 case IP_VERSION(11, 0, 13):
2282 case IP_VERSION(11, 5, 0):
2283 case IP_VERSION(11, 5, 2):
2284 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
2285 break;
2286 case IP_VERSION(11, 0, 8):
2287 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
2288 break;
2289 case IP_VERSION(11, 0, 3):
2290 case IP_VERSION(12, 0, 1):
2291 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
2292 break;
2293 case IP_VERSION(13, 0, 0):
2294 case IP_VERSION(13, 0, 1):
2295 case IP_VERSION(13, 0, 2):
2296 case IP_VERSION(13, 0, 3):
2297 case IP_VERSION(13, 0, 5):
2298 case IP_VERSION(13, 0, 6):
2299 case IP_VERSION(13, 0, 7):
2300 case IP_VERSION(13, 0, 8):
2301 case IP_VERSION(13, 0, 10):
2302 case IP_VERSION(13, 0, 11):
2303 case IP_VERSION(13, 0, 12):
2304 case IP_VERSION(13, 0, 14):
2305 case IP_VERSION(13, 0, 15):
2306 case IP_VERSION(14, 0, 0):
2307 case IP_VERSION(14, 0, 1):
2308 case IP_VERSION(14, 0, 4):
2309 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
2310 break;
2311 case IP_VERSION(13, 0, 4):
2312 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
2313 break;
2314 case IP_VERSION(14, 0, 2):
2315 case IP_VERSION(14, 0, 3):
2316 case IP_VERSION(14, 0, 5):
2317 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
2318 break;
2319 case IP_VERSION(15, 0, 0):
2320 case IP_VERSION(15, 0, 5):
2321 case IP_VERSION(15, 0, 9):
2322 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block);
2323 break;
2324 case IP_VERSION(15, 0, 8):
2325 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block);
2326 break;
2327 default:
2328 dev_err(adev->dev,
2329 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
2330 amdgpu_ip_version(adev, MP0_HWIP, 0));
2331 return -EINVAL;
2332 }
2333 return 0;
2334 }
2335
amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device * adev)2336 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
2337 {
2338 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2339 case IP_VERSION(9, 0, 0):
2340 case IP_VERSION(10, 0, 0):
2341 case IP_VERSION(10, 0, 1):
2342 case IP_VERSION(11, 0, 2):
2343 if (adev->asic_type == CHIP_ARCTURUS)
2344 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2345 else
2346 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2347 break;
2348 case IP_VERSION(11, 0, 0):
2349 case IP_VERSION(11, 0, 5):
2350 case IP_VERSION(11, 0, 9):
2351 case IP_VERSION(11, 0, 7):
2352 case IP_VERSION(11, 0, 11):
2353 case IP_VERSION(11, 0, 12):
2354 case IP_VERSION(11, 0, 13):
2355 case IP_VERSION(11, 5, 0):
2356 case IP_VERSION(11, 5, 2):
2357 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2358 break;
2359 case IP_VERSION(11, 0, 8):
2360 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
2361 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2362 break;
2363 case IP_VERSION(12, 0, 0):
2364 case IP_VERSION(12, 0, 1):
2365 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
2366 break;
2367 case IP_VERSION(13, 0, 0):
2368 case IP_VERSION(13, 0, 1):
2369 case IP_VERSION(13, 0, 2):
2370 case IP_VERSION(13, 0, 3):
2371 case IP_VERSION(13, 0, 4):
2372 case IP_VERSION(13, 0, 5):
2373 case IP_VERSION(13, 0, 6):
2374 case IP_VERSION(13, 0, 7):
2375 case IP_VERSION(13, 0, 8):
2376 case IP_VERSION(13, 0, 10):
2377 case IP_VERSION(13, 0, 11):
2378 case IP_VERSION(13, 0, 14):
2379 case IP_VERSION(13, 0, 12):
2380 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
2381 break;
2382 case IP_VERSION(14, 0, 0):
2383 case IP_VERSION(14, 0, 1):
2384 case IP_VERSION(14, 0, 2):
2385 case IP_VERSION(14, 0, 3):
2386 case IP_VERSION(14, 0, 4):
2387 case IP_VERSION(14, 0, 5):
2388 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
2389 break;
2390 case IP_VERSION(15, 0, 0):
2391 case IP_VERSION(15, 0, 5):
2392 case IP_VERSION(15, 0, 8):
2393 case IP_VERSION(15, 0, 9):
2394 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block);
2395 break;
2396 default:
2397 dev_err(adev->dev,
2398 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
2399 amdgpu_ip_version(adev, MP1_HWIP, 0));
2400 return -EINVAL;
2401 }
2402 return 0;
2403 }
2404
2405 #if defined(CONFIG_DRM_AMD_DC)
amdgpu_discovery_set_sriov_display(struct amdgpu_device * adev)2406 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
2407 {
2408 amdgpu_device_set_sriov_virtual_display(adev);
2409 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2410 }
2411 #endif
2412
amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device * adev)2413 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
2414 {
2415 if (adev->enable_virtual_display) {
2416 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2417 return 0;
2418 }
2419
2420 if (!amdgpu_device_has_dc_support(adev))
2421 return 0;
2422
2423 #if defined(CONFIG_DRM_AMD_DC)
2424 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2425 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2426 case IP_VERSION(1, 0, 0):
2427 case IP_VERSION(1, 0, 1):
2428 case IP_VERSION(2, 0, 2):
2429 case IP_VERSION(2, 0, 0):
2430 case IP_VERSION(2, 0, 3):
2431 case IP_VERSION(2, 1, 0):
2432 case IP_VERSION(3, 0, 0):
2433 case IP_VERSION(3, 0, 2):
2434 case IP_VERSION(3, 0, 3):
2435 case IP_VERSION(3, 0, 1):
2436 case IP_VERSION(3, 1, 2):
2437 case IP_VERSION(3, 1, 3):
2438 case IP_VERSION(3, 1, 4):
2439 case IP_VERSION(3, 1, 5):
2440 case IP_VERSION(3, 1, 6):
2441 case IP_VERSION(3, 2, 0):
2442 case IP_VERSION(3, 2, 1):
2443 case IP_VERSION(3, 5, 0):
2444 case IP_VERSION(3, 5, 1):
2445 case IP_VERSION(3, 6, 0):
2446 case IP_VERSION(4, 1, 0):
2447 case IP_VERSION(4, 2, 0):
2448 case IP_VERSION(4, 2, 1):
2449 /* TODO: Fix IP version. DC code expects version 4.0.1 */
2450 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))
2451 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);
2452
2453 if (amdgpu_sriov_vf(adev))
2454 amdgpu_discovery_set_sriov_display(adev);
2455 else
2456 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2457 break;
2458 default:
2459 dev_err(adev->dev,
2460 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
2461 amdgpu_ip_version(adev, DCE_HWIP, 0));
2462 return -EINVAL;
2463 }
2464 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2465 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2466 case IP_VERSION(12, 0, 0):
2467 case IP_VERSION(12, 0, 1):
2468 case IP_VERSION(12, 1, 0):
2469 if (amdgpu_sriov_vf(adev))
2470 amdgpu_discovery_set_sriov_display(adev);
2471 else
2472 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2473 break;
2474 default:
2475 dev_err(adev->dev,
2476 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
2477 amdgpu_ip_version(adev, DCI_HWIP, 0));
2478 return -EINVAL;
2479 }
2480 }
2481 #endif
2482 return 0;
2483 }
2484
amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device * adev)2485 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
2486 {
2487 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2488 case IP_VERSION(9, 0, 1):
2489 case IP_VERSION(9, 1, 0):
2490 case IP_VERSION(9, 2, 1):
2491 case IP_VERSION(9, 2, 2):
2492 case IP_VERSION(9, 3, 0):
2493 case IP_VERSION(9, 4, 0):
2494 case IP_VERSION(9, 4, 1):
2495 case IP_VERSION(9, 4, 2):
2496 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
2497 break;
2498 case IP_VERSION(9, 4, 3):
2499 case IP_VERSION(9, 4, 4):
2500 case IP_VERSION(9, 5, 0):
2501 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
2502 break;
2503 case IP_VERSION(10, 1, 10):
2504 case IP_VERSION(10, 1, 2):
2505 case IP_VERSION(10, 1, 1):
2506 case IP_VERSION(10, 1, 3):
2507 case IP_VERSION(10, 1, 4):
2508 case IP_VERSION(10, 3, 0):
2509 case IP_VERSION(10, 3, 2):
2510 case IP_VERSION(10, 3, 1):
2511 case IP_VERSION(10, 3, 4):
2512 case IP_VERSION(10, 3, 5):
2513 case IP_VERSION(10, 3, 6):
2514 case IP_VERSION(10, 3, 3):
2515 case IP_VERSION(10, 3, 7):
2516 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
2517 break;
2518 case IP_VERSION(11, 0, 0):
2519 case IP_VERSION(11, 0, 1):
2520 case IP_VERSION(11, 0, 2):
2521 case IP_VERSION(11, 0, 3):
2522 case IP_VERSION(11, 0, 4):
2523 case IP_VERSION(11, 5, 0):
2524 case IP_VERSION(11, 5, 1):
2525 case IP_VERSION(11, 5, 2):
2526 case IP_VERSION(11, 5, 3):
2527 case IP_VERSION(11, 5, 4):
2528 case IP_VERSION(11, 5, 6):
2529 case IP_VERSION(11, 7, 0):
2530 case IP_VERSION(11, 7, 1):
2531 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
2532 break;
2533 case IP_VERSION(12, 0, 0):
2534 case IP_VERSION(12, 0, 1):
2535 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block);
2536 break;
2537 case IP_VERSION(12, 1, 0):
2538 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block);
2539 break;
2540 default:
2541 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
2542 amdgpu_ip_version(adev, GC_HWIP, 0));
2543 return -EINVAL;
2544 }
2545 return 0;
2546 }
2547
amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device * adev)2548 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
2549 {
2550 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2551 case IP_VERSION(4, 0, 0):
2552 case IP_VERSION(4, 0, 1):
2553 case IP_VERSION(4, 1, 0):
2554 case IP_VERSION(4, 1, 1):
2555 case IP_VERSION(4, 1, 2):
2556 case IP_VERSION(4, 2, 0):
2557 case IP_VERSION(4, 2, 2):
2558 case IP_VERSION(4, 4, 0):
2559 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2560 break;
2561 case IP_VERSION(4, 4, 2):
2562 case IP_VERSION(4, 4, 5):
2563 case IP_VERSION(4, 4, 4):
2564 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
2565 break;
2566 case IP_VERSION(5, 0, 0):
2567 case IP_VERSION(5, 0, 1):
2568 case IP_VERSION(5, 0, 2):
2569 case IP_VERSION(5, 0, 5):
2570 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2571 break;
2572 case IP_VERSION(5, 2, 0):
2573 case IP_VERSION(5, 2, 2):
2574 case IP_VERSION(5, 2, 4):
2575 case IP_VERSION(5, 2, 5):
2576 case IP_VERSION(5, 2, 6):
2577 case IP_VERSION(5, 2, 3):
2578 case IP_VERSION(5, 2, 1):
2579 case IP_VERSION(5, 2, 7):
2580 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2581 break;
2582 case IP_VERSION(6, 0, 0):
2583 case IP_VERSION(6, 0, 1):
2584 case IP_VERSION(6, 0, 2):
2585 case IP_VERSION(6, 0, 3):
2586 case IP_VERSION(6, 1, 0):
2587 case IP_VERSION(6, 1, 1):
2588 case IP_VERSION(6, 1, 2):
2589 case IP_VERSION(6, 1, 3):
2590 case IP_VERSION(6, 1, 4):
2591 case IP_VERSION(6, 4, 0):
2592 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2593 break;
2594 case IP_VERSION(7, 0, 0):
2595 case IP_VERSION(7, 0, 1):
2596 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block);
2597 break;
2598 case IP_VERSION(7, 1, 0):
2599 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block);
2600 break;
2601 default:
2602 dev_err(adev->dev,
2603 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2604 amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2605 return -EINVAL;
2606 }
2607
2608 return 0;
2609 }
2610
amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device * adev)2611 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)
2612 {
2613 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2614 case IP_VERSION(13, 0, 6):
2615 case IP_VERSION(13, 0, 12):
2616 case IP_VERSION(13, 0, 14):
2617 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block);
2618 break;
2619 default:
2620 break;
2621 }
2622 return 0;
2623 }
2624
amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device * adev)2625 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2626 {
2627 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2628 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2629 case IP_VERSION(7, 0, 0):
2630 case IP_VERSION(7, 2, 0):
2631 /* UVD is not supported on vega20 SR-IOV */
2632 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2633 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2634 break;
2635 default:
2636 dev_err(adev->dev,
2637 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2638 amdgpu_ip_version(adev, UVD_HWIP, 0));
2639 return -EINVAL;
2640 }
2641 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2642 case IP_VERSION(4, 0, 0):
2643 case IP_VERSION(4, 1, 0):
2644 /* VCE is not supported on vega20 SR-IOV */
2645 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2646 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2647 break;
2648 default:
2649 dev_err(adev->dev,
2650 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2651 amdgpu_ip_version(adev, VCE_HWIP, 0));
2652 return -EINVAL;
2653 }
2654 } else {
2655 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2656 case IP_VERSION(1, 0, 0):
2657 case IP_VERSION(1, 0, 1):
2658 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2659 break;
2660 case IP_VERSION(2, 0, 0):
2661 case IP_VERSION(2, 0, 2):
2662 case IP_VERSION(2, 2, 0):
2663 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2664 if (!amdgpu_sriov_vf(adev))
2665 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2666 break;
2667 case IP_VERSION(2, 0, 3):
2668 break;
2669 case IP_VERSION(2, 5, 0):
2670 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2671 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2672 break;
2673 case IP_VERSION(2, 6, 0):
2674 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2675 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2676 break;
2677 case IP_VERSION(3, 0, 0):
2678 case IP_VERSION(3, 0, 16):
2679 case IP_VERSION(3, 1, 1):
2680 case IP_VERSION(3, 1, 2):
2681 case IP_VERSION(3, 0, 2):
2682 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2683 if (!amdgpu_sriov_vf(adev))
2684 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2685 break;
2686 case IP_VERSION(3, 0, 33):
2687 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2688 break;
2689 case IP_VERSION(4, 0, 0):
2690 case IP_VERSION(4, 0, 2):
2691 case IP_VERSION(4, 0, 4):
2692 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2693 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2694 break;
2695 case IP_VERSION(4, 0, 3):
2696 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2697 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2698 break;
2699 case IP_VERSION(4, 0, 5):
2700 case IP_VERSION(4, 0, 6):
2701 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2702 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2703 break;
2704 case IP_VERSION(5, 0, 0):
2705 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2706 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
2707 break;
2708 case IP_VERSION(5, 3, 0):
2709 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2710 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block);
2711 break;
2712 case IP_VERSION(5, 0, 1):
2713 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block);
2714 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block);
2715 break;
2716 case IP_VERSION(5, 0, 2):
2717 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block);
2718 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block);
2719 break;
2720 default:
2721 dev_err(adev->dev,
2722 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2723 amdgpu_ip_version(adev, UVD_HWIP, 0));
2724 return -EINVAL;
2725 }
2726 }
2727 return 0;
2728 }
2729
amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device * adev)2730 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2731 {
2732 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2733 case IP_VERSION(11, 0, 0):
2734 case IP_VERSION(11, 0, 1):
2735 case IP_VERSION(11, 0, 2):
2736 case IP_VERSION(11, 0, 3):
2737 case IP_VERSION(11, 0, 4):
2738 case IP_VERSION(11, 5, 0):
2739 case IP_VERSION(11, 5, 1):
2740 case IP_VERSION(11, 5, 2):
2741 case IP_VERSION(11, 5, 3):
2742 case IP_VERSION(11, 5, 4):
2743 case IP_VERSION(11, 5, 6):
2744 case IP_VERSION(11, 7, 0):
2745 case IP_VERSION(11, 7, 1):
2746 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2747 adev->enable_mes = true;
2748 adev->enable_mes_kiq = true;
2749 break;
2750 case IP_VERSION(12, 0, 0):
2751 case IP_VERSION(12, 0, 1):
2752 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block);
2753 adev->enable_mes = true;
2754 adev->enable_mes_kiq = true;
2755 if (amdgpu_uni_mes)
2756 adev->enable_uni_mes = true;
2757 break;
2758 case IP_VERSION(12, 1, 0):
2759 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block);
2760 adev->enable_mes = true;
2761 adev->enable_mes_kiq = true;
2762 if (amdgpu_uni_mes)
2763 adev->enable_uni_mes = true;
2764 break;
2765 default:
2766 break;
2767 }
2768 return 0;
2769 }
2770
amdgpu_discovery_init_soc_config(struct amdgpu_device * adev)2771 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
2772 {
2773 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2774 case IP_VERSION(9, 4, 3):
2775 case IP_VERSION(9, 4, 4):
2776 case IP_VERSION(9, 5, 0):
2777 aqua_vanjaram_init_soc_config(adev);
2778 break;
2779 case IP_VERSION(12, 1, 0):
2780 soc_v1_0_init_soc_config(adev);
2781 break;
2782 default:
2783 break;
2784 }
2785 }
2786
amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device * adev)2787 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
2788 {
2789 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
2790 case IP_VERSION(6, 1, 0):
2791 case IP_VERSION(6, 1, 1):
2792 case IP_VERSION(6, 1, 3):
2793 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
2794 break;
2795 case IP_VERSION(2, 0, 0):
2796 case IP_VERSION(2, 2, 0):
2797 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block);
2798 break;
2799 default:
2800 break;
2801 }
2802
2803 return 0;
2804 }
2805
amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device * adev)2806 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
2807 {
2808 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2809 case IP_VERSION(4, 0, 5):
2810 case IP_VERSION(4, 0, 6):
2811 if (amdgpu_umsch_mm & 0x1) {
2812 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
2813 adev->enable_umsch_mm = true;
2814 }
2815 break;
2816 default:
2817 break;
2818 }
2819
2820 return 0;
2821 }
2822
amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device * adev)2823 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
2824 {
2825 #if defined(CONFIG_DRM_AMD_ISP)
2826 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
2827 case IP_VERSION(4, 1, 0):
2828 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block);
2829 break;
2830 case IP_VERSION(4, 1, 1):
2831 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block);
2832 break;
2833 default:
2834 break;
2835 }
2836 #endif
2837
2838 return 0;
2839 }
2840
amdgpu_discovery_set_ip_blocks(struct amdgpu_device * adev)2841 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
2842 {
2843 int r;
2844
2845 switch (adev->asic_type) {
2846 case CHIP_VEGA10:
2847 /* This is not fatal. We only need the discovery
2848 * binary for sysfs. We don't need it for a
2849 * functional system.
2850 */
2851 amdgpu_discovery_init(adev);
2852 vega10_reg_base_init(adev);
2853 adev->sdma.num_instances = 2;
2854 adev->sdma.sdma_mask = 3;
2855 adev->gmc.num_umc = 4;
2856 adev->gfx.xcc_mask = 1;
2857 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2858 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2859 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
2860 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
2861 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
2862 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
2863 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2864 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
2865 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
2866 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2867 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2868 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2869 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
2870 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
2871 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2872 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2873 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2874 break;
2875 case CHIP_VEGA12:
2876 /* This is not fatal. We only need the discovery
2877 * binary for sysfs. We don't need it for a
2878 * functional system.
2879 */
2880 amdgpu_discovery_init(adev);
2881 vega10_reg_base_init(adev);
2882 adev->sdma.num_instances = 2;
2883 adev->sdma.sdma_mask = 3;
2884 adev->gmc.num_umc = 4;
2885 adev->gfx.xcc_mask = 1;
2886 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2887 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2888 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
2889 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
2890 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
2891 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
2892 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
2893 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
2894 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
2895 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2896 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2897 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2898 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
2899 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
2900 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2901 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2902 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2903 break;
2904 case CHIP_RAVEN:
2905 /* This is not fatal. We only need the discovery
2906 * binary for sysfs. We don't need it for a
2907 * functional system.
2908 */
2909 amdgpu_discovery_init(adev);
2910 vega10_reg_base_init(adev);
2911 adev->sdma.num_instances = 1;
2912 adev->sdma.sdma_mask = 1;
2913 adev->vcn.num_vcn_inst = 1;
2914 adev->gmc.num_umc = 2;
2915 adev->gfx.xcc_mask = 1;
2916 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
2917 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2918 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2919 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
2920 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
2921 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
2922 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
2923 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2924 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2925 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2926 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2927 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2928 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2929 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2930 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2931 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2932 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
2933 } else {
2934 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2935 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2936 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2937 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2938 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2939 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2940 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2941 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2942 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2943 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2944 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2945 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2946 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2947 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2948 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2949 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
2950 }
2951 break;
2952 case CHIP_VEGA20:
2953 /* This is not fatal. We only need the discovery
2954 * binary for sysfs. We don't need it for a
2955 * functional system.
2956 */
2957 amdgpu_discovery_init(adev);
2958 vega20_reg_base_init(adev);
2959 adev->sdma.num_instances = 2;
2960 adev->sdma.sdma_mask = 3;
2961 adev->gmc.num_umc = 8;
2962 adev->gfx.xcc_mask = 1;
2963 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2964 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2965 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2966 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2967 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2968 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2969 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2970 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2971 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2972 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2973 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2974 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2975 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2976 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2977 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2978 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2979 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2980 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2981 break;
2982 case CHIP_ARCTURUS:
2983 /* This is not fatal. We only need the discovery
2984 * binary for sysfs. We don't need it for a
2985 * functional system.
2986 */
2987 amdgpu_discovery_init(adev);
2988 arct_reg_base_init(adev);
2989 adev->sdma.num_instances = 8;
2990 adev->sdma.sdma_mask = 0xff;
2991 adev->vcn.num_vcn_inst = 2;
2992 adev->gmc.num_umc = 8;
2993 adev->gfx.xcc_mask = 1;
2994 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2995 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2996 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2997 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2998 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2999 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
3000 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
3001 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
3002 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
3003 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
3004 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
3005 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
3006 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
3007 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
3008 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
3009 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
3010 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3011 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
3012 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
3013 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
3014 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
3015 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
3016 break;
3017 case CHIP_ALDEBARAN:
3018 /* This is not fatal. We only need the discovery
3019 * binary for sysfs. We don't need it for a
3020 * functional system.
3021 */
3022 amdgpu_discovery_init(adev);
3023 aldebaran_reg_base_init(adev);
3024 adev->sdma.num_instances = 5;
3025 adev->sdma.sdma_mask = 0x1f;
3026 adev->vcn.num_vcn_inst = 2;
3027 adev->gmc.num_umc = 4;
3028 adev->gfx.xcc_mask = 1;
3029 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3030 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3031 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
3032 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
3033 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
3034 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
3035 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
3036 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
3037 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
3038 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
3039 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
3040 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
3041 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
3042 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
3043 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
3044 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
3045 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
3046 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
3047 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
3048 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
3049 break;
3050 case CHIP_CYAN_SKILLFISH:
3051 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
3052 r = amdgpu_discovery_reg_base_init(adev);
3053 if (r)
3054 return -EINVAL;
3055
3056 amdgpu_discovery_harvest_ip(adev);
3057 amdgpu_discovery_get_gfx_info(adev);
3058 amdgpu_discovery_get_mall_info(adev);
3059 amdgpu_discovery_get_vcn_info(adev);
3060 } else {
3061 cyan_skillfish_reg_base_init(adev);
3062 adev->sdma.num_instances = 2;
3063 adev->sdma.sdma_mask = 3;
3064 adev->gfx.xcc_mask = 1;
3065 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3066 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3067 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1);
3068 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1);
3069 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1);
3070 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1);
3071 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0);
3072 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);
3073 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1);
3074 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8);
3075 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8);
3076 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1);
3077 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8);
3078 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3);
3079 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3);
3080 }
3081 break;
3082 default:
3083 r = amdgpu_discovery_reg_base_init(adev);
3084 if (r) {
3085 drm_err(&adev->ddev, "discovery failed: %d\n", r);
3086 return r;
3087 }
3088
3089 amdgpu_discovery_harvest_ip(adev);
3090 amdgpu_discovery_get_gfx_info(adev);
3091 amdgpu_discovery_get_mall_info(adev);
3092 amdgpu_discovery_get_vcn_info(adev);
3093 break;
3094 }
3095
3096 amdgpu_discovery_init_soc_config(adev);
3097 amdgpu_discovery_sysfs_init(adev);
3098
3099 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3100 case IP_VERSION(9, 0, 1):
3101 case IP_VERSION(9, 2, 1):
3102 case IP_VERSION(9, 4, 0):
3103 case IP_VERSION(9, 4, 1):
3104 case IP_VERSION(9, 4, 2):
3105 case IP_VERSION(9, 4, 3):
3106 case IP_VERSION(9, 4, 4):
3107 case IP_VERSION(9, 5, 0):
3108 adev->family = AMDGPU_FAMILY_AI;
3109 break;
3110 case IP_VERSION(9, 1, 0):
3111 case IP_VERSION(9, 2, 2):
3112 case IP_VERSION(9, 3, 0):
3113 adev->family = AMDGPU_FAMILY_RV;
3114 break;
3115 case IP_VERSION(10, 1, 10):
3116 case IP_VERSION(10, 1, 1):
3117 case IP_VERSION(10, 1, 2):
3118 case IP_VERSION(10, 1, 3):
3119 case IP_VERSION(10, 1, 4):
3120 case IP_VERSION(10, 3, 0):
3121 case IP_VERSION(10, 3, 2):
3122 case IP_VERSION(10, 3, 4):
3123 case IP_VERSION(10, 3, 5):
3124 adev->family = AMDGPU_FAMILY_NV;
3125 break;
3126 case IP_VERSION(10, 3, 1):
3127 adev->family = AMDGPU_FAMILY_VGH;
3128 adev->apu_flags |= AMD_APU_IS_VANGOGH;
3129 break;
3130 case IP_VERSION(10, 3, 3):
3131 adev->family = AMDGPU_FAMILY_YC;
3132 break;
3133 case IP_VERSION(10, 3, 6):
3134 adev->family = AMDGPU_FAMILY_GC_10_3_6;
3135 break;
3136 case IP_VERSION(10, 3, 7):
3137 adev->family = AMDGPU_FAMILY_GC_10_3_7;
3138 break;
3139 case IP_VERSION(11, 0, 0):
3140 case IP_VERSION(11, 0, 2):
3141 case IP_VERSION(11, 0, 3):
3142 adev->family = AMDGPU_FAMILY_GC_11_0_0;
3143 break;
3144 case IP_VERSION(11, 0, 1):
3145 case IP_VERSION(11, 0, 4):
3146 adev->family = AMDGPU_FAMILY_GC_11_0_1;
3147 break;
3148 case IP_VERSION(11, 5, 0):
3149 case IP_VERSION(11, 5, 1):
3150 case IP_VERSION(11, 5, 2):
3151 case IP_VERSION(11, 5, 3):
3152 case IP_VERSION(11, 5, 4):
3153 case IP_VERSION(11, 5, 6):
3154 adev->family = AMDGPU_FAMILY_GC_11_5_0;
3155 break;
3156 case IP_VERSION(11, 7, 0):
3157 case IP_VERSION(11, 7, 1):
3158 adev->family = AMDGPU_FAMILY_GC_11_5_4;
3159 break;
3160 case IP_VERSION(12, 0, 0):
3161 case IP_VERSION(12, 0, 1):
3162 case IP_VERSION(12, 1, 0):
3163 adev->family = AMDGPU_FAMILY_GC_12_0_0;
3164 break;
3165 default:
3166 return -EINVAL;
3167 }
3168
3169 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3170 case IP_VERSION(9, 1, 0):
3171 case IP_VERSION(9, 2, 2):
3172 case IP_VERSION(9, 3, 0):
3173 case IP_VERSION(10, 1, 3):
3174 case IP_VERSION(10, 1, 4):
3175 case IP_VERSION(10, 3, 1):
3176 case IP_VERSION(10, 3, 3):
3177 case IP_VERSION(10, 3, 6):
3178 case IP_VERSION(10, 3, 7):
3179 case IP_VERSION(11, 0, 1):
3180 case IP_VERSION(11, 0, 4):
3181 case IP_VERSION(11, 5, 0):
3182 case IP_VERSION(11, 5, 1):
3183 case IP_VERSION(11, 5, 2):
3184 case IP_VERSION(11, 5, 3):
3185 case IP_VERSION(11, 5, 4):
3186 case IP_VERSION(11, 5, 6):
3187 case IP_VERSION(11, 7, 0):
3188 case IP_VERSION(11, 7, 1):
3189 adev->flags |= AMD_IS_APU;
3190 break;
3191 default:
3192 break;
3193 }
3194
3195 /* set NBIO version */
3196 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
3197 case IP_VERSION(6, 1, 0):
3198 case IP_VERSION(6, 2, 0):
3199 adev->nbio.funcs = &nbio_v6_1_funcs;
3200 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
3201 break;
3202 case IP_VERSION(7, 0, 0):
3203 case IP_VERSION(7, 0, 1):
3204 case IP_VERSION(2, 5, 0):
3205 adev->nbio.funcs = &nbio_v7_0_funcs;
3206 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
3207 break;
3208 case IP_VERSION(7, 4, 0):
3209 case IP_VERSION(7, 4, 1):
3210 case IP_VERSION(7, 4, 4):
3211 adev->nbio.funcs = &nbio_v7_4_funcs;
3212 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
3213 break;
3214 case IP_VERSION(7, 9, 0):
3215 case IP_VERSION(7, 9, 1):
3216 adev->nbio.funcs = &nbio_v7_9_funcs;
3217 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
3218 break;
3219 case IP_VERSION(7, 11, 0):
3220 case IP_VERSION(7, 11, 1):
3221 case IP_VERSION(7, 11, 2):
3222 case IP_VERSION(7, 11, 3):
3223 adev->nbio.funcs = &nbio_v7_11_funcs;
3224 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
3225 break;
3226 case IP_VERSION(7, 2, 0):
3227 case IP_VERSION(7, 2, 1):
3228 case IP_VERSION(7, 3, 0):
3229 case IP_VERSION(7, 5, 0):
3230 case IP_VERSION(7, 5, 1):
3231 adev->nbio.funcs = &nbio_v7_2_funcs;
3232 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
3233 break;
3234 case IP_VERSION(2, 1, 1):
3235 case IP_VERSION(2, 3, 0):
3236 case IP_VERSION(2, 3, 1):
3237 case IP_VERSION(2, 3, 2):
3238 case IP_VERSION(3, 3, 0):
3239 case IP_VERSION(3, 3, 1):
3240 case IP_VERSION(3, 3, 2):
3241 case IP_VERSION(3, 3, 3):
3242 adev->nbio.funcs = &nbio_v2_3_funcs;
3243 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
3244 break;
3245 case IP_VERSION(4, 3, 0):
3246 case IP_VERSION(4, 3, 1):
3247 if (amdgpu_sriov_vf(adev))
3248 adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
3249 else
3250 adev->nbio.funcs = &nbio_v4_3_funcs;
3251 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
3252 break;
3253 case IP_VERSION(7, 7, 0):
3254 case IP_VERSION(7, 7, 1):
3255 adev->nbio.funcs = &nbio_v7_7_funcs;
3256 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
3257 break;
3258 case IP_VERSION(6, 3, 1):
3259 case IP_VERSION(7, 11, 4):
3260 case IP_VERSION(7, 11, 5):
3261 adev->nbio.funcs = &nbif_v6_3_1_funcs;
3262 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
3263 break;
3264 case IP_VERSION(6, 3, 2):
3265 adev->nbio.funcs = &nbio_v6_3_2_funcs;
3266 break;
3267 default:
3268 break;
3269 }
3270
3271 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
3272 case IP_VERSION(4, 0, 0):
3273 case IP_VERSION(4, 0, 1):
3274 case IP_VERSION(4, 1, 0):
3275 case IP_VERSION(4, 1, 1):
3276 case IP_VERSION(4, 1, 2):
3277 case IP_VERSION(4, 2, 0):
3278 case IP_VERSION(4, 2, 1):
3279 case IP_VERSION(4, 4, 0):
3280 case IP_VERSION(4, 4, 2):
3281 case IP_VERSION(4, 4, 5):
3282 adev->hdp.funcs = &hdp_v4_0_funcs;
3283 break;
3284 case IP_VERSION(5, 0, 0):
3285 case IP_VERSION(5, 0, 1):
3286 case IP_VERSION(5, 0, 2):
3287 case IP_VERSION(5, 0, 3):
3288 case IP_VERSION(5, 0, 4):
3289 case IP_VERSION(5, 2, 0):
3290 adev->hdp.funcs = &hdp_v5_0_funcs;
3291 break;
3292 case IP_VERSION(5, 2, 1):
3293 adev->hdp.funcs = &hdp_v5_2_funcs;
3294 break;
3295 case IP_VERSION(6, 0, 0):
3296 case IP_VERSION(6, 0, 1):
3297 case IP_VERSION(6, 1, 0):
3298 case IP_VERSION(6, 1, 1):
3299 case IP_VERSION(6, 4, 0):
3300 adev->hdp.funcs = &hdp_v6_0_funcs;
3301 break;
3302 case IP_VERSION(7, 0, 0):
3303 adev->hdp.funcs = &hdp_v7_0_funcs;
3304 break;
3305 default:
3306 break;
3307 }
3308
3309 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
3310 case IP_VERSION(3, 6, 0):
3311 case IP_VERSION(3, 6, 1):
3312 case IP_VERSION(3, 6, 2):
3313 adev->df.funcs = &df_v3_6_funcs;
3314 break;
3315 case IP_VERSION(2, 1, 0):
3316 case IP_VERSION(2, 1, 1):
3317 case IP_VERSION(2, 5, 0):
3318 case IP_VERSION(3, 5, 1):
3319 case IP_VERSION(3, 5, 2):
3320 adev->df.funcs = &df_v1_7_funcs;
3321 break;
3322 case IP_VERSION(4, 3, 0):
3323 adev->df.funcs = &df_v4_3_funcs;
3324 break;
3325 case IP_VERSION(4, 6, 2):
3326 adev->df.funcs = &df_v4_6_2_funcs;
3327 break;
3328 case IP_VERSION(4, 15, 0):
3329 case IP_VERSION(4, 15, 1):
3330 adev->df.funcs = &df_v4_15_funcs;
3331 break;
3332 default:
3333 break;
3334 }
3335
3336 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
3337 case IP_VERSION(9, 0, 0):
3338 case IP_VERSION(9, 0, 1):
3339 case IP_VERSION(10, 0, 0):
3340 case IP_VERSION(10, 0, 1):
3341 case IP_VERSION(10, 0, 2):
3342 adev->smuio.funcs = &smuio_v9_0_funcs;
3343 break;
3344 case IP_VERSION(11, 0, 0):
3345 case IP_VERSION(11, 0, 2):
3346 case IP_VERSION(11, 0, 3):
3347 case IP_VERSION(11, 0, 4):
3348 case IP_VERSION(11, 0, 7):
3349 case IP_VERSION(11, 0, 8):
3350 adev->smuio.funcs = &smuio_v11_0_funcs;
3351 break;
3352 case IP_VERSION(11, 0, 6):
3353 case IP_VERSION(11, 0, 10):
3354 case IP_VERSION(11, 0, 11):
3355 case IP_VERSION(11, 5, 0):
3356 case IP_VERSION(11, 5, 2):
3357 case IP_VERSION(13, 0, 1):
3358 case IP_VERSION(13, 0, 9):
3359 case IP_VERSION(13, 0, 10):
3360 adev->smuio.funcs = &smuio_v11_0_6_funcs;
3361 break;
3362 case IP_VERSION(13, 0, 2):
3363 adev->smuio.funcs = &smuio_v13_0_funcs;
3364 break;
3365 case IP_VERSION(13, 0, 3):
3366 case IP_VERSION(13, 0, 11):
3367 adev->smuio.funcs = &smuio_v13_0_3_funcs;
3368 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
3369 adev->flags |= AMD_IS_APU;
3370 }
3371 break;
3372 case IP_VERSION(13, 0, 6):
3373 case IP_VERSION(13, 0, 8):
3374 case IP_VERSION(14, 0, 0):
3375 case IP_VERSION(14, 0, 1):
3376 adev->smuio.funcs = &smuio_v13_0_6_funcs;
3377 break;
3378 case IP_VERSION(14, 0, 2):
3379 adev->smuio.funcs = &smuio_v14_0_2_funcs;
3380 break;
3381 case IP_VERSION(15, 0, 0):
3382 case IP_VERSION(15, 0, 5):
3383 adev->smuio.funcs = &smuio_v15_0_0_funcs;
3384 break;
3385 case IP_VERSION(15, 0, 8):
3386 adev->smuio.funcs = &smuio_v15_0_8_funcs;
3387 break;
3388 default:
3389 break;
3390 }
3391
3392 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
3393 case IP_VERSION(6, 0, 0):
3394 case IP_VERSION(6, 0, 1):
3395 case IP_VERSION(6, 0, 2):
3396 case IP_VERSION(6, 0, 3):
3397 adev->lsdma.funcs = &lsdma_v6_0_funcs;
3398 break;
3399 case IP_VERSION(7, 0, 0):
3400 case IP_VERSION(7, 0, 1):
3401 adev->lsdma.funcs = &lsdma_v7_0_funcs;
3402 break;
3403 case IP_VERSION(7, 1, 0):
3404 adev->lsdma.funcs = &lsdma_v7_1_funcs;
3405 break;
3406 default:
3407 break;
3408 }
3409
3410 r = amdgpu_discovery_set_common_ip_blocks(adev);
3411 if (r)
3412 return r;
3413
3414 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
3415 if (r)
3416 return r;
3417
3418 /* For SR-IOV, PSP needs to be initialized before IH */
3419 if (amdgpu_sriov_vf(adev)) {
3420 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3421 if (r)
3422 return r;
3423 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3424 if (r)
3425 return r;
3426 } else {
3427 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3428 if (r)
3429 return r;
3430
3431 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3432 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3433 if (r)
3434 return r;
3435 }
3436 }
3437
3438 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3439 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3440 if (r)
3441 return r;
3442 }
3443
3444 r = amdgpu_discovery_set_display_ip_blocks(adev);
3445 if (r)
3446 return r;
3447
3448 r = amdgpu_discovery_set_gc_ip_blocks(adev);
3449 if (r)
3450 return r;
3451
3452 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
3453 if (r)
3454 return r;
3455
3456 r = amdgpu_discovery_set_ras_ip_blocks(adev);
3457 if (r)
3458 return r;
3459
3460 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
3461 !amdgpu_sriov_vf(adev) &&
3462 amdgpu_dpm == 1) ||
3463 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO &&
3464 amdgpu_dpm == 1)) {
3465 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3466 if (r)
3467 return r;
3468 }
3469
3470 r = amdgpu_discovery_set_mm_ip_blocks(adev);
3471 if (r)
3472 return r;
3473
3474 r = amdgpu_discovery_set_mes_ip_blocks(adev);
3475 if (r)
3476 return r;
3477
3478 r = amdgpu_discovery_set_vpe_ip_blocks(adev);
3479 if (r)
3480 return r;
3481
3482 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);
3483 if (r)
3484 return r;
3485
3486 r = amdgpu_discovery_set_isp_ip_blocks(adev);
3487 if (r)
3488 return r;
3489 return 0;
3490 }
3491
amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device * adev,uint16_t * major,uint16_t * minor)3492 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
3493 uint16_t *major, uint16_t *minor)
3494 {
3495 uint8_t *discovery_bin = adev->discovery.bin;
3496 struct table_info *info;
3497 union gc_info *gc_info;
3498 u16 offset;
3499
3500 if (!discovery_bin)
3501 return -EINVAL;
3502 if (amdgpu_discovery_get_table_info(adev, &info, GC))
3503 return -EINVAL;
3504
3505 offset = le16_to_cpu(info->offset);
3506 if (!offset)
3507 return -EINVAL;
3508
3509 gc_info = (union gc_info *)(discovery_bin + offset);
3510
3511 if (major)
3512 *major = le16_to_cpu(gc_info->v1.header.version_major);
3513 if (minor)
3514 *minor = le16_to_cpu(gc_info->v1.header.version_minor);
3515 return 0;
3516 }
3517