1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #include "linux/bitmap.h" 7 #include "test_util.h" 8 #include "kvm_util.h" 9 #include "pmu.h" 10 #include "processor.h" 11 #include "smm.h" 12 #include "svm_util.h" 13 #include "sev.h" 14 #include "vmx.h" 15 16 #ifndef NUM_INTERRUPTS 17 #define NUM_INTERRUPTS 256 18 #endif 19 20 #define KERNEL_CS 0x8 21 #define KERNEL_DS 0x10 22 #define KERNEL_TSS 0x18 23 24 gva_t exception_handlers; 25 bool host_cpu_is_amd; 26 bool host_cpu_is_intel; 27 bool host_cpu_is_hygon; 28 bool host_cpu_is_amd_compatible; 29 bool host_cpu_is_zhaoxin; 30 bool host_cpu_is_intel_compatible; 31 bool is_forced_emulation_enabled; 32 u64 guest_tsc_khz; 33 struct kvm_mmu guest_mmu; 34 35 struct guest_regs guest_regs; 36 37 const char *ex_str(int vector) 38 { 39 switch (vector) { 40 #define VEC_STR(v) case v##_VECTOR: return "#" #v 41 case DE_VECTOR: return "no exception"; 42 case KVM_MAGIC_DE_VECTOR: return "#DE"; 43 VEC_STR(DB); 44 VEC_STR(NMI); 45 VEC_STR(BP); 46 VEC_STR(OF); 47 VEC_STR(BR); 48 VEC_STR(UD); 49 VEC_STR(NM); 50 VEC_STR(DF); 51 VEC_STR(TS); 52 VEC_STR(NP); 53 VEC_STR(SS); 54 VEC_STR(GP); 55 VEC_STR(PF); 56 VEC_STR(MF); 57 VEC_STR(AC); 58 VEC_STR(MC); 59 VEC_STR(XM); 60 VEC_STR(VE); 61 VEC_STR(CP); 62 VEC_STR(HV); 63 VEC_STR(VC); 64 VEC_STR(SX); 65 default: return "#??"; 66 #undef VEC_STR 67 } 68 } 69 70 static void regs_dump(FILE *stream, struct kvm_regs *regs, u8 indent) 71 { 72 fprintf(stream, "%*srax: 0x%.16llx rbx: 0x%.16llx " 73 "rcx: 0x%.16llx rdx: 0x%.16llx\n", 74 indent, "", 75 regs->rax, regs->rbx, regs->rcx, regs->rdx); 76 fprintf(stream, "%*srsi: 0x%.16llx rdi: 0x%.16llx " 77 "rsp: 0x%.16llx rbp: 0x%.16llx\n", 78 indent, "", 79 regs->rsi, regs->rdi, regs->rsp, regs->rbp); 80 fprintf(stream, "%*sr8: 0x%.16llx r9: 0x%.16llx " 81 "r10: 0x%.16llx r11: 0x%.16llx\n", 82 indent, "", 83 regs->r8, regs->r9, regs->r10, regs->r11); 84 fprintf(stream, "%*sr12: 0x%.16llx r13: 0x%.16llx " 85 "r14: 0x%.16llx r15: 0x%.16llx\n", 86 indent, "", 87 regs->r12, regs->r13, regs->r14, regs->r15); 88 fprintf(stream, "%*srip: 0x%.16llx rfl: 0x%.16llx\n", 89 indent, "", 90 regs->rip, regs->rflags); 91 } 92 93 static void segment_dump(FILE *stream, struct kvm_segment *segment, 94 u8 indent) 95 { 96 fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.8x " 97 "selector: 0x%.4x type: 0x%.2x\n", 98 indent, "", segment->base, segment->limit, 99 segment->selector, segment->type); 100 fprintf(stream, "%*spresent: 0x%.2x dpl: 0x%.2x " 101 "db: 0x%.2x s: 0x%.2x l: 0x%.2x\n", 102 indent, "", segment->present, segment->dpl, 103 segment->db, segment->s, segment->l); 104 fprintf(stream, "%*sg: 0x%.2x avl: 0x%.2x " 105 "unusable: 0x%.2x padding: 0x%.2x\n", 106 indent, "", segment->g, segment->avl, 107 segment->unusable, segment->padding); 108 } 109 110 static void dtable_dump(FILE *stream, struct kvm_dtable *dtable, 111 u8 indent) 112 { 113 fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.4x " 114 "padding: 0x%.4x 0x%.4x 0x%.4x\n", 115 indent, "", dtable->base, dtable->limit, 116 dtable->padding[0], dtable->padding[1], dtable->padding[2]); 117 } 118 119 static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, u8 indent) 120 { 121 unsigned int i; 122 123 fprintf(stream, "%*scs:\n", indent, ""); 124 segment_dump(stream, &sregs->cs, indent + 2); 125 fprintf(stream, "%*sds:\n", indent, ""); 126 segment_dump(stream, &sregs->ds, indent + 2); 127 fprintf(stream, "%*ses:\n", indent, ""); 128 segment_dump(stream, &sregs->es, indent + 2); 129 fprintf(stream, "%*sfs:\n", indent, ""); 130 segment_dump(stream, &sregs->fs, indent + 2); 131 fprintf(stream, "%*sgs:\n", indent, ""); 132 segment_dump(stream, &sregs->gs, indent + 2); 133 fprintf(stream, "%*sss:\n", indent, ""); 134 segment_dump(stream, &sregs->ss, indent + 2); 135 fprintf(stream, "%*str:\n", indent, ""); 136 segment_dump(stream, &sregs->tr, indent + 2); 137 fprintf(stream, "%*sldt:\n", indent, ""); 138 segment_dump(stream, &sregs->ldt, indent + 2); 139 140 fprintf(stream, "%*sgdt:\n", indent, ""); 141 dtable_dump(stream, &sregs->gdt, indent + 2); 142 fprintf(stream, "%*sidt:\n", indent, ""); 143 dtable_dump(stream, &sregs->idt, indent + 2); 144 145 fprintf(stream, "%*scr0: 0x%.16llx cr2: 0x%.16llx " 146 "cr3: 0x%.16llx cr4: 0x%.16llx\n", 147 indent, "", 148 sregs->cr0, sregs->cr2, sregs->cr3, sregs->cr4); 149 fprintf(stream, "%*scr8: 0x%.16llx efer: 0x%.16llx " 150 "apic_base: 0x%.16llx\n", 151 indent, "", 152 sregs->cr8, sregs->efer, sregs->apic_base); 153 154 fprintf(stream, "%*sinterrupt_bitmap:\n", indent, ""); 155 for (i = 0; i < (KVM_NR_INTERRUPTS + 63) / 64; i++) { 156 fprintf(stream, "%*s%.16llx\n", indent + 2, "", 157 sregs->interrupt_bitmap[i]); 158 } 159 } 160 161 bool kvm_is_tdp_enabled(void) 162 { 163 if (host_cpu_is_intel_compatible) 164 return get_kvm_intel_param_bool("ept"); 165 else 166 return get_kvm_amd_param_bool("npt"); 167 } 168 169 static void virt_mmu_init(struct kvm_vm *vm, struct kvm_mmu *mmu, 170 struct pte_masks *pte_masks) 171 { 172 /* If needed, create the top-level page table. */ 173 if (!mmu->pgd_created) { 174 mmu->pgd = vm_alloc_page_table(vm); 175 mmu->pgd_created = true; 176 mmu->arch.pte_masks = *pte_masks; 177 } 178 179 TEST_ASSERT(mmu->pgtable_levels == 4 || mmu->pgtable_levels == 5, 180 "Selftests MMU only supports 4-level and 5-level paging, not %u-level paging", 181 mmu->pgtable_levels); 182 } 183 184 void virt_arch_pgd_alloc(struct kvm_vm *vm) 185 { 186 TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K, 187 "Unknown or unsupported guest mode: 0x%x", vm->mode); 188 189 struct pte_masks pte_masks = (struct pte_masks){ 190 .present = BIT_ULL(0), 191 .writable = BIT_ULL(1), 192 .user = BIT_ULL(2), 193 .accessed = BIT_ULL(5), 194 .dirty = BIT_ULL(6), 195 .huge = BIT_ULL(7), 196 .nx = BIT_ULL(63), 197 .executable = 0, 198 .c = vm->arch.c_bit, 199 .s = vm->arch.s_bit, 200 }; 201 202 virt_mmu_init(vm, &vm->mmu, &pte_masks); 203 } 204 205 void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels, 206 struct pte_masks *pte_masks) 207 { 208 TEST_ASSERT(!vm->stage2_mmu.pgtable_levels, "TDP MMU already initialized"); 209 210 vm->stage2_mmu.pgtable_levels = pgtable_levels; 211 virt_mmu_init(vm, &vm->stage2_mmu, pte_masks); 212 } 213 214 static void *virt_get_pte(struct kvm_vm *vm, struct kvm_mmu *mmu, 215 u64 *parent_pte, gva_t gva, int level) 216 { 217 u64 pt_gpa = PTE_GET_PA(*parent_pte); 218 u64 *page_table = addr_gpa2hva(vm, pt_gpa); 219 int index = (gva >> PG_LEVEL_SHIFT(level)) & 0x1ffu; 220 221 TEST_ASSERT((*parent_pte == mmu->pgd) || is_present_pte(mmu, parent_pte), 222 "Parent PTE (level %d) not PRESENT for gva: 0x%08lx", 223 level + 1, gva); 224 225 return &page_table[index]; 226 } 227 228 static u64 *virt_create_upper_pte(struct kvm_vm *vm, 229 struct kvm_mmu *mmu, 230 u64 *parent_pte, 231 gva_t gva, 232 gpa_t gpa, 233 int current_level, 234 int target_level) 235 { 236 u64 *pte = virt_get_pte(vm, mmu, parent_pte, gva, current_level); 237 238 gpa = vm_untag_gpa(vm, gpa); 239 240 if (!is_present_pte(mmu, pte)) { 241 *pte = PTE_PRESENT_MASK(mmu) | PTE_READABLE_MASK(mmu) | 242 PTE_WRITABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu) | 243 PTE_ALWAYS_SET_MASK(mmu); 244 if (current_level == target_level) 245 *pte |= PTE_HUGE_MASK(mmu) | (gpa & PHYSICAL_PAGE_MASK); 246 else 247 *pte |= vm_alloc_page_table(vm) & PHYSICAL_PAGE_MASK; 248 } else { 249 /* 250 * Entry already present. Assert that the caller doesn't want 251 * a hugepage at this level, and that there isn't a hugepage at 252 * this level. 253 */ 254 TEST_ASSERT(current_level != target_level, 255 "Cannot create hugepage at level: %u, gva: 0x%lx", 256 current_level, gva); 257 TEST_ASSERT(!is_huge_pte(mmu, pte), 258 "Cannot create page table at level: %u, gva: 0x%lx", 259 current_level, gva); 260 } 261 return pte; 262 } 263 264 void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva, 265 gpa_t gpa, int level) 266 { 267 const u64 pg_size = PG_LEVEL_SIZE(level); 268 u64 *pte = &mmu->pgd; 269 int current_level; 270 271 TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K, 272 "Unknown or unsupported guest mode: 0x%x", vm->mode); 273 274 TEST_ASSERT((gva % pg_size) == 0, 275 "Virtual address not aligned,\n" 276 "gva: 0x%lx page size: 0x%lx", gva, pg_size); 277 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), 278 "Invalid virtual address, gva: 0x%lx", gva); 279 TEST_ASSERT((gpa % pg_size) == 0, 280 "Physical address not aligned,\n" 281 " gpa: 0x%lx page size: 0x%lx", gpa, pg_size); 282 TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, 283 "Physical address beyond maximum supported,\n" 284 " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 285 gpa, vm->max_gfn, vm->page_size); 286 TEST_ASSERT(vm_untag_gpa(vm, gpa) == gpa, 287 "Unexpected bits in gpa: %lx", gpa); 288 289 TEST_ASSERT(!PTE_EXECUTABLE_MASK(mmu) || !PTE_NX_MASK(mmu), 290 "X and NX bit masks cannot be used simultaneously"); 291 292 /* 293 * Allocate upper level page tables, if not already present. Return 294 * early if a hugepage was created. 295 */ 296 for (current_level = mmu->pgtable_levels; 297 current_level > PG_LEVEL_4K; 298 current_level--) { 299 pte = virt_create_upper_pte(vm, mmu, pte, gva, gpa, 300 current_level, level); 301 if (is_huge_pte(mmu, pte)) 302 return; 303 } 304 305 /* Fill in page table entry. */ 306 pte = virt_get_pte(vm, mmu, pte, gva, PG_LEVEL_4K); 307 TEST_ASSERT(!is_present_pte(mmu, pte), 308 "PTE already present for 4k page at gva: 0x%lx", gva); 309 *pte = PTE_PRESENT_MASK(mmu) | PTE_READABLE_MASK(mmu) | 310 PTE_WRITABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu) | 311 PTE_ALWAYS_SET_MASK(mmu) | (gpa & PHYSICAL_PAGE_MASK); 312 313 /* 314 * Neither SEV nor TDX supports shared page tables, so only the final 315 * leaf PTE needs manually set the C/S-bit. 316 */ 317 if (vm_is_gpa_protected(vm, gpa)) 318 *pte |= PTE_C_BIT_MASK(mmu); 319 else 320 *pte |= PTE_S_BIT_MASK(mmu); 321 } 322 323 void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) 324 { 325 __virt_pg_map(vm, &vm->mmu, gva, gpa, PG_LEVEL_4K); 326 } 327 328 void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa, 329 u64 nr_bytes, int level) 330 { 331 u64 pg_size = PG_LEVEL_SIZE(level); 332 u64 nr_pages = nr_bytes / pg_size; 333 int i; 334 335 TEST_ASSERT(nr_bytes % pg_size == 0, 336 "Region size not aligned: nr_bytes: 0x%lx, page size: 0x%lx", 337 nr_bytes, pg_size); 338 339 for (i = 0; i < nr_pages; i++) { 340 __virt_pg_map(vm, &vm->mmu, gva, gpa, level); 341 sparsebit_set_num(vm->vpages_mapped, gva >> vm->page_shift, 342 nr_bytes / PAGE_SIZE); 343 344 gva += pg_size; 345 gpa += pg_size; 346 } 347 } 348 349 static bool vm_is_target_pte(struct kvm_mmu *mmu, u64 *pte, 350 int *level, int current_level) 351 { 352 if (is_huge_pte(mmu, pte)) { 353 TEST_ASSERT(*level == PG_LEVEL_NONE || 354 *level == current_level, 355 "Unexpected hugepage at level %d", current_level); 356 *level = current_level; 357 } 358 359 return *level == current_level; 360 } 361 362 static u64 *__vm_get_page_table_entry(struct kvm_vm *vm, 363 struct kvm_mmu *mmu, 364 gva_t gva, 365 int *level) 366 { 367 int va_width = 12 + (mmu->pgtable_levels) * 9; 368 u64 *pte = &mmu->pgd; 369 int current_level; 370 371 TEST_ASSERT(!vm->arch.is_pt_protected, 372 "Walking page tables of protected guests is impossible"); 373 374 TEST_ASSERT(*level >= PG_LEVEL_NONE && *level <= mmu->pgtable_levels, 375 "Invalid PG_LEVEL_* '%d'", *level); 376 377 TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K, 378 "Unknown or unsupported guest mode: 0x%x", vm->mode); 379 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), 380 "Invalid virtual address, gva: 0x%lx", gva); 381 /* 382 * Check that the gva is a sign-extended va_width value. 383 */ 384 TEST_ASSERT(gva == (((s64)gva << (64 - va_width) >> (64 - va_width))), 385 "Canonical check failed. The virtual address is invalid."); 386 387 for (current_level = mmu->pgtable_levels; 388 current_level > PG_LEVEL_4K; 389 current_level--) { 390 pte = virt_get_pte(vm, mmu, pte, gva, current_level); 391 if (vm_is_target_pte(mmu, pte, level, current_level)) 392 return pte; 393 } 394 395 return virt_get_pte(vm, mmu, pte, gva, PG_LEVEL_4K); 396 } 397 398 u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa) 399 { 400 int level = PG_LEVEL_4K; 401 402 return __vm_get_page_table_entry(vm, &vm->stage2_mmu, l2_gpa, &level); 403 } 404 405 u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva) 406 { 407 int level = PG_LEVEL_4K; 408 409 return __vm_get_page_table_entry(vm, &vm->mmu, gva, &level); 410 } 411 412 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) 413 { 414 struct kvm_mmu *mmu = &vm->mmu; 415 u64 *pml4e, *pml4e_start; 416 u64 *pdpe, *pdpe_start; 417 u64 *pde, *pde_start; 418 u64 *pte, *pte_start; 419 420 if (!mmu->pgd_created) 421 return; 422 423 fprintf(stream, "%*s " 424 " no\n", indent, ""); 425 fprintf(stream, "%*s index hvaddr gpaddr " 426 "addr w exec dirty\n", 427 indent, ""); 428 pml4e_start = (u64 *)addr_gpa2hva(vm, mmu->pgd); 429 for (u16 n1 = 0; n1 <= 0x1ffu; n1++) { 430 pml4e = &pml4e_start[n1]; 431 if (!is_present_pte(mmu, pml4e)) 432 continue; 433 fprintf(stream, "%*spml4e 0x%-3zx %p 0x%-12lx 0x%-10llx %u " 434 " %u\n", 435 indent, "", 436 pml4e - pml4e_start, pml4e, 437 addr_hva2gpa(vm, pml4e), PTE_GET_PFN(*pml4e), 438 is_writable_pte(mmu, pml4e), is_nx_pte(mmu, pml4e)); 439 440 pdpe_start = addr_gpa2hva(vm, *pml4e & PHYSICAL_PAGE_MASK); 441 for (u16 n2 = 0; n2 <= 0x1ffu; n2++) { 442 pdpe = &pdpe_start[n2]; 443 if (!is_present_pte(mmu, pdpe)) 444 continue; 445 fprintf(stream, "%*spdpe 0x%-3zx %p 0x%-12lx 0x%-10llx " 446 "%u %u\n", 447 indent, "", 448 pdpe - pdpe_start, pdpe, 449 addr_hva2gpa(vm, pdpe), 450 PTE_GET_PFN(*pdpe), is_writable_pte(mmu, pdpe), 451 is_nx_pte(mmu, pdpe)); 452 453 pde_start = addr_gpa2hva(vm, *pdpe & PHYSICAL_PAGE_MASK); 454 for (u16 n3 = 0; n3 <= 0x1ffu; n3++) { 455 pde = &pde_start[n3]; 456 if (!is_present_pte(mmu, pde)) 457 continue; 458 fprintf(stream, "%*spde 0x%-3zx %p " 459 "0x%-12lx 0x%-10llx %u %u\n", 460 indent, "", pde - pde_start, pde, 461 addr_hva2gpa(vm, pde), 462 PTE_GET_PFN(*pde), is_writable_pte(mmu, pde), 463 is_nx_pte(mmu, pde)); 464 465 pte_start = addr_gpa2hva(vm, *pde & PHYSICAL_PAGE_MASK); 466 for (u16 n4 = 0; n4 <= 0x1ffu; n4++) { 467 pte = &pte_start[n4]; 468 if (!is_present_pte(mmu, pte)) 469 continue; 470 fprintf(stream, "%*spte 0x%-3zx %p " 471 "0x%-12lx 0x%-10llx %u %u " 472 " %u 0x%-10lx\n", 473 indent, "", 474 pte - pte_start, pte, 475 addr_hva2gpa(vm, pte), 476 PTE_GET_PFN(*pte), 477 is_writable_pte(mmu, pte), 478 is_nx_pte(mmu, pte), 479 is_dirty_pte(mmu, pte), 480 ((u64)n1 << 27) 481 | ((u64)n2 << 18) 482 | ((u64)n3 << 9) 483 | ((u64)n4)); 484 } 485 } 486 } 487 } 488 } 489 490 void vm_enable_tdp(struct kvm_vm *vm) 491 { 492 if (kvm_cpu_has(X86_FEATURE_VMX)) 493 vm_enable_ept(vm); 494 else 495 vm_enable_npt(vm); 496 } 497 498 bool kvm_cpu_has_tdp(void) 499 { 500 return kvm_cpu_has_ept() || kvm_cpu_has_npt(); 501 } 502 503 void __tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size, int level) 504 { 505 size_t page_size = PG_LEVEL_SIZE(level); 506 size_t npages = size / page_size; 507 508 TEST_ASSERT(l2_gpa + size > l2_gpa, "L2 GPA overflow"); 509 TEST_ASSERT(gpa + size > gpa, "GPA overflow"); 510 511 while (npages--) { 512 __virt_pg_map(vm, &vm->stage2_mmu, l2_gpa, gpa, level); 513 l2_gpa += page_size; 514 gpa += page_size; 515 } 516 } 517 518 void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size) 519 { 520 __tdp_map(vm, l2_gpa, gpa, size, PG_LEVEL_4K); 521 } 522 523 /* Prepare an identity extended page table that maps all the 524 * physical pages in VM. 525 */ 526 void tdp_identity_map_default_memslots(struct kvm_vm *vm) 527 { 528 u32 s, memslot = 0; 529 sparsebit_idx_t i, last; 530 struct userspace_mem_region *region = memslot2region(vm, memslot); 531 532 /* Only memslot 0 is mapped here, ensure it's the only one being used */ 533 for (s = 0; s < NR_MEM_REGIONS; s++) 534 TEST_ASSERT(!vm->memslots[s] || 535 vm->memslots[s] == KVM_INVALID_MEMSLOT, 536 "Unhandled memslot '%u' for type '%u'", 537 vm->memslots[s], s); 538 539 i = (region->region.guest_phys_addr >> vm->page_shift) - 1; 540 last = i + (region->region.memory_size >> vm->page_shift); 541 for (;;) { 542 i = sparsebit_next_clear(region->unused_phy_pages, i); 543 if (i > last) 544 break; 545 546 tdp_map(vm, (u64)i << vm->page_shift, 547 (u64)i << vm->page_shift, 1 << vm->page_shift); 548 } 549 } 550 551 /* Identity map a region with 1GiB Pages. */ 552 void tdp_identity_map_1g(struct kvm_vm *vm, u64 addr, u64 size) 553 { 554 __tdp_map(vm, addr, addr, size, PG_LEVEL_1G); 555 } 556 557 /* 558 * Set Unusable Segment 559 * 560 * Input Args: None 561 * 562 * Output Args: 563 * segp - Pointer to segment register 564 * 565 * Return: None 566 * 567 * Sets the segment register pointed to by @segp to an unusable state. 568 */ 569 static void kvm_seg_set_unusable(struct kvm_segment *segp) 570 { 571 memset(segp, 0, sizeof(*segp)); 572 segp->unusable = true; 573 } 574 575 static void kvm_seg_fill_gdt_64bit(struct kvm_vm *vm, struct kvm_segment *segp) 576 { 577 void *gdt = addr_gva2hva(vm, vm->arch.gdt); 578 struct desc64 *desc = gdt + (segp->selector >> 3) * 8; 579 580 desc->limit0 = segp->limit & 0xFFFF; 581 desc->base0 = segp->base & 0xFFFF; 582 desc->base1 = segp->base >> 16; 583 desc->type = segp->type; 584 desc->s = segp->s; 585 desc->dpl = segp->dpl; 586 desc->p = segp->present; 587 desc->limit1 = segp->limit >> 16; 588 desc->avl = segp->avl; 589 desc->l = segp->l; 590 desc->db = segp->db; 591 desc->g = segp->g; 592 desc->base2 = segp->base >> 24; 593 if (!segp->s) 594 desc->base3 = segp->base >> 32; 595 } 596 597 static void kvm_seg_set_kernel_code_64bit(struct kvm_segment *segp) 598 { 599 memset(segp, 0, sizeof(*segp)); 600 segp->selector = KERNEL_CS; 601 segp->limit = 0xFFFFFFFFu; 602 segp->s = 0x1; /* kTypeCodeData */ 603 segp->type = 0x08 | 0x01 | 0x02; /* kFlagCode | kFlagCodeAccessed 604 * | kFlagCodeReadable 605 */ 606 segp->g = true; 607 segp->l = true; 608 segp->present = 1; 609 } 610 611 static void kvm_seg_set_kernel_data_64bit(struct kvm_segment *segp) 612 { 613 memset(segp, 0, sizeof(*segp)); 614 segp->selector = KERNEL_DS; 615 segp->limit = 0xFFFFFFFFu; 616 segp->s = 0x1; /* kTypeCodeData */ 617 segp->type = 0x00 | 0x01 | 0x02; /* kFlagData | kFlagDataAccessed 618 * | kFlagDataWritable 619 */ 620 segp->g = true; 621 segp->present = true; 622 } 623 624 gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) 625 { 626 int level = PG_LEVEL_NONE; 627 u64 *pte = __vm_get_page_table_entry(vm, &vm->mmu, gva, &level); 628 629 TEST_ASSERT(is_present_pte(&vm->mmu, pte), 630 "Leaf PTE not PRESENT for gva: 0x%08lx", gva); 631 632 /* 633 * No need for a hugepage mask on the PTE, x86-64 requires the "unused" 634 * address bits to be zero. 635 */ 636 return vm_untag_gpa(vm, PTE_GET_PA(*pte)) | (gva & ~HUGEPAGE_MASK(level)); 637 } 638 639 static void kvm_seg_set_tss_64bit(gva_t base, struct kvm_segment *segp) 640 { 641 memset(segp, 0, sizeof(*segp)); 642 segp->base = base; 643 segp->limit = 0x67; 644 segp->selector = KERNEL_TSS; 645 segp->type = 0xb; 646 segp->present = 1; 647 } 648 649 static void vcpu_init_sregs(struct kvm_vm *vm, struct kvm_vcpu *vcpu) 650 { 651 struct kvm_sregs sregs; 652 653 TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K, 654 "Unknown or unsupported guest mode: 0x%x", vm->mode); 655 656 /* Set mode specific system register values. */ 657 vcpu_sregs_get(vcpu, &sregs); 658 659 sregs.idt.base = vm->arch.idt; 660 sregs.idt.limit = NUM_INTERRUPTS * sizeof(struct idt_entry) - 1; 661 sregs.gdt.base = vm->arch.gdt; 662 sregs.gdt.limit = getpagesize() - 1; 663 664 sregs.cr0 = X86_CR0_PE | X86_CR0_NE | X86_CR0_PG; 665 sregs.cr4 |= X86_CR4_PAE | X86_CR4_OSFXSR; 666 if (kvm_cpu_has(X86_FEATURE_XSAVE)) 667 sregs.cr4 |= X86_CR4_OSXSAVE; 668 if (vm->mmu.pgtable_levels == 5) 669 sregs.cr4 |= X86_CR4_LA57; 670 sregs.efer |= (EFER_LME | EFER_LMA | EFER_NX); 671 672 kvm_seg_set_unusable(&sregs.ldt); 673 kvm_seg_set_kernel_code_64bit(&sregs.cs); 674 kvm_seg_set_kernel_data_64bit(&sregs.ds); 675 kvm_seg_set_kernel_data_64bit(&sregs.es); 676 kvm_seg_set_kernel_data_64bit(&sregs.gs); 677 kvm_seg_set_tss_64bit(vm->arch.tss, &sregs.tr); 678 679 sregs.cr3 = vm->mmu.pgd; 680 vcpu_sregs_set(vcpu, &sregs); 681 } 682 683 static void vcpu_init_xcrs(struct kvm_vm *vm, struct kvm_vcpu *vcpu) 684 { 685 struct kvm_xcrs xcrs = { 686 .nr_xcrs = 1, 687 .xcrs[0].xcr = 0, 688 .xcrs[0].value = kvm_cpu_supported_xcr0(), 689 }; 690 691 if (!kvm_cpu_has(X86_FEATURE_XSAVE)) 692 return; 693 694 vcpu_xcrs_set(vcpu, &xcrs); 695 } 696 697 static void set_idt_entry(struct kvm_vm *vm, int vector, unsigned long addr, 698 int dpl, unsigned short selector) 699 { 700 struct idt_entry *base = 701 (struct idt_entry *)addr_gva2hva(vm, vm->arch.idt); 702 struct idt_entry *e = &base[vector]; 703 704 memset(e, 0, sizeof(*e)); 705 e->offset0 = addr; 706 e->selector = selector; 707 e->ist = 0; 708 e->type = 14; 709 e->dpl = dpl; 710 e->p = 1; 711 e->offset1 = addr >> 16; 712 e->offset2 = addr >> 32; 713 } 714 715 static bool kvm_fixup_exception(struct ex_regs *regs) 716 { 717 if (regs->r9 != KVM_EXCEPTION_MAGIC || regs->rip != regs->r10) 718 return false; 719 720 if (regs->vector == DE_VECTOR) 721 regs->vector = KVM_MAGIC_DE_VECTOR; 722 723 regs->rip = regs->r11; 724 regs->r9 = regs->vector; 725 regs->r10 = regs->error_code; 726 return true; 727 } 728 729 void route_exception(struct ex_regs *regs) 730 { 731 typedef void(*handler)(struct ex_regs *); 732 handler *handlers = (handler *)exception_handlers; 733 734 if (handlers && handlers[regs->vector]) { 735 handlers[regs->vector](regs); 736 return; 737 } 738 739 if (kvm_fixup_exception(regs)) 740 return; 741 742 GUEST_FAIL("Unhandled exception '0x%lx' at guest RIP '0x%lx'", 743 regs->vector, regs->rip); 744 } 745 746 static void vm_init_descriptor_tables(struct kvm_vm *vm) 747 { 748 extern void *idt_handlers; 749 struct kvm_segment seg; 750 int i; 751 752 vm->arch.gdt = __vm_alloc_page(vm, MEM_REGION_DATA); 753 vm->arch.idt = __vm_alloc_page(vm, MEM_REGION_DATA); 754 vm->handlers = __vm_alloc_page(vm, MEM_REGION_DATA); 755 vm->arch.tss = __vm_alloc_page(vm, MEM_REGION_DATA); 756 757 /* Handlers have the same address in both address spaces.*/ 758 for (i = 0; i < NUM_INTERRUPTS; i++) 759 set_idt_entry(vm, i, (unsigned long)(&idt_handlers)[i], 0, KERNEL_CS); 760 761 *(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers; 762 763 kvm_seg_set_kernel_code_64bit(&seg); 764 kvm_seg_fill_gdt_64bit(vm, &seg); 765 766 kvm_seg_set_kernel_data_64bit(&seg); 767 kvm_seg_fill_gdt_64bit(vm, &seg); 768 769 kvm_seg_set_tss_64bit(vm->arch.tss, &seg); 770 kvm_seg_fill_gdt_64bit(vm, &seg); 771 } 772 773 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 774 void (*handler)(struct ex_regs *)) 775 { 776 gva_t *handlers = (gva_t *)addr_gva2hva(vm, vm->handlers); 777 778 handlers[vector] = (gva_t)handler; 779 } 780 781 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 782 { 783 struct ucall uc; 784 785 if (get_ucall(vcpu, &uc) == UCALL_ABORT) 786 REPORT_GUEST_ASSERT(uc); 787 } 788 789 gva_t vm_alloc_stack(struct kvm_vm *vm, int nr_pages) 790 { 791 int size = nr_pages * getpagesize(); 792 gva_t stack_gva; 793 794 stack_gva = __vm_alloc(vm, size, DEFAULT_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); 795 stack_gva += size; 796 797 /* 798 * Align stack to match calling sequence requirements in section "The 799 * Stack Frame" of the System V ABI AMD64 Architecture Processor 800 * Supplement, which requires the value (%rsp + 8) to be a multiple of 801 * 16 when control is transferred to the function entry point. 802 * 803 * If this code is ever used to launch a vCPU with 32-bit entry point it 804 * may need to subtract 4 bytes instead of 8 bytes. 805 */ 806 TEST_ASSERT(IS_ALIGNED(stack_gva, PAGE_SIZE), 807 "__vm_alloc() did not provide a page-aligned address"); 808 stack_gva -= 8; 809 810 return stack_gva; 811 } 812 813 void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus) 814 { 815 int r; 816 817 TEST_ASSERT(kvm_has_cap(KVM_CAP_GET_TSC_KHZ), 818 "Require KVM_GET_TSC_KHZ to provide udelay() to guest."); 819 820 vm_create_irqchip(vm); 821 vm_init_descriptor_tables(vm); 822 823 sync_global_to_guest(vm, host_cpu_is_intel); 824 sync_global_to_guest(vm, host_cpu_is_amd); 825 sync_global_to_guest(vm, host_cpu_is_hygon); 826 sync_global_to_guest(vm, host_cpu_is_amd_compatible); 827 sync_global_to_guest(vm, host_cpu_is_zhaoxin); 828 sync_global_to_guest(vm, host_cpu_is_intel_compatible); 829 sync_global_to_guest(vm, is_forced_emulation_enabled); 830 sync_global_to_guest(vm, pmu_errata_mask); 831 832 if (is_sev_vm(vm)) { 833 struct kvm_sev_init init = { 0 }; 834 835 vm_sev_ioctl(vm, KVM_SEV_INIT2, &init); 836 } 837 838 r = __vm_ioctl(vm, KVM_GET_TSC_KHZ, NULL); 839 TEST_ASSERT(r > 0, "KVM_GET_TSC_KHZ did not provide a valid TSC frequency."); 840 guest_tsc_khz = r; 841 sync_global_to_guest(vm, guest_tsc_khz); 842 843 /* 844 * The guest MMU is just a placeholder to provide access to PTE masks 845 * (for now). The guest does not have mappings for its own page tables 846 * by default, so any meaningful use of guest page tables requires 847 * explicit setup by the test. Zero the PGD to make it obvious the guest 848 * page tables are not immediately usable by guest code. 849 */ 850 guest_mmu = vm->mmu; 851 guest_mmu.pgd = 0; 852 sync_global_to_guest(vm, guest_mmu); 853 } 854 855 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) 856 { 857 struct kvm_regs regs; 858 859 vcpu_regs_get(vcpu, ®s); 860 regs.rip = (unsigned long) guest_code; 861 vcpu_regs_set(vcpu, ®s); 862 } 863 864 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) 865 { 866 struct kvm_mp_state mp_state; 867 struct kvm_regs regs; 868 struct kvm_vcpu *vcpu; 869 870 vcpu = __vm_vcpu_add(vm, vcpu_id); 871 vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid()); 872 vcpu_init_sregs(vm, vcpu); 873 vcpu_init_xcrs(vm, vcpu); 874 875 /* Setup guest general purpose registers */ 876 vcpu_regs_get(vcpu, ®s); 877 regs.rflags = regs.rflags | X86_EFLAGS_FIXED; 878 regs.rsp = vm_alloc_stack(vm, DEFAULT_STACK_PGS); 879 vcpu_regs_set(vcpu, ®s); 880 881 /* Setup the MP state */ 882 mp_state.mp_state = 0; 883 vcpu_mp_state_set(vcpu, &mp_state); 884 885 /* 886 * Refresh CPUID after setting SREGS and XCR0, so that KVM's "runtime" 887 * updates to guest CPUID, e.g. for OSXSAVE and XSAVE state size, are 888 * reflected into selftests' vCPU CPUID cache, i.e. so that the cache 889 * is consistent with vCPU state. 890 */ 891 vcpu_get_cpuid(vcpu); 892 return vcpu; 893 } 894 895 struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, u32 vcpu_id) 896 { 897 struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); 898 899 vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid()); 900 901 return vcpu; 902 } 903 904 void vcpu_arch_free(struct kvm_vcpu *vcpu) 905 { 906 if (vcpu->cpuid) 907 free(vcpu->cpuid); 908 } 909 910 /* Do not use kvm_supported_cpuid directly except for validity checks. */ 911 static void *kvm_supported_cpuid; 912 913 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void) 914 { 915 int kvm_fd; 916 917 if (kvm_supported_cpuid) 918 return kvm_supported_cpuid; 919 920 kvm_supported_cpuid = allocate_kvm_cpuid2(MAX_NR_CPUID_ENTRIES); 921 kvm_fd = open_kvm_dev_path_or_exit(); 922 923 kvm_ioctl(kvm_fd, KVM_GET_SUPPORTED_CPUID, 924 (struct kvm_cpuid2 *)kvm_supported_cpuid); 925 926 close(kvm_fd); 927 return kvm_supported_cpuid; 928 } 929 930 static u32 __kvm_cpu_has(const struct kvm_cpuid2 *cpuid, 931 u32 function, u32 index, 932 u8 reg, u8 lo, u8 hi) 933 { 934 const struct kvm_cpuid_entry2 *entry; 935 int i; 936 937 for (i = 0; i < cpuid->nent; i++) { 938 entry = &cpuid->entries[i]; 939 940 /* 941 * The output registers in kvm_cpuid_entry2 are in alphabetical 942 * order, but kvm_x86_cpu_feature matches that mess, so yay 943 * pointer shenanigans! 944 */ 945 if (entry->function == function && entry->index == index) 946 return ((&entry->eax)[reg] & GENMASK(hi, lo)) >> lo; 947 } 948 949 return 0; 950 } 951 952 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 953 struct kvm_x86_cpu_feature feature) 954 { 955 return __kvm_cpu_has(cpuid, feature.function, feature.index, 956 feature.reg, feature.bit, feature.bit); 957 } 958 959 u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 960 struct kvm_x86_cpu_property property) 961 { 962 return __kvm_cpu_has(cpuid, property.function, property.index, 963 property.reg, property.lo_bit, property.hi_bit); 964 } 965 966 u64 kvm_get_feature_msr(u64 msr_index) 967 { 968 struct { 969 struct kvm_msrs header; 970 struct kvm_msr_entry entry; 971 } buffer = {}; 972 int r, kvm_fd; 973 974 buffer.header.nmsrs = 1; 975 buffer.entry.index = msr_index; 976 kvm_fd = open_kvm_dev_path_or_exit(); 977 978 r = __kvm_ioctl(kvm_fd, KVM_GET_MSRS, &buffer.header); 979 TEST_ASSERT(r == 1, KVM_IOCTL_ERROR(KVM_GET_MSRS, r)); 980 981 close(kvm_fd); 982 return buffer.entry.data; 983 } 984 985 void __vm_xsave_require_permission(u64 xfeature, const char *name) 986 { 987 int kvm_fd; 988 u64 bitmask; 989 long rc; 990 struct kvm_device_attr attr = { 991 .group = 0, 992 .attr = KVM_X86_XCOMP_GUEST_SUPP, 993 .addr = (unsigned long) &bitmask, 994 }; 995 996 TEST_ASSERT(!kvm_supported_cpuid, 997 "kvm_get_supported_cpuid() cannot be used before ARCH_REQ_XCOMP_GUEST_PERM"); 998 999 TEST_ASSERT(is_power_of_2(xfeature), 1000 "Dynamic XFeatures must be enabled one at a time"); 1001 1002 kvm_fd = open_kvm_dev_path_or_exit(); 1003 rc = __kvm_ioctl(kvm_fd, KVM_GET_DEVICE_ATTR, &attr); 1004 close(kvm_fd); 1005 1006 if (rc == -1 && (errno == ENXIO || errno == EINVAL)) 1007 __TEST_REQUIRE(0, "KVM_X86_XCOMP_GUEST_SUPP not supported"); 1008 1009 TEST_ASSERT(rc == 0, "KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) error: %ld", rc); 1010 1011 __TEST_REQUIRE(bitmask & xfeature, 1012 "Required XSAVE feature '%s' not supported", name); 1013 1014 TEST_REQUIRE(!syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, ilog2(xfeature))); 1015 1016 rc = syscall(SYS_arch_prctl, ARCH_GET_XCOMP_GUEST_PERM, &bitmask); 1017 TEST_ASSERT(rc == 0, "prctl(ARCH_GET_XCOMP_GUEST_PERM) error: %ld", rc); 1018 TEST_ASSERT(bitmask & xfeature, 1019 "'%s' (0x%lx) not permitted after prctl(ARCH_REQ_XCOMP_GUEST_PERM) permitted=0x%lx", 1020 name, xfeature, bitmask); 1021 } 1022 1023 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid) 1024 { 1025 TEST_ASSERT(cpuid != vcpu->cpuid, "@cpuid can't be the vCPU's CPUID"); 1026 1027 /* Allow overriding the default CPUID. */ 1028 if (vcpu->cpuid && vcpu->cpuid->nent < cpuid->nent) { 1029 free(vcpu->cpuid); 1030 vcpu->cpuid = NULL; 1031 } 1032 1033 if (!vcpu->cpuid) 1034 vcpu->cpuid = allocate_kvm_cpuid2(cpuid->nent); 1035 1036 memcpy(vcpu->cpuid, cpuid, kvm_cpuid2_size(cpuid->nent)); 1037 vcpu_set_cpuid(vcpu); 1038 } 1039 1040 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1041 struct kvm_x86_cpu_property property, 1042 u32 value) 1043 { 1044 struct kvm_cpuid_entry2 *entry; 1045 1046 entry = __vcpu_get_cpuid_entry(vcpu, property.function, property.index); 1047 1048 (&entry->eax)[property.reg] &= ~GENMASK(property.hi_bit, property.lo_bit); 1049 (&entry->eax)[property.reg] |= value << property.lo_bit; 1050 1051 vcpu_set_cpuid(vcpu); 1052 1053 /* Sanity check that @value doesn't exceed the bounds in any way. */ 1054 TEST_ASSERT_EQ(kvm_cpuid_property(vcpu->cpuid, property), value); 1055 } 1056 1057 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function) 1058 { 1059 struct kvm_cpuid_entry2 *entry = vcpu_get_cpuid_entry(vcpu, function); 1060 1061 entry->eax = 0; 1062 entry->ebx = 0; 1063 entry->ecx = 0; 1064 entry->edx = 0; 1065 vcpu_set_cpuid(vcpu); 1066 } 1067 1068 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1069 struct kvm_x86_cpu_feature feature, 1070 bool set) 1071 { 1072 struct kvm_cpuid_entry2 *entry; 1073 u32 *reg; 1074 1075 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1076 reg = (&entry->eax) + feature.reg; 1077 1078 if (set) 1079 *reg |= BIT(feature.bit); 1080 else 1081 *reg &= ~BIT(feature.bit); 1082 1083 vcpu_set_cpuid(vcpu); 1084 } 1085 1086 u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index) 1087 { 1088 struct { 1089 struct kvm_msrs header; 1090 struct kvm_msr_entry entry; 1091 } buffer = {}; 1092 1093 buffer.header.nmsrs = 1; 1094 buffer.entry.index = msr_index; 1095 1096 vcpu_msrs_get(vcpu, &buffer.header); 1097 1098 return buffer.entry.data; 1099 } 1100 1101 int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value) 1102 { 1103 struct { 1104 struct kvm_msrs header; 1105 struct kvm_msr_entry entry; 1106 } buffer = {}; 1107 1108 memset(&buffer, 0, sizeof(buffer)); 1109 buffer.header.nmsrs = 1; 1110 buffer.entry.index = msr_index; 1111 buffer.entry.data = msr_value; 1112 1113 return __vcpu_ioctl(vcpu, KVM_SET_MSRS, &buffer.header); 1114 } 1115 1116 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 1117 { 1118 va_list ap; 1119 struct kvm_regs regs; 1120 1121 TEST_ASSERT(num >= 1 && num <= 6, "Unsupported number of args,\n" 1122 " num: %u", 1123 num); 1124 1125 va_start(ap, num); 1126 vcpu_regs_get(vcpu, ®s); 1127 1128 if (num >= 1) 1129 regs.rdi = va_arg(ap, u64); 1130 1131 if (num >= 2) 1132 regs.rsi = va_arg(ap, u64); 1133 1134 if (num >= 3) 1135 regs.rdx = va_arg(ap, u64); 1136 1137 if (num >= 4) 1138 regs.rcx = va_arg(ap, u64); 1139 1140 if (num >= 5) 1141 regs.r8 = va_arg(ap, u64); 1142 1143 if (num >= 6) 1144 regs.r9 = va_arg(ap, u64); 1145 1146 vcpu_regs_set(vcpu, ®s); 1147 va_end(ap); 1148 } 1149 1150 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) 1151 { 1152 struct kvm_regs regs; 1153 struct kvm_sregs sregs; 1154 1155 fprintf(stream, "%*svCPU ID: %u\n", indent, "", vcpu->id); 1156 1157 fprintf(stream, "%*sregs:\n", indent + 2, ""); 1158 vcpu_regs_get(vcpu, ®s); 1159 regs_dump(stream, ®s, indent + 4); 1160 1161 fprintf(stream, "%*ssregs:\n", indent + 2, ""); 1162 vcpu_sregs_get(vcpu, &sregs); 1163 sregs_dump(stream, &sregs, indent + 4); 1164 } 1165 1166 static struct kvm_msr_list *__kvm_get_msr_index_list(bool feature_msrs) 1167 { 1168 struct kvm_msr_list *list; 1169 struct kvm_msr_list nmsrs; 1170 int kvm_fd, r; 1171 1172 kvm_fd = open_kvm_dev_path_or_exit(); 1173 1174 nmsrs.nmsrs = 0; 1175 if (!feature_msrs) 1176 r = __kvm_ioctl(kvm_fd, KVM_GET_MSR_INDEX_LIST, &nmsrs); 1177 else 1178 r = __kvm_ioctl(kvm_fd, KVM_GET_MSR_FEATURE_INDEX_LIST, &nmsrs); 1179 1180 TEST_ASSERT(r == -1 && errno == E2BIG, 1181 "Expected -E2BIG, got rc: %i errno: %i (%s)", 1182 r, errno, strerror(errno)); 1183 1184 list = malloc(sizeof(*list) + nmsrs.nmsrs * sizeof(list->indices[0])); 1185 TEST_ASSERT(list, "-ENOMEM when allocating MSR index list"); 1186 list->nmsrs = nmsrs.nmsrs; 1187 1188 if (!feature_msrs) 1189 kvm_ioctl(kvm_fd, KVM_GET_MSR_INDEX_LIST, list); 1190 else 1191 kvm_ioctl(kvm_fd, KVM_GET_MSR_FEATURE_INDEX_LIST, list); 1192 close(kvm_fd); 1193 1194 TEST_ASSERT(list->nmsrs == nmsrs.nmsrs, 1195 "Number of MSRs in list changed, was %d, now %d", 1196 nmsrs.nmsrs, list->nmsrs); 1197 return list; 1198 } 1199 1200 const struct kvm_msr_list *kvm_get_msr_index_list(void) 1201 { 1202 static const struct kvm_msr_list *list; 1203 1204 if (!list) 1205 list = __kvm_get_msr_index_list(false); 1206 return list; 1207 } 1208 1209 1210 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void) 1211 { 1212 static const struct kvm_msr_list *list; 1213 1214 if (!list) 1215 list = __kvm_get_msr_index_list(true); 1216 return list; 1217 } 1218 1219 bool kvm_msr_is_in_save_restore_list(u32 msr_index) 1220 { 1221 const struct kvm_msr_list *list = kvm_get_msr_index_list(); 1222 int i; 1223 1224 for (i = 0; i < list->nmsrs; ++i) { 1225 if (list->indices[i] == msr_index) 1226 return true; 1227 } 1228 1229 return false; 1230 } 1231 1232 static void vcpu_save_xsave_state(struct kvm_vcpu *vcpu, 1233 struct kvm_x86_state *state) 1234 { 1235 int size = vm_check_cap(vcpu->vm, KVM_CAP_XSAVE2); 1236 1237 if (size) { 1238 state->xsave = malloc(size); 1239 vcpu_xsave2_get(vcpu, state->xsave); 1240 } else { 1241 state->xsave = malloc(sizeof(struct kvm_xsave)); 1242 vcpu_xsave_get(vcpu, state->xsave); 1243 } 1244 } 1245 1246 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu) 1247 { 1248 const struct kvm_msr_list *msr_list = kvm_get_msr_index_list(); 1249 struct kvm_x86_state *state; 1250 int i; 1251 1252 static int nested_size = -1; 1253 1254 if (nested_size == -1) { 1255 nested_size = kvm_check_cap(KVM_CAP_NESTED_STATE); 1256 TEST_ASSERT(nested_size <= sizeof(state->nested_), 1257 "Nested state size too big, %i > %zi", 1258 nested_size, sizeof(state->nested_)); 1259 } 1260 1261 /* 1262 * When KVM exits to userspace with KVM_EXIT_IO, KVM guarantees 1263 * guest state is consistent only after userspace re-enters the 1264 * kernel with KVM_RUN. Complete IO prior to migrating state 1265 * to a new VM. 1266 */ 1267 vcpu_run_complete_io(vcpu); 1268 1269 state = malloc(sizeof(*state) + msr_list->nmsrs * sizeof(state->msrs.entries[0])); 1270 TEST_ASSERT(state, "-ENOMEM when allocating kvm state"); 1271 1272 vcpu_events_get(vcpu, &state->events); 1273 vcpu_mp_state_get(vcpu, &state->mp_state); 1274 vcpu_regs_get(vcpu, &state->regs); 1275 vcpu_save_xsave_state(vcpu, state); 1276 1277 if (kvm_has_cap(KVM_CAP_XCRS)) 1278 vcpu_xcrs_get(vcpu, &state->xcrs); 1279 1280 vcpu_sregs_get(vcpu, &state->sregs); 1281 1282 if (nested_size) { 1283 state->nested.size = sizeof(state->nested_); 1284 1285 vcpu_nested_state_get(vcpu, &state->nested); 1286 TEST_ASSERT(state->nested.size <= nested_size, 1287 "Nested state size too big, %i (KVM_CHECK_CAP gave %i)", 1288 state->nested.size, nested_size); 1289 } else { 1290 state->nested.size = 0; 1291 } 1292 1293 state->msrs.nmsrs = msr_list->nmsrs; 1294 for (i = 0; i < msr_list->nmsrs; i++) 1295 state->msrs.entries[i].index = msr_list->indices[i]; 1296 vcpu_msrs_get(vcpu, &state->msrs); 1297 1298 vcpu_debugregs_get(vcpu, &state->debugregs); 1299 1300 return state; 1301 } 1302 1303 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state) 1304 { 1305 vcpu_sregs_set(vcpu, &state->sregs); 1306 vcpu_msrs_set(vcpu, &state->msrs); 1307 1308 if (kvm_has_cap(KVM_CAP_XCRS)) 1309 vcpu_xcrs_set(vcpu, &state->xcrs); 1310 1311 vcpu_xsave_set(vcpu, state->xsave); 1312 vcpu_events_set(vcpu, &state->events); 1313 vcpu_mp_state_set(vcpu, &state->mp_state); 1314 vcpu_debugregs_set(vcpu, &state->debugregs); 1315 vcpu_regs_set(vcpu, &state->regs); 1316 1317 if (state->nested.size) 1318 vcpu_nested_state_set(vcpu, &state->nested); 1319 } 1320 1321 void kvm_x86_state_cleanup(struct kvm_x86_state *state) 1322 { 1323 free(state->xsave); 1324 free(state); 1325 } 1326 1327 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits) 1328 { 1329 if (!kvm_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) { 1330 *pa_bits = kvm_cpu_has(X86_FEATURE_PAE) ? 36 : 32; 1331 *va_bits = 32; 1332 } else { 1333 *pa_bits = kvm_cpu_property(X86_PROPERTY_MAX_PHY_ADDR); 1334 *va_bits = kvm_cpu_property(X86_PROPERTY_MAX_VIRT_ADDR); 1335 } 1336 } 1337 1338 void kvm_init_vm_address_properties(struct kvm_vm *vm) 1339 { 1340 if (is_sev_vm(vm)) { 1341 vm->arch.sev_fd = open_sev_dev_path_or_exit(); 1342 vm->arch.c_bit = BIT_ULL(this_cpu_property(X86_PROPERTY_SEV_C_BIT)); 1343 vm->gpa_tag_mask = vm->arch.c_bit; 1344 } else { 1345 vm->arch.sev_fd = -1; 1346 } 1347 } 1348 1349 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 1350 u32 function, u32 index) 1351 { 1352 int i; 1353 1354 for (i = 0; i < cpuid->nent; i++) { 1355 if (cpuid->entries[i].function == function && 1356 cpuid->entries[i].index == index) 1357 return &cpuid->entries[i]; 1358 } 1359 1360 TEST_FAIL("CPUID function 0x%x index 0x%x not found ", function, index); 1361 1362 return NULL; 1363 } 1364 1365 #define X86_HYPERCALL(inputs...) \ 1366 ({ \ 1367 u64 r; \ 1368 \ 1369 asm volatile("test %[use_vmmcall], %[use_vmmcall]\n\t" \ 1370 "jnz 1f\n\t" \ 1371 "vmcall\n\t" \ 1372 "jmp 2f\n\t" \ 1373 "1: vmmcall\n\t" \ 1374 "2:" \ 1375 : "=a"(r) \ 1376 : [use_vmmcall] "r" (host_cpu_is_amd_compatible), \ 1377 inputs); \ 1378 \ 1379 r; \ 1380 }) 1381 1382 u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3) 1383 { 1384 return X86_HYPERCALL("a"(nr), "b"(a0), "c"(a1), "d"(a2), "S"(a3)); 1385 } 1386 1387 u64 __xen_hypercall(u64 nr, u64 a0, void *a1) 1388 { 1389 return X86_HYPERCALL("a"(nr), "D"(a0), "S"(a1)); 1390 } 1391 1392 void xen_hypercall(u64 nr, u64 a0, void *a1) 1393 { 1394 GUEST_ASSERT(!__xen_hypercall(nr, a0, a1)); 1395 } 1396 1397 unsigned long vm_compute_max_gfn(struct kvm_vm *vm) 1398 { 1399 const unsigned long num_ht_pages = 12 << (30 - vm->page_shift); /* 12 GiB */ 1400 unsigned long ht_gfn, max_gfn, max_pfn; 1401 u8 maxphyaddr, guest_maxphyaddr; 1402 1403 /* 1404 * Use "guest MAXPHYADDR" from KVM if it's available. Guest MAXPHYADDR 1405 * enumerates the max _mappable_ GPA, which can be less than the raw 1406 * MAXPHYADDR, e.g. if MAXPHYADDR=52, KVM is using TDP, and the CPU 1407 * doesn't support 5-level TDP. 1408 */ 1409 guest_maxphyaddr = kvm_cpu_property(X86_PROPERTY_GUEST_MAX_PHY_ADDR); 1410 guest_maxphyaddr = guest_maxphyaddr ?: vm->pa_bits; 1411 TEST_ASSERT(guest_maxphyaddr <= vm->pa_bits, 1412 "Guest MAXPHYADDR should never be greater than raw MAXPHYADDR"); 1413 1414 max_gfn = (1ULL << (guest_maxphyaddr - vm->page_shift)) - 1; 1415 1416 /* Avoid reserved HyperTransport region on AMD or Hygon processors. */ 1417 if (!host_cpu_is_amd_compatible) 1418 return max_gfn; 1419 1420 /* On parts with <40 physical address bits, the area is fully hidden */ 1421 if (vm->pa_bits < 40) 1422 return max_gfn; 1423 1424 /* Before family 17h, the HyperTransport area is just below 1T. */ 1425 ht_gfn = (1 << 28) - num_ht_pages; 1426 if (this_cpu_family() < 0x17) 1427 goto done; 1428 1429 /* 1430 * Otherwise it's at the top of the physical address space, possibly 1431 * reduced due to SME or CSV by bits 11:6 of CPUID[0x8000001f].EBX. Use 1432 * the old conservative value if MAXPHYADDR is not enumerated. 1433 */ 1434 if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) 1435 goto done; 1436 1437 maxphyaddr = this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR); 1438 max_pfn = (1ULL << (maxphyaddr - vm->page_shift)) - 1; 1439 1440 if (this_cpu_has_p(X86_PROPERTY_PHYS_ADDR_REDUCTION)) 1441 max_pfn >>= this_cpu_property(X86_PROPERTY_PHYS_ADDR_REDUCTION); 1442 1443 ht_gfn = max_pfn - num_ht_pages; 1444 done: 1445 return min(max_gfn, ht_gfn - 1); 1446 } 1447 1448 void kvm_selftest_arch_init(void) 1449 { 1450 host_cpu_is_intel = this_cpu_is_intel(); 1451 host_cpu_is_amd = this_cpu_is_amd(); 1452 host_cpu_is_hygon = this_cpu_is_hygon(); 1453 host_cpu_is_amd_compatible = host_cpu_is_amd || host_cpu_is_hygon; 1454 host_cpu_is_zhaoxin = this_cpu_is_zhaoxin(); 1455 host_cpu_is_intel_compatible = host_cpu_is_intel || host_cpu_is_zhaoxin; 1456 is_forced_emulation_enabled = kvm_is_forced_emulation_enabled(); 1457 1458 kvm_init_pmu_errata(); 1459 } 1460 1461 bool sys_clocksource_is_based_on_tsc(void) 1462 { 1463 char *clk_name = sys_get_cur_clocksource(); 1464 bool ret = !strcmp(clk_name, "tsc\n") || 1465 !strcmp(clk_name, "hyperv_clocksource_tsc_page\n"); 1466 1467 free(clk_name); 1468 1469 return ret; 1470 } 1471 1472 bool kvm_arch_has_default_irqchip(void) 1473 { 1474 return true; 1475 } 1476 1477 void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, gpa_t smram_gpa, 1478 const void *smi_handler, size_t handler_size) 1479 { 1480 vm_override_mem_region(vm, MEM_REGION_TEST_EXTRA, VM_MEM_SRC_ANONYMOUS, 1481 smram_gpa, SMRAM_MEMSLOT, SMRAM_PAGES); 1482 1483 TEST_ASSERT(vm_phy_pages_alloc(vm, SMRAM_PAGES, MEM_REGION_TEST_EXTRA) == smram_gpa, 1484 "Could not allocate guest physical addresses for SMRAM"); 1485 1486 memset(addr_gpa2hva(vm, smram_gpa), 0x0, SMRAM_SIZE); 1487 memcpy(addr_gpa2hva(vm, smram_gpa) + 0x8000, smi_handler, handler_size); 1488 vcpu_set_msr(vcpu, MSR_IA32_SMBASE, smram_gpa); 1489 } 1490 1491 void inject_smi(struct kvm_vcpu *vcpu) 1492 { 1493 struct kvm_vcpu_events events; 1494 1495 vcpu_events_get(vcpu, &events); 1496 events.smi.pending = 1; 1497 events.flags |= KVM_VCPUEVENT_VALID_SMM; 1498 vcpu_events_set(vcpu, &events); 1499 } 1500