1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 /** 143 * 144 * dirty rect cmd version legacy 145 */ 146 #define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 147 /** 148 * dirty rect cmd version with multi edp support 149 */ 150 #define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 151 /** 152 * dirty rect cmd version with external monitor support 153 */ 154 #define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 155 156 /** 157 * 158 * Cursor update cmd version legacy 159 */ 160 #define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 161 /** 162 * Cursor update cmd version with multi edp support 163 */ 164 #define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 165 /** 166 * Cursor update cmd version with external monitor support 167 */ 168 #define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 169 170 /** 171 * ABM control version legacy 172 */ 173 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 174 175 /** 176 * ABM control version with multi edp support 177 */ 178 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 179 180 /** 181 * Physical framebuffer address location, 64-bit. 182 */ 183 #ifndef PHYSICAL_ADDRESS_LOC 184 #define PHYSICAL_ADDRESS_LOC union large_integer 185 #endif 186 187 /** 188 * OS/FW agnostic memcpy 189 */ 190 #ifndef dmub_memcpy 191 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 192 #endif 193 194 /** 195 * OS/FW agnostic memset 196 */ 197 #ifndef dmub_memset 198 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 199 #endif 200 201 /** 202 * OS/FW agnostic memcmp 203 */ 204 #ifndef dmub_memcmp 205 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 206 #endif 207 208 /** 209 * OS/FW agnostic udelay 210 */ 211 #ifndef dmub_udelay 212 #define dmub_udelay(microseconds) udelay(microseconds) 213 #endif 214 215 #pragma pack(push, 1) 216 #define ABM_NUM_OF_ACE_SEGMENTS 5 217 218 /** 219 * Debug FW state offset 220 */ 221 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 222 223 union abm_flags { 224 struct { 225 /** 226 * @abm_enabled: Indicates if ABM is enabled. 227 */ 228 unsigned int abm_enabled : 1; 229 230 /** 231 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 232 */ 233 unsigned int disable_abm_requested : 1; 234 235 /** 236 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 237 */ 238 unsigned int disable_abm_immediately : 1; 239 240 /** 241 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 242 * to be disabled immediately and keep gain. 243 */ 244 unsigned int disable_abm_immediate_keep_gain : 1; 245 246 /** 247 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 248 */ 249 unsigned int fractional_pwm : 1; 250 251 /** 252 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 253 * of user backlight level. 254 */ 255 unsigned int abm_gradual_bl_change : 1; 256 257 /** 258 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 259 */ 260 unsigned int abm_new_frame : 1; 261 262 /** 263 * @vb_scaling_enabled: Indicates variBright Scaling Enable 264 */ 265 unsigned int vb_scaling_enabled : 1; 266 } bitfields; 267 268 unsigned int u32All; 269 }; 270 271 struct abm_save_restore { 272 /** 273 * @flags: Misc. ABM flags. 274 */ 275 union abm_flags flags; 276 277 /** 278 * @pause: true: pause ABM and get state 279 * false: unpause ABM after setting state 280 */ 281 uint32_t pause; 282 283 /** 284 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 285 */ 286 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 287 288 /** 289 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 290 */ 291 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 292 293 /** 294 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 295 */ 296 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 297 298 299 /** 300 * @knee_threshold: Current x-position of ACE knee (u0.16). 301 */ 302 uint32_t knee_threshold; 303 /** 304 * @current_gain: Current backlight reduction (u16.16). 305 */ 306 uint32_t current_gain; 307 /** 308 * @curr_bl_level: Current actual backlight level converging to target backlight level. 309 */ 310 uint16_t curr_bl_level; 311 312 /** 313 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 314 */ 315 uint16_t curr_user_bl_level; 316 317 }; 318 319 /** 320 * union dmub_addr - DMUB physical/virtual 64-bit address. 321 */ 322 union dmub_addr { 323 struct { 324 uint32_t low_part; /**< Lower 32 bits */ 325 uint32_t high_part; /**< Upper 32 bits */ 326 } u; /*<< Low/high bit access */ 327 uint64_t quad_part; /*<< 64 bit address */ 328 }; 329 330 /* Flattened structure containing SOC BB parameters stored in the VBIOS 331 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 332 * This also prevents alighment issues when new parameters are added to the SoC BB. 333 * The following parameters should be added since these values can't be obtained elsewhere: 334 * -dml2_soc_power_management_parameters 335 * -dml2_soc_vmin_clock_limits 336 */ 337 struct dmub_soc_bb_params { 338 uint32_t dram_clk_change_blackout_ns; 339 uint32_t dram_clk_change_read_only_ns; 340 uint32_t dram_clk_change_write_only_ns; 341 uint32_t fclk_change_blackout_ns; 342 uint32_t g7_ppt_blackout_ns; 343 uint32_t stutter_enter_plus_exit_latency_ns; 344 uint32_t stutter_exit_latency_ns; 345 uint32_t z8_stutter_enter_plus_exit_latency_ns; 346 uint32_t z8_stutter_exit_latency_ns; 347 uint32_t z8_min_idle_time_ns; 348 uint32_t type_b_dram_clk_change_blackout_ns; 349 uint32_t type_b_ppt_blackout_ns; 350 uint32_t vmin_limit_dispclk_khz; 351 uint32_t vmin_limit_dcfclk_khz; 352 uint32_t g7_temperature_read_blackout_ns; 353 }; 354 #pragma pack(pop) 355 356 /** 357 * Dirty rect definition. 358 */ 359 struct dmub_rect { 360 /** 361 * Dirty rect x offset. 362 */ 363 uint32_t x; 364 365 /** 366 * Dirty rect y offset. 367 */ 368 uint32_t y; 369 370 /** 371 * Dirty rect width. 372 */ 373 uint32_t width; 374 375 /** 376 * Dirty rect height. 377 */ 378 uint32_t height; 379 }; 380 381 /** 382 * Flags that can be set by driver to change some PSR behaviour. 383 */ 384 union dmub_psr_debug_flags { 385 /** 386 * Debug flags. 387 */ 388 struct { 389 /** 390 * Enable visual confirm in FW. 391 */ 392 uint32_t visual_confirm : 1; 393 394 /** 395 * Force all selective updates to bw full frame updates. 396 */ 397 uint32_t force_full_frame_update : 1; 398 399 /** 400 * Use HW Lock Mgr object to do HW locking in FW. 401 */ 402 uint32_t use_hw_lock_mgr : 1; 403 404 /** 405 * Use TPS3 signal when restore main link. 406 */ 407 uint32_t force_wakeup_by_tps3 : 1; 408 409 /** 410 * Back to back flip, therefore cannot power down PHY 411 */ 412 uint32_t back_to_back_flip : 1; 413 414 /** 415 * Enable visual confirm for IPS 416 */ 417 uint32_t enable_ips_visual_confirm : 1; 418 } bitfields; 419 420 /** 421 * Union for debug flags. 422 */ 423 uint32_t u32All; 424 }; 425 426 /** 427 * Flags that can be set by driver to change some Replay behaviour. 428 */ 429 union replay_debug_flags { 430 struct { 431 /** 432 * 0x1 (bit 0) 433 * Enable visual confirm in FW. 434 */ 435 uint32_t visual_confirm : 1; 436 437 /** 438 * 0x2 (bit 1) 439 * @skip_crc: Set if need to skip CRC. 440 */ 441 uint32_t skip_crc : 1; 442 443 /** 444 * 0x4 (bit 2) 445 * @force_link_power_on: Force disable ALPM control 446 */ 447 uint32_t force_link_power_on : 1; 448 449 /** 450 * 0x8 (bit 3) 451 * @force_phy_power_on: Force phy power on 452 */ 453 uint32_t force_phy_power_on : 1; 454 455 /** 456 * 0x10 (bit 4) 457 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 458 */ 459 uint32_t timing_resync_disabled : 1; 460 461 /** 462 * 0x20 (bit 5) 463 * @skip_crtc_disabled: CRTC disable skipped 464 */ 465 uint32_t skip_crtc_disabled : 1; 466 467 /** 468 * 0x40 (bit 6) 469 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 470 */ 471 uint32_t force_defer_one_frame_update : 1; 472 473 /** 474 * 0x80 (bit 7) 475 * @disable_delay_alpm_on: Force disable delay alpm on 476 */ 477 uint32_t disable_delay_alpm_on : 1; 478 479 /** 480 * 0x100 (bit 8) 481 * @disable_desync_error_check: Force disable desync error check 482 */ 483 uint32_t disable_desync_error_check : 1; 484 485 /** 486 * 0x200 (bit 9) 487 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 488 */ 489 uint32_t force_self_update_when_abm_non_steady : 1; 490 491 /** 492 * 0x400 (bit 10) 493 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 494 * If we enter IPS2, the Visual confirm bar will change to yellow 495 */ 496 uint32_t enable_ips_visual_confirm : 1; 497 498 /** 499 * 0x800 (bit 11) 500 * @enable_ips_residency_profiling: Enable IPS residency profiling 501 */ 502 uint32_t enable_ips_residency_profiling : 1; 503 504 /** 505 * 0x1000 (bit 12) 506 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 507 */ 508 uint32_t enable_coasting_vtotal_check : 1; 509 /** 510 * 0x2000 (bit 13) 511 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 512 */ 513 uint32_t enable_visual_confirm_debug : 1; 514 515 /** 516 * 0x4000 (bit 14) 517 * @debug_log_enabled: Debug Log Enabled 518 */ 519 uint32_t debug_log_enabled : 1; 520 521 /** 522 * 0x8000 (bit 15) 523 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm 524 */ 525 uint32_t enable_sub_feature_visual_confirm : 1; 526 527 uint32_t reserved : 16; 528 } bitfields; 529 530 uint32_t u32All; 531 }; 532 533 /** 534 * Flags record error state. 535 */ 536 union replay_visual_confirm_error_state_flags { 537 struct { 538 /** 539 * 0x1 (bit 0) - Desync Error flag. 540 */ 541 uint32_t desync_error : 1; 542 543 /** 544 * 0x2 (bit 1) - State Transition Error flag. 545 */ 546 uint32_t state_transition_error : 1; 547 548 /** 549 * 0x4 (bit 2) - Crc Error flag 550 */ 551 uint32_t crc_error : 1; 552 553 /** 554 * 0x8 (bit 3) - Reserved 555 */ 556 uint32_t reserved_3 : 1; 557 558 /** 559 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 560 * Added new debug flag to control DPCD. 561 */ 562 uint32_t incorrect_vtotal_in_static_screen : 1; 563 564 /** 565 * 0x20 (bit 5) - No doubled Refresh Rate. 566 */ 567 uint32_t no_double_rr : 1; 568 569 /** 570 * Reserved bit 6-7 571 */ 572 uint32_t reserved_6_7 : 2; 573 574 /** 575 * Reserved bit 9-31 576 */ 577 uint32_t reserved_9_31 : 24; 578 } bitfields; 579 580 uint32_t u32All; 581 }; 582 583 union replay_hw_flags { 584 struct { 585 /** 586 * @allow_alpm_fw_standby_mode: To indicate whether the 587 * ALPM FW standby mode is allowed 588 */ 589 uint32_t allow_alpm_fw_standby_mode : 1; 590 591 /* 592 * @dsc_enable_status: DSC enable status in driver 593 */ 594 uint32_t dsc_enable_status : 1; 595 596 /** 597 * @fec_enable_status: receive fec enable/disable status from driver 598 */ 599 uint32_t fec_enable_status : 1; 600 601 /* 602 * @smu_optimizations_en: SMU power optimization. 603 * Only when active display is Replay capable and display enters Replay. 604 * Trigger interrupt to SMU to powerup/down. 605 */ 606 uint32_t smu_optimizations_en : 1; 607 608 /** 609 * @phy_power_state: Indicates current phy power state 610 */ 611 uint32_t phy_power_state : 1; 612 613 /** 614 * @link_power_state: Indicates current link power state 615 */ 616 uint32_t link_power_state : 1; 617 /** 618 * Use TPS3 signal when restore main link. 619 */ 620 uint32_t force_wakeup_by_tps3 : 1; 621 /** 622 * @is_alpm_initialized: Indicates whether ALPM is initialized 623 */ 624 uint32_t is_alpm_initialized : 1; 625 626 /** 627 * @alpm_mode: Indicates ALPM mode selected 628 */ 629 uint32_t alpm_mode : 2; 630 } bitfields; 631 632 uint32_t u32All; 633 }; 634 635 /** 636 * Flags that can be set by driver to change some Panel Replay behaviour. 637 */ 638 union pr_debug_flags { 639 struct { 640 /** 641 * 0x1 (bit 0) 642 * Enable visual confirm in FW. 643 */ 644 uint32_t visual_confirm : 1; 645 646 /** 647 * 0x2 (bit 1) 648 * @skip_crc: Set if need to skip CRC. 649 */ 650 uint32_t skip_crc : 1; 651 652 /** 653 * 0x4 (bit 2) 654 * @force_link_power_on: Force disable ALPM control 655 */ 656 uint32_t force_link_power_on : 1; 657 658 /** 659 * 0x8 (bit 3) 660 * @force_phy_power_on: Force phy power on 661 */ 662 uint32_t force_phy_power_on : 1; 663 664 /** 665 * 0x10 (bit 4) 666 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection 667 */ 668 uint32_t visual_confirm_rate_control : 1; 669 670 /** 671 * 0x20 (bit 5) 672 * @force_full_frame_update: Force all selective updates to be full frame updates 673 */ 674 uint32_t force_full_frame_update : 1; 675 676 /** 677 * 0x40 (bit 6) 678 * @force_dpg_on: Force DPG on 679 */ 680 uint32_t force_dpg_on : 1; 681 682 /** 683 * 0x80 (bit 7) 684 * @force_hubp_on: Force Hubp on 685 */ 686 uint32_t force_hubp_on : 1; 687 688 uint32_t reserved : 24; 689 } bitfields; 690 691 uint32_t u32All; 692 }; 693 694 union pr_hw_flags { 695 struct { 696 /** 697 * @allow_alpm_fw_standby_mode: To indicate whether the 698 * ALPM FW standby mode is allowed 699 */ 700 uint32_t allow_alpm_fw_standby_mode : 1; 701 702 /* 703 * @dsc_enable_status: DSC enable status in driver 704 */ 705 uint32_t dsc_enable_status : 1; 706 707 /** 708 * @fec_enable_status: receive fec enable/disable status from driver 709 */ 710 uint32_t fec_enable_status : 1; 711 /* 712 * @smu_optimizations_en: SMU power optimization. 713 * Only when active display is Replay capable and display enters Replay. 714 * Trigger interrupt to SMU to powerup/down. 715 */ 716 uint32_t smu_optimizations_en : 1; 717 /** 718 * @link_power_state: Indicates current link power state 719 */ 720 uint32_t link_power_state : 1; 721 /** 722 * Use TPS3 signal when restore main link. 723 */ 724 uint32_t force_wakeup_by_tps3 : 1; 725 /** 726 * @is_alpm_initialized: Indicates whether ALPM is initialized 727 */ 728 uint32_t is_alpm_initialized : 1; 729 /** 730 * @alpm_mode: Indicates ALPM mode selected 731 */ 732 uint32_t alpm_mode : 2; 733 uint32_t reserved : 23; 734 } bitfields; 735 736 uint32_t u32All; 737 }; 738 739 union fw_assisted_mclk_switch_version { 740 struct { 741 uint8_t minor : 5; 742 uint8_t major : 3; 743 }; 744 uint8_t ver; 745 }; 746 747 /** 748 * DMUB feature capabilities. 749 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 750 */ 751 struct dmub_feature_caps { 752 /** 753 * Max PSR version supported by FW. 754 */ 755 uint8_t psr; 756 uint8_t fw_assisted_mclk_switch_ver; 757 uint8_t reserved[4]; 758 uint8_t subvp_psr_support; 759 uint8_t gecc_enable; 760 uint8_t replay_supported; 761 uint8_t replay_reserved[3]; 762 uint8_t abm_aux_backlight_support; 763 uint8_t lsdma_support_in_dmu; 764 }; 765 766 struct dmub_visual_confirm_color { 767 /** 768 * Maximum 10 bits color value 769 */ 770 uint16_t color_r_cr; 771 uint16_t color_g_y; 772 uint16_t color_b_cb; 773 uint16_t panel_inst; 774 }; 775 776 /** 777 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. 778 */ 779 struct dmub_cursor_offload_pipe_data_dcn30_v1 { 780 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 781 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 782 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 783 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 784 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 785 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 786 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 787 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 788 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 789 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 790 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 791 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 792 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 793 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 794 uint32_t reserved0[4]; 795 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 796 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 797 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 798 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 799 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 800 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 801 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; 802 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; 803 uint32_t reserved1[5]; 804 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 805 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 806 uint32_t reserved2[3]; 807 }; 808 809 /** 810 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. 811 */ 812 struct dmub_cursor_offload_pipe_data_dcn401_v1 { 813 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 814 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 815 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 816 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 817 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 818 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 819 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 820 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 821 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 822 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 823 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 824 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 825 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 826 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 827 uint32_t reserved0[4]; 828 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 829 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 830 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 831 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 832 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 833 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 834 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 835 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 836 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 837 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 838 uint32_t reserved1[4]; 839 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 840 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 841 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; 842 uint32_t reserved2[3]; 843 }; 844 845 /** 846 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. 847 */ 848 struct dmub_cursor_offload_pipe_data_v1 { 849 union { 850 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ 851 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ 852 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ 853 }; 854 }; 855 856 /** 857 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. 858 */ 859 struct dmub_cursor_offload_payload_data_v1 { 860 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ 861 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ 862 uint32_t pipe_mask; /**< Mask of pipes to update. */ 863 uint32_t reserved; /**< Reserved for future use. */ 864 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ 865 }; 866 867 /** 868 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. 869 */ 870 struct dmub_cursor_offload_stream_v1 { 871 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ 872 uint32_t write_idx; /**< The index of the last written payload. */ 873 }; 874 875 /** 876 * struct dmub_cursor_offload_v1 - Cursor offload feature state. 877 */ 878 struct dmub_cursor_offload_v1 { 879 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ 880 }; 881 882 //============================================================================== 883 //</DMUB_TYPES>================================================================= 884 //============================================================================== 885 //< DMUB_META>================================================================== 886 //============================================================================== 887 #pragma pack(push, 1) 888 889 /* Magic value for identifying dmub_fw_meta_info */ 890 #define DMUB_FW_META_MAGIC 0x444D5542 891 892 /* Offset from the end of the file to the dmub_fw_meta_info */ 893 #define DMUB_FW_META_OFFSET 0x24 894 895 /** 896 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 897 */ 898 union dmub_fw_meta_feature_bits { 899 struct { 900 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 901 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ 902 uint32_t reserved : 30; 903 } bits; /**< status bits */ 904 uint32_t all; /**< 32-bit access to status bits */ 905 }; 906 907 /** 908 * struct dmub_fw_meta_info - metadata associated with fw binary 909 * 910 * NOTE: This should be considered a stable API. Fields should 911 * not be repurposed or reordered. New fields should be 912 * added instead to extend the structure. 913 * 914 * @magic_value: magic value identifying DMUB firmware meta info 915 * @fw_region_size: size of the firmware state region 916 * @trace_buffer_size: size of the tracebuffer region 917 * @fw_version: the firmware version information 918 * @dal_fw: 1 if the firmware is DAL 919 * @shared_state_size: size of the shared state region in bytes 920 * @shared_state_features: number of shared state features 921 */ 922 struct dmub_fw_meta_info { 923 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 924 uint32_t fw_region_size; /**< size of the firmware state region */ 925 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 926 uint32_t fw_version; /**< the firmware version information */ 927 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 928 uint8_t reserved[3]; /**< padding bits */ 929 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 930 uint16_t shared_state_features; /**< number of shared state features */ 931 uint16_t reserved2; /**< padding bytes */ 932 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 933 }; 934 935 /** 936 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 937 */ 938 union dmub_fw_meta { 939 struct dmub_fw_meta_info info; /**< metadata info */ 940 uint8_t reserved[64]; /**< padding bits */ 941 }; 942 943 #pragma pack(pop) 944 945 //============================================================================== 946 //< DMUB Trace Buffer>================================================================ 947 //============================================================================== 948 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 949 /** 950 * dmub_trace_code_t - firmware trace code, 32-bits 951 */ 952 typedef uint32_t dmub_trace_code_t; 953 954 /** 955 * struct dmcub_trace_buf_entry - Firmware trace entry 956 */ 957 struct dmcub_trace_buf_entry { 958 dmub_trace_code_t trace_code; /**< trace code for the event */ 959 uint32_t tick_count; /**< the tick count at time of trace */ 960 uint32_t param0; /**< trace defined parameter 0 */ 961 uint32_t param1; /**< trace defined parameter 1 */ 962 }; 963 #endif 964 965 //============================================================================== 966 //< DMUB_STATUS>================================================================ 967 //============================================================================== 968 969 /** 970 * DMCUB scratch registers can be used to determine firmware status. 971 * Current scratch register usage is as follows: 972 * 973 * SCRATCH0: FW Boot Status register 974 * SCRATCH5: LVTMA Status Register 975 * SCRATCH15: FW Boot Options register 976 */ 977 978 /** 979 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 980 */ 981 union dmub_fw_boot_status { 982 struct { 983 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 984 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 985 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 986 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 987 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 988 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 989 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 990 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 991 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 992 } bits; /**< status bits */ 993 uint32_t all; /**< 32-bit access to status bits */ 994 }; 995 996 /** 997 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 998 */ 999 enum dmub_fw_boot_status_bit { 1000 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 1001 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 1002 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 1003 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 1004 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 1005 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 1006 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 1007 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 1008 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 1009 }; 1010 1011 /* Register bit definition for SCRATCH5 */ 1012 union dmub_lvtma_status { 1013 struct { 1014 uint32_t psp_ok : 1; 1015 uint32_t edp_on : 1; 1016 uint32_t reserved : 30; 1017 } bits; 1018 uint32_t all; 1019 }; 1020 1021 enum dmub_lvtma_status_bit { 1022 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 1023 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 1024 }; 1025 1026 enum dmub_ips_disable_type { 1027 DMUB_IPS_ENABLE = 0, 1028 DMUB_IPS_DISABLE_ALL = 1, 1029 DMUB_IPS_DISABLE_IPS1 = 2, 1030 DMUB_IPS_DISABLE_IPS2 = 3, 1031 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 1032 DMUB_IPS_DISABLE_DYNAMIC = 5, 1033 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 1034 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 1035 }; 1036 1037 enum dmub_ips_rcg_disable_type { 1038 DMUB_IPS_RCG_ENABLE = 0, 1039 DMUB_IPS0_RCG_DISABLE = 1, 1040 DMUB_IPS1_RCG_DISABLE = 2, 1041 DMUB_IPS_RCG_DISABLE = 3 1042 }; 1043 1044 enum dmub_ips_in_vpb_disable_type { 1045 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 1046 DMUB_IPS_VPB_DISABLE_ALL = 1, 1047 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 1048 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 1049 }; 1050 1051 #define DMUB_IPS1_ALLOW_MASK 0x00000001 1052 #define DMUB_IPS2_ALLOW_MASK 0x00000002 1053 #define DMUB_IPS1_COMMIT_MASK 0x00000004 1054 #define DMUB_IPS2_COMMIT_MASK 0x00000008 1055 1056 enum dmub_ips_comand_type { 1057 /** 1058 * Start/stop IPS residency measurements for a given IPS mode 1059 */ 1060 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 1061 /** 1062 * Query IPS residency information for a given IPS mode 1063 */ 1064 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 1065 }; 1066 1067 /** 1068 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. 1069 */ 1070 enum dmub_cursor_offload_comand_type { 1071 /** 1072 * Initializes the cursor offload feature. 1073 */ 1074 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, 1075 /** 1076 * Enables cursor offloading for a stream and updates the timing parameters. 1077 */ 1078 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, 1079 /** 1080 * Disables cursor offloading for a given stream. 1081 */ 1082 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, 1083 /** 1084 * Programs the latest data for a given stream. 1085 */ 1086 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, 1087 }; 1088 1089 /** 1090 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 1091 */ 1092 union dmub_fw_boot_options { 1093 struct { 1094 uint32_t pemu_env : 1; /**< 1 if PEMU */ 1095 uint32_t fpga_env : 1; /**< 1 if FPGA */ 1096 uint32_t optimized_init : 1; /**< 1 if optimized init */ 1097 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 1098 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 1099 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 1100 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 1101 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 1102 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 1103 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 1104 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 1105 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 1106 uint32_t power_optimization: 1; 1107 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 1108 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 1109 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 1110 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 1111 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 1112 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 1113 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 1114 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 1115 uint32_t ips_disable: 3; /* options to disable ips support*/ 1116 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 1117 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 1118 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 1119 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 1120 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ 1121 uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/ 1122 uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/ 1123 uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/ 1124 uint32_t reserved : 1; /**< reserved */ 1125 } bits; /**< boot bits */ 1126 uint32_t all; /**< 32-bit access to bits */ 1127 }; 1128 1129 enum dmub_fw_boot_options_bit { 1130 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 1131 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 1132 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 1133 }; 1134 1135 //============================================================================== 1136 //< DMUB_SHARED_STATE>========================================================== 1137 //============================================================================== 1138 1139 /** 1140 * Shared firmware state between driver and firmware for lockless communication 1141 * in situations where the inbox/outbox may be unavailable. 1142 * 1143 * Each structure *must* be at most 256-bytes in size. The layout allocation is 1144 * described below: 1145 * 1146 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 1147 */ 1148 1149 /** 1150 * enum dmub_shared_state_feature_id - List of shared state features. 1151 */ 1152 enum dmub_shared_state_feature_id { 1153 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 1154 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 1155 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 1156 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 1157 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, 1158 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 1159 }; 1160 1161 /** 1162 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 1163 */ 1164 union dmub_shared_state_ips_fw_signals { 1165 struct { 1166 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 1167 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 1168 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 1169 uint32_t detection_required : 1; /**< 1 if detection is required */ 1170 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 1171 uint32_t reserved_bits : 27; /**< Reversed */ 1172 } bits; 1173 uint32_t all; 1174 }; 1175 1176 /** 1177 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 1178 */ 1179 union dmub_shared_state_ips_driver_signals { 1180 struct { 1181 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 1182 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 1183 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 1184 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 1185 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 1186 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 1187 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 1188 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 1189 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 1190 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 1191 uint32_t reserved_bits : 22; /**< Reversed bits */ 1192 } bits; 1193 uint32_t all; 1194 }; 1195 1196 /** 1197 * IPS FW Version 1198 */ 1199 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 1200 1201 struct dmub_shared_state_debug_setup { 1202 union { 1203 struct { 1204 uint32_t exclude_points[62]; 1205 } profile_mode; 1206 }; 1207 }; 1208 1209 /** 1210 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 1211 */ 1212 struct dmub_shared_state_ips_fw { 1213 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 1214 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 1215 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 1216 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 1217 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 1218 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 1219 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 1220 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 1221 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 1222 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 1223 }; /* 248-bytes, fixed */ 1224 1225 /** 1226 * IPS Driver Version 1227 */ 1228 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 1229 1230 /** 1231 * struct dmub_shared_state_ips_driver - Driver state for IPS. 1232 */ 1233 struct dmub_shared_state_ips_driver { 1234 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 1235 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 1236 }; /* 248-bytes, fixed */ 1237 1238 /** 1239 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1240 */ 1241 struct dmub_shared_state_cursor_offload_stream_v1 { 1242 uint32_t last_write_idx; /**< Last write index */ 1243 uint8_t reserved[28]; /**< Reserved bytes. */ 1244 }; /* 32-bytes, fixed */ 1245 1246 /** 1247 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1248 */ 1249 struct dmub_shared_state_cursor_offload_v1 { 1250 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ 1251 uint8_t reserved[56]; /**< reserved for future use */ 1252 }; /* 248-bytes, fixed */ 1253 1254 /** 1255 * enum dmub_shared_state_feature_common - Generic payload. 1256 */ 1257 struct dmub_shared_state_feature_common { 1258 uint32_t padding[62]; 1259 }; /* 248-bytes, fixed */ 1260 1261 /** 1262 * enum dmub_shared_state_feature_header - Feature description. 1263 */ 1264 struct dmub_shared_state_feature_header { 1265 uint16_t id; /**< Feature ID */ 1266 uint16_t version; /**< Feature version */ 1267 uint32_t reserved; /**< Reserved bytes. */ 1268 }; /* 8 bytes, fixed */ 1269 1270 /** 1271 * struct dmub_shared_state_feature_block - Feature block. 1272 */ 1273 struct dmub_shared_state_feature_block { 1274 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 1275 union dmub_shared_feature_state_union { 1276 struct dmub_shared_state_feature_common common; /**< Generic data */ 1277 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 1278 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 1279 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 1280 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ 1281 } data; /**< Shared state data. */ 1282 }; /* 256-bytes, fixed */ 1283 1284 /** 1285 * Shared state size in bytes. 1286 */ 1287 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 1288 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 1289 1290 //============================================================================== 1291 //</DMUB_STATUS>================================================================ 1292 //============================================================================== 1293 //< DMUB_VBIOS>================================================================= 1294 //============================================================================== 1295 1296 /* 1297 * enum dmub_cmd_vbios_type - VBIOS commands. 1298 * 1299 * Command IDs should be treated as stable ABI. 1300 * Do not reuse or modify IDs. 1301 */ 1302 enum dmub_cmd_vbios_type { 1303 /** 1304 * Configures the DIG encoder. 1305 */ 1306 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1307 /** 1308 * Controls the PHY. 1309 */ 1310 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1311 /** 1312 * Sets the pixel clock/symbol clock. 1313 */ 1314 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1315 /** 1316 * Enables or disables power gating. 1317 */ 1318 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1319 /** 1320 * Controls embedded panels. 1321 */ 1322 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1323 /** 1324 * Query DP alt status on a transmitter. 1325 */ 1326 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1327 /** 1328 * Control PHY FSM 1329 */ 1330 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1331 /** 1332 * Controls domain power gating 1333 */ 1334 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1335 }; 1336 1337 //============================================================================== 1338 //</DMUB_VBIOS>================================================================= 1339 //============================================================================== 1340 //< DMUB_GPINT>================================================================= 1341 //============================================================================== 1342 1343 /** 1344 * The shifts and masks below may alternatively be used to format and read 1345 * the command register bits. 1346 */ 1347 1348 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1349 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1350 1351 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1352 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1353 1354 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1355 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1356 1357 /** 1358 * Command responses. 1359 */ 1360 1361 /** 1362 * Return response for DMUB_GPINT__STOP_FW command. 1363 */ 1364 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1365 1366 /** 1367 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1368 */ 1369 union dmub_gpint_data_register { 1370 struct { 1371 uint32_t param : 16; /**< 16-bit parameter */ 1372 uint32_t command_code : 12; /**< GPINT command */ 1373 uint32_t status : 4; /**< Command status bit */ 1374 } bits; /**< GPINT bit access */ 1375 uint32_t all; /**< GPINT 32-bit access */ 1376 }; 1377 1378 /* 1379 * enum dmub_gpint_command - GPINT command to DMCUB FW 1380 * 1381 * Command IDs should be treated as stable ABI. 1382 * Do not reuse or modify IDs. 1383 */ 1384 enum dmub_gpint_command { 1385 /** 1386 * Invalid command, ignored. 1387 */ 1388 DMUB_GPINT__INVALID_COMMAND = 0, 1389 /** 1390 * DESC: Queries the firmware version. 1391 * RETURN: Firmware version. 1392 */ 1393 DMUB_GPINT__GET_FW_VERSION = 1, 1394 /** 1395 * DESC: Halts the firmware. 1396 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1397 */ 1398 DMUB_GPINT__STOP_FW = 2, 1399 /** 1400 * DESC: Get PSR state from FW. 1401 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1402 */ 1403 DMUB_GPINT__GET_PSR_STATE = 7, 1404 /** 1405 * DESC: Notifies DMCUB of the currently active streams. 1406 * ARGS: Stream mask, 1 bit per active stream index. 1407 */ 1408 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1409 /** 1410 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1411 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1412 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1413 * RETURN: PSR residency in milli-percent. 1414 */ 1415 DMUB_GPINT__PSR_RESIDENCY = 9, 1416 1417 /** 1418 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1419 */ 1420 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1421 1422 /** 1423 * DESC: Get REPLAY state from FW. 1424 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1425 */ 1426 DMUB_GPINT__GET_REPLAY_STATE = 13, 1427 1428 /** 1429 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1430 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1431 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1432 * RETURN: REPLAY residency in milli-percent. 1433 */ 1434 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1435 1436 /** 1437 * DESC: Copy bounding box to the host. 1438 * ARGS: Version of bounding box to copy 1439 * RETURN: Result of copying bounding box 1440 */ 1441 DMUB_GPINT__BB_COPY = 96, 1442 1443 /** 1444 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1445 * ARGS: The word3 for the 64 bit address 1446 */ 1447 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1448 1449 /** 1450 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1451 * ARGS: The word2 for the 64 bit address 1452 */ 1453 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1454 1455 /** 1456 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1457 * ARGS: The word1 for the 64 bit address 1458 */ 1459 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1460 1461 /** 1462 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1463 * ARGS: The word0 for the 64 bit address 1464 */ 1465 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1466 1467 /** 1468 * DESC: Updates the trace buffer lower 32-bit mask. 1469 * ARGS: The new mask 1470 * RETURN: Lower 32-bit mask. 1471 */ 1472 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1473 1474 /** 1475 * DESC: Updates the trace buffer mask bit0~bit15. 1476 * ARGS: The new mask 1477 * RETURN: Lower 32-bit mask. 1478 */ 1479 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1480 1481 /** 1482 * DESC: Updates the trace buffer mask bit16~bit31. 1483 * ARGS: The new mask 1484 * RETURN: Lower 32-bit mask. 1485 */ 1486 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1487 1488 /** 1489 * DESC: Updates the trace buffer mask bit32~bit47. 1490 * ARGS: The new mask 1491 * RETURN: Lower 32-bit mask. 1492 */ 1493 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1494 1495 /** 1496 * DESC: Updates the trace buffer mask bit48~bit63. 1497 * ARGS: The new mask 1498 * RETURN: Lower 32-bit mask. 1499 */ 1500 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1501 1502 /** 1503 * DESC: Read the trace buffer mask bi0~bit15. 1504 */ 1505 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1506 1507 /** 1508 * DESC: Read the trace buffer mask bit16~bit31. 1509 */ 1510 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1511 1512 /** 1513 * DESC: Read the trace buffer mask bi32~bit47. 1514 */ 1515 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1516 1517 /** 1518 * DESC: Updates the trace buffer mask bit32~bit63. 1519 */ 1520 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1521 1522 /** 1523 * DESC: Set IPS residency measurement 1524 * ARGS: 0 - Disable ips measurement 1525 * 1 - Enable ips measurement 1526 */ 1527 DMUB_GPINT__IPS_RESIDENCY = 121, 1528 1529 /** 1530 * DESC: Enable measurements for various task duration 1531 * ARGS: 0 - Disable measurement 1532 * 1 - Enable measurement 1533 */ 1534 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1535 1536 /** 1537 * DESC: Gets IPS residency in microseconds 1538 * ARGS: 0 - Return IPS1 residency 1539 * 1 - Return IPS2 residency 1540 * 2 - Return IPS1_RCG residency 1541 * 3 - Return IPS1_ONO2_ON residency 1542 * RETURN: Total residency in microseconds - lower 32 bits 1543 */ 1544 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1545 1546 /** 1547 * DESC: Gets IPS1 histogram counts 1548 * ARGS: Bucket index 1549 * RETURN: Total count for the bucket 1550 */ 1551 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1552 1553 /** 1554 * DESC: Gets IPS2 histogram counts 1555 * ARGS: Bucket index 1556 * RETURN: Total count for the bucket 1557 */ 1558 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1559 1560 /** 1561 * DESC: Gets IPS residency 1562 * ARGS: 0 - Return IPS1 residency 1563 * 1 - Return IPS2 residency 1564 * 2 - Return IPS1_RCG residency 1565 * 3 - Return IPS1_ONO2_ON residency 1566 * RETURN: Total residency in milli-percent. 1567 */ 1568 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1569 1570 /** 1571 * DESC: Gets IPS1_RCG histogram counts 1572 * ARGS: Bucket index 1573 * RETURN: Total count for the bucket 1574 */ 1575 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1576 1577 /** 1578 * DESC: Gets IPS1_ONO2_ON histogram counts 1579 * ARGS: Bucket index 1580 * RETURN: Total count for the bucket 1581 */ 1582 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1583 1584 /** 1585 * DESC: Gets IPS entry counter during residency measurement 1586 * ARGS: 0 - Return IPS1 entry counts 1587 * 1 - Return IPS2 entry counts 1588 * 2 - Return IPS1_RCG entry counts 1589 * 3 - Return IPS2_ONO2_ON entry counts 1590 * RETURN: Entry counter for selected IPS mode 1591 */ 1592 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1593 1594 /** 1595 * DESC: Gets IPS inactive residency in microseconds 1596 * ARGS: 0 - Return IPS1_MAX residency 1597 * 1 - Return IPS2 residency 1598 * 2 - Return IPS1_RCG residency 1599 * 3 - Return IPS1_ONO2_ON residency 1600 * RETURN: Total inactive residency in microseconds - lower 32 bits 1601 */ 1602 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1603 1604 /** 1605 * DESC: Gets IPS inactive residency in microseconds 1606 * ARGS: 0 - Return IPS1_MAX residency 1607 * 1 - Return IPS2 residency 1608 * 2 - Return IPS1_RCG residency 1609 * 3 - Return IPS1_ONO2_ON residency 1610 * RETURN: Total inactive residency in microseconds - upper 32 bits 1611 */ 1612 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1613 1614 /** 1615 * DESC: Gets IPS residency in microseconds 1616 * ARGS: 0 - Return IPS1 residency 1617 * 1 - Return IPS2 residency 1618 * 2 - Return IPS1_RCG residency 1619 * 3 - Return IPS1_ONO2_ON residency 1620 * RETURN: Total residency in microseconds - upper 32 bits 1621 */ 1622 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1623 /** 1624 * DESC: Setup debug configs. 1625 */ 1626 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1627 /** 1628 * DESC: Initiates IPS wake sequence. 1629 */ 1630 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1631 }; 1632 1633 /** 1634 * INBOX0 generic command definition 1635 */ 1636 union dmub_inbox0_cmd_common { 1637 struct { 1638 uint32_t command_code: 8; /**< INBOX0 command code */ 1639 uint32_t param: 24; /**< 24-bit parameter */ 1640 } bits; 1641 uint32_t all; 1642 }; 1643 1644 /** 1645 * INBOX0 hw_lock command definition 1646 */ 1647 union dmub_inbox0_cmd_lock_hw { 1648 struct { 1649 uint32_t command_code: 8; 1650 1651 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1652 uint32_t hw_lock_client: 2; 1653 1654 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1655 uint32_t otg_inst: 3; 1656 uint32_t opp_inst: 3; 1657 uint32_t dig_inst: 3; 1658 1659 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1660 uint32_t lock_pipe: 1; 1661 uint32_t lock_cursor: 1; 1662 uint32_t lock_dig: 1; 1663 uint32_t triple_buffer_lock: 1; 1664 1665 uint32_t lock: 1; /**< Lock */ 1666 uint32_t should_release: 1; /**< Release */ 1667 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1668 } bits; 1669 uint32_t all; 1670 }; 1671 1672 union dmub_inbox0_data_register { 1673 union dmub_inbox0_cmd_common inbox0_cmd_common; 1674 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1675 }; 1676 1677 enum dmub_inbox0_command { 1678 /** 1679 * DESC: Invalid command, ignored. 1680 */ 1681 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1682 /** 1683 * DESC: Notification to acquire/release HW lock 1684 * ARGS: 1685 */ 1686 DMUB_INBOX0_CMD__HW_LOCK = 1, 1687 }; 1688 //============================================================================== 1689 //</DMUB_GPINT>================================================================= 1690 //============================================================================== 1691 //< DMUB_CMD>=================================================================== 1692 //============================================================================== 1693 1694 /** 1695 * Size in bytes of each DMUB command. 1696 */ 1697 #define DMUB_RB_CMD_SIZE 64 1698 1699 /** 1700 * Maximum number of items in the DMUB ringbuffer. 1701 */ 1702 #define DMUB_RB_MAX_ENTRY 128 1703 1704 /** 1705 * Ringbuffer size in bytes. 1706 */ 1707 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1708 1709 /** 1710 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1711 */ 1712 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1713 1714 /** 1715 * Ringbuffer size in bytes. 1716 */ 1717 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1718 1719 /** 1720 * REG_SET mask for reg offload. 1721 */ 1722 #define REG_SET_MASK 0xFFFF 1723 1724 /* 1725 * enum dmub_cmd_type - DMUB inbox command. 1726 * 1727 * Command IDs should be treated as stable ABI. 1728 * Do not reuse or modify IDs. 1729 */ 1730 enum dmub_cmd_type { 1731 /** 1732 * Invalid command. 1733 */ 1734 DMUB_CMD__NULL = 0, 1735 /** 1736 * Read modify write register sequence offload. 1737 */ 1738 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1739 /** 1740 * Field update register sequence offload. 1741 */ 1742 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1743 /** 1744 * Burst write sequence offload. 1745 */ 1746 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1747 /** 1748 * Reg wait sequence offload. 1749 */ 1750 DMUB_CMD__REG_REG_WAIT = 4, 1751 /** 1752 * Workaround to avoid HUBP underflow during NV12 playback. 1753 */ 1754 DMUB_CMD__PLAT_54186_WA = 5, 1755 /** 1756 * Command type used to query FW feature caps. 1757 */ 1758 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1759 /** 1760 * Command type used to get visual confirm color. 1761 */ 1762 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1763 /** 1764 * Command type used for all PSR commands. 1765 */ 1766 DMUB_CMD__PSR = 64, 1767 /** 1768 * Command type used for all MALL commands. 1769 */ 1770 DMUB_CMD__MALL = 65, 1771 /** 1772 * Command type used for all ABM commands. 1773 */ 1774 DMUB_CMD__ABM = 66, 1775 /** 1776 * Command type used to update dirty rects in FW. 1777 */ 1778 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1779 /** 1780 * Command type used to update cursor info in FW. 1781 */ 1782 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1783 /** 1784 * Command type used for HW locking in FW. 1785 */ 1786 DMUB_CMD__HW_LOCK = 69, 1787 /** 1788 * Command type used to access DP AUX. 1789 */ 1790 DMUB_CMD__DP_AUX_ACCESS = 70, 1791 /** 1792 * Command type used for OUTBOX1 notification enable 1793 */ 1794 DMUB_CMD__OUTBOX1_ENABLE = 71, 1795 1796 /** 1797 * Command type used for all idle optimization commands. 1798 */ 1799 DMUB_CMD__IDLE_OPT = 72, 1800 /** 1801 * Command type used for all clock manager commands. 1802 */ 1803 DMUB_CMD__CLK_MGR = 73, 1804 /** 1805 * Command type used for all panel control commands. 1806 */ 1807 DMUB_CMD__PANEL_CNTL = 74, 1808 1809 /** 1810 * Command type used for all CAB commands. 1811 */ 1812 DMUB_CMD__CAB_FOR_SS = 75, 1813 1814 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1815 1816 /** 1817 * Command type used for interfacing with DPIA. 1818 */ 1819 DMUB_CMD__DPIA = 77, 1820 /** 1821 * Command type used for EDID CEA parsing 1822 */ 1823 DMUB_CMD__EDID_CEA = 79, 1824 /** 1825 * Command type used for getting usbc cable ID 1826 */ 1827 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1828 /** 1829 * Command type used to query HPD state. 1830 */ 1831 DMUB_CMD__QUERY_HPD_STATE = 82, 1832 /** 1833 * Command type used for all VBIOS interface commands. 1834 */ 1835 /** 1836 * Command type used for all REPLAY commands. 1837 */ 1838 DMUB_CMD__REPLAY = 83, 1839 1840 /** 1841 * Command type used for all SECURE_DISPLAY commands. 1842 */ 1843 DMUB_CMD__SECURE_DISPLAY = 85, 1844 1845 /** 1846 * Command type used to set DPIA HPD interrupt state 1847 */ 1848 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1849 1850 /** 1851 * Command type used for all PSP commands. 1852 */ 1853 DMUB_CMD__PSP = 88, 1854 1855 /** 1856 * Command type used for all Fused IO commands. 1857 */ 1858 DMUB_CMD__FUSED_IO = 89, 1859 1860 /** 1861 * Command type used for all LSDMA commands. 1862 */ 1863 DMUB_CMD__LSDMA = 90, 1864 1865 /** 1866 * Command type use for all IPS commands. 1867 */ 1868 DMUB_CMD__IPS = 91, 1869 1870 /** 1871 * Command type use for Cursor offload. 1872 */ 1873 DMUB_CMD__CURSOR_OFFLOAD = 92, 1874 1875 /** 1876 * Command type used for all SMART_POWER_OLED commands. 1877 */ 1878 DMUB_CMD__SMART_POWER_OLED = 93, 1879 1880 /** 1881 * Command type use for all Panel Replay commands. 1882 */ 1883 DMUB_CMD__PR = 94, 1884 1885 1886 /** 1887 * Command type use for VBIOS shared commands. 1888 */ 1889 DMUB_CMD__VBIOS = 128, 1890 }; 1891 1892 /** 1893 * enum dmub_out_cmd_type - DMUB outbox commands. 1894 */ 1895 enum dmub_out_cmd_type { 1896 /** 1897 * Invalid outbox command, ignored. 1898 */ 1899 DMUB_OUT_CMD__NULL = 0, 1900 /** 1901 * Command type used for DP AUX Reply data notification 1902 */ 1903 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1904 /** 1905 * Command type used for DP HPD event notification 1906 */ 1907 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1908 /** 1909 * Command type used for SET_CONFIG Reply notification 1910 */ 1911 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1912 /** 1913 * Command type used for USB4 DPIA notification 1914 */ 1915 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1916 /** 1917 * Command type used for HPD redetect notification 1918 */ 1919 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1920 /** 1921 * Command type used for Fused IO notification 1922 */ 1923 DMUB_OUT_CMD__FUSED_IO = 7, 1924 }; 1925 1926 /* DMUB_CMD__DPIA command sub-types. */ 1927 enum dmub_cmd_dpia_type { 1928 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1929 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1930 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1931 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1932 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1933 }; 1934 1935 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1936 enum dmub_cmd_dpia_notification_type { 1937 DPIA_NOTIFY__BW_ALLOCATION = 0, 1938 }; 1939 1940 #pragma pack(push, 1) 1941 1942 /** 1943 * struct dmub_cmd_header - Common command header fields. 1944 */ 1945 struct dmub_cmd_header { 1946 unsigned int type : 8; /**< command type */ 1947 unsigned int sub_type : 8; /**< command sub type */ 1948 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1949 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1950 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1951 unsigned int reserved0 : 5; /**< reserved bits */ 1952 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1953 unsigned int reserved1 : 2; /**< reserved bits */ 1954 }; 1955 1956 /* 1957 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1958 * 1959 * 60 payload bytes can hold up to 5 sets of read modify writes, 1960 * each take 3 dwords. 1961 * 1962 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1963 * 1964 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1965 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1966 */ 1967 struct dmub_cmd_read_modify_write_sequence { 1968 uint32_t addr; /**< register address */ 1969 uint32_t modify_mask; /**< modify mask */ 1970 uint32_t modify_value; /**< modify value */ 1971 }; 1972 1973 /** 1974 * Maximum number of ops in read modify write sequence. 1975 */ 1976 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1977 1978 /** 1979 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1980 */ 1981 struct dmub_rb_cmd_read_modify_write { 1982 struct dmub_cmd_header header; /**< command header */ 1983 /** 1984 * Read modify write sequence. 1985 */ 1986 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1987 }; 1988 1989 /* 1990 * Update a register with specified masks and values sequeunce 1991 * 1992 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1993 * 1994 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1995 * 1996 * 1997 * USE CASE: 1998 * 1. auto-increment register where additional read would update pointer and produce wrong result 1999 * 2. toggle a bit without read in the middle 2000 */ 2001 2002 struct dmub_cmd_reg_field_update_sequence { 2003 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 2004 uint32_t modify_value; /**< value to update with */ 2005 }; 2006 2007 /** 2008 * Maximum number of ops in field update sequence. 2009 */ 2010 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 2011 2012 /** 2013 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 2014 */ 2015 struct dmub_rb_cmd_reg_field_update_sequence { 2016 struct dmub_cmd_header header; /**< command header */ 2017 uint32_t addr; /**< register address */ 2018 /** 2019 * Field update sequence. 2020 */ 2021 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 2022 }; 2023 2024 2025 /** 2026 * Maximum number of burst write values. 2027 */ 2028 #define DMUB_BURST_WRITE_VALUES__MAX 14 2029 2030 /* 2031 * struct dmub_rb_cmd_burst_write - Burst write 2032 * 2033 * support use case such as writing out LUTs. 2034 * 2035 * 60 payload bytes can hold up to 14 values to write to given address 2036 * 2037 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 2038 */ 2039 struct dmub_rb_cmd_burst_write { 2040 struct dmub_cmd_header header; /**< command header */ 2041 uint32_t addr; /**< register start address */ 2042 /** 2043 * Burst write register values. 2044 */ 2045 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 2046 }; 2047 2048 /** 2049 * struct dmub_rb_cmd_common - Common command header 2050 */ 2051 struct dmub_rb_cmd_common { 2052 struct dmub_cmd_header header; /**< command header */ 2053 /** 2054 * Padding to RB_CMD_SIZE 2055 */ 2056 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 2057 }; 2058 2059 /** 2060 * struct dmub_cmd_reg_wait_data - Register wait data 2061 */ 2062 struct dmub_cmd_reg_wait_data { 2063 uint32_t addr; /**< Register address */ 2064 uint32_t mask; /**< Mask for register bits */ 2065 uint32_t condition_field_value; /**< Value to wait for */ 2066 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 2067 }; 2068 2069 /** 2070 * struct dmub_rb_cmd_reg_wait - Register wait command 2071 */ 2072 struct dmub_rb_cmd_reg_wait { 2073 struct dmub_cmd_header header; /**< Command header */ 2074 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 2075 }; 2076 2077 /** 2078 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 2079 * 2080 * Reprograms surface parameters to avoid underflow. 2081 */ 2082 struct dmub_cmd_PLAT_54186_wa { 2083 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 2084 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 2085 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 2086 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 2087 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 2088 struct { 2089 uint32_t hubp_inst : 4; /**< HUBP instance */ 2090 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 2091 uint32_t immediate :1; /**< Immediate flip */ 2092 uint32_t vmid : 4; /**< VMID */ 2093 uint32_t grph_stereo : 1; /**< 1 if stereo */ 2094 uint32_t reserved : 21; /**< Reserved */ 2095 } flip_params; /**< Pageflip parameters */ 2096 uint32_t reserved[9]; /**< Reserved bits */ 2097 }; 2098 2099 /** 2100 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 2101 */ 2102 struct dmub_rb_cmd_PLAT_54186_wa { 2103 struct dmub_cmd_header header; /**< Command header */ 2104 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 2105 }; 2106 2107 /** 2108 * enum dmub_cmd_mall_type - MALL commands 2109 */ 2110 enum dmub_cmd_mall_type { 2111 /** 2112 * Allows display refresh from MALL. 2113 */ 2114 DMUB_CMD__MALL_ACTION_ALLOW = 0, 2115 /** 2116 * Disallows display refresh from MALL. 2117 */ 2118 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 2119 /** 2120 * Cursor copy for MALL. 2121 */ 2122 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 2123 /** 2124 * Controls DF requests. 2125 */ 2126 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 2127 }; 2128 2129 /** 2130 * struct dmub_rb_cmd_mall - MALL command data. 2131 */ 2132 struct dmub_rb_cmd_mall { 2133 struct dmub_cmd_header header; /**< Common command header */ 2134 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 2135 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 2136 uint32_t tmr_delay; /**< Timer delay */ 2137 uint32_t tmr_scale; /**< Timer scale */ 2138 uint16_t cursor_width; /**< Cursor width in pixels */ 2139 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 2140 uint16_t cursor_height; /**< Cursor height in pixels */ 2141 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 2142 uint8_t debug_bits; /**< Debug bits */ 2143 2144 uint8_t reserved1; /**< Reserved bits */ 2145 uint8_t reserved2; /**< Reserved bits */ 2146 }; 2147 2148 /** 2149 * enum dmub_cmd_cab_type - CAB command data. 2150 */ 2151 enum dmub_cmd_cab_type { 2152 /** 2153 * No idle optimizations (i.e. no CAB) 2154 */ 2155 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 2156 /** 2157 * No DCN requests for memory 2158 */ 2159 DMUB_CMD__CAB_NO_DCN_REQ = 1, 2160 /** 2161 * Fit surfaces in CAB (i.e. CAB enable) 2162 */ 2163 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 2164 /** 2165 * Do not fit surfaces in CAB (i.e. no CAB) 2166 */ 2167 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 2168 }; 2169 2170 /** 2171 * struct dmub_rb_cmd_cab - CAB command data. 2172 */ 2173 struct dmub_rb_cmd_cab_for_ss { 2174 struct dmub_cmd_header header; 2175 uint8_t cab_alloc_ways; /* total number of ways */ 2176 uint8_t debug_bits; /* debug bits */ 2177 }; 2178 2179 /** 2180 * Enum for indicating which MCLK switch mode per pipe 2181 */ 2182 enum mclk_switch_mode { 2183 NONE = 0, 2184 FPO = 1, 2185 SUBVP = 2, 2186 VBLANK = 3, 2187 }; 2188 2189 /* Per pipe struct which stores the MCLK switch mode 2190 * data to be sent to DMUB. 2191 * Named "v2" for now -- once FPO and SUBVP are fully merged 2192 * the type name can be updated 2193 */ 2194 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 2195 union { 2196 struct { 2197 uint32_t pix_clk_100hz; 2198 uint16_t main_vblank_start; 2199 uint16_t main_vblank_end; 2200 uint16_t mall_region_lines; 2201 uint16_t prefetch_lines; 2202 uint16_t prefetch_to_mall_start_lines; 2203 uint16_t processing_delay_lines; 2204 uint16_t htotal; // required to calculate line time for multi-display cases 2205 uint16_t vtotal; 2206 uint8_t main_pipe_index; 2207 uint8_t phantom_pipe_index; 2208 /* Since the microschedule is calculated in terms of OTG lines, 2209 * include any scaling factors to make sure when we get accurate 2210 * conversion when programming MALL_START_LINE (which is in terms 2211 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 2212 * is 1/2 (numerator = 1, denominator = 2). 2213 */ 2214 uint8_t scale_factor_numerator; 2215 uint8_t scale_factor_denominator; 2216 uint8_t is_drr; 2217 uint8_t main_split_pipe_index; 2218 uint8_t phantom_split_pipe_index; 2219 } subvp_data; 2220 2221 struct { 2222 uint32_t pix_clk_100hz; 2223 uint16_t vblank_start; 2224 uint16_t vblank_end; 2225 uint16_t vstartup_start; 2226 uint16_t vtotal; 2227 uint16_t htotal; 2228 uint8_t vblank_pipe_index; 2229 uint8_t padding[1]; 2230 struct { 2231 uint8_t drr_in_use; 2232 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 2233 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 2234 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 2235 uint8_t use_ramping; // Use ramping or not 2236 uint8_t drr_vblank_start_margin; 2237 } drr_info; // DRR considered as part of SubVP + VBLANK case 2238 } vblank_data; 2239 } pipe_config; 2240 2241 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 2242 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 2243 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 2244 */ 2245 uint8_t mode; // enum mclk_switch_mode 2246 }; 2247 2248 /** 2249 * Config data for Sub-VP and FPO 2250 * Named "v2" for now -- once FPO and SUBVP are fully merged 2251 * the type name can be updated 2252 */ 2253 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 2254 uint16_t watermark_a_cache; 2255 uint8_t vertical_int_margin_us; 2256 uint8_t pstate_allow_width_us; 2257 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 2258 }; 2259 2260 /** 2261 * DMUB rb command definition for Sub-VP and FPO 2262 * Named "v2" for now -- once FPO and SUBVP are fully merged 2263 * the type name can be updated 2264 */ 2265 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 2266 struct dmub_cmd_header header; 2267 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 2268 }; 2269 2270 struct dmub_flip_addr_info { 2271 uint32_t surf_addr_lo; 2272 uint32_t surf_addr_c_lo; 2273 uint32_t meta_addr_lo; 2274 uint32_t meta_addr_c_lo; 2275 uint16_t surf_addr_hi; 2276 uint16_t surf_addr_c_hi; 2277 uint16_t meta_addr_hi; 2278 uint16_t meta_addr_c_hi; 2279 }; 2280 2281 struct dmub_fams2_flip_info { 2282 union { 2283 struct { 2284 uint8_t is_immediate: 1; 2285 } bits; 2286 uint8_t all; 2287 } config; 2288 uint8_t otg_inst; 2289 uint8_t pipe_mask; 2290 uint8_t pad; 2291 struct dmub_flip_addr_info addr_info; 2292 }; 2293 2294 struct dmub_rb_cmd_fams2_flip { 2295 struct dmub_cmd_header header; 2296 struct dmub_fams2_flip_info flip_info; 2297 }; 2298 2299 struct dmub_cmd_lsdma_data { 2300 union { 2301 struct lsdma_init_data { 2302 union dmub_addr gpu_addr_base; 2303 uint32_t ring_size; 2304 } init_data; 2305 struct lsdma_tiled_copy_data { 2306 uint32_t src_addr_lo; 2307 uint32_t src_addr_hi; 2308 2309 uint32_t dst_addr_lo; 2310 uint32_t dst_addr_hi; 2311 2312 uint32_t src_x : 16; 2313 uint32_t src_y : 16; 2314 2315 uint32_t dst_x : 16; 2316 uint32_t dst_y : 16; 2317 2318 uint32_t src_width : 16; 2319 uint32_t src_height : 16; 2320 2321 uint32_t dst_width : 16; 2322 uint32_t dst_height : 16; 2323 2324 uint32_t rect_x : 16; 2325 uint32_t rect_y : 16; 2326 2327 uint32_t src_swizzle_mode : 5; 2328 uint32_t src_mip_max : 5; 2329 uint32_t src_mip_id : 5; 2330 uint32_t dst_mip_max : 5; 2331 uint32_t dst_swizzle_mode : 5; 2332 uint32_t dst_mip_id : 5; 2333 uint32_t tmz : 1; 2334 uint32_t dcc : 1; 2335 2336 uint32_t data_format : 6; 2337 uint32_t padding1 : 4; 2338 uint32_t dst_element_size : 3; 2339 uint32_t num_type : 3; 2340 uint32_t src_element_size : 3; 2341 uint32_t write_compress : 2; 2342 uint32_t cache_policy_dst : 2; 2343 uint32_t cache_policy_src : 2; 2344 uint32_t read_compress : 2; 2345 uint32_t src_dim : 2; 2346 uint32_t dst_dim : 2; 2347 uint32_t max_uncom : 1; 2348 2349 uint32_t max_com : 2; 2350 uint32_t padding : 30; 2351 } tiled_copy_data; 2352 struct lsdma_linear_copy_data { 2353 uint32_t src_lo; 2354 uint32_t src_hi; 2355 2356 uint32_t dst_lo; 2357 uint32_t dst_hi; 2358 2359 uint32_t count : 30; 2360 uint32_t cache_policy_dst : 2; 2361 2362 uint32_t tmz : 1; 2363 uint32_t cache_policy_src : 2; 2364 uint32_t padding : 29; 2365 } linear_copy_data; 2366 struct lsdma_linear_sub_window_copy_data { 2367 uint32_t src_lo; 2368 uint32_t src_hi; 2369 2370 uint32_t dst_lo; 2371 uint32_t dst_hi; 2372 2373 uint32_t src_x : 16; 2374 uint32_t src_y : 16; 2375 2376 uint32_t dst_x : 16; 2377 uint32_t dst_y : 16; 2378 2379 uint32_t rect_x : 16; 2380 uint32_t rect_y : 16; 2381 2382 uint32_t src_pitch : 16; 2383 uint32_t dst_pitch : 16; 2384 2385 uint32_t src_slice_pitch; 2386 uint32_t dst_slice_pitch; 2387 2388 uint32_t tmz : 1; 2389 uint32_t element_size : 3; 2390 uint32_t src_cache_policy : 3; 2391 uint32_t dst_cache_policy : 3; 2392 uint32_t reserved0 : 22; 2393 } linear_sub_window_copy_data; 2394 struct lsdma_reg_write_data { 2395 uint32_t reg_addr; 2396 uint32_t reg_data; 2397 } reg_write_data; 2398 struct lsdma_pio_copy_data { 2399 uint32_t src_lo; 2400 uint32_t src_hi; 2401 2402 uint32_t dst_lo; 2403 uint32_t dst_hi; 2404 2405 union { 2406 struct { 2407 uint32_t byte_count : 26; 2408 uint32_t src_loc : 1; 2409 uint32_t dst_loc : 1; 2410 uint32_t src_addr_inc : 1; 2411 uint32_t dst_addr_inc : 1; 2412 uint32_t overlap_disable : 1; 2413 uint32_t constant_fill : 1; 2414 } fields; 2415 uint32_t raw; 2416 } packet; 2417 } pio_copy_data; 2418 struct lsdma_pio_constfill_data { 2419 uint32_t dst_lo; 2420 uint32_t dst_hi; 2421 2422 union { 2423 struct { 2424 uint32_t byte_count : 26; 2425 uint32_t src_loc : 1; 2426 uint32_t dst_loc : 1; 2427 uint32_t src_addr_inc : 1; 2428 uint32_t dst_addr_inc : 1; 2429 uint32_t overlap_disable : 1; 2430 uint32_t constant_fill : 1; 2431 } fields; 2432 uint32_t raw; 2433 } packet; 2434 2435 uint32_t data; 2436 } pio_constfill_data; 2437 2438 uint32_t all[14]; 2439 } u; 2440 }; 2441 2442 struct dmub_rb_cmd_lsdma { 2443 struct dmub_cmd_header header; 2444 struct dmub_cmd_lsdma_data lsdma_data; 2445 }; 2446 2447 struct dmub_optc_state_v2 { 2448 uint32_t v_total_min; 2449 uint32_t v_total_max; 2450 uint32_t v_total_mid; 2451 uint32_t v_total_mid_frame_num; 2452 uint8_t program_manual_trigger; 2453 uint8_t tg_inst; 2454 uint8_t pad[2]; 2455 }; 2456 2457 struct dmub_optc_position { 2458 uint32_t vpos; 2459 uint32_t hpos; 2460 uint32_t frame; 2461 }; 2462 2463 struct dmub_rb_cmd_fams2_drr_update { 2464 struct dmub_cmd_header header; 2465 struct dmub_optc_state_v2 dmub_optc_state_req; 2466 }; 2467 2468 /* HW and FW global configuration data for FAMS2 */ 2469 /* FAMS2 types and structs */ 2470 enum fams2_stream_type { 2471 FAMS2_STREAM_TYPE_NONE = 0, 2472 FAMS2_STREAM_TYPE_VBLANK = 1, 2473 FAMS2_STREAM_TYPE_VACTIVE = 2, 2474 FAMS2_STREAM_TYPE_DRR = 3, 2475 FAMS2_STREAM_TYPE_SUBVP = 4, 2476 }; 2477 2478 struct dmub_rect16 { 2479 /** 2480 * Dirty rect x offset. 2481 */ 2482 uint16_t x; 2483 2484 /** 2485 * Dirty rect y offset. 2486 */ 2487 uint16_t y; 2488 2489 /** 2490 * Dirty rect width. 2491 */ 2492 uint16_t width; 2493 2494 /** 2495 * Dirty rect height. 2496 */ 2497 uint16_t height; 2498 }; 2499 2500 /* static stream state */ 2501 struct dmub_fams2_legacy_stream_static_state { 2502 uint8_t vactive_det_fill_delay_otg_vlines; 2503 uint8_t programming_delay_otg_vlines; 2504 }; //v0 2505 2506 struct dmub_fams2_subvp_stream_static_state { 2507 uint16_t vratio_numerator; 2508 uint16_t vratio_denominator; 2509 uint16_t phantom_vtotal; 2510 uint16_t phantom_vactive; 2511 union { 2512 struct { 2513 uint8_t is_multi_planar : 1; 2514 uint8_t is_yuv420 : 1; 2515 } bits; 2516 uint8_t all; 2517 } config; 2518 uint8_t programming_delay_otg_vlines; 2519 uint8_t prefetch_to_mall_otg_vlines; 2520 uint8_t phantom_otg_inst; 2521 uint8_t phantom_pipe_mask; 2522 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2523 }; //v0 2524 2525 struct dmub_fams2_drr_stream_static_state { 2526 uint16_t nom_stretched_vtotal; 2527 uint8_t programming_delay_otg_vlines; 2528 uint8_t only_stretch_if_required; 2529 uint8_t pad[2]; 2530 }; //v0 2531 2532 struct dmub_fams2_cmd_legacy_stream_static_state { 2533 uint16_t vactive_det_fill_delay_otg_vlines; 2534 uint16_t programming_delay_otg_vlines; 2535 uint32_t disallow_time_us; 2536 }; //v1 2537 2538 struct dmub_fams2_cmd_subvp_stream_static_state { 2539 uint16_t vratio_numerator; 2540 uint16_t vratio_denominator; 2541 uint16_t phantom_vtotal; 2542 uint16_t phantom_vactive; 2543 uint16_t programming_delay_otg_vlines; 2544 uint16_t prefetch_to_mall_otg_vlines; 2545 union { 2546 struct { 2547 uint8_t is_multi_planar : 1; 2548 uint8_t is_yuv420 : 1; 2549 } bits; 2550 uint8_t all; 2551 } config; 2552 uint8_t phantom_otg_inst; 2553 uint8_t phantom_pipe_mask; 2554 uint8_t pad0; 2555 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2556 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2557 }; //v1 2558 2559 struct dmub_fams2_cmd_drr_stream_static_state { 2560 uint16_t nom_stretched_vtotal; 2561 uint16_t programming_delay_otg_vlines; 2562 uint8_t only_stretch_if_required; 2563 uint8_t pad[3]; 2564 }; //v1 2565 2566 union dmub_fams2_stream_static_sub_state { 2567 struct dmub_fams2_legacy_stream_static_state legacy; 2568 struct dmub_fams2_subvp_stream_static_state subvp; 2569 struct dmub_fams2_drr_stream_static_state drr; 2570 }; //v0 2571 2572 union dmub_fams2_cmd_stream_static_sub_state { 2573 COMMON_STREAM_STATIC_SUB_STATE 2574 }; //v1 2575 2576 union dmub_fams2_stream_static_sub_state_v2 { 2577 COMMON_STREAM_STATIC_SUB_STATE 2578 }; //v2 2579 2580 struct dmub_fams2_stream_static_state { 2581 enum fams2_stream_type type; 2582 uint32_t otg_vline_time_ns; 2583 uint32_t otg_vline_time_ticks; 2584 uint16_t htotal; 2585 uint16_t vtotal; // nominal vtotal 2586 uint16_t vblank_start; 2587 uint16_t vblank_end; 2588 uint16_t max_vtotal; 2589 uint16_t allow_start_otg_vline; 2590 uint16_t allow_end_otg_vline; 2591 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2592 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2593 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2594 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2595 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2596 union { 2597 struct { 2598 uint8_t is_drr: 1; // stream is DRR enabled 2599 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2600 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2601 } bits; 2602 uint8_t all; 2603 } config; 2604 uint8_t otg_inst; 2605 uint8_t pipe_mask; // pipe mask for the whole config 2606 uint8_t num_planes; 2607 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2608 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2609 union dmub_fams2_stream_static_sub_state sub_state; 2610 }; //v0 2611 2612 struct dmub_fams2_cmd_stream_static_base_state { 2613 enum fams2_stream_type type; 2614 uint32_t otg_vline_time_ns; 2615 uint32_t otg_vline_time_ticks; 2616 uint16_t htotal; 2617 uint16_t vtotal; // nominal vtotal 2618 uint16_t vblank_start; 2619 uint16_t vblank_end; 2620 uint16_t max_vtotal; 2621 uint16_t allow_start_otg_vline; 2622 uint16_t allow_end_otg_vline; 2623 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2624 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2625 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2626 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2627 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2628 union { 2629 struct { 2630 uint8_t is_drr : 1; // stream is DRR enabled 2631 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2632 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2633 } bits; 2634 uint8_t all; 2635 } config; 2636 uint8_t otg_inst; 2637 uint8_t pipe_mask; // pipe mask for the whole config 2638 uint8_t num_planes; 2639 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2640 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2641 }; //v1 2642 2643 struct dmub_fams2_stream_static_state_v1 { 2644 struct dmub_fams2_cmd_stream_static_base_state base; 2645 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2646 }; //v1 2647 2648 /** 2649 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2650 * p-state request to allow latency 2651 */ 2652 enum dmub_fams2_allow_delay_check_mode { 2653 /* No check for request to allow delay */ 2654 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2655 /* Check for request to allow delay */ 2656 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2657 /* Check for prepare to allow delay */ 2658 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2659 }; 2660 2661 union dmub_fams2_global_feature_config { 2662 struct { 2663 uint32_t enable: 1; 2664 uint32_t enable_ppt_check: 1; 2665 uint32_t enable_stall_recovery: 1; 2666 uint32_t enable_debug: 1; 2667 uint32_t enable_offload_flip: 1; 2668 uint32_t enable_visual_confirm: 1; 2669 uint32_t allow_delay_check_mode: 2; 2670 uint32_t legacy_method_no_fams2 : 1; 2671 uint32_t reserved : 23; 2672 } bits; 2673 uint32_t all; 2674 }; 2675 2676 struct dmub_cmd_fams2_global_config { 2677 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2678 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2679 uint32_t num_streams; 2680 union dmub_fams2_global_feature_config features; 2681 uint32_t recovery_timeout_us; 2682 uint32_t hwfq_flip_programming_delay_us; 2683 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2684 }; 2685 2686 union dmub_cmd_fams2_config { 2687 struct dmub_cmd_fams2_global_config global; 2688 struct dmub_fams2_stream_static_state stream; //v0 2689 union { 2690 struct dmub_fams2_cmd_stream_static_base_state base; 2691 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2692 } stream_v1; //v1 2693 }; 2694 2695 struct dmub_fams2_config_v2 { 2696 struct dmub_cmd_fams2_global_config global; 2697 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2698 }; 2699 2700 /** 2701 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2702 */ 2703 struct dmub_rb_cmd_fams2 { 2704 struct dmub_cmd_header header; 2705 union dmub_cmd_fams2_config config; 2706 }; 2707 2708 /** 2709 * Indirect buffer descriptor 2710 */ 2711 struct dmub_ib_data { 2712 union dmub_addr src; // location of indirect buffer in memory 2713 uint16_t size; // indirect buffer size in bytes 2714 }; 2715 2716 /** 2717 * DMUB rb command definition for commands passed over indirect buffer 2718 */ 2719 struct dmub_rb_cmd_ib { 2720 struct dmub_cmd_header header; 2721 struct dmub_ib_data ib_data; 2722 }; 2723 2724 /** 2725 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2726 */ 2727 enum dmub_cmd_idle_opt_type { 2728 /** 2729 * DCN hardware restore. 2730 */ 2731 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2732 2733 /** 2734 * DCN hardware save. 2735 */ 2736 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2737 2738 /** 2739 * DCN hardware notify idle. 2740 */ 2741 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2742 2743 /** 2744 * DCN hardware notify power state. 2745 */ 2746 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2747 2748 /** 2749 * DCN notify to release HW. 2750 */ 2751 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2752 }; 2753 2754 /** 2755 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2756 */ 2757 struct dmub_rb_cmd_idle_opt_dcn_restore { 2758 struct dmub_cmd_header header; /**< header */ 2759 }; 2760 2761 /** 2762 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2763 */ 2764 struct dmub_dcn_notify_idle_cntl_data { 2765 uint8_t driver_idle; 2766 uint8_t skip_otg_disable; 2767 uint8_t reserved[58]; 2768 }; 2769 2770 /** 2771 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2772 */ 2773 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2774 struct dmub_cmd_header header; /**< header */ 2775 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2776 }; 2777 2778 /** 2779 * enum dmub_idle_opt_dc_power_state - DC power states. 2780 */ 2781 enum dmub_idle_opt_dc_power_state { 2782 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2783 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2784 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2785 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2786 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2787 }; 2788 2789 /** 2790 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2791 */ 2792 struct dmub_idle_opt_set_dc_power_state_data { 2793 uint8_t power_state; /**< power state */ 2794 uint8_t pad[3]; /**< padding */ 2795 }; 2796 2797 /** 2798 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2799 */ 2800 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2801 struct dmub_cmd_header header; /**< header */ 2802 struct dmub_idle_opt_set_dc_power_state_data data; 2803 }; 2804 2805 /** 2806 * struct dmub_clocks - Clock update notification. 2807 */ 2808 struct dmub_clocks { 2809 uint32_t dispclk_khz; /**< dispclk kHz */ 2810 uint32_t dppclk_khz; /**< dppclk kHz */ 2811 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2812 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2813 }; 2814 2815 /** 2816 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2817 */ 2818 enum dmub_cmd_clk_mgr_type { 2819 /** 2820 * Notify DMCUB of clock update. 2821 */ 2822 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2823 }; 2824 2825 /** 2826 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2827 */ 2828 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2829 struct dmub_cmd_header header; /**< header */ 2830 struct dmub_clocks clocks; /**< clock data */ 2831 }; 2832 2833 /** 2834 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2835 */ 2836 struct dmub_cmd_digx_encoder_control_data { 2837 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2838 }; 2839 2840 /** 2841 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2842 */ 2843 struct dmub_rb_cmd_digx_encoder_control { 2844 struct dmub_cmd_header header; /**< header */ 2845 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2846 }; 2847 2848 /** 2849 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2850 */ 2851 struct dmub_cmd_set_pixel_clock_data { 2852 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2853 }; 2854 2855 /** 2856 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2857 */ 2858 struct dmub_rb_cmd_set_pixel_clock { 2859 struct dmub_cmd_header header; /**< header */ 2860 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2861 }; 2862 2863 /** 2864 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2865 */ 2866 struct dmub_cmd_enable_disp_power_gating_data { 2867 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2868 }; 2869 2870 /** 2871 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2872 */ 2873 struct dmub_rb_cmd_enable_disp_power_gating { 2874 struct dmub_cmd_header header; /**< header */ 2875 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2876 }; 2877 2878 /** 2879 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2880 */ 2881 struct dmub_dig_transmitter_control_data_v1_7 { 2882 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2883 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2884 union { 2885 uint8_t digmode; /**< enum atom_encode_mode_def */ 2886 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2887 } mode_laneset; 2888 uint8_t lanenum; /**< Number of lanes */ 2889 union { 2890 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2891 } symclk_units; 2892 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2893 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2894 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2895 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2896 uint8_t reserved1; /**< For future use */ 2897 uint8_t skip_phy_ssc_reduction; 2898 uint8_t reserved2[2]; /**< For future use */ 2899 uint32_t reserved3[11]; /**< For future use */ 2900 }; 2901 2902 /** 2903 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2904 */ 2905 union dmub_cmd_dig1_transmitter_control_data { 2906 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2907 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2908 }; 2909 2910 /** 2911 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2912 */ 2913 struct dmub_rb_cmd_dig1_transmitter_control { 2914 struct dmub_cmd_header header; /**< header */ 2915 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2916 }; 2917 2918 /** 2919 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2920 */ 2921 struct dmub_rb_cmd_domain_control_data { 2922 uint8_t inst : 6; /**< DOMAIN instance to control */ 2923 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2924 uint8_t reserved[3]; /**< Reserved for future use */ 2925 }; 2926 2927 /** 2928 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2929 */ 2930 struct dmub_rb_cmd_domain_control { 2931 struct dmub_cmd_header header; /**< header */ 2932 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2933 }; 2934 2935 /** 2936 * DPIA tunnel command parameters. 2937 */ 2938 struct dmub_cmd_dig_dpia_control_data { 2939 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2940 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2941 union { 2942 uint8_t digmode; /** enum atom_encode_mode_def */ 2943 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2944 } mode_laneset; 2945 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2946 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2947 uint8_t hpdsel; /** =0: HPD is not assigned */ 2948 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2949 uint8_t dpia_id; /** Index of DPIA */ 2950 uint8_t fec_rdy : 1; 2951 uint8_t reserved : 7; 2952 uint32_t reserved1; 2953 }; 2954 2955 /** 2956 * DMUB command for DPIA tunnel control. 2957 */ 2958 struct dmub_rb_cmd_dig1_dpia_control { 2959 struct dmub_cmd_header header; 2960 struct dmub_cmd_dig_dpia_control_data dpia_control; 2961 }; 2962 2963 /** 2964 * SET_CONFIG Command Payload (deprecated) 2965 */ 2966 struct set_config_cmd_payload { 2967 uint8_t msg_type; /* set config message type */ 2968 uint8_t msg_data; /* set config message data */ 2969 }; 2970 2971 /** 2972 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2973 */ 2974 struct dmub_cmd_set_config_control_data { 2975 struct set_config_cmd_payload cmd_pkt; 2976 uint8_t instance; /* DPIA instance */ 2977 uint8_t immed_status; /* Immediate status returned in case of error */ 2978 }; 2979 2980 /** 2981 * SET_CONFIG Request Command Payload 2982 */ 2983 struct set_config_request_cmd_payload { 2984 uint8_t instance; /* DPIA instance */ 2985 uint8_t immed_status; /* Immediate status returned in case of error */ 2986 uint8_t msg_type; /* set config message type */ 2987 uint8_t reserved; 2988 uint32_t msg_data; /* set config message data */ 2989 }; 2990 2991 /** 2992 * DMUB command structure for SET_CONFIG command. 2993 */ 2994 struct dmub_rb_cmd_set_config_access { 2995 struct dmub_cmd_header header; /* header */ 2996 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2997 }; 2998 2999 /** 3000 * DMUB command structure for SET_CONFIG request command. 3001 */ 3002 struct dmub_rb_cmd_set_config_request { 3003 struct dmub_cmd_header header; /* header */ 3004 struct set_config_request_cmd_payload payload; /* set config request payload */ 3005 }; 3006 3007 /** 3008 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3009 */ 3010 struct dmub_cmd_mst_alloc_slots_control_data { 3011 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 3012 uint8_t instance; /* DPIA instance */ 3013 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 3014 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 3015 }; 3016 3017 /** 3018 * DMUB command structure for SET_ command. 3019 */ 3020 struct dmub_rb_cmd_set_mst_alloc_slots { 3021 struct dmub_cmd_header header; /* header */ 3022 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 3023 }; 3024 3025 /** 3026 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 3027 */ 3028 struct dmub_cmd_tps_notification_data { 3029 uint8_t instance; /* DPIA instance */ 3030 uint8_t tps; /* requested training pattern */ 3031 uint8_t reserved1; 3032 uint8_t reserved2; 3033 }; 3034 3035 /** 3036 * DMUB command structure for SET_TPS_NOTIFICATION command. 3037 */ 3038 struct dmub_rb_cmd_set_tps_notification { 3039 struct dmub_cmd_header header; /* header */ 3040 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 3041 }; 3042 3043 /** 3044 * DMUB command structure for DPIA HPD int enable control. 3045 */ 3046 struct dmub_rb_cmd_dpia_hpd_int_enable { 3047 struct dmub_cmd_header header; /* header */ 3048 uint32_t enable; /* dpia hpd interrupt enable */ 3049 }; 3050 3051 /** 3052 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 3053 */ 3054 struct dmub_rb_cmd_dpphy_init { 3055 struct dmub_cmd_header header; /**< header */ 3056 uint8_t reserved[60]; /**< reserved bits */ 3057 }; 3058 3059 /** 3060 * enum dp_aux_request_action - DP AUX request command listing. 3061 * 3062 * 4 AUX request command bits are shifted to high nibble. 3063 */ 3064 enum dp_aux_request_action { 3065 /** I2C-over-AUX write request */ 3066 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 3067 /** I2C-over-AUX read request */ 3068 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 3069 /** I2C-over-AUX write status request */ 3070 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 3071 /** I2C-over-AUX write request with MOT=1 */ 3072 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 3073 /** I2C-over-AUX read request with MOT=1 */ 3074 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 3075 /** I2C-over-AUX write status request with MOT=1 */ 3076 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 3077 /** Native AUX write request */ 3078 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 3079 /** Native AUX read request */ 3080 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 3081 }; 3082 3083 /** 3084 * enum aux_return_code_type - DP AUX process return code listing. 3085 */ 3086 enum aux_return_code_type { 3087 /** AUX process succeeded */ 3088 AUX_RET_SUCCESS = 0, 3089 /** AUX process failed with unknown reason */ 3090 AUX_RET_ERROR_UNKNOWN, 3091 /** AUX process completed with invalid reply */ 3092 AUX_RET_ERROR_INVALID_REPLY, 3093 /** AUX process timed out */ 3094 AUX_RET_ERROR_TIMEOUT, 3095 /** HPD was low during AUX process */ 3096 AUX_RET_ERROR_HPD_DISCON, 3097 /** Failed to acquire AUX engine */ 3098 AUX_RET_ERROR_ENGINE_ACQUIRE, 3099 /** AUX request not supported */ 3100 AUX_RET_ERROR_INVALID_OPERATION, 3101 /** AUX process not available */ 3102 AUX_RET_ERROR_PROTOCOL_ERROR, 3103 }; 3104 3105 /** 3106 * enum aux_channel_type - DP AUX channel type listing. 3107 */ 3108 enum aux_channel_type { 3109 /** AUX thru Legacy DP AUX */ 3110 AUX_CHANNEL_LEGACY_DDC, 3111 /** AUX thru DPIA DP tunneling */ 3112 AUX_CHANNEL_DPIA 3113 }; 3114 3115 /** 3116 * struct aux_transaction_parameters - DP AUX request transaction data 3117 */ 3118 struct aux_transaction_parameters { 3119 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 3120 uint8_t action; /**< enum dp_aux_request_action */ 3121 uint8_t length; /**< DP AUX request data length */ 3122 uint8_t reserved; /**< For future use */ 3123 uint32_t address; /**< DP AUX address */ 3124 uint8_t data[16]; /**< DP AUX write data */ 3125 }; 3126 3127 /** 3128 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3129 */ 3130 struct dmub_cmd_dp_aux_control_data { 3131 uint8_t instance; /**< AUX instance or DPIA instance */ 3132 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 3133 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 3134 uint8_t reserved0; /**< For future use */ 3135 uint16_t timeout; /**< timeout time in us */ 3136 uint16_t reserved1; /**< For future use */ 3137 enum aux_channel_type type; /**< enum aux_channel_type */ 3138 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 3139 }; 3140 3141 /** 3142 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3143 */ 3144 struct dmub_rb_cmd_dp_aux_access { 3145 /** 3146 * Command header. 3147 */ 3148 struct dmub_cmd_header header; 3149 /** 3150 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3151 */ 3152 struct dmub_cmd_dp_aux_control_data aux_control; 3153 }; 3154 3155 /** 3156 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3157 */ 3158 struct dmub_rb_cmd_outbox1_enable { 3159 /** 3160 * Command header. 3161 */ 3162 struct dmub_cmd_header header; 3163 /** 3164 * enable: 0x0 -> disable outbox1 notification (default value) 3165 * 0x1 -> enable outbox1 notification 3166 */ 3167 uint32_t enable; 3168 }; 3169 3170 /* DP AUX Reply command - OutBox Cmd */ 3171 /** 3172 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3173 */ 3174 struct aux_reply_data { 3175 /** 3176 * Aux cmd 3177 */ 3178 uint8_t command; 3179 /** 3180 * Aux reply data length (max: 16 bytes) 3181 */ 3182 uint8_t length; 3183 /** 3184 * Alignment only 3185 */ 3186 uint8_t pad[2]; 3187 /** 3188 * Aux reply data 3189 */ 3190 uint8_t data[16]; 3191 }; 3192 3193 /** 3194 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3195 */ 3196 struct aux_reply_control_data { 3197 /** 3198 * Reserved for future use 3199 */ 3200 uint32_t handle; 3201 /** 3202 * Aux Instance 3203 */ 3204 uint8_t instance; 3205 /** 3206 * Aux transaction result: definition in enum aux_return_code_type 3207 */ 3208 uint8_t result; 3209 /** 3210 * Alignment only 3211 */ 3212 uint16_t pad; 3213 }; 3214 3215 /** 3216 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 3217 */ 3218 struct dmub_rb_cmd_dp_aux_reply { 3219 /** 3220 * Command header. 3221 */ 3222 struct dmub_cmd_header header; 3223 /** 3224 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3225 */ 3226 struct aux_reply_control_data control; 3227 /** 3228 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3229 */ 3230 struct aux_reply_data reply_data; 3231 }; 3232 3233 /* DP HPD Notify command - OutBox Cmd */ 3234 /** 3235 * DP HPD Type 3236 */ 3237 enum dp_hpd_type { 3238 /** 3239 * Normal DP HPD 3240 */ 3241 DP_HPD = 0, 3242 /** 3243 * DP HPD short pulse 3244 */ 3245 DP_IRQ = 1, 3246 /** 3247 * Failure to acquire DP HPD state 3248 */ 3249 DP_NONE_HPD = 2 3250 }; 3251 3252 /** 3253 * DP HPD Status 3254 */ 3255 enum dp_hpd_status { 3256 /** 3257 * DP_HPD status low 3258 */ 3259 DP_HPD_UNPLUG = 0, 3260 /** 3261 * DP_HPD status high 3262 */ 3263 DP_HPD_PLUG 3264 }; 3265 3266 /** 3267 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3268 */ 3269 struct dp_hpd_data { 3270 /** 3271 * DP HPD instance 3272 */ 3273 uint8_t instance; 3274 /** 3275 * HPD type 3276 */ 3277 uint8_t hpd_type; 3278 /** 3279 * HPD status: only for type: DP_HPD to indicate status 3280 */ 3281 uint8_t hpd_status; 3282 /** 3283 * Alignment only 3284 */ 3285 uint8_t pad; 3286 }; 3287 3288 /** 3289 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3290 */ 3291 struct dmub_rb_cmd_dp_hpd_notify { 3292 /** 3293 * Command header. 3294 */ 3295 struct dmub_cmd_header header; 3296 /** 3297 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3298 */ 3299 struct dp_hpd_data hpd_data; 3300 }; 3301 3302 /** 3303 * Definition of a SET_CONFIG reply from DPOA. 3304 */ 3305 enum set_config_status { 3306 SET_CONFIG_PENDING = 0, 3307 SET_CONFIG_ACK_RECEIVED, 3308 SET_CONFIG_RX_TIMEOUT, 3309 SET_CONFIG_UNKNOWN_ERROR, 3310 }; 3311 3312 /** 3313 * Definition of a set_config reply 3314 */ 3315 struct set_config_reply_control_data { 3316 uint8_t instance; /* DPIA Instance */ 3317 uint8_t status; /* Set Config reply */ 3318 uint16_t pad; /* Alignment */ 3319 }; 3320 3321 /** 3322 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3323 */ 3324 struct dmub_rb_cmd_dp_set_config_reply { 3325 struct dmub_cmd_header header; 3326 struct set_config_reply_control_data set_config_reply_control; 3327 }; 3328 3329 /** 3330 * Definition of a DPIA notification header 3331 */ 3332 struct dpia_notification_header { 3333 uint8_t instance; /**< DPIA Instance */ 3334 uint8_t reserved[3]; 3335 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3336 }; 3337 3338 /** 3339 * Definition of the common data struct of DPIA notification 3340 */ 3341 struct dpia_notification_common { 3342 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3343 - sizeof(struct dpia_notification_header)]; 3344 }; 3345 3346 /** 3347 * Definition of a DPIA notification data 3348 */ 3349 struct dpia_bw_allocation_notify_data { 3350 union { 3351 struct { 3352 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3353 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3354 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3355 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3356 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3357 uint16_t reserved: 11; /**< Reserved */ 3358 } bits; 3359 3360 uint16_t flags; 3361 }; 3362 3363 uint8_t cm_id; /**< CM ID */ 3364 uint8_t group_id; /**< Group ID */ 3365 uint8_t granularity; /**< BW Allocation Granularity */ 3366 uint8_t estimated_bw; /**< Estimated_BW */ 3367 uint8_t allocated_bw; /**< Allocated_BW */ 3368 uint8_t reserved; 3369 }; 3370 3371 /** 3372 * union dpia_notify_data_type - DPIA Notification in Outbox command 3373 */ 3374 union dpia_notification_data { 3375 /** 3376 * DPIA Notification for common data struct 3377 */ 3378 struct dpia_notification_common common_data; 3379 3380 /** 3381 * DPIA Notification for DP BW Allocation support 3382 */ 3383 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3384 }; 3385 3386 /** 3387 * Definition of a DPIA notification payload 3388 */ 3389 struct dpia_notification_payload { 3390 struct dpia_notification_header header; 3391 union dpia_notification_data data; /**< DPIA notification payload data */ 3392 }; 3393 3394 /** 3395 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3396 */ 3397 struct dmub_rb_cmd_dpia_notification { 3398 struct dmub_cmd_header header; /**< DPIA notification header */ 3399 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3400 }; 3401 3402 /** 3403 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3404 */ 3405 struct dmub_cmd_hpd_state_query_data { 3406 uint8_t instance; /**< HPD instance or DPIA instance */ 3407 uint8_t result; /**< For returning HPD state */ 3408 uint16_t pad; /** < Alignment */ 3409 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3410 enum aux_return_code_type status; /**< for returning the status of command */ 3411 }; 3412 3413 /** 3414 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3415 */ 3416 struct dmub_rb_cmd_query_hpd_state { 3417 /** 3418 * Command header. 3419 */ 3420 struct dmub_cmd_header header; 3421 /** 3422 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3423 */ 3424 struct dmub_cmd_hpd_state_query_data data; 3425 }; 3426 3427 /** 3428 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3429 */ 3430 struct dmub_rb_cmd_hpd_sense_notify_data { 3431 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3432 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3433 }; 3434 3435 /** 3436 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3437 */ 3438 struct dmub_rb_cmd_hpd_sense_notify { 3439 struct dmub_cmd_header header; /**< header */ 3440 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3441 }; 3442 3443 /* 3444 * Command IDs should be treated as stable ABI. 3445 * Do not reuse or modify IDs. 3446 */ 3447 3448 /** 3449 * PSR command sub-types. 3450 */ 3451 enum dmub_cmd_psr_type { 3452 /** 3453 * Set PSR version support. 3454 */ 3455 DMUB_CMD__PSR_SET_VERSION = 0, 3456 /** 3457 * Copy driver-calculated parameters to PSR state. 3458 */ 3459 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3460 /** 3461 * Enable PSR. 3462 */ 3463 DMUB_CMD__PSR_ENABLE = 2, 3464 3465 /** 3466 * Disable PSR. 3467 */ 3468 DMUB_CMD__PSR_DISABLE = 3, 3469 3470 /** 3471 * Set PSR level. 3472 * PSR level is a 16-bit value dicated by driver that 3473 * will enable/disable different functionality. 3474 */ 3475 DMUB_CMD__PSR_SET_LEVEL = 4, 3476 3477 /** 3478 * Forces PSR enabled until an explicit PSR disable call. 3479 */ 3480 DMUB_CMD__PSR_FORCE_STATIC = 5, 3481 /** 3482 * Set vtotal in psr active for FreeSync PSR. 3483 */ 3484 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3485 /** 3486 * Set PSR power option 3487 */ 3488 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3489 }; 3490 3491 /** 3492 * Different PSR residency modes. 3493 * Different modes change the definition of PSR residency. 3494 */ 3495 enum psr_residency_mode { 3496 PSR_RESIDENCY_MODE_PHY = 0, 3497 PSR_RESIDENCY_MODE_ALPM, 3498 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3499 /* Do not add below. */ 3500 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3501 }; 3502 3503 enum dmub_cmd_fams_type { 3504 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3505 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3506 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3507 /** 3508 * For SubVP set manual trigger in FW because it 3509 * triggers DRR_UPDATE_PENDING which SubVP relies 3510 * on (for any SubVP cases that use a DRR display) 3511 */ 3512 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3513 DMUB_CMD__FAMS2_CONFIG = 4, 3514 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3515 DMUB_CMD__FAMS2_FLIP = 6, 3516 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3517 }; 3518 3519 /** 3520 * PSR versions. 3521 */ 3522 enum psr_version { 3523 /** 3524 * PSR version 1. 3525 */ 3526 PSR_VERSION_1 = 0, 3527 /** 3528 * Freesync PSR SU. 3529 */ 3530 PSR_VERSION_SU_1 = 1, 3531 /** 3532 * PSR not supported. 3533 */ 3534 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3535 }; 3536 3537 /** 3538 * PHY Link rate for DP. 3539 */ 3540 enum phy_link_rate { 3541 /** 3542 * not supported. 3543 */ 3544 PHY_RATE_UNKNOWN = 0, 3545 /** 3546 * Rate_1 (RBR) - 1.62 Gbps/Lane 3547 */ 3548 PHY_RATE_162 = 1, 3549 /** 3550 * Rate_2 - 2.16 Gbps/Lane 3551 */ 3552 PHY_RATE_216 = 2, 3553 /** 3554 * Rate_3 - 2.43 Gbps/Lane 3555 */ 3556 PHY_RATE_243 = 3, 3557 /** 3558 * Rate_4 (HBR) - 2.70 Gbps/Lane 3559 */ 3560 PHY_RATE_270 = 4, 3561 /** 3562 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3563 */ 3564 PHY_RATE_324 = 5, 3565 /** 3566 * Rate_6 - 4.32 Gbps/Lane 3567 */ 3568 PHY_RATE_432 = 6, 3569 /** 3570 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3571 */ 3572 PHY_RATE_540 = 7, 3573 /** 3574 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3575 */ 3576 PHY_RATE_810 = 8, 3577 /** 3578 * UHBR10 - 10.0 Gbps/Lane 3579 */ 3580 PHY_RATE_1000 = 9, 3581 /** 3582 * UHBR13.5 - 13.5 Gbps/Lane 3583 */ 3584 PHY_RATE_1350 = 10, 3585 /** 3586 * UHBR10 - 20.0 Gbps/Lane 3587 */ 3588 PHY_RATE_2000 = 11, 3589 3590 PHY_RATE_675 = 12, 3591 /** 3592 * Rate 12 - 6.75 Gbps/Lane 3593 */ 3594 }; 3595 3596 /** 3597 * enum dmub_phy_fsm_state - PHY FSM states. 3598 * PHY FSM state to transit to during PSR enable/disable. 3599 */ 3600 enum dmub_phy_fsm_state { 3601 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3602 DMUB_PHY_FSM_RESET, 3603 DMUB_PHY_FSM_RESET_RELEASED, 3604 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3605 DMUB_PHY_FSM_INITIALIZED, 3606 DMUB_PHY_FSM_CALIBRATED, 3607 DMUB_PHY_FSM_CALIBRATED_LP, 3608 DMUB_PHY_FSM_CALIBRATED_PG, 3609 DMUB_PHY_FSM_POWER_DOWN, 3610 DMUB_PHY_FSM_PLL_EN, 3611 DMUB_PHY_FSM_TX_EN, 3612 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3613 DMUB_PHY_FSM_FAST_LP, 3614 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3615 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3616 DMUB_PHY_FSM_P2_PLL_OFF, 3617 DMUB_PHY_FSM_P2_PLL_ON, 3618 }; 3619 3620 /** 3621 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3622 */ 3623 struct dmub_cmd_psr_copy_settings_data { 3624 /** 3625 * Flags that can be set by driver to change some PSR behaviour. 3626 */ 3627 union dmub_psr_debug_flags debug; 3628 /** 3629 * 16-bit value dicated by driver that will enable/disable different functionality. 3630 */ 3631 uint16_t psr_level; 3632 /** 3633 * DPP HW instance. 3634 */ 3635 uint8_t dpp_inst; 3636 /** 3637 * MPCC HW instance. 3638 * Not used in dmub fw, 3639 * dmub fw will get active opp by reading odm registers. 3640 */ 3641 uint8_t mpcc_inst; 3642 /** 3643 * OPP HW instance. 3644 * Not used in dmub fw, 3645 * dmub fw will get active opp by reading odm registers. 3646 */ 3647 uint8_t opp_inst; 3648 /** 3649 * OTG HW instance. 3650 */ 3651 uint8_t otg_inst; 3652 /** 3653 * DIG FE HW instance. 3654 */ 3655 uint8_t digfe_inst; 3656 /** 3657 * DIG BE HW instance. 3658 */ 3659 uint8_t digbe_inst; 3660 /** 3661 * DP PHY HW instance. 3662 */ 3663 uint8_t dpphy_inst; 3664 /** 3665 * AUX HW instance. 3666 */ 3667 uint8_t aux_inst; 3668 /** 3669 * Determines if SMU optimzations are enabled/disabled. 3670 */ 3671 uint8_t smu_optimizations_en; 3672 /** 3673 * Unused. 3674 * TODO: Remove. 3675 */ 3676 uint8_t frame_delay; 3677 /** 3678 * If RFB setup time is greater than the total VBLANK time, 3679 * it is not possible for the sink to capture the video frame 3680 * in the same frame the SDP is sent. In this case, 3681 * the frame capture indication bit should be set and an extra 3682 * static frame should be transmitted to the sink. 3683 */ 3684 uint8_t frame_cap_ind; 3685 /** 3686 * Granularity of Y offset supported by sink. 3687 */ 3688 uint8_t su_y_granularity; 3689 /** 3690 * Indicates whether sink should start capturing 3691 * immediately following active scan line, 3692 * or starting with the 2nd active scan line. 3693 */ 3694 uint8_t line_capture_indication; 3695 /** 3696 * Multi-display optimizations are implemented on certain ASICs. 3697 */ 3698 uint8_t multi_disp_optimizations_en; 3699 /** 3700 * The last possible line SDP may be transmitted without violating 3701 * the RFB setup time or entering the active video frame. 3702 */ 3703 uint16_t init_sdp_deadline; 3704 /** 3705 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3706 */ 3707 uint8_t rate_control_caps; 3708 /* 3709 * Force PSRSU always doing full frame update 3710 */ 3711 uint8_t force_ffu_mode; 3712 /** 3713 * Length of each horizontal line in us. 3714 */ 3715 uint32_t line_time_in_us; 3716 /** 3717 * FEC enable status in driver 3718 */ 3719 uint8_t fec_enable_status; 3720 /** 3721 * FEC re-enable delay when PSR exit. 3722 * unit is 100us, range form 0~255(0xFF). 3723 */ 3724 uint8_t fec_enable_delay_in100us; 3725 /** 3726 * PSR control version. 3727 */ 3728 uint8_t cmd_version; 3729 /** 3730 * Panel Instance. 3731 * Panel instance to identify which psr_state to use 3732 * Currently the support is only for 0 or 1 3733 */ 3734 uint8_t panel_inst; 3735 /* 3736 * DSC enable status in driver 3737 */ 3738 uint8_t dsc_enable_status; 3739 /* 3740 * Use FSM state for PSR power up/down 3741 */ 3742 uint8_t use_phy_fsm; 3743 /** 3744 * frame delay for frame re-lock 3745 */ 3746 uint8_t relock_delay_frame_cnt; 3747 /** 3748 * esd recovery indicate. 3749 */ 3750 uint8_t esd_recovery; 3751 /** 3752 * DSC Slice height. 3753 */ 3754 uint16_t dsc_slice_height; 3755 /** 3756 * Some panels request main link off before xth vertical line 3757 */ 3758 uint16_t poweroff_before_vertical_line; 3759 /** 3760 * Some panels cannot handle idle pattern during PSR entry. 3761 * To power down phy before disable stream to avoid sending 3762 * idle pattern. 3763 */ 3764 uint8_t power_down_phy_before_disable_stream; 3765 }; 3766 3767 /** 3768 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3769 */ 3770 struct dmub_rb_cmd_psr_copy_settings { 3771 /** 3772 * Command header. 3773 */ 3774 struct dmub_cmd_header header; 3775 /** 3776 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3777 */ 3778 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3779 }; 3780 3781 /** 3782 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3783 */ 3784 struct dmub_cmd_psr_set_level_data { 3785 /** 3786 * 16-bit value dicated by driver that will enable/disable different functionality. 3787 */ 3788 uint16_t psr_level; 3789 /** 3790 * PSR control version. 3791 */ 3792 uint8_t cmd_version; 3793 /** 3794 * Panel Instance. 3795 * Panel instance to identify which psr_state to use 3796 * Currently the support is only for 0 or 1 3797 */ 3798 uint8_t panel_inst; 3799 }; 3800 3801 /** 3802 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3803 */ 3804 struct dmub_rb_cmd_psr_set_level { 3805 /** 3806 * Command header. 3807 */ 3808 struct dmub_cmd_header header; 3809 /** 3810 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3811 */ 3812 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3813 }; 3814 3815 struct dmub_rb_cmd_psr_enable_data { 3816 /** 3817 * PSR control version. 3818 */ 3819 uint8_t cmd_version; 3820 /** 3821 * Panel Instance. 3822 * Panel instance to identify which psr_state to use 3823 * Currently the support is only for 0 or 1 3824 */ 3825 uint8_t panel_inst; 3826 /** 3827 * Phy state to enter. 3828 * Values to use are defined in dmub_phy_fsm_state 3829 */ 3830 uint8_t phy_fsm_state; 3831 /** 3832 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3833 * Set this using enum phy_link_rate. 3834 * This does not support HDMI/DP2 for now. 3835 */ 3836 uint8_t phy_rate; 3837 }; 3838 3839 /** 3840 * Definition of a DMUB_CMD__PSR_ENABLE command. 3841 * PSR enable/disable is controlled using the sub_type. 3842 */ 3843 struct dmub_rb_cmd_psr_enable { 3844 /** 3845 * Command header. 3846 */ 3847 struct dmub_cmd_header header; 3848 3849 struct dmub_rb_cmd_psr_enable_data data; 3850 }; 3851 3852 /** 3853 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3854 */ 3855 struct dmub_cmd_psr_set_version_data { 3856 /** 3857 * PSR version that FW should implement. 3858 */ 3859 enum psr_version version; 3860 /** 3861 * PSR control version. 3862 */ 3863 uint8_t cmd_version; 3864 /** 3865 * Panel Instance. 3866 * Panel instance to identify which psr_state to use 3867 * Currently the support is only for 0 or 1 3868 */ 3869 uint8_t panel_inst; 3870 /** 3871 * Explicit padding to 4 byte boundary. 3872 */ 3873 uint8_t pad[2]; 3874 }; 3875 3876 /** 3877 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3878 */ 3879 struct dmub_rb_cmd_psr_set_version { 3880 /** 3881 * Command header. 3882 */ 3883 struct dmub_cmd_header header; 3884 /** 3885 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3886 */ 3887 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3888 }; 3889 3890 struct dmub_cmd_psr_force_static_data { 3891 /** 3892 * PSR control version. 3893 */ 3894 uint8_t cmd_version; 3895 /** 3896 * Panel Instance. 3897 * Panel instance to identify which psr_state to use 3898 * Currently the support is only for 0 or 1 3899 */ 3900 uint8_t panel_inst; 3901 /** 3902 * Explicit padding to 4 byte boundary. 3903 */ 3904 uint8_t pad[2]; 3905 }; 3906 3907 /** 3908 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3909 */ 3910 struct dmub_rb_cmd_psr_force_static { 3911 /** 3912 * Command header. 3913 */ 3914 struct dmub_cmd_header header; 3915 /** 3916 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3917 */ 3918 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3919 }; 3920 3921 /** 3922 * PSR SU debug flags. 3923 */ 3924 union dmub_psr_su_debug_flags { 3925 /** 3926 * PSR SU debug flags. 3927 */ 3928 struct { 3929 /** 3930 * Update dirty rect in SW only. 3931 */ 3932 uint8_t update_dirty_rect_only : 1; 3933 /** 3934 * Reset the cursor/plane state before processing the call. 3935 */ 3936 uint8_t reset_state : 1; 3937 } bitfields; 3938 3939 /** 3940 * Union for debug flags. 3941 */ 3942 uint32_t u32All; 3943 }; 3944 3945 /** 3946 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3947 * This triggers a selective update for PSR SU. 3948 */ 3949 struct dmub_cmd_update_dirty_rect_data { 3950 /** 3951 * Dirty rects from OS. 3952 */ 3953 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3954 /** 3955 * PSR SU debug flags. 3956 */ 3957 union dmub_psr_su_debug_flags debug_flags; 3958 /** 3959 * Pipe index. 3960 */ 3961 uint8_t pipe_idx; 3962 /** 3963 * Number of dirty rects. 3964 */ 3965 uint8_t dirty_rect_count; 3966 /** 3967 * dirty rects cmd version. 3968 */ 3969 uint8_t cmd_version; 3970 /** 3971 * Panel Instance. 3972 * Panel instance to identify which psr_state to use 3973 * Currently the support is only for 0 or 1 3974 */ 3975 uint8_t panel_inst; 3976 /** 3977 * OTG HW instance 3978 */ 3979 uint8_t otg_inst; 3980 /** 3981 * Padding for 4 byte alignment 3982 */ 3983 uint8_t padding[3]; 3984 }; 3985 3986 /** 3987 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3988 */ 3989 struct dmub_rb_cmd_update_dirty_rect { 3990 /** 3991 * Command header. 3992 */ 3993 struct dmub_cmd_header header; 3994 /** 3995 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3996 */ 3997 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3998 }; 3999 4000 /** 4001 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4002 */ 4003 union dmub_reg_cursor_control_cfg { 4004 struct { 4005 uint32_t cur_enable: 1; 4006 uint32_t reser0: 3; 4007 uint32_t cur_2x_magnify: 1; 4008 uint32_t reser1: 3; 4009 uint32_t mode: 3; 4010 uint32_t reser2: 5; 4011 uint32_t pitch: 2; 4012 uint32_t reser3: 6; 4013 uint32_t line_per_chunk: 5; 4014 uint32_t reser4: 3; 4015 } bits; 4016 uint32_t raw; 4017 }; 4018 struct dmub_cursor_position_cache_hubp { 4019 union dmub_reg_cursor_control_cfg cur_ctl; 4020 union dmub_reg_position_cfg { 4021 struct { 4022 uint32_t cur_x_pos: 16; 4023 uint32_t cur_y_pos: 16; 4024 } bits; 4025 uint32_t raw; 4026 } position; 4027 union dmub_reg_hot_spot_cfg { 4028 struct { 4029 uint32_t hot_x: 16; 4030 uint32_t hot_y: 16; 4031 } bits; 4032 uint32_t raw; 4033 } hot_spot; 4034 union dmub_reg_dst_offset_cfg { 4035 struct { 4036 uint32_t dst_x_offset: 13; 4037 uint32_t reserved: 19; 4038 } bits; 4039 uint32_t raw; 4040 } dst_offset; 4041 }; 4042 4043 union dmub_reg_cur0_control_cfg { 4044 struct { 4045 uint32_t cur0_enable: 1; 4046 uint32_t expansion_mode: 1; 4047 uint32_t reser0: 1; 4048 uint32_t cur0_rom_en: 1; 4049 uint32_t mode: 3; 4050 uint32_t reserved: 25; 4051 } bits; 4052 uint32_t raw; 4053 }; 4054 struct dmub_cursor_position_cache_dpp { 4055 union dmub_reg_cur0_control_cfg cur0_ctl; 4056 }; 4057 struct dmub_cursor_position_cfg { 4058 struct dmub_cursor_position_cache_hubp pHubp; 4059 struct dmub_cursor_position_cache_dpp pDpp; 4060 uint8_t pipe_idx; 4061 /* 4062 * Padding is required. To be 4 Bytes Aligned. 4063 */ 4064 uint8_t padding[3]; 4065 }; 4066 4067 struct dmub_cursor_attribute_cache_hubp { 4068 uint32_t SURFACE_ADDR_HIGH; 4069 uint32_t SURFACE_ADDR; 4070 union dmub_reg_cursor_control_cfg cur_ctl; 4071 union dmub_reg_cursor_size_cfg { 4072 struct { 4073 uint32_t width: 16; 4074 uint32_t height: 16; 4075 } bits; 4076 uint32_t raw; 4077 } size; 4078 union dmub_reg_cursor_settings_cfg { 4079 struct { 4080 uint32_t dst_y_offset: 8; 4081 uint32_t chunk_hdl_adjust: 2; 4082 uint32_t reserved: 22; 4083 } bits; 4084 uint32_t raw; 4085 } settings; 4086 }; 4087 struct dmub_cursor_attribute_cache_dpp { 4088 union dmub_reg_cur0_control_cfg cur0_ctl; 4089 }; 4090 struct dmub_cursor_attributes_cfg { 4091 struct dmub_cursor_attribute_cache_hubp aHubp; 4092 struct dmub_cursor_attribute_cache_dpp aDpp; 4093 }; 4094 4095 struct dmub_cmd_update_cursor_payload0 { 4096 /** 4097 * Cursor dirty rects. 4098 */ 4099 struct dmub_rect cursor_rect; 4100 /** 4101 * PSR SU debug flags. 4102 */ 4103 union dmub_psr_su_debug_flags debug_flags; 4104 /** 4105 * Cursor enable/disable. 4106 */ 4107 uint8_t enable; 4108 /** 4109 * Pipe index. 4110 */ 4111 uint8_t pipe_idx; 4112 /** 4113 * Cursor update cmd version. 4114 */ 4115 uint8_t cmd_version; 4116 /** 4117 * Panel Instance. 4118 * Panel instance to identify which psr_state to use 4119 * Currently the support is only for 0 or 1 4120 */ 4121 uint8_t panel_inst; 4122 /** 4123 * Cursor Position Register. 4124 * Registers contains Hubp & Dpp modules 4125 */ 4126 struct dmub_cursor_position_cfg position_cfg; 4127 /** 4128 * OTG HW instance 4129 */ 4130 uint8_t otg_inst; 4131 /** 4132 * Padding for 4 byte alignment 4133 */ 4134 uint8_t padding[3]; 4135 }; 4136 4137 struct dmub_cmd_update_cursor_payload1 { 4138 struct dmub_cursor_attributes_cfg attribute_cfg; 4139 }; 4140 4141 union dmub_cmd_update_cursor_info_data { 4142 struct dmub_cmd_update_cursor_payload0 payload0; 4143 struct dmub_cmd_update_cursor_payload1 payload1; 4144 }; 4145 /** 4146 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4147 */ 4148 struct dmub_rb_cmd_update_cursor_info { 4149 /** 4150 * Command header. 4151 */ 4152 struct dmub_cmd_header header; 4153 /** 4154 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4155 */ 4156 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 4157 }; 4158 4159 /** 4160 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4161 */ 4162 struct dmub_cmd_psr_set_vtotal_data { 4163 /** 4164 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 4165 */ 4166 uint16_t psr_vtotal_idle; 4167 /** 4168 * PSR control version. 4169 */ 4170 uint8_t cmd_version; 4171 /** 4172 * Panel Instance. 4173 * Panel instance to identify which psr_state to use 4174 * Currently the support is only for 0 or 1 4175 */ 4176 uint8_t panel_inst; 4177 /* 4178 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 4179 */ 4180 uint16_t psr_vtotal_su; 4181 /** 4182 * Explicit padding to 4 byte boundary. 4183 */ 4184 uint8_t pad2[2]; 4185 }; 4186 4187 /** 4188 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4189 */ 4190 struct dmub_rb_cmd_psr_set_vtotal { 4191 /** 4192 * Command header. 4193 */ 4194 struct dmub_cmd_header header; 4195 /** 4196 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4197 */ 4198 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 4199 }; 4200 4201 /** 4202 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 4203 */ 4204 struct dmub_cmd_psr_set_power_opt_data { 4205 /** 4206 * PSR control version. 4207 */ 4208 uint8_t cmd_version; 4209 /** 4210 * Panel Instance. 4211 * Panel instance to identify which psr_state to use 4212 * Currently the support is only for 0 or 1 4213 */ 4214 uint8_t panel_inst; 4215 /** 4216 * Explicit padding to 4 byte boundary. 4217 */ 4218 uint8_t pad[2]; 4219 /** 4220 * PSR power option 4221 */ 4222 uint32_t power_opt; 4223 }; 4224 4225 /** 4226 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4227 */ 4228 struct dmub_rb_cmd_psr_set_power_opt { 4229 /** 4230 * Command header. 4231 */ 4232 struct dmub_cmd_header header; 4233 /** 4234 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4235 */ 4236 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 4237 }; 4238 4239 enum dmub_alpm_mode { 4240 ALPM_AUXWAKE = 0, 4241 ALPM_AUXLESS = 1, 4242 ALPM_UNSUPPORTED = 2, 4243 }; 4244 4245 /** 4246 * Definition of Replay Residency GPINT command. 4247 * Bit[0] - Residency mode for Revision 0 4248 * Bit[1] - Enable/Disable state 4249 * Bit[2-3] - Revision number 4250 * Bit[4-7] - Residency mode for Revision 1 4251 * Bit[8] - Panel instance 4252 * Bit[9-15] - Reserved 4253 */ 4254 4255 enum pr_residency_mode { 4256 PR_RESIDENCY_MODE_PHY = 0x0, 4257 PR_RESIDENCY_MODE_ALPM, 4258 PR_RESIDENCY_MODE_IPS2, 4259 PR_RESIDENCY_MODE_FRAME_CNT, 4260 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 4261 }; 4262 4263 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 4264 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 4265 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 4266 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 4267 4268 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4269 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 4270 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4271 4272 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 4273 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 4274 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 4275 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 4276 4277 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4278 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4279 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4280 4281 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 4282 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 4283 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 4284 4285 /** 4286 * Definition of a replay_state. 4287 */ 4288 enum replay_state { 4289 REPLAY_STATE_0 = 0x0, 4290 REPLAY_STATE_1 = 0x10, 4291 REPLAY_STATE_1A = 0x11, 4292 REPLAY_STATE_2 = 0x20, 4293 REPLAY_STATE_2A = 0x21, 4294 REPLAY_STATE_3 = 0x30, 4295 REPLAY_STATE_3INIT = 0x31, 4296 REPLAY_STATE_4 = 0x40, 4297 REPLAY_STATE_4A = 0x41, 4298 REPLAY_STATE_4B = 0x42, 4299 REPLAY_STATE_4C = 0x43, 4300 REPLAY_STATE_4D = 0x44, 4301 REPLAY_STATE_4E = 0x45, 4302 REPLAY_STATE_4B_LOCKED = 0x4A, 4303 REPLAY_STATE_4C_UNLOCKED = 0x4B, 4304 REPLAY_STATE_5 = 0x50, 4305 REPLAY_STATE_5A = 0x51, 4306 REPLAY_STATE_5B = 0x52, 4307 REPLAY_STATE_5A_LOCKED = 0x5A, 4308 REPLAY_STATE_5B_UNLOCKED = 0x5B, 4309 REPLAY_STATE_6 = 0x60, 4310 REPLAY_STATE_6A = 0x61, 4311 REPLAY_STATE_6B = 0x62, 4312 REPLAY_STATE_INVALID = 0xFF, 4313 }; 4314 4315 /** 4316 * Definition of a panel replay state 4317 */ 4318 enum pr_state { 4319 PR_STATE_0 = 0x00, // State 0 steady state 4320 // Pending SDP and Unlock before back to State 0 4321 PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01, 4322 PR_STATE_1 = 0x10, // State 1 4323 PR_STATE_2 = 0x20, // State 2 steady state 4324 // Pending frame transmission before transition to State 2 4325 PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30, 4326 // Active and Powered Up 4327 PR_STATE_2_POWERED = 0x31, 4328 // Active and Powered Down, but need to blank HUBP after DPG_EN latch 4329 PR_STATE_2_PENDING_HUBP_BLANK = 0x32, 4330 // Active and Pending Power Up 4331 PR_STATE_2_PENDING_POWER_UP = 0x33, 4332 // Active and Powered Up, Pending DPG latch 4333 PR_STATE_2_PENDING_LOCK = 0x34, 4334 // Active and Powered Up, Pending SDP and Unlock 4335 PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, 4336 // Pending transmission of AS SDP for timing sync, but no rfb update 4337 PR_STATE_2_PENDING_AS_SDP = 0x36, 4338 // Invalid 4339 PR_STATE_INVALID = 0xFF, 4340 }; 4341 4342 /** 4343 * Replay command sub-types. 4344 */ 4345 enum dmub_cmd_replay_type { 4346 /** 4347 * Copy driver-calculated parameters to REPLAY state. 4348 */ 4349 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 4350 /** 4351 * Enable REPLAY. 4352 */ 4353 DMUB_CMD__REPLAY_ENABLE = 1, 4354 /** 4355 * Set Replay power option. 4356 */ 4357 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 4358 /** 4359 * Set coasting vtotal. 4360 */ 4361 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4362 /** 4363 * Set power opt and coasting vtotal. 4364 */ 4365 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4366 /** 4367 * Set disabled iiming sync. 4368 */ 4369 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4370 /** 4371 * Set Residency Frameupdate Timer. 4372 */ 4373 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4374 /** 4375 * Set pseudo vtotal 4376 */ 4377 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4378 /** 4379 * Set adaptive sync sdp enabled 4380 */ 4381 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4382 /** 4383 * Set Replay General command. 4384 */ 4385 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4386 }; 4387 4388 /* 4389 * Panel Replay sub-types 4390 */ 4391 enum dmub_cmd_panel_replay_type { 4392 DMUB_CMD__PR_ENABLE = 0, 4393 DMUB_CMD__PR_COPY_SETTINGS = 1, 4394 DMUB_CMD__PR_UPDATE_STATE = 2, 4395 DMUB_CMD__PR_GENERAL_CMD = 3, 4396 }; 4397 4398 enum dmub_cmd_panel_replay_state_update_subtype { 4399 PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, 4400 PR_STATE_UPDATE_SYNC_MODE = 0x2, 4401 }; 4402 4403 enum dmub_cmd_panel_replay_general_subtype { 4404 PR_GENERAL_CMD_DEBUG_OPTION = 0x1, 4405 }; 4406 4407 /** 4408 * Replay general command sub-types. 4409 */ 4410 enum dmub_cmd_replay_general_subtype { 4411 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4412 /** 4413 * TODO: For backward compatible, allow new command only. 4414 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4415 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4416 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4417 */ 4418 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4419 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4420 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4421 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4422 REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, 4423 REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, 4424 }; 4425 4426 struct dmub_alpm_auxless_data { 4427 uint16_t lfps_setup_ns; 4428 uint16_t lfps_period_ns; 4429 uint16_t lfps_silence_ns; 4430 uint16_t lfps_t1_t2_override_us; 4431 short lfps_t1_t2_offset_us; 4432 uint8_t lttpr_count; 4433 /* 4434 * Padding to align structure to 4 byte boundary. 4435 */ 4436 uint8_t pad[1]; 4437 }; 4438 4439 /** 4440 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4441 */ 4442 struct dmub_cmd_replay_copy_settings_data { 4443 /** 4444 * Flags that can be set by driver to change some replay behaviour. 4445 */ 4446 union replay_debug_flags debug; 4447 4448 /** 4449 * @flags: Flags used to determine feature functionality. 4450 */ 4451 union replay_hw_flags flags; 4452 4453 /** 4454 * DPP HW instance. 4455 */ 4456 uint8_t dpp_inst; 4457 /** 4458 * OTG HW instance. 4459 */ 4460 uint8_t otg_inst; 4461 /** 4462 * DIG FE HW instance. 4463 */ 4464 uint8_t digfe_inst; 4465 /** 4466 * DIG BE HW instance. 4467 */ 4468 uint8_t digbe_inst; 4469 /** 4470 * AUX HW instance. 4471 */ 4472 uint8_t aux_inst; 4473 /** 4474 * Panel Instance. 4475 * Panel isntance to identify which psr_state to use 4476 * Currently the support is only for 0 or 1 4477 */ 4478 uint8_t panel_inst; 4479 /** 4480 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4481 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4482 */ 4483 uint8_t pixel_deviation_per_line; 4484 /** 4485 * @max_deviation_line: The max number of deviation line that can keep the timing 4486 * synchronized between the Source and Sink during Replay normal sleep mode. 4487 */ 4488 uint8_t max_deviation_line; 4489 /** 4490 * Length of each horizontal line in ns. 4491 */ 4492 uint32_t line_time_in_ns; 4493 /** 4494 * PHY instance. 4495 */ 4496 uint8_t dpphy_inst; 4497 /** 4498 * Determines if SMU optimzations are enabled/disabled. 4499 */ 4500 uint8_t smu_optimizations_en; 4501 /** 4502 * Determines if timing sync are enabled/disabled. 4503 */ 4504 uint8_t replay_timing_sync_supported; 4505 /* 4506 * Use FSM state for Replay power up/down 4507 */ 4508 uint8_t use_phy_fsm; 4509 /** 4510 * Use for AUX-less ALPM LFPS wake operation 4511 */ 4512 struct dmub_alpm_auxless_data auxless_alpm_data; 4513 /** 4514 * @hpo_stream_enc_inst: HPO stream encoder instance 4515 */ 4516 uint8_t hpo_stream_enc_inst; 4517 /** 4518 * @hpo_link_enc_inst: HPO link encoder instance 4519 */ 4520 uint8_t hpo_link_enc_inst; 4521 /** 4522 * Determines if fast resync in ultra sleep mode is enabled/disabled. 4523 */ 4524 uint8_t replay_support_fast_resync_in_ultra_sleep_mode; 4525 /** 4526 * @pad: Align structure to 4 byte boundary. 4527 */ 4528 uint8_t pad[1]; 4529 }; 4530 4531 4532 /** 4533 * Replay versions. 4534 */ 4535 enum replay_version { 4536 /** 4537 * FreeSync Replay 4538 */ 4539 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4540 /** 4541 * Panel Replay 4542 */ 4543 REPLAY_VERSION_PANEL_REPLAY = 1, 4544 /** 4545 * Replay not supported. 4546 */ 4547 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4548 }; 4549 4550 /** 4551 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4552 */ 4553 struct dmub_rb_cmd_replay_copy_settings { 4554 /** 4555 * Command header. 4556 */ 4557 struct dmub_cmd_header header; 4558 /** 4559 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4560 */ 4561 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4562 }; 4563 4564 /** 4565 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4566 */ 4567 enum replay_enable { 4568 /** 4569 * Disable REPLAY. 4570 */ 4571 REPLAY_DISABLE = 0, 4572 /** 4573 * Enable REPLAY. 4574 */ 4575 REPLAY_ENABLE = 1, 4576 }; 4577 4578 /** 4579 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 4580 */ 4581 struct dmub_rb_cmd_smart_power_oled_enable_data { 4582 /** 4583 * SMART_POWER_OLED enable or disable. 4584 */ 4585 uint8_t enable; 4586 /** 4587 * Panel Instance. 4588 * Panel isntance to identify which replay_state to use 4589 * Currently the support is only for 0 or 1 4590 */ 4591 uint8_t panel_inst; 4592 4593 uint16_t peak_nits; 4594 /** 4595 * OTG HW instance. 4596 */ 4597 uint8_t otg_inst; 4598 /** 4599 * DIG FE HW instance. 4600 */ 4601 uint8_t digfe_inst; 4602 /** 4603 * DIG BE HW instance. 4604 */ 4605 uint8_t digbe_inst; 4606 uint8_t debugcontrol; 4607 /* 4608 * vertical interrupt trigger line 4609 */ 4610 uint32_t triggerline; 4611 4612 uint16_t fixed_max_cll; 4613 4614 uint8_t pad[2]; 4615 }; 4616 4617 /** 4618 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4619 */ 4620 struct dmub_rb_cmd_replay_enable_data { 4621 /** 4622 * Replay enable or disable. 4623 */ 4624 uint8_t enable; 4625 /** 4626 * Panel Instance. 4627 * Panel isntance to identify which replay_state to use 4628 * Currently the support is only for 0 or 1 4629 */ 4630 uint8_t panel_inst; 4631 /** 4632 * Phy state to enter. 4633 * Values to use are defined in dmub_phy_fsm_state 4634 */ 4635 uint8_t phy_fsm_state; 4636 /** 4637 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4638 * Set this using enum phy_link_rate. 4639 * This does not support HDMI/DP2 for now. 4640 */ 4641 uint8_t phy_rate; 4642 }; 4643 4644 /** 4645 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4646 * Replay enable/disable is controlled using action in data. 4647 */ 4648 struct dmub_rb_cmd_replay_enable { 4649 /** 4650 * Command header. 4651 */ 4652 struct dmub_cmd_header header; 4653 4654 struct dmub_rb_cmd_replay_enable_data data; 4655 }; 4656 4657 /** 4658 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4659 */ 4660 struct dmub_cmd_replay_set_power_opt_data { 4661 /** 4662 * Panel Instance. 4663 * Panel isntance to identify which replay_state to use 4664 * Currently the support is only for 0 or 1 4665 */ 4666 uint8_t panel_inst; 4667 /** 4668 * Explicit padding to 4 byte boundary. 4669 */ 4670 uint8_t pad[3]; 4671 /** 4672 * REPLAY power option 4673 */ 4674 uint32_t power_opt; 4675 }; 4676 4677 /** 4678 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4679 */ 4680 struct dmub_cmd_replay_set_timing_sync_data { 4681 /** 4682 * Panel Instance. 4683 * Panel isntance to identify which replay_state to use 4684 * Currently the support is only for 0 or 1 4685 */ 4686 uint8_t panel_inst; 4687 /** 4688 * REPLAY set_timing_sync 4689 */ 4690 uint8_t timing_sync_supported; 4691 /** 4692 * Explicit padding to 4 byte boundary. 4693 */ 4694 uint8_t pad[2]; 4695 }; 4696 4697 /** 4698 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4699 */ 4700 struct dmub_cmd_replay_set_pseudo_vtotal { 4701 /** 4702 * Panel Instance. 4703 * Panel isntance to identify which replay_state to use 4704 * Currently the support is only for 0 or 1 4705 */ 4706 uint8_t panel_inst; 4707 /** 4708 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4709 */ 4710 uint16_t vtotal; 4711 /** 4712 * Explicit padding to 4 byte boundary. 4713 */ 4714 uint8_t pad; 4715 }; 4716 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4717 /** 4718 * Panel Instance. 4719 * Panel isntance to identify which replay_state to use 4720 * Currently the support is only for 0 or 1 4721 */ 4722 uint8_t panel_inst; 4723 /** 4724 * enabled: set adaptive sync sdp enabled 4725 */ 4726 uint8_t force_disabled; 4727 4728 uint8_t pad[2]; 4729 }; 4730 struct dmub_cmd_replay_set_general_cmd_data { 4731 /** 4732 * Panel Instance. 4733 * Panel isntance to identify which replay_state to use 4734 * Currently the support is only for 0 or 1 4735 */ 4736 uint8_t panel_inst; 4737 /** 4738 * subtype: replay general cmd sub type 4739 */ 4740 uint8_t subtype; 4741 4742 uint8_t pad[2]; 4743 /** 4744 * config data with param1 and param2 4745 */ 4746 uint32_t param1; 4747 4748 uint32_t param2; 4749 }; 4750 4751 /** 4752 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4753 */ 4754 struct dmub_rb_cmd_replay_set_power_opt { 4755 /** 4756 * Command header. 4757 */ 4758 struct dmub_cmd_header header; 4759 /** 4760 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4761 */ 4762 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4763 }; 4764 4765 /** 4766 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4767 */ 4768 struct dmub_cmd_replay_set_coasting_vtotal_data { 4769 /** 4770 * 16-bit value dicated by driver that indicates the coasting vtotal. 4771 */ 4772 uint16_t coasting_vtotal; 4773 /** 4774 * REPLAY control version. 4775 */ 4776 uint8_t cmd_version; 4777 /** 4778 * Panel Instance. 4779 * Panel isntance to identify which replay_state to use 4780 * Currently the support is only for 0 or 1 4781 */ 4782 uint8_t panel_inst; 4783 /** 4784 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4785 */ 4786 uint16_t coasting_vtotal_high; 4787 /** 4788 * frame skip number. 4789 */ 4790 uint16_t frame_skip_number; 4791 }; 4792 4793 /** 4794 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4795 */ 4796 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4797 /** 4798 * Command header. 4799 */ 4800 struct dmub_cmd_header header; 4801 /** 4802 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4803 */ 4804 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4805 }; 4806 4807 /** 4808 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4809 */ 4810 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4811 /** 4812 * Command header. 4813 */ 4814 struct dmub_cmd_header header; 4815 /** 4816 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4817 */ 4818 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4819 /** 4820 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4821 */ 4822 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4823 }; 4824 4825 /** 4826 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4827 */ 4828 struct dmub_rb_cmd_replay_set_timing_sync { 4829 /** 4830 * Command header. 4831 */ 4832 struct dmub_cmd_header header; 4833 /** 4834 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4835 */ 4836 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4837 }; 4838 4839 /** 4840 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4841 */ 4842 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4843 /** 4844 * Command header. 4845 */ 4846 struct dmub_cmd_header header; 4847 /** 4848 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4849 */ 4850 struct dmub_cmd_replay_set_pseudo_vtotal data; 4851 }; 4852 4853 /** 4854 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4855 */ 4856 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4857 /** 4858 * Command header. 4859 */ 4860 struct dmub_cmd_header header; 4861 /** 4862 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4863 */ 4864 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4865 }; 4866 4867 /** 4868 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4869 */ 4870 struct dmub_rb_cmd_replay_set_general_cmd { 4871 /** 4872 * Command header. 4873 */ 4874 struct dmub_cmd_header header; 4875 /** 4876 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4877 */ 4878 struct dmub_cmd_replay_set_general_cmd_data data; 4879 }; 4880 4881 /** 4882 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4883 */ 4884 struct dmub_cmd_replay_frameupdate_timer_data { 4885 /** 4886 * Panel Instance. 4887 * Panel isntance to identify which replay_state to use 4888 * Currently the support is only for 0 or 1 4889 */ 4890 uint8_t panel_inst; 4891 /** 4892 * Replay Frameupdate Timer Enable or not 4893 */ 4894 uint8_t enable; 4895 /** 4896 * REPLAY force reflash frame update number 4897 */ 4898 uint16_t frameupdate_count; 4899 }; 4900 /** 4901 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4902 */ 4903 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4904 /** 4905 * Command header. 4906 */ 4907 struct dmub_cmd_header header; 4908 /** 4909 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4910 */ 4911 struct dmub_cmd_replay_frameupdate_timer_data data; 4912 }; 4913 4914 /** 4915 * Definition union of replay command set 4916 */ 4917 union dmub_replay_cmd_set { 4918 /** 4919 * Panel Instance. 4920 * Panel isntance to identify which replay_state to use 4921 * Currently the support is only for 0 or 1 4922 */ 4923 uint8_t panel_inst; 4924 /** 4925 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4926 */ 4927 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4928 /** 4929 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4930 */ 4931 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4932 /** 4933 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4934 */ 4935 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4936 /** 4937 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4938 */ 4939 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4940 /** 4941 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4942 */ 4943 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4944 }; 4945 4946 /** 4947 * SMART POWER OLED command sub-types. 4948 */ 4949 enum dmub_cmd_smart_power_oled_type { 4950 4951 /** 4952 * Enable/Disable SMART_POWER_OLED. 4953 */ 4954 DMUB_CMD__SMART_POWER_OLED_ENABLE = 1, 4955 /** 4956 * Get current MaxCLL value if SMART POWER OLED is enabled. 4957 */ 4958 DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2, 4959 }; 4960 4961 /** 4962 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 4963 */ 4964 struct dmub_rb_cmd_smart_power_oled_enable { 4965 /** 4966 * Command header. 4967 */ 4968 struct dmub_cmd_header header; 4969 4970 struct dmub_rb_cmd_smart_power_oled_enable_data data; 4971 }; 4972 4973 struct dmub_cmd_smart_power_oled_getmaxcll_input { 4974 uint8_t panel_inst; 4975 uint8_t pad[3]; 4976 }; 4977 4978 struct dmub_cmd_smart_power_oled_getmaxcll_output { 4979 uint16_t current_max_cll; 4980 uint8_t pad[2]; 4981 }; 4982 4983 /** 4984 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 4985 */ 4986 struct dmub_rb_cmd_smart_power_oled_getmaxcll { 4987 struct dmub_cmd_header header; /**< Command header */ 4988 /** 4989 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 4990 */ 4991 union dmub_cmd_smart_power_oled_getmaxcll_data { 4992 struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */ 4993 struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */ 4994 uint32_t output_raw; /**< Raw data output */ 4995 } data; 4996 }; 4997 4998 /** 4999 * Set of HW components that can be locked. 5000 * 5001 * Note: If updating with more HW components, fields 5002 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5003 */ 5004 union dmub_hw_lock_flags { 5005 /** 5006 * Set of HW components that can be locked. 5007 */ 5008 struct { 5009 /** 5010 * Lock/unlock OTG master update lock. 5011 */ 5012 uint8_t lock_pipe : 1; 5013 /** 5014 * Lock/unlock cursor. 5015 */ 5016 uint8_t lock_cursor : 1; 5017 /** 5018 * Lock/unlock global update lock. 5019 */ 5020 uint8_t lock_dig : 1; 5021 /** 5022 * Triple buffer lock requires additional hw programming to usual OTG master lock. 5023 */ 5024 uint8_t triple_buffer_lock : 1; 5025 } bits; 5026 5027 /** 5028 * Union for HW Lock flags. 5029 */ 5030 uint8_t u8All; 5031 }; 5032 5033 /** 5034 * Instances of HW to be locked. 5035 * 5036 * Note: If updating with more HW components, fields 5037 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5038 */ 5039 struct dmub_hw_lock_inst_flags { 5040 /** 5041 * OTG HW instance for OTG master update lock. 5042 */ 5043 uint8_t otg_inst; 5044 /** 5045 * OPP instance for cursor lock. 5046 */ 5047 uint8_t opp_inst; 5048 /** 5049 * OTG HW instance for global update lock. 5050 * TODO: Remove, and re-use otg_inst. 5051 */ 5052 uint8_t dig_inst; 5053 /** 5054 * Explicit pad to 4 byte boundary. 5055 */ 5056 uint8_t pad; 5057 }; 5058 5059 /** 5060 * Clients that can acquire the HW Lock Manager. 5061 * 5062 * Note: If updating with more clients, fields in 5063 * dmub_inbox0_cmd_lock_hw must be updated to match. 5064 */ 5065 enum hw_lock_client { 5066 /** 5067 * Driver is the client of HW Lock Manager. 5068 */ 5069 HW_LOCK_CLIENT_DRIVER = 0, 5070 /** 5071 * PSR SU is the client of HW Lock Manager. 5072 */ 5073 HW_LOCK_CLIENT_PSR_SU = 1, 5074 HW_LOCK_CLIENT_SUBVP = 3, 5075 /** 5076 * Replay is the client of HW Lock Manager. 5077 */ 5078 HW_LOCK_CLIENT_REPLAY = 4, 5079 HW_LOCK_CLIENT_FAMS2 = 5, 5080 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, 5081 /** 5082 * Invalid client. 5083 */ 5084 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 5085 }; 5086 5087 /** 5088 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5089 */ 5090 struct dmub_cmd_lock_hw_data { 5091 /** 5092 * Specifies the client accessing HW Lock Manager. 5093 */ 5094 enum hw_lock_client client; 5095 /** 5096 * HW instances to be locked. 5097 */ 5098 struct dmub_hw_lock_inst_flags inst_flags; 5099 /** 5100 * Which components to be locked. 5101 */ 5102 union dmub_hw_lock_flags hw_locks; 5103 /** 5104 * Specifies lock/unlock. 5105 */ 5106 uint8_t lock; 5107 /** 5108 * HW can be unlocked separately from releasing the HW Lock Mgr. 5109 * This flag is set if the client wishes to release the object. 5110 */ 5111 uint8_t should_release; 5112 /** 5113 * Explicit padding to 4 byte boundary. 5114 */ 5115 uint8_t pad; 5116 }; 5117 5118 /** 5119 * Definition of a DMUB_CMD__HW_LOCK command. 5120 * Command is used by driver and FW. 5121 */ 5122 struct dmub_rb_cmd_lock_hw { 5123 /** 5124 * Command header. 5125 */ 5126 struct dmub_cmd_header header; 5127 /** 5128 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5129 */ 5130 struct dmub_cmd_lock_hw_data lock_hw_data; 5131 }; 5132 5133 /** 5134 * ABM command sub-types. 5135 */ 5136 enum dmub_cmd_abm_type { 5137 /** 5138 * Initialize parameters for ABM algorithm. 5139 * Data is passed through an indirect buffer. 5140 */ 5141 DMUB_CMD__ABM_INIT_CONFIG = 0, 5142 /** 5143 * Set OTG and panel HW instance. 5144 */ 5145 DMUB_CMD__ABM_SET_PIPE = 1, 5146 /** 5147 * Set user requested backklight level. 5148 */ 5149 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 5150 /** 5151 * Set ABM operating/aggression level. 5152 */ 5153 DMUB_CMD__ABM_SET_LEVEL = 3, 5154 /** 5155 * Set ambient light level. 5156 */ 5157 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 5158 /** 5159 * Enable/disable fractional duty cycle for backlight PWM. 5160 */ 5161 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 5162 5163 /** 5164 * unregister vertical interrupt after steady state is reached 5165 */ 5166 DMUB_CMD__ABM_PAUSE = 6, 5167 5168 /** 5169 * Save and Restore ABM state. On save we save parameters, and 5170 * on restore we update state with passed in data. 5171 */ 5172 DMUB_CMD__ABM_SAVE_RESTORE = 7, 5173 5174 /** 5175 * Query ABM caps. 5176 */ 5177 DMUB_CMD__ABM_QUERY_CAPS = 8, 5178 5179 /** 5180 * Set ABM Events 5181 */ 5182 DMUB_CMD__ABM_SET_EVENT = 9, 5183 5184 /** 5185 * Get the current ACE curve. 5186 */ 5187 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 5188 5189 /** 5190 * Get current histogram data 5191 */ 5192 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 5193 }; 5194 5195 /** 5196 * LSDMA command sub-types. 5197 */ 5198 enum dmub_cmd_lsdma_type { 5199 /** 5200 * Initialize parameters for LSDMA. 5201 * Ring buffer is mapped to the ring buffer 5202 */ 5203 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 5204 /** 5205 * LSDMA copies data from source to destination linearly 5206 */ 5207 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 5208 /** 5209 * LSDMA copies data from source to destination linearly in sub window 5210 */ 5211 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 5212 /** 5213 * Send the tiled-to-tiled copy command 5214 */ 5215 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 5216 /** 5217 * Send the poll reg write command 5218 */ 5219 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 5220 /** 5221 * Send the pio copy command 5222 */ 5223 DMUB_CMD__LSDMA_PIO_COPY = 5, 5224 /** 5225 * Send the pio constfill command 5226 */ 5227 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 5228 }; 5229 5230 struct abm_ace_curve { 5231 /** 5232 * @offsets: ACE curve offsets. 5233 */ 5234 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5235 5236 /** 5237 * @thresholds: ACE curve thresholds. 5238 */ 5239 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5240 5241 /** 5242 * @slopes: ACE curve slopes. 5243 */ 5244 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5245 }; 5246 5247 struct fixed_pt_format { 5248 /** 5249 * @sign_bit: Indicates whether one bit is reserved for the sign. 5250 */ 5251 bool sign_bit; 5252 5253 /** 5254 * @num_int_bits: Number of bits used for integer part. 5255 */ 5256 uint8_t num_int_bits; 5257 5258 /** 5259 * @num_frac_bits: Number of bits used for fractional part. 5260 */ 5261 uint8_t num_frac_bits; 5262 5263 /** 5264 * @pad: Explicit padding to 4 byte boundary. 5265 */ 5266 uint8_t pad; 5267 }; 5268 5269 struct abm_caps { 5270 /** 5271 * @num_hg_bins: Number of histogram bins. 5272 */ 5273 uint8_t num_hg_bins; 5274 5275 /** 5276 * @num_ace_segments: Number of ACE curve segments. 5277 */ 5278 uint8_t num_ace_segments; 5279 5280 /** 5281 * @pad: Explicit padding to 4 byte boundary. 5282 */ 5283 uint8_t pad[2]; 5284 5285 /** 5286 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 5287 */ 5288 struct fixed_pt_format ace_thresholds_format; 5289 5290 /** 5291 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 5292 */ 5293 struct fixed_pt_format ace_offsets_format; 5294 5295 /** 5296 * @ace_slopes_format: Format of the ACE slopes. 5297 */ 5298 struct fixed_pt_format ace_slopes_format; 5299 }; 5300 5301 /** 5302 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 5303 * Requirements: 5304 * - Padded explicitly to 32-bit boundary. 5305 * - Must ensure this structure matches the one on driver-side, 5306 * otherwise it won't be aligned. 5307 */ 5308 struct abm_config_table { 5309 /** 5310 * Gamma curve thresholds, used for crgb conversion. 5311 */ 5312 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 5313 /** 5314 * Gamma curve offsets, used for crgb conversion. 5315 */ 5316 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 5317 /** 5318 * Gamma curve slopes, used for crgb conversion. 5319 */ 5320 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 5321 /** 5322 * Custom backlight curve thresholds. 5323 */ 5324 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 5325 /** 5326 * Custom backlight curve offsets. 5327 */ 5328 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 5329 /** 5330 * Ambient light thresholds. 5331 */ 5332 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 5333 /** 5334 * Minimum programmable backlight. 5335 */ 5336 uint16_t min_abm_backlight; // 122B 5337 /** 5338 * Minimum reduction values. 5339 */ 5340 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 5341 /** 5342 * Maximum reduction values. 5343 */ 5344 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 5345 /** 5346 * Bright positive gain. 5347 */ 5348 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 5349 /** 5350 * Dark negative gain. 5351 */ 5352 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 5353 /** 5354 * Hybrid factor. 5355 */ 5356 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 5357 /** 5358 * Contrast factor. 5359 */ 5360 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 5361 /** 5362 * Deviation gain. 5363 */ 5364 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 5365 /** 5366 * Minimum knee. 5367 */ 5368 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 5369 /** 5370 * Maximum knee. 5371 */ 5372 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 5373 /** 5374 * Unused. 5375 */ 5376 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 5377 /** 5378 * Explicit padding to 4 byte boundary. 5379 */ 5380 uint8_t pad3[3]; // 229B 5381 /** 5382 * Backlight ramp reduction. 5383 */ 5384 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 5385 /** 5386 * Backlight ramp start. 5387 */ 5388 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 5389 }; 5390 5391 /** 5392 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5393 */ 5394 struct dmub_cmd_abm_set_pipe_data { 5395 /** 5396 * OTG HW instance. 5397 */ 5398 uint8_t otg_inst; 5399 5400 /** 5401 * Panel Control HW instance. 5402 */ 5403 uint8_t panel_inst; 5404 5405 /** 5406 * Controls how ABM will interpret a set pipe or set level command. 5407 */ 5408 uint8_t set_pipe_option; 5409 5410 /** 5411 * Unused. 5412 * TODO: Remove. 5413 */ 5414 uint8_t ramping_boundary; 5415 5416 /** 5417 * PwrSeq HW Instance. 5418 */ 5419 uint8_t pwrseq_inst; 5420 5421 /** 5422 * Explicit padding to 4 byte boundary. 5423 */ 5424 uint8_t pad[3]; 5425 }; 5426 5427 /** 5428 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5429 */ 5430 struct dmub_rb_cmd_abm_set_pipe { 5431 /** 5432 * Command header. 5433 */ 5434 struct dmub_cmd_header header; 5435 5436 /** 5437 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5438 */ 5439 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5440 }; 5441 5442 /** 5443 * Type of backlight control method to be used by ABM module 5444 */ 5445 enum dmub_backlight_control_type { 5446 /** 5447 * PWM Backlight control 5448 */ 5449 DMU_BACKLIGHT_CONTROL_PWM = 0, 5450 /** 5451 * VESA Aux-based backlight control 5452 */ 5453 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5454 /** 5455 * AMD DPCD Aux-based backlight control 5456 */ 5457 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5458 }; 5459 5460 /** 5461 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5462 */ 5463 struct dmub_cmd_abm_set_backlight_data { 5464 /** 5465 * Number of frames to ramp to backlight user level. 5466 */ 5467 uint32_t frame_ramp; 5468 5469 /** 5470 * Requested backlight level from user. 5471 */ 5472 uint32_t backlight_user_level; 5473 5474 /** 5475 * ABM control version. 5476 */ 5477 uint8_t version; 5478 5479 /** 5480 * Panel Control HW instance mask. 5481 * Bit 0 is Panel Control HW instance 0. 5482 * Bit 1 is Panel Control HW instance 1. 5483 */ 5484 uint8_t panel_mask; 5485 5486 /** 5487 * AUX HW Instance. 5488 */ 5489 uint8_t aux_inst; 5490 5491 /** 5492 * Explicit padding to 4 byte boundary. 5493 */ 5494 uint8_t pad[1]; 5495 5496 /** 5497 * Backlight control type. 5498 * Value 0 is PWM backlight control. 5499 * Value 1 is VAUX backlight control. 5500 * Value 2 is AMD DPCD AUX backlight control. 5501 */ 5502 enum dmub_backlight_control_type backlight_control_type; 5503 5504 /** 5505 * Minimum luminance in nits. 5506 */ 5507 uint32_t min_luminance; 5508 5509 /** 5510 * Maximum luminance in nits. 5511 */ 5512 uint32_t max_luminance; 5513 5514 /** 5515 * Minimum backlight in pwm. 5516 */ 5517 uint32_t min_backlight_pwm; 5518 5519 /** 5520 * Maximum backlight in pwm. 5521 */ 5522 uint32_t max_backlight_pwm; 5523 }; 5524 5525 /** 5526 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5527 */ 5528 struct dmub_rb_cmd_abm_set_backlight { 5529 /** 5530 * Command header. 5531 */ 5532 struct dmub_cmd_header header; 5533 5534 /** 5535 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5536 */ 5537 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5538 }; 5539 5540 /** 5541 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5542 */ 5543 struct dmub_cmd_abm_set_level_data { 5544 /** 5545 * Set current ABM operating/aggression level. 5546 */ 5547 uint32_t level; 5548 5549 /** 5550 * ABM control version. 5551 */ 5552 uint8_t version; 5553 5554 /** 5555 * Panel Control HW instance mask. 5556 * Bit 0 is Panel Control HW instance 0. 5557 * Bit 1 is Panel Control HW instance 1. 5558 */ 5559 uint8_t panel_mask; 5560 5561 /** 5562 * Explicit padding to 4 byte boundary. 5563 */ 5564 uint8_t pad[2]; 5565 }; 5566 5567 /** 5568 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5569 */ 5570 struct dmub_rb_cmd_abm_set_level { 5571 /** 5572 * Command header. 5573 */ 5574 struct dmub_cmd_header header; 5575 5576 /** 5577 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5578 */ 5579 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5580 }; 5581 5582 /** 5583 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5584 */ 5585 struct dmub_cmd_abm_set_ambient_level_data { 5586 /** 5587 * Ambient light sensor reading from OS. 5588 */ 5589 uint32_t ambient_lux; 5590 5591 /** 5592 * ABM control version. 5593 */ 5594 uint8_t version; 5595 5596 /** 5597 * Panel Control HW instance mask. 5598 * Bit 0 is Panel Control HW instance 0. 5599 * Bit 1 is Panel Control HW instance 1. 5600 */ 5601 uint8_t panel_mask; 5602 5603 /** 5604 * Explicit padding to 4 byte boundary. 5605 */ 5606 uint8_t pad[2]; 5607 }; 5608 5609 /** 5610 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5611 */ 5612 struct dmub_rb_cmd_abm_set_ambient_level { 5613 /** 5614 * Command header. 5615 */ 5616 struct dmub_cmd_header header; 5617 5618 /** 5619 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5620 */ 5621 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5622 }; 5623 5624 /** 5625 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5626 */ 5627 struct dmub_cmd_abm_set_pwm_frac_data { 5628 /** 5629 * Enable/disable fractional duty cycle for backlight PWM. 5630 * TODO: Convert to uint8_t. 5631 */ 5632 uint32_t fractional_pwm; 5633 5634 /** 5635 * ABM control version. 5636 */ 5637 uint8_t version; 5638 5639 /** 5640 * Panel Control HW instance mask. 5641 * Bit 0 is Panel Control HW instance 0. 5642 * Bit 1 is Panel Control HW instance 1. 5643 */ 5644 uint8_t panel_mask; 5645 5646 /** 5647 * Explicit padding to 4 byte boundary. 5648 */ 5649 uint8_t pad[2]; 5650 }; 5651 5652 /** 5653 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5654 */ 5655 struct dmub_rb_cmd_abm_set_pwm_frac { 5656 /** 5657 * Command header. 5658 */ 5659 struct dmub_cmd_header header; 5660 5661 /** 5662 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5663 */ 5664 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5665 }; 5666 5667 /** 5668 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5669 */ 5670 struct dmub_cmd_abm_init_config_data { 5671 /** 5672 * Location of indirect buffer used to pass init data to ABM. 5673 */ 5674 union dmub_addr src; 5675 5676 /** 5677 * Indirect buffer length. 5678 */ 5679 uint16_t bytes; 5680 5681 5682 /** 5683 * ABM control version. 5684 */ 5685 uint8_t version; 5686 5687 /** 5688 * Panel Control HW instance mask. 5689 * Bit 0 is Panel Control HW instance 0. 5690 * Bit 1 is Panel Control HW instance 1. 5691 */ 5692 uint8_t panel_mask; 5693 5694 /** 5695 * Explicit padding to 4 byte boundary. 5696 */ 5697 uint8_t pad[2]; 5698 }; 5699 5700 /** 5701 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5702 */ 5703 struct dmub_rb_cmd_abm_init_config { 5704 /** 5705 * Command header. 5706 */ 5707 struct dmub_cmd_header header; 5708 5709 /** 5710 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5711 */ 5712 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5713 }; 5714 5715 /** 5716 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5717 */ 5718 5719 struct dmub_cmd_abm_pause_data { 5720 5721 /** 5722 * Panel Control HW instance mask. 5723 * Bit 0 is Panel Control HW instance 0. 5724 * Bit 1 is Panel Control HW instance 1. 5725 */ 5726 uint8_t panel_mask; 5727 5728 /** 5729 * OTG hw instance 5730 */ 5731 uint8_t otg_inst; 5732 5733 /** 5734 * Enable or disable ABM pause 5735 */ 5736 uint8_t enable; 5737 5738 /** 5739 * Explicit padding to 4 byte boundary. 5740 */ 5741 uint8_t pad[1]; 5742 }; 5743 5744 /** 5745 * Definition of a DMUB_CMD__ABM_PAUSE command. 5746 */ 5747 struct dmub_rb_cmd_abm_pause { 5748 /** 5749 * Command header. 5750 */ 5751 struct dmub_cmd_header header; 5752 5753 /** 5754 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5755 */ 5756 struct dmub_cmd_abm_pause_data abm_pause_data; 5757 }; 5758 5759 /** 5760 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5761 */ 5762 struct dmub_cmd_abm_query_caps_in { 5763 /** 5764 * Panel instance. 5765 */ 5766 uint8_t panel_inst; 5767 5768 /** 5769 * Explicit padding to 4 byte boundary. 5770 */ 5771 uint8_t pad[3]; 5772 }; 5773 5774 /** 5775 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5776 */ 5777 struct dmub_cmd_abm_query_caps_out { 5778 /** 5779 * SW Algorithm caps. 5780 */ 5781 struct abm_caps sw_caps; 5782 5783 /** 5784 * ABM HW caps. 5785 */ 5786 struct abm_caps hw_caps; 5787 }; 5788 5789 /** 5790 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5791 */ 5792 struct dmub_rb_cmd_abm_query_caps { 5793 /** 5794 * Command header. 5795 */ 5796 struct dmub_cmd_header header; 5797 5798 /** 5799 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5800 */ 5801 union { 5802 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5803 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5804 } data; 5805 }; 5806 5807 /** 5808 * enum dmub_abm_ace_curve_type - ACE curve type. 5809 */ 5810 enum dmub_abm_ace_curve_type { 5811 /** 5812 * ACE curve as defined by the SW layer. 5813 */ 5814 ABM_ACE_CURVE_TYPE__SW = 0, 5815 /** 5816 * ACE curve as defined by the SW to HW translation interface layer. 5817 */ 5818 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5819 }; 5820 5821 /** 5822 * enum dmub_abm_histogram_type - Histogram type. 5823 */ 5824 enum dmub_abm_histogram_type { 5825 /** 5826 * ACE curve as defined by the SW layer. 5827 */ 5828 ABM_HISTOGRAM_TYPE__SW = 0, 5829 /** 5830 * ACE curve as defined by the SW to HW translation interface layer. 5831 */ 5832 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5833 }; 5834 5835 /** 5836 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5837 */ 5838 struct dmub_rb_cmd_abm_get_ace_curve { 5839 /** 5840 * Command header. 5841 */ 5842 struct dmub_cmd_header header; 5843 5844 /** 5845 * Address where ACE curve should be copied. 5846 */ 5847 union dmub_addr dest; 5848 5849 /** 5850 * Type of ACE curve being queried. 5851 */ 5852 enum dmub_abm_ace_curve_type ace_type; 5853 5854 /** 5855 * Indirect buffer length. 5856 */ 5857 uint16_t bytes; 5858 5859 /** 5860 * eDP panel instance. 5861 */ 5862 uint8_t panel_inst; 5863 5864 /** 5865 * Explicit padding to 4 byte boundary. 5866 */ 5867 uint8_t pad; 5868 }; 5869 5870 /** 5871 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5872 */ 5873 struct dmub_rb_cmd_abm_get_histogram { 5874 /** 5875 * Command header. 5876 */ 5877 struct dmub_cmd_header header; 5878 5879 /** 5880 * Address where Histogram should be copied. 5881 */ 5882 union dmub_addr dest; 5883 5884 /** 5885 * Type of Histogram being queried. 5886 */ 5887 enum dmub_abm_histogram_type histogram_type; 5888 5889 /** 5890 * Indirect buffer length. 5891 */ 5892 uint16_t bytes; 5893 5894 /** 5895 * eDP panel instance. 5896 */ 5897 uint8_t panel_inst; 5898 5899 /** 5900 * Explicit padding to 4 byte boundary. 5901 */ 5902 uint8_t pad; 5903 }; 5904 5905 /** 5906 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5907 */ 5908 struct dmub_rb_cmd_abm_save_restore { 5909 /** 5910 * Command header. 5911 */ 5912 struct dmub_cmd_header header; 5913 5914 /** 5915 * OTG hw instance 5916 */ 5917 uint8_t otg_inst; 5918 5919 /** 5920 * Enable or disable ABM pause 5921 */ 5922 uint8_t freeze; 5923 5924 /** 5925 * Explicit padding to 4 byte boundary. 5926 */ 5927 uint8_t debug; 5928 5929 /** 5930 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5931 */ 5932 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5933 }; 5934 5935 /** 5936 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5937 */ 5938 5939 struct dmub_cmd_abm_set_event_data { 5940 5941 /** 5942 * VB Scaling Init. Strength Mapping 5943 * Byte 0: 0~255 for VB level 0 5944 * Byte 1: 0~255 for VB level 1 5945 * Byte 2: 0~255 for VB level 2 5946 * Byte 3: 0~255 for VB level 3 5947 */ 5948 uint32_t vb_scaling_strength_mapping; 5949 /** 5950 * VariBright Scaling Enable 5951 */ 5952 uint8_t vb_scaling_enable; 5953 /** 5954 * Panel Control HW instance mask. 5955 * Bit 0 is Panel Control HW instance 0. 5956 * Bit 1 is Panel Control HW instance 1. 5957 */ 5958 uint8_t panel_mask; 5959 5960 /** 5961 * Explicit padding to 4 byte boundary. 5962 */ 5963 uint8_t pad[2]; 5964 }; 5965 5966 /** 5967 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5968 */ 5969 struct dmub_rb_cmd_abm_set_event { 5970 /** 5971 * Command header. 5972 */ 5973 struct dmub_cmd_header header; 5974 5975 /** 5976 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5977 */ 5978 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5979 }; 5980 5981 /** 5982 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5983 */ 5984 struct dmub_cmd_query_feature_caps_data { 5985 /** 5986 * DMUB feature capabilities. 5987 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5988 */ 5989 struct dmub_feature_caps feature_caps; 5990 }; 5991 5992 /** 5993 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5994 */ 5995 struct dmub_rb_cmd_query_feature_caps { 5996 /** 5997 * Command header. 5998 */ 5999 struct dmub_cmd_header header; 6000 /** 6001 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 6002 */ 6003 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 6004 }; 6005 6006 /** 6007 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6008 */ 6009 struct dmub_cmd_visual_confirm_color_data { 6010 /** 6011 * DMUB visual confirm color 6012 */ 6013 struct dmub_visual_confirm_color visual_confirm_color; 6014 }; 6015 6016 /** 6017 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6018 */ 6019 struct dmub_rb_cmd_get_visual_confirm_color { 6020 /** 6021 * Command header. 6022 */ 6023 struct dmub_cmd_header header; 6024 /** 6025 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6026 */ 6027 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 6028 }; 6029 6030 /** 6031 * enum dmub_cmd_panel_cntl_type - Panel control command. 6032 */ 6033 enum dmub_cmd_panel_cntl_type { 6034 /** 6035 * Initializes embedded panel hardware blocks. 6036 */ 6037 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 6038 /** 6039 * Queries backlight info for the embedded panel. 6040 */ 6041 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 6042 /** 6043 * Sets the PWM Freq as per user's requirement. 6044 */ 6045 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 6046 }; 6047 6048 /** 6049 * struct dmub_cmd_panel_cntl_data - Panel control data. 6050 */ 6051 struct dmub_cmd_panel_cntl_data { 6052 uint32_t pwrseq_inst; /**< pwrseq instance */ 6053 uint32_t current_backlight; /* in/out */ 6054 uint32_t bl_pwm_cntl; /* in/out */ 6055 uint32_t bl_pwm_period_cntl; /* in/out */ 6056 uint32_t bl_pwm_ref_div1; /* in/out */ 6057 uint8_t is_backlight_on : 1; /* in/out */ 6058 uint8_t is_powered_on : 1; /* in/out */ 6059 uint8_t padding[3]; 6060 uint32_t bl_pwm_ref_div2; /* in/out */ 6061 uint8_t reserved[4]; 6062 }; 6063 6064 /** 6065 * struct dmub_rb_cmd_panel_cntl - Panel control command. 6066 */ 6067 struct dmub_rb_cmd_panel_cntl { 6068 struct dmub_cmd_header header; /**< header */ 6069 struct dmub_cmd_panel_cntl_data data; /**< payload */ 6070 }; 6071 6072 struct dmub_optc_state { 6073 uint32_t v_total_max; 6074 uint32_t v_total_min; 6075 uint32_t tg_inst; 6076 }; 6077 6078 struct dmub_rb_cmd_drr_update { 6079 struct dmub_cmd_header header; 6080 struct dmub_optc_state dmub_optc_state_req; 6081 }; 6082 6083 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 6084 uint32_t pix_clk_100hz; 6085 uint8_t max_ramp_step; 6086 uint8_t pipes; 6087 uint8_t min_refresh_in_hz; 6088 uint8_t pipe_count; 6089 uint8_t pipe_index[4]; 6090 }; 6091 6092 struct dmub_cmd_fw_assisted_mclk_switch_config { 6093 uint8_t fams_enabled; 6094 uint8_t visual_confirm_enabled; 6095 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 6096 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 6097 }; 6098 6099 struct dmub_rb_cmd_fw_assisted_mclk_switch { 6100 struct dmub_cmd_header header; 6101 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 6102 }; 6103 6104 /** 6105 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6106 */ 6107 struct dmub_cmd_lvtma_control_data { 6108 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 6109 uint8_t bypass_panel_control_wait; 6110 uint8_t reserved_0[2]; /**< For future use */ 6111 uint8_t pwrseq_inst; /**< LVTMA control instance */ 6112 uint8_t reserved_1[3]; /**< For future use */ 6113 }; 6114 6115 /** 6116 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6117 */ 6118 struct dmub_rb_cmd_lvtma_control { 6119 /** 6120 * Command header. 6121 */ 6122 struct dmub_cmd_header header; 6123 /** 6124 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6125 */ 6126 struct dmub_cmd_lvtma_control_data data; 6127 }; 6128 6129 /** 6130 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6131 */ 6132 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 6133 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6134 uint8_t is_usb; /**< is phy is usb */ 6135 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 6136 uint8_t is_dp4; /**< is dp in 4 lane */ 6137 }; 6138 6139 /** 6140 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6141 */ 6142 struct dmub_rb_cmd_transmitter_query_dp_alt { 6143 struct dmub_cmd_header header; /**< header */ 6144 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 6145 }; 6146 6147 struct phy_test_mode { 6148 uint8_t mode; 6149 uint8_t pat0; 6150 uint8_t pad[2]; 6151 }; 6152 6153 /** 6154 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6155 */ 6156 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 6157 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6158 uint8_t mode; /**< HDMI/DP/DP2 etc */ 6159 uint8_t lane_num; /**< Number of lanes */ 6160 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 6161 struct phy_test_mode test_mode; 6162 enum dmub_phy_fsm_state state; 6163 uint32_t status; 6164 uint8_t pad; 6165 }; 6166 6167 /** 6168 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6169 */ 6170 struct dmub_rb_cmd_transmitter_set_phy_fsm { 6171 struct dmub_cmd_header header; /**< header */ 6172 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 6173 }; 6174 6175 /** 6176 * Maximum number of bytes a chunk sent to DMUB for parsing 6177 */ 6178 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 6179 6180 /** 6181 * Represent a chunk of CEA blocks sent to DMUB for parsing 6182 */ 6183 struct dmub_cmd_send_edid_cea { 6184 uint16_t offset; /**< offset into the CEA block */ 6185 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 6186 uint16_t cea_total_length; /**< total length of the CEA block */ 6187 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 6188 uint8_t pad[3]; /**< padding and for future expansion */ 6189 }; 6190 6191 /** 6192 * Result of VSDB parsing from CEA block 6193 */ 6194 struct dmub_cmd_edid_cea_amd_vsdb { 6195 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 6196 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 6197 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 6198 uint16_t min_frame_rate; /**< Maximum frame rate */ 6199 uint16_t max_frame_rate; /**< Minimum frame rate */ 6200 }; 6201 6202 /** 6203 * Result of sending a CEA chunk 6204 */ 6205 struct dmub_cmd_edid_cea_ack { 6206 uint16_t offset; /**< offset of the chunk into the CEA block */ 6207 uint8_t success; /**< 1 if this sending of chunk succeeded */ 6208 uint8_t pad; /**< padding and for future expansion */ 6209 }; 6210 6211 /** 6212 * Specify whether the result is an ACK/NACK or the parsing has finished 6213 */ 6214 enum dmub_cmd_edid_cea_reply_type { 6215 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 6216 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 6217 }; 6218 6219 /** 6220 * Definition of a DMUB_CMD__EDID_CEA command. 6221 */ 6222 struct dmub_rb_cmd_edid_cea { 6223 struct dmub_cmd_header header; /**< Command header */ 6224 union dmub_cmd_edid_cea_data { 6225 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 6226 struct dmub_cmd_edid_cea_output { /**< output with results */ 6227 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 6228 union { 6229 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 6230 struct dmub_cmd_edid_cea_ack ack; 6231 }; 6232 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 6233 } data; /**< Command data */ 6234 6235 }; 6236 6237 /** 6238 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 6239 */ 6240 struct dmub_cmd_cable_id_input { 6241 uint8_t phy_inst; /**< phy inst for cable id data */ 6242 }; 6243 6244 /** 6245 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 6246 */ 6247 struct dmub_cmd_cable_id_output { 6248 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 6249 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 6250 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 6251 uint8_t RESERVED :2; /**< reserved means not defined */ 6252 }; 6253 6254 /** 6255 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 6256 */ 6257 struct dmub_rb_cmd_get_usbc_cable_id { 6258 struct dmub_cmd_header header; /**< Command header */ 6259 /** 6260 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 6261 */ 6262 union dmub_cmd_cable_id_data { 6263 struct dmub_cmd_cable_id_input input; /**< Input */ 6264 struct dmub_cmd_cable_id_output output; /**< Output */ 6265 uint8_t output_raw; /**< Raw data output */ 6266 } data; 6267 }; 6268 6269 enum dmub_cmd_fused_io_sub_type { 6270 DMUB_CMD__FUSED_IO_EXECUTE = 0, 6271 DMUB_CMD__FUSED_IO_ABORT = 1, 6272 }; 6273 6274 enum dmub_cmd_fused_request_type { 6275 FUSED_REQUEST_READ, 6276 FUSED_REQUEST_WRITE, 6277 FUSED_REQUEST_POLL, 6278 }; 6279 6280 enum dmub_cmd_fused_request_status { 6281 FUSED_REQUEST_STATUS_SUCCESS, 6282 FUSED_REQUEST_STATUS_BEGIN, 6283 FUSED_REQUEST_STATUS_SUBMIT, 6284 FUSED_REQUEST_STATUS_REPLY, 6285 FUSED_REQUEST_STATUS_POLL, 6286 FUSED_REQUEST_STATUS_ABORTED, 6287 FUSED_REQUEST_STATUS_FAILED = 0x80, 6288 FUSED_REQUEST_STATUS_INVALID, 6289 FUSED_REQUEST_STATUS_BUSY, 6290 FUSED_REQUEST_STATUS_TIMEOUT, 6291 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 6292 }; 6293 6294 struct dmub_cmd_fused_request { 6295 uint8_t status; 6296 uint8_t type : 2; 6297 uint8_t _reserved0 : 3; 6298 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 6299 uint8_t identifier; 6300 uint8_t _reserved1; 6301 uint32_t timeout_us; 6302 union dmub_cmd_fused_request_location { 6303 struct dmub_cmd_fused_request_location_i2c { 6304 uint8_t is_aux : 1; // False 6305 uint8_t ddc_line : 3; 6306 uint8_t over_aux : 1; 6307 uint8_t _reserved0 : 3; 6308 uint8_t address; 6309 uint8_t offset; 6310 uint8_t length; 6311 } i2c; 6312 struct dmub_cmd_fused_request_location_aux { 6313 uint32_t is_aux : 1; // True 6314 uint32_t ddc_line : 3; 6315 uint32_t address : 20; 6316 uint32_t length : 8; // Automatically split into 16B transactions 6317 } aux; 6318 } u; 6319 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 6320 }; 6321 6322 struct dmub_rb_cmd_fused_io { 6323 struct dmub_cmd_header header; 6324 struct dmub_cmd_fused_request request; 6325 }; 6326 6327 /** 6328 * Command type of a DMUB_CMD__SECURE_DISPLAY command 6329 */ 6330 enum dmub_cmd_secure_display_type { 6331 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 6332 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 6333 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 6334 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 6335 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 6336 }; 6337 6338 #define MAX_ROI_NUM 2 6339 6340 struct dmub_cmd_roi_info { 6341 uint16_t x_start; 6342 uint16_t x_end; 6343 uint16_t y_start; 6344 uint16_t y_end; 6345 uint8_t otg_id; 6346 uint8_t phy_id; 6347 }; 6348 6349 struct dmub_cmd_roi_window_ctl { 6350 uint16_t x_start; 6351 uint16_t x_end; 6352 uint16_t y_start; 6353 uint16_t y_end; 6354 bool enable; 6355 }; 6356 6357 struct dmub_cmd_roi_ctl_info { 6358 uint8_t otg_id; 6359 uint8_t phy_id; 6360 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 6361 }; 6362 6363 /** 6364 * Definition of a DMUB_CMD__SECURE_DISPLAY command 6365 */ 6366 struct dmub_rb_cmd_secure_display { 6367 struct dmub_cmd_header header; 6368 /** 6369 * Data passed from driver to dmub firmware. 6370 */ 6371 struct dmub_cmd_roi_info roi_info; 6372 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 6373 }; 6374 6375 /** 6376 * Command type of a DMUB_CMD__PSP command 6377 */ 6378 enum dmub_cmd_psp_type { 6379 DMUB_CMD__PSP_ASSR_ENABLE = 0 6380 }; 6381 6382 /** 6383 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 6384 */ 6385 struct dmub_cmd_assr_enable_data { 6386 /** 6387 * ASSR enable or disable. 6388 */ 6389 uint8_t enable; 6390 /** 6391 * PHY port type. 6392 * Indicates eDP / non-eDP port type 6393 */ 6394 uint8_t phy_port_type; 6395 /** 6396 * PHY port ID. 6397 */ 6398 uint8_t phy_port_id; 6399 /** 6400 * Link encoder index. 6401 */ 6402 uint8_t link_enc_index; 6403 /** 6404 * HPO mode. 6405 */ 6406 uint8_t hpo_mode; 6407 6408 /** 6409 * Reserved field. 6410 */ 6411 uint8_t reserved[7]; 6412 }; 6413 6414 /** 6415 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6416 */ 6417 struct dmub_rb_cmd_assr_enable { 6418 /** 6419 * Command header. 6420 */ 6421 struct dmub_cmd_header header; 6422 6423 /** 6424 * Assr data. 6425 */ 6426 struct dmub_cmd_assr_enable_data assr_data; 6427 6428 /** 6429 * Reserved field. 6430 */ 6431 uint32_t reserved[3]; 6432 }; 6433 6434 /** 6435 * Current definition of "ips_mode" from driver 6436 */ 6437 enum ips_residency_mode { 6438 IPS_RESIDENCY__IPS1_MAX, 6439 IPS_RESIDENCY__IPS2, 6440 IPS_RESIDENCY__IPS1_RCG, 6441 IPS_RESIDENCY__IPS1_ONO2_ON, 6442 IPS_RESIDENCY__IPS1_Z8_RETENTION, 6443 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 6444 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 6445 }; 6446 6447 #define NUM_IPS_HISTOGRAM_BUCKETS 16 6448 6449 /** 6450 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 6451 */ 6452 struct dmub_ips_residency_info { 6453 uint32_t residency_millipercent; 6454 uint32_t entry_counter; 6455 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 6456 uint64_t total_time_us; 6457 uint64_t total_inactive_time_us; 6458 uint32_t ono_pg_state_at_collection; 6459 uint32_t ono_pg_state_last_seen_in_ips; 6460 }; 6461 6462 /** 6463 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 6464 */ 6465 struct dmub_cmd_ips_residency_cntl_data { 6466 uint8_t panel_inst; 6467 uint8_t start_measurement; 6468 uint8_t padding[2]; // align to 4-byte boundary 6469 }; 6470 6471 struct dmub_rb_cmd_ips_residency_cntl { 6472 struct dmub_cmd_header header; 6473 struct dmub_cmd_ips_residency_cntl_data cntl_data; 6474 }; 6475 6476 /** 6477 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 6478 */ 6479 struct dmub_cmd_ips_query_residency_info_data { 6480 union dmub_addr dest; 6481 uint32_t size; 6482 uint32_t ips_mode; 6483 uint8_t panel_inst; 6484 uint8_t padding[3]; // align to 4-byte boundary 6485 }; 6486 6487 struct dmub_rb_cmd_ips_query_residency_info { 6488 struct dmub_cmd_header header; 6489 struct dmub_cmd_ips_query_residency_info_data info_data; 6490 }; 6491 6492 /** 6493 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. 6494 */ 6495 struct dmub_cmd_cursor_offload_init_data { 6496 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ 6497 uint32_t state_size; /**< State size for dmub_cursor_offload */ 6498 }; 6499 6500 /** 6501 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. 6502 */ 6503 struct dmub_rb_cmd_cursor_offload_init { 6504 struct dmub_cmd_header header; 6505 struct dmub_cmd_cursor_offload_init_data init_data; 6506 }; 6507 6508 /** 6509 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. 6510 */ 6511 struct dmub_cmd_cursor_offload_stream_data { 6512 uint32_t otg_inst: 4; /**< OTG instance to control */ 6513 uint32_t reserved: 28; /**< Reserved for future use */ 6514 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ 6515 uint32_t v_total_max; /**< OTG v_total_max */ 6516 }; 6517 6518 /** 6519 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. 6520 */ 6521 struct dmub_rb_cmd_cursor_offload_stream_cntl { 6522 struct dmub_cmd_header header; 6523 struct dmub_cmd_cursor_offload_stream_data data; 6524 }; 6525 6526 /** 6527 * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command. 6528 */ 6529 struct dmub_cmd_pr_enable_data { 6530 /** 6531 * Panel Replay enable or disable. 6532 */ 6533 uint8_t enable; 6534 /** 6535 * Panel Instance. 6536 * Panel isntance to identify which replay_state to use 6537 * Currently the support is only for 0 or 1 6538 */ 6539 uint8_t panel_inst; 6540 /** 6541 * Phy state to enter. 6542 * Values to use are defined in dmub_phy_fsm_state 6543 */ 6544 uint8_t phy_fsm_state; 6545 /** 6546 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 6547 * Set this using enum phy_link_rate. 6548 * This does not support HDMI/DP2 for now. 6549 */ 6550 uint8_t phy_rate; 6551 /** 6552 * @hpo_stream_enc_inst: HPO stream encoder instance 6553 */ 6554 uint8_t hpo_stream_enc_inst; 6555 /** 6556 * @hpo_link_enc_inst: HPO link encoder instance 6557 */ 6558 uint8_t hpo_link_enc_inst; 6559 /** 6560 * @pad: Align structure to 4 byte boundary. 6561 */ 6562 uint8_t pad[2]; 6563 }; 6564 6565 /** 6566 * Definition of a DMUB_CMD__PR_ENABLE command. 6567 * Panel Replay enable/disable is controlled using action in data. 6568 */ 6569 struct dmub_rb_cmd_pr_enable { 6570 /** 6571 * Command header. 6572 */ 6573 struct dmub_cmd_header header; 6574 6575 struct dmub_cmd_pr_enable_data data; 6576 }; 6577 6578 /** 6579 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 6580 */ 6581 struct dmub_cmd_pr_copy_settings_data { 6582 /** 6583 * Flags that can be set by driver to change some replay behaviour. 6584 */ 6585 union pr_debug_flags debug; 6586 6587 /** 6588 * @flags: Flags used to determine feature functionality. 6589 */ 6590 union pr_hw_flags flags; 6591 6592 /** 6593 * DPP HW instance. 6594 */ 6595 uint8_t dpp_inst; 6596 /** 6597 * OTG HW instance. 6598 */ 6599 uint8_t otg_inst; 6600 /** 6601 * DIG FE HW instance. 6602 */ 6603 uint8_t digfe_inst; 6604 /** 6605 * DIG BE HW instance. 6606 */ 6607 uint8_t digbe_inst; 6608 /** 6609 * AUX HW instance. 6610 */ 6611 uint8_t aux_inst; 6612 /** 6613 * Panel Instance. 6614 * Panel isntance to identify which psr_state to use 6615 * Currently the support is only for 0 or 1 6616 */ 6617 uint8_t panel_inst; 6618 /** 6619 * PHY instance. 6620 */ 6621 uint8_t dpphy_inst; 6622 /** 6623 * Determines if SMU optimzations are enabled/disabled. 6624 */ 6625 uint8_t smu_optimizations_en; 6626 /** 6627 * Length of each horizontal line in ns. 6628 */ 6629 uint32_t line_time_in_ns; 6630 /* 6631 * Use FSFT afftet pixel clk 6632 */ 6633 uint32_t pix_clk_100hz; 6634 /* 6635 * Use Original pixel clock 6636 */ 6637 uint32_t sink_pix_clk_100hz; 6638 /** 6639 * Use for AUX-less ALPM LFPS wake operation 6640 */ 6641 struct dmub_alpm_auxless_data auxless_alpm_data; 6642 /** 6643 * DSC Slice height. 6644 */ 6645 uint16_t dsc_slice_height; 6646 /* 6647 * Use FSM state for Replay power up/down 6648 */ 6649 uint8_t use_phy_fsm; 6650 /** 6651 * @hpo_stream_enc_inst: HPO stream encoder instance 6652 */ 6653 uint8_t hpo_stream_enc_inst; 6654 /** 6655 * @hpo_link_enc_inst: HPO link encoder instance 6656 */ 6657 uint8_t hpo_link_enc_inst; 6658 /* 6659 * Selective Update granularity needed. 6660 */ 6661 uint8_t su_granularity_needed; 6662 /* 6663 * Horizontal granularity for Selective Update. 6664 */ 6665 uint16_t su_x_granularity; 6666 /* 6667 * Extended caps of vertical granularity for Selective Update. 6668 */ 6669 uint16_t su_y_granularity_extended_caps; 6670 /* 6671 * Vertical granularity for Selective Update. 6672 */ 6673 uint8_t su_y_granularity; 6674 /** 6675 * @main_link_activity_option: Indicates main link activity option selected 6676 */ 6677 uint8_t main_link_activity_option; 6678 }; 6679 6680 /** 6681 * Definition of a DMUB_CMD__PR_COPY_SETTINGS command. 6682 */ 6683 struct dmub_rb_cmd_pr_copy_settings { 6684 /** 6685 * Command header. 6686 */ 6687 struct dmub_cmd_header header; 6688 /** 6689 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 6690 */ 6691 struct dmub_cmd_pr_copy_settings_data data; 6692 }; 6693 6694 struct dmub_cmd_pr_update_state_data { 6695 /** 6696 * Panel Instance. 6697 * Panel isntance to identify which psr_state to use 6698 * Currently the support is only for 0 or 1 6699 */ 6700 uint8_t panel_inst; 6701 6702 uint8_t pad[3]; // align to 4-byte boundary 6703 /* 6704 * Update flags to control the update behavior. 6705 */ 6706 uint32_t update_flag; 6707 /** 6708 * state/data to set. 6709 */ 6710 uint32_t coasting_vtotal; 6711 uint32_t sync_mode; 6712 }; 6713 6714 struct dmub_cmd_pr_general_cmd_data { 6715 /** 6716 * Panel Instance. 6717 * Panel isntance to identify which psr_state to use 6718 * Currently the support is only for 0 or 1 6719 */ 6720 uint8_t panel_inst; 6721 /** 6722 * subtype: PR general cmd sub type 6723 */ 6724 uint8_t subtype; 6725 6726 uint8_t pad[2]; 6727 /** 6728 * config data by different subtypes 6729 */ 6730 union { 6731 uint32_t u32All; 6732 } data; 6733 }; 6734 6735 /** 6736 * Definition of a DMUB_CMD__PR_UPDATE_STATE command. 6737 */ 6738 struct dmub_rb_cmd_pr_update_state { 6739 /** 6740 * Command header. 6741 */ 6742 struct dmub_cmd_header header; 6743 /** 6744 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command. 6745 */ 6746 struct dmub_cmd_pr_update_state_data data; 6747 }; 6748 6749 /** 6750 * Definition of a DMUB_CMD__PR_GENERAL_CMD command. 6751 */ 6752 struct dmub_rb_cmd_pr_general_cmd { 6753 /** 6754 * Command header. 6755 */ 6756 struct dmub_cmd_header header; 6757 /** 6758 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command. 6759 */ 6760 struct dmub_cmd_pr_general_cmd_data data; 6761 }; 6762 6763 /** 6764 * union dmub_rb_cmd - DMUB inbox command. 6765 */ 6766 union dmub_rb_cmd { 6767 /** 6768 * Elements shared with all commands. 6769 */ 6770 struct dmub_rb_cmd_common cmd_common; 6771 /** 6772 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 6773 */ 6774 struct dmub_rb_cmd_read_modify_write read_modify_write; 6775 /** 6776 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 6777 */ 6778 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 6779 /** 6780 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 6781 */ 6782 struct dmub_rb_cmd_burst_write burst_write; 6783 /** 6784 * Definition of a DMUB_CMD__REG_REG_WAIT command. 6785 */ 6786 struct dmub_rb_cmd_reg_wait reg_wait; 6787 /** 6788 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 6789 */ 6790 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 6791 /** 6792 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 6793 */ 6794 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 6795 /** 6796 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 6797 */ 6798 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 6799 /** 6800 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 6801 */ 6802 struct dmub_rb_cmd_dpphy_init dpphy_init; 6803 /** 6804 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 6805 */ 6806 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 6807 /** 6808 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 6809 */ 6810 struct dmub_rb_cmd_domain_control domain_control; 6811 /** 6812 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 6813 */ 6814 struct dmub_rb_cmd_psr_set_version psr_set_version; 6815 /** 6816 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 6817 */ 6818 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 6819 /** 6820 * Definition of a DMUB_CMD__PSR_ENABLE command. 6821 */ 6822 struct dmub_rb_cmd_psr_enable psr_enable; 6823 /** 6824 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6825 */ 6826 struct dmub_rb_cmd_psr_set_level psr_set_level; 6827 /** 6828 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6829 */ 6830 struct dmub_rb_cmd_psr_force_static psr_force_static; 6831 /** 6832 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6833 */ 6834 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6835 /** 6836 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6837 */ 6838 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6839 /** 6840 * Definition of a DMUB_CMD__HW_LOCK command. 6841 * Command is used by driver and FW. 6842 */ 6843 struct dmub_rb_cmd_lock_hw lock_hw; 6844 /** 6845 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6846 */ 6847 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6848 /** 6849 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6850 */ 6851 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6852 /** 6853 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6854 */ 6855 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6856 /** 6857 * Definition of a DMUB_CMD__MALL command. 6858 */ 6859 struct dmub_rb_cmd_mall mall; 6860 6861 /** 6862 * Definition of a DMUB_CMD__CAB command. 6863 */ 6864 struct dmub_rb_cmd_cab_for_ss cab; 6865 6866 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6867 6868 /** 6869 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6870 */ 6871 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6872 6873 /** 6874 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6875 */ 6876 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6877 6878 /** 6879 * Definition of DMUB_CMD__PANEL_CNTL commands. 6880 */ 6881 struct dmub_rb_cmd_panel_cntl panel_cntl; 6882 6883 /** 6884 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6885 */ 6886 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6887 6888 /** 6889 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6890 */ 6891 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6892 6893 /** 6894 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6895 */ 6896 struct dmub_rb_cmd_abm_set_level abm_set_level; 6897 6898 /** 6899 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6900 */ 6901 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6902 6903 /** 6904 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6905 */ 6906 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6907 6908 /** 6909 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6910 */ 6911 struct dmub_rb_cmd_abm_init_config abm_init_config; 6912 6913 /** 6914 * Definition of a DMUB_CMD__ABM_PAUSE command. 6915 */ 6916 struct dmub_rb_cmd_abm_pause abm_pause; 6917 6918 /** 6919 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6920 */ 6921 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6922 6923 /** 6924 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6925 */ 6926 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6927 6928 /** 6929 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6930 */ 6931 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6932 6933 /** 6934 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6935 */ 6936 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6937 6938 /** 6939 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6940 */ 6941 struct dmub_rb_cmd_abm_set_event abm_set_event; 6942 6943 /** 6944 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6945 */ 6946 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6947 6948 /** 6949 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6950 */ 6951 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6952 6953 /** 6954 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6955 */ 6956 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6957 6958 /** 6959 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6960 */ 6961 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6962 struct dmub_rb_cmd_drr_update drr_update; 6963 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6964 6965 /** 6966 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6967 */ 6968 struct dmub_rb_cmd_lvtma_control lvtma_control; 6969 /** 6970 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6971 */ 6972 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6973 /** 6974 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6975 */ 6976 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6977 /** 6978 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6979 */ 6980 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6981 /** 6982 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6983 */ 6984 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6985 /** 6986 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6987 */ 6988 struct dmub_rb_cmd_set_config_request set_config_request; 6989 /** 6990 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6991 */ 6992 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6993 /** 6994 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6995 */ 6996 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6997 /** 6998 * Definition of a DMUB_CMD__EDID_CEA command. 6999 */ 7000 struct dmub_rb_cmd_edid_cea edid_cea; 7001 /** 7002 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 7003 */ 7004 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 7005 7006 /** 7007 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 7008 */ 7009 struct dmub_rb_cmd_query_hpd_state query_hpd; 7010 /** 7011 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 7012 */ 7013 struct dmub_rb_cmd_secure_display secure_display; 7014 7015 /** 7016 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 7017 */ 7018 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 7019 /** 7020 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 7021 */ 7022 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 7023 /** 7024 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 7025 */ 7026 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 7027 /* 7028 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7029 */ 7030 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 7031 /** 7032 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7033 */ 7034 struct dmub_rb_cmd_replay_enable replay_enable; 7035 /** 7036 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 7037 */ 7038 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 7039 /** 7040 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 7041 */ 7042 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 7043 /** 7044 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 7045 */ 7046 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 7047 7048 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 7049 /** 7050 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 7051 */ 7052 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 7053 /** 7054 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 7055 */ 7056 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 7057 /** 7058 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 7059 */ 7060 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 7061 /** 7062 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 7063 */ 7064 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 7065 /** 7066 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 7067 */ 7068 struct dmub_rb_cmd_assr_enable assr_enable; 7069 7070 struct dmub_rb_cmd_fams2 fams2_config; 7071 7072 struct dmub_rb_cmd_ib ib_fams2_config; 7073 7074 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 7075 7076 struct dmub_rb_cmd_fams2_flip fams2_flip; 7077 7078 struct dmub_rb_cmd_fused_io fused_io; 7079 7080 /** 7081 * Definition of a DMUB_CMD__LSDMA command. 7082 */ 7083 struct dmub_rb_cmd_lsdma lsdma; 7084 7085 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 7086 7087 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 7088 /** 7089 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. 7090 */ 7091 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; 7092 /** 7093 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. 7094 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE 7095 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE 7096 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM 7097 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR 7098 */ 7099 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 7100 /** 7101 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 7102 */ 7103 struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable; 7104 /** 7105 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 7106 */ 7107 struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll; 7108 /* 7109 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7110 */ 7111 struct dmub_rb_cmd_pr_copy_settings pr_copy_settings; 7112 /** 7113 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7114 */ 7115 struct dmub_rb_cmd_pr_enable pr_enable; 7116 7117 struct dmub_rb_cmd_pr_update_state pr_update_state; 7118 7119 struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; 7120 }; 7121 7122 /** 7123 * union dmub_rb_out_cmd - Outbox command 7124 */ 7125 union dmub_rb_out_cmd { 7126 /** 7127 * Parameters common to every command. 7128 */ 7129 struct dmub_rb_cmd_common cmd_common; 7130 /** 7131 * AUX reply command. 7132 */ 7133 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 7134 /** 7135 * HPD notify command. 7136 */ 7137 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 7138 /** 7139 * SET_CONFIG reply command. 7140 */ 7141 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 7142 /** 7143 * DPIA notification command. 7144 */ 7145 struct dmub_rb_cmd_dpia_notification dpia_notification; 7146 /** 7147 * HPD sense notification command. 7148 */ 7149 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 7150 struct dmub_rb_cmd_fused_io fused_io; 7151 }; 7152 #pragma pack(pop) 7153 7154 7155 //============================================================================== 7156 //</DMUB_CMD>=================================================================== 7157 //============================================================================== 7158 //< DMUB_RB>==================================================================== 7159 //============================================================================== 7160 7161 /** 7162 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 7163 */ 7164 struct dmub_rb_init_params { 7165 void *ctx; /**< Caller provided context pointer */ 7166 void *base_address; /**< CPU base address for ring's data */ 7167 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 7168 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 7169 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 7170 }; 7171 7172 /** 7173 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 7174 */ 7175 struct dmub_rb { 7176 void *base_address; /**< CPU address for the ring's data */ 7177 uint32_t rptr; /**< Read pointer for consumer in bytes */ 7178 uint32_t wrpt; /**< Write pointer for producer in bytes */ 7179 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 7180 7181 void *ctx; /**< Caller provided context pointer */ 7182 void *dmub; /**< Pointer to the DMUB interface */ 7183 }; 7184 7185 /** 7186 * @brief Checks if the ringbuffer is empty. 7187 * 7188 * @param rb DMUB Ringbuffer 7189 * @return true if empty 7190 * @return false otherwise 7191 */ 7192 static inline bool dmub_rb_empty(struct dmub_rb *rb) 7193 { 7194 return (rb->wrpt == rb->rptr); 7195 } 7196 7197 /** 7198 * @brief gets number of outstanding requests in the RB 7199 * 7200 * @param rb DMUB Ringbuffer 7201 * @return true if full 7202 */ 7203 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 7204 { 7205 uint32_t data_count; 7206 7207 if (rb->wrpt >= rb->rptr) 7208 data_count = rb->wrpt - rb->rptr; 7209 else 7210 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7211 7212 return data_count / DMUB_RB_CMD_SIZE; 7213 } 7214 7215 /** 7216 * @brief gets number of free buffers in the RB 7217 * 7218 * @param rb DMUB Ringbuffer 7219 * @return true if full 7220 */ 7221 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 7222 { 7223 uint32_t data_count; 7224 7225 if (rb->wrpt >= rb->rptr) 7226 data_count = rb->wrpt - rb->rptr; 7227 else 7228 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7229 7230 /* +1 because 1 entry is always unusable */ 7231 data_count += DMUB_RB_CMD_SIZE; 7232 7233 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 7234 } 7235 7236 /** 7237 * @brief Checks if the ringbuffer is full 7238 * 7239 * @param rb DMUB Ringbuffer 7240 * @return true if full 7241 * @return false otherwise 7242 */ 7243 static inline bool dmub_rb_full(struct dmub_rb *rb) 7244 { 7245 uint32_t data_count; 7246 7247 if (rb->wrpt >= rb->rptr) 7248 data_count = rb->wrpt - rb->rptr; 7249 else 7250 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7251 7252 /* -1 because 1 entry is always unusable */ 7253 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 7254 } 7255 7256 /** 7257 * @brief Pushes a command into the ringbuffer 7258 * 7259 * @param rb DMUB ringbuffer 7260 * @param cmd The command to push 7261 * @return true if the ringbuffer was not full 7262 * @return false otherwise 7263 */ 7264 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 7265 const union dmub_rb_cmd *cmd) 7266 { 7267 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 7268 const uint8_t *src = (const uint8_t *)cmd; 7269 uint8_t i; 7270 7271 if (rb->capacity == 0) 7272 return false; 7273 7274 if (dmub_rb_full(rb)) 7275 return false; 7276 7277 // copying data 7278 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 7279 *dst++ = *src++; 7280 7281 rb->wrpt += DMUB_RB_CMD_SIZE; 7282 7283 if (rb->wrpt >= rb->capacity) 7284 rb->wrpt %= rb->capacity; 7285 7286 return true; 7287 } 7288 7289 /** 7290 * @brief Pushes a command into the DMUB outbox ringbuffer 7291 * 7292 * @param rb DMUB outbox ringbuffer 7293 * @param cmd Outbox command 7294 * @return true if not full 7295 * @return false otherwise 7296 */ 7297 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 7298 const union dmub_rb_out_cmd *cmd) 7299 { 7300 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 7301 const uint8_t *src = (const uint8_t *)cmd; 7302 7303 if (rb->capacity == 0) 7304 return false; 7305 7306 if (dmub_rb_full(rb)) 7307 return false; 7308 7309 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 7310 7311 rb->wrpt += DMUB_RB_CMD_SIZE; 7312 7313 if (rb->wrpt >= rb->capacity) 7314 rb->wrpt %= rb->capacity; 7315 7316 return true; 7317 } 7318 7319 /** 7320 * @brief Returns the next unprocessed command in the ringbuffer. 7321 * 7322 * @param rb DMUB ringbuffer 7323 * @param cmd The command to return 7324 * @return true if not empty 7325 * @return false otherwise 7326 */ 7327 static inline bool dmub_rb_front(struct dmub_rb *rb, 7328 union dmub_rb_cmd **cmd) 7329 { 7330 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 7331 7332 if (dmub_rb_empty(rb)) 7333 return false; 7334 7335 *cmd = (union dmub_rb_cmd *)rb_cmd; 7336 7337 return true; 7338 } 7339 7340 /** 7341 * @brief Determines the next ringbuffer offset. 7342 * 7343 * @param rb DMUB inbox ringbuffer 7344 * @param num_cmds Number of commands 7345 * @param next_rptr The next offset in the ringbuffer 7346 */ 7347 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 7348 uint32_t num_cmds, 7349 uint32_t *next_rptr) 7350 { 7351 if (rb->capacity == 0) 7352 return; 7353 7354 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 7355 7356 if (*next_rptr >= rb->capacity) 7357 *next_rptr %= rb->capacity; 7358 } 7359 7360 /** 7361 * @brief Returns a pointer to a command in the inbox. 7362 * 7363 * @param rb DMUB inbox ringbuffer 7364 * @param cmd The inbox command to return 7365 * @param rptr The ringbuffer offset 7366 * @return true if not empty 7367 * @return false otherwise 7368 */ 7369 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 7370 union dmub_rb_cmd **cmd, 7371 uint32_t rptr) 7372 { 7373 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 7374 7375 if (dmub_rb_empty(rb)) 7376 return false; 7377 7378 *cmd = (union dmub_rb_cmd *)rb_cmd; 7379 7380 return true; 7381 } 7382 7383 /** 7384 * @brief Returns the next unprocessed command in the outbox. 7385 * 7386 * @param rb DMUB outbox ringbuffer 7387 * @param cmd The outbox command to return 7388 * @return true if not empty 7389 * @return false otherwise 7390 */ 7391 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 7392 union dmub_rb_out_cmd *cmd) 7393 { 7394 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 7395 uint64_t *dst = (uint64_t *)cmd; 7396 uint8_t i; 7397 7398 if (dmub_rb_empty(rb)) 7399 return false; 7400 7401 // copying data 7402 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 7403 *dst++ = *src++; 7404 7405 return true; 7406 } 7407 7408 /** 7409 * @brief Removes the front entry in the ringbuffer. 7410 * 7411 * @param rb DMUB ringbuffer 7412 * @return true if the command was removed 7413 * @return false if there were no commands 7414 */ 7415 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 7416 { 7417 if (rb->capacity == 0) 7418 return false; 7419 7420 if (dmub_rb_empty(rb)) 7421 return false; 7422 7423 rb->rptr += DMUB_RB_CMD_SIZE; 7424 7425 if (rb->rptr >= rb->capacity) 7426 rb->rptr %= rb->capacity; 7427 7428 return true; 7429 } 7430 7431 /** 7432 * @brief Flushes commands in the ringbuffer to framebuffer memory. 7433 * 7434 * Avoids a race condition where DMCUB accesses memory while 7435 * there are still writes in flight to framebuffer. 7436 * 7437 * @param rb DMUB ringbuffer 7438 */ 7439 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 7440 { 7441 uint32_t rptr = rb->rptr; 7442 uint32_t wptr = rb->wrpt; 7443 7444 if (rb->capacity == 0) 7445 return; 7446 7447 while (rptr != wptr) { 7448 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 7449 uint8_t i; 7450 7451 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 7452 (void)READ_ONCE(*data++); 7453 7454 rptr += DMUB_RB_CMD_SIZE; 7455 if (rptr >= rb->capacity) 7456 rptr %= rb->capacity; 7457 } 7458 } 7459 7460 /** 7461 * @brief Initializes a DMCUB ringbuffer 7462 * 7463 * @param rb DMUB ringbuffer 7464 * @param init_params initial configuration for the ringbuffer 7465 */ 7466 static inline void dmub_rb_init(struct dmub_rb *rb, 7467 struct dmub_rb_init_params *init_params) 7468 { 7469 rb->base_address = init_params->base_address; 7470 rb->capacity = init_params->capacity; 7471 rb->rptr = init_params->read_ptr; 7472 rb->wrpt = init_params->write_ptr; 7473 } 7474 7475 /** 7476 * @brief Copies output data from in/out commands into the given command. 7477 * 7478 * @param rb DMUB ringbuffer 7479 * @param cmd Command to copy data into 7480 */ 7481 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 7482 union dmub_rb_cmd *cmd) 7483 { 7484 // Copy rb entry back into command 7485 uint8_t *rd_ptr = (rb->rptr == 0) ? 7486 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 7487 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 7488 7489 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 7490 } 7491 7492 //============================================================================== 7493 //</DMUB_RB>==================================================================== 7494 //============================================================================== 7495 #endif /* _DMUB_CMD_H_ */ 7496