1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/bitfield.h> 10 #include <linux/component.h> 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io.h> 14 #include <linux/media-bus-format.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/regmap.h> 22 23 #include <drm/clients/drm_client_setup.h> 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_bridge_connector.h> 28 #include <drm/drm_color_mgmt.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_damage_helper.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_encoder.h> 33 #include <drm/drm_gem_dma_helper.h> 34 #include <drm/drm_fb_dma_helper.h> 35 #include <drm/drm_fbdev_dma.h> 36 #include <drm/drm_fourcc.h> 37 #include <drm/drm_framebuffer.h> 38 #include <drm/drm_gem_atomic_helper.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_managed.h> 41 #include <drm/drm_of.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_plane.h> 44 #include <drm/drm_probe_helper.h> 45 #include <drm/drm_vblank.h> 46 47 #define HWDESC_PALETTE 2 48 49 struct ingenic_dma_hwdesc { 50 u32 next; 51 u32 addr; 52 u32 id; 53 u32 cmd; 54 /* extended hw descriptor for jz4780 */ 55 u32 offsize; 56 u32 pagewidth; 57 u32 cpos; 58 u32 dessize; 59 } __aligned(16); 60 61 struct ingenic_dma_hwdescs { 62 struct ingenic_dma_hwdesc hwdesc[3]; 63 u16 palette[256] __aligned(16); 64 }; 65 66 struct jz_soc_info { 67 bool needs_dev_clk; 68 bool has_osd; 69 bool has_alpha; 70 bool map_noncoherent; 71 bool use_extended_hwdesc; 72 bool plane_f0_not_working; 73 u32 max_burst; 74 unsigned int max_width, max_height; 75 const u32 *formats_f0, *formats_f1; 76 unsigned int num_formats_f0, num_formats_f1; 77 }; 78 79 struct ingenic_drm_private_state { 80 struct drm_private_state base; 81 bool use_palette; 82 }; 83 84 struct ingenic_drm { 85 struct drm_device drm; 86 /* 87 * f1 (aka. foreground1) is our primary plane, on top of which 88 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 89 * hardware and cannot be changed. 90 */ 91 struct drm_plane f0, f1, *ipu_plane; 92 struct drm_crtc crtc; 93 94 struct device *dev; 95 struct regmap *map; 96 struct clk *lcd_clk, *pix_clk; 97 const struct jz_soc_info *soc_info; 98 99 struct ingenic_dma_hwdescs *dma_hwdescs; 100 dma_addr_t dma_hwdescs_phys; 101 102 bool panel_is_sharp; 103 bool no_vblank; 104 105 /* 106 * clk_mutex is used to synchronize the pixel clock rate update with 107 * the VBLANK. When the pixel clock's parent clock needs to be updated, 108 * clock_nb's notifier function will lock the mutex, then wait until the 109 * next VBLANK. At that point, the parent clock's rate can be updated, 110 * and the mutex is then unlocked. If an atomic commit happens in the 111 * meantime, it will lock on the mutex, effectively waiting until the 112 * clock update process finishes. Finally, the pixel clock's rate will 113 * be recomputed when the mutex has been released, in the pending atomic 114 * commit, or a future one. 115 */ 116 struct mutex clk_mutex; 117 bool update_clk_rate; 118 struct notifier_block clock_nb; 119 120 struct drm_private_obj private_obj; 121 }; 122 123 struct ingenic_drm_bridge { 124 struct drm_encoder encoder; 125 struct drm_bridge bridge, *next_bridge; 126 127 struct drm_bus_cfg bus_cfg; 128 }; 129 130 static inline struct ingenic_drm_bridge * 131 to_ingenic_drm_bridge(struct drm_encoder *encoder) 132 { 133 return container_of(encoder, struct ingenic_drm_bridge, encoder); 134 } 135 136 static inline struct ingenic_drm_private_state * 137 to_ingenic_drm_priv_state(struct drm_private_state *state) 138 { 139 return container_of(state, struct ingenic_drm_private_state, base); 140 } 141 142 static struct ingenic_drm_private_state * 143 ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 144 { 145 struct drm_private_state *priv_state; 146 147 priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj); 148 if (IS_ERR(priv_state)) 149 return ERR_CAST(priv_state); 150 151 return to_ingenic_drm_priv_state(priv_state); 152 } 153 154 static struct ingenic_drm_private_state * 155 ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 156 { 157 struct drm_private_state *priv_state; 158 159 priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj); 160 if (!priv_state) 161 return NULL; 162 163 return to_ingenic_drm_priv_state(priv_state); 164 } 165 166 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 167 { 168 switch (reg) { 169 case JZ_REG_LCD_IID: 170 case JZ_REG_LCD_SA0: 171 case JZ_REG_LCD_FID0: 172 case JZ_REG_LCD_CMD0: 173 case JZ_REG_LCD_SA1: 174 case JZ_REG_LCD_FID1: 175 case JZ_REG_LCD_CMD1: 176 return false; 177 default: 178 return true; 179 } 180 } 181 182 static const struct regmap_config ingenic_drm_regmap_config = { 183 .reg_bits = 32, 184 .val_bits = 32, 185 .reg_stride = 4, 186 187 .writeable_reg = ingenic_drm_writeable_reg, 188 }; 189 190 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 191 { 192 return container_of(drm, struct ingenic_drm, drm); 193 } 194 195 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 196 { 197 return container_of(crtc, struct ingenic_drm, crtc); 198 } 199 200 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 201 { 202 return container_of(nb, struct ingenic_drm, clock_nb); 203 } 204 205 static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv, 206 unsigned int idx) 207 { 208 u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]); 209 210 return priv->dma_hwdescs_phys + offset; 211 } 212 213 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 214 unsigned long action, 215 void *data) 216 { 217 struct ingenic_drm *priv = drm_nb_get_priv(nb); 218 219 switch (action) { 220 case PRE_RATE_CHANGE: 221 mutex_lock(&priv->clk_mutex); 222 priv->update_clk_rate = true; 223 drm_crtc_wait_one_vblank(&priv->crtc); 224 return NOTIFY_OK; 225 default: 226 mutex_unlock(&priv->clk_mutex); 227 return NOTIFY_OK; 228 } 229 } 230 231 static void ingenic_drm_bridge_atomic_enable(struct drm_bridge *bridge, 232 struct drm_atomic_state *state) 233 { 234 struct ingenic_drm *priv = drm_device_get_priv(bridge->dev); 235 236 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 237 238 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 239 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 240 JZ_LCD_CTRL_ENABLE); 241 } 242 243 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 244 struct drm_atomic_state *state) 245 { 246 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 247 struct ingenic_drm_private_state *priv_state; 248 unsigned int next_id; 249 250 priv_state = ingenic_drm_get_new_priv_state(priv, state); 251 if (WARN_ON(!priv_state)) 252 return; 253 254 /* Set addresses of our DMA descriptor chains */ 255 next_id = priv_state->use_palette ? HWDESC_PALETTE : 0; 256 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id)); 257 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); 258 259 drm_crtc_vblank_on(crtc); 260 } 261 262 static void ingenic_drm_bridge_atomic_disable(struct drm_bridge *bridge, 263 struct drm_atomic_state *state) 264 { 265 struct ingenic_drm *priv = drm_device_get_priv(bridge->dev); 266 unsigned int var; 267 268 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 269 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 270 271 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 272 var & JZ_LCD_STATE_DISABLED, 273 1000, 0); 274 } 275 276 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 277 struct drm_atomic_state *state) 278 { 279 drm_crtc_vblank_off(crtc); 280 } 281 282 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 283 struct drm_display_mode *mode) 284 { 285 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 286 287 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 288 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 289 vde = vds + mode->crtc_vdisplay; 290 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 291 292 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 293 hds = mode->crtc_htotal - mode->crtc_hsync_start; 294 hde = hds + mode->crtc_hdisplay; 295 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 296 297 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 298 0 << JZ_LCD_VSYNC_VPS_OFFSET | 299 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 300 301 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 302 0 << JZ_LCD_HSYNC_HPS_OFFSET | 303 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 304 305 regmap_write(priv->map, JZ_REG_LCD_VAT, 306 ht << JZ_LCD_VAT_HT_OFFSET | 307 vt << JZ_LCD_VAT_VT_OFFSET); 308 309 regmap_write(priv->map, JZ_REG_LCD_DAH, 310 hds << JZ_LCD_DAH_HDS_OFFSET | 311 hde << JZ_LCD_DAH_HDE_OFFSET); 312 regmap_write(priv->map, JZ_REG_LCD_DAV, 313 vds << JZ_LCD_DAV_VDS_OFFSET | 314 vde << JZ_LCD_DAV_VDE_OFFSET); 315 316 if (priv->panel_is_sharp) { 317 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 318 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 319 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 320 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 321 } 322 323 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 324 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_MASK, 325 JZ_LCD_CTRL_OFUP | priv->soc_info->max_burst); 326 327 /* 328 * IPU restart - specify how much time the LCDC will wait before 329 * transferring a new frame from the IPU. The value is the one 330 * suggested in the programming manual. 331 */ 332 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 333 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 334 } 335 336 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 337 struct drm_atomic_state *state) 338 { 339 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 340 crtc); 341 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 342 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 343 struct ingenic_drm_private_state *priv_state; 344 345 if (crtc_state->gamma_lut && 346 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 347 dev_dbg(priv->dev, "Invalid palette size\n"); 348 return -EINVAL; 349 } 350 351 /* We will need the state in atomic_enable, so let's make sure it's part of the state */ 352 priv_state = ingenic_drm_get_priv_state(priv, state); 353 if (IS_ERR(priv_state)) 354 return PTR_ERR(priv_state); 355 356 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 357 f1_state = drm_atomic_get_plane_state(crtc_state->state, 358 &priv->f1); 359 if (IS_ERR(f1_state)) 360 return PTR_ERR(f1_state); 361 362 f0_state = drm_atomic_get_plane_state(crtc_state->state, 363 &priv->f0); 364 if (IS_ERR(f0_state)) 365 return PTR_ERR(f0_state); 366 367 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 368 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 369 priv->ipu_plane); 370 if (IS_ERR(ipu_state)) 371 return PTR_ERR(ipu_state); 372 373 /* IPU and F1 planes cannot be enabled at the same time. */ 374 if (f1_state->fb && ipu_state->fb) { 375 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 376 return -EINVAL; 377 } 378 } 379 380 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 381 priv->no_vblank = !f1_state->fb && !f0_state->fb && 382 !(ipu_state && ipu_state->fb); 383 } 384 385 return 0; 386 } 387 388 static enum drm_mode_status 389 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 390 { 391 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 392 long rate; 393 394 if (mode->hdisplay > priv->soc_info->max_width) 395 return MODE_BAD_HVALUE; 396 if (mode->vdisplay > priv->soc_info->max_height) 397 return MODE_BAD_VVALUE; 398 399 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 400 if (rate < 0) 401 return MODE_CLOCK_RANGE; 402 403 return MODE_OK; 404 } 405 406 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 407 struct drm_atomic_state *state) 408 { 409 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 410 crtc); 411 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 412 u32 ctrl = 0; 413 414 if (priv->soc_info->has_osd && 415 drm_atomic_crtc_needs_modeset(crtc_state)) { 416 /* 417 * If IPU plane is enabled, enable IPU as source for the F1 418 * plane; otherwise use regular DMA. 419 */ 420 if (priv->ipu_plane && priv->ipu_plane->state->fb) 421 ctrl |= JZ_LCD_OSDCTRL_IPU; 422 423 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 424 JZ_LCD_OSDCTRL_IPU, ctrl); 425 } 426 } 427 428 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 429 struct drm_atomic_state *state) 430 { 431 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 432 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 433 crtc); 434 struct drm_pending_vblank_event *event = crtc_state->event; 435 436 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 437 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 438 priv->update_clk_rate = true; 439 } 440 441 if (priv->update_clk_rate) { 442 mutex_lock(&priv->clk_mutex); 443 clk_set_rate(priv->pix_clk, 444 crtc_state->adjusted_mode.crtc_clock * 1000); 445 priv->update_clk_rate = false; 446 mutex_unlock(&priv->clk_mutex); 447 } 448 449 if (event) { 450 crtc_state->event = NULL; 451 452 spin_lock_irq(&crtc->dev->event_lock); 453 if (drm_crtc_vblank_get(crtc) == 0) 454 drm_crtc_arm_vblank_event(crtc, event); 455 else 456 drm_crtc_send_vblank_event(crtc, event); 457 spin_unlock_irq(&crtc->dev->event_lock); 458 } 459 } 460 461 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 462 struct drm_atomic_state *state) 463 { 464 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 465 plane); 466 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 467 plane); 468 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 469 struct ingenic_drm_private_state *priv_state; 470 struct drm_crtc_state *crtc_state; 471 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 472 int ret; 473 474 if (!crtc) 475 return 0; 476 477 if (priv->soc_info->plane_f0_not_working && plane == &priv->f0) 478 return -EINVAL; 479 480 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 481 if (WARN_ON(!crtc_state)) 482 return -EINVAL; 483 484 priv_state = ingenic_drm_get_priv_state(priv, state); 485 if (IS_ERR(priv_state)) 486 return PTR_ERR(priv_state); 487 488 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 489 DRM_PLANE_NO_SCALING, 490 DRM_PLANE_NO_SCALING, 491 priv->soc_info->has_osd, 492 true); 493 if (ret) 494 return ret; 495 496 /* 497 * If OSD is not available, check that the width/height match. 498 * Note that state->src_* are in 16.16 fixed-point format. 499 */ 500 if (!priv->soc_info->has_osd && 501 (new_plane_state->src_x != 0 || 502 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 503 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 504 return -EINVAL; 505 506 priv_state->use_palette = new_plane_state->fb && 507 new_plane_state->fb->format->format == DRM_FORMAT_C8; 508 509 /* 510 * Require full modeset if enabling or disabling a plane, or changing 511 * its position, size or depth. 512 */ 513 if (priv->soc_info->has_osd && 514 (!old_plane_state->fb || !new_plane_state->fb || 515 old_plane_state->crtc_x != new_plane_state->crtc_x || 516 old_plane_state->crtc_y != new_plane_state->crtc_y || 517 old_plane_state->crtc_w != new_plane_state->crtc_w || 518 old_plane_state->crtc_h != new_plane_state->crtc_h || 519 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 520 crtc_state->mode_changed = true; 521 522 if (priv->soc_info->map_noncoherent) 523 drm_atomic_helper_check_plane_damage(state, new_plane_state); 524 525 return 0; 526 } 527 528 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 529 struct drm_plane *plane) 530 { 531 unsigned int en_bit; 532 533 if (priv->soc_info->has_osd) { 534 if (plane != &priv->f0) 535 en_bit = JZ_LCD_OSDC_F1EN; 536 else 537 en_bit = JZ_LCD_OSDC_F0EN; 538 539 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 540 } 541 } 542 543 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 544 { 545 struct ingenic_drm *priv = dev_get_drvdata(dev); 546 unsigned int en_bit; 547 548 if (priv->soc_info->has_osd) { 549 if (plane != &priv->f0) 550 en_bit = JZ_LCD_OSDC_F1EN; 551 else 552 en_bit = JZ_LCD_OSDC_F0EN; 553 554 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 555 } 556 } 557 558 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 559 struct drm_atomic_state *state) 560 { 561 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 562 563 ingenic_drm_plane_disable(priv->dev, plane); 564 } 565 566 void ingenic_drm_plane_config(struct device *dev, 567 struct drm_plane *plane, u32 fourcc) 568 { 569 struct ingenic_drm *priv = dev_get_drvdata(dev); 570 struct drm_plane_state *state = plane->state; 571 unsigned int xy_reg, size_reg; 572 unsigned int ctrl = 0; 573 574 ingenic_drm_plane_enable(priv, plane); 575 576 if (priv->soc_info->has_osd && plane != &priv->f0) { 577 switch (fourcc) { 578 case DRM_FORMAT_XRGB1555: 579 ctrl |= JZ_LCD_OSDCTRL_RGB555; 580 fallthrough; 581 case DRM_FORMAT_RGB565: 582 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 583 break; 584 case DRM_FORMAT_RGB888: 585 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 586 break; 587 case DRM_FORMAT_XRGB8888: 588 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 589 break; 590 case DRM_FORMAT_XRGB2101010: 591 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 592 break; 593 } 594 595 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 596 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 597 } else { 598 switch (fourcc) { 599 case DRM_FORMAT_C8: 600 ctrl |= JZ_LCD_CTRL_BPP_8; 601 break; 602 case DRM_FORMAT_XRGB1555: 603 ctrl |= JZ_LCD_CTRL_RGB555; 604 fallthrough; 605 case DRM_FORMAT_RGB565: 606 ctrl |= JZ_LCD_CTRL_BPP_15_16; 607 break; 608 case DRM_FORMAT_RGB888: 609 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 610 break; 611 case DRM_FORMAT_XRGB8888: 612 ctrl |= JZ_LCD_CTRL_BPP_18_24; 613 break; 614 case DRM_FORMAT_XRGB2101010: 615 ctrl |= JZ_LCD_CTRL_BPP_30; 616 break; 617 } 618 619 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 620 JZ_LCD_CTRL_BPP_MASK, ctrl); 621 } 622 623 if (priv->soc_info->has_osd) { 624 if (plane != &priv->f0) { 625 xy_reg = JZ_REG_LCD_XYP1; 626 size_reg = JZ_REG_LCD_SIZE1; 627 } else { 628 xy_reg = JZ_REG_LCD_XYP0; 629 size_reg = JZ_REG_LCD_SIZE0; 630 } 631 632 regmap_write(priv->map, xy_reg, 633 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 634 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 635 regmap_write(priv->map, size_reg, 636 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 637 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 638 } 639 } 640 641 bool ingenic_drm_map_noncoherent(const struct device *dev) 642 { 643 const struct ingenic_drm *priv = dev_get_drvdata(dev); 644 645 return priv->soc_info->map_noncoherent; 646 } 647 648 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 649 const struct drm_color_lut *lut) 650 { 651 unsigned int i; 652 653 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 654 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 655 | drm_color_lut_extract(lut[i].green, 6) << 5 656 | drm_color_lut_extract(lut[i].blue, 5); 657 658 priv->dma_hwdescs->palette[i] = color; 659 } 660 } 661 662 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 663 struct drm_atomic_state *state) 664 { 665 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 666 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 667 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 668 unsigned int width, height, cpp, next_id, plane_id; 669 struct ingenic_drm_private_state *priv_state; 670 struct drm_crtc_state *crtc_state; 671 struct ingenic_dma_hwdesc *hwdesc; 672 dma_addr_t addr; 673 u32 fourcc; 674 675 if (newstate && newstate->fb) { 676 if (priv->soc_info->map_noncoherent) 677 drm_fb_dma_sync_non_coherent(&priv->drm, oldstate, newstate); 678 679 crtc_state = newstate->crtc->state; 680 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0); 681 682 addr = drm_fb_dma_get_gem_addr(newstate->fb, newstate, 0); 683 width = newstate->src_w >> 16; 684 height = newstate->src_h >> 16; 685 cpp = newstate->fb->format->cpp[0]; 686 687 priv_state = ingenic_drm_get_new_priv_state(priv, state); 688 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; 689 690 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; 691 hwdesc->addr = addr; 692 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 693 hwdesc->next = dma_hwdesc_addr(priv, next_id); 694 695 if (priv->soc_info->use_extended_hwdesc) { 696 hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE; 697 698 /* Extended 8-byte descriptor */ 699 hwdesc->cpos = 0; 700 hwdesc->offsize = 0; 701 hwdesc->pagewidth = 0; 702 703 switch (newstate->fb->format->format) { 704 case DRM_FORMAT_XRGB1555: 705 hwdesc->cpos |= JZ_LCD_CPOS_RGB555; 706 fallthrough; 707 case DRM_FORMAT_RGB565: 708 hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16; 709 break; 710 case DRM_FORMAT_XRGB8888: 711 hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24; 712 break; 713 } 714 hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 << 715 JZ_LCD_CPOS_COEFFICIENT_OFFSET); 716 hwdesc->dessize = 717 (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) | 718 FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height - 1) | 719 FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width - 1); 720 } 721 722 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 723 fourcc = newstate->fb->format->format; 724 725 ingenic_drm_plane_config(priv->dev, plane, fourcc); 726 727 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 728 } 729 730 if (crtc_state->color_mgmt_changed) 731 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 732 } 733 } 734 735 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 736 struct drm_crtc_state *crtc_state, 737 struct drm_connector_state *conn_state) 738 { 739 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 740 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 741 struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder); 742 unsigned int cfg, rgbcfg = 0; 743 744 priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS; 745 746 if (priv->panel_is_sharp) { 747 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 748 } else { 749 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 750 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 751 } 752 753 if (priv->soc_info->use_extended_hwdesc) 754 cfg |= JZ_LCD_CFG_DESCRIPTOR_8; 755 756 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 757 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 758 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 759 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 760 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW) 761 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 762 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 763 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 764 765 if (!priv->panel_is_sharp) { 766 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) { 767 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 768 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 769 else 770 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 771 } else { 772 switch (bridge->bus_cfg.format) { 773 case MEDIA_BUS_FMT_RGB565_1X16: 774 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 775 break; 776 case MEDIA_BUS_FMT_RGB666_1X18: 777 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 778 break; 779 case MEDIA_BUS_FMT_RGB888_1X24: 780 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 781 break; 782 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 783 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 784 fallthrough; 785 case MEDIA_BUS_FMT_RGB888_3X8: 786 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 787 break; 788 default: 789 break; 790 } 791 } 792 } 793 794 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 795 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 796 } 797 798 static int ingenic_drm_bridge_attach(struct drm_bridge *bridge, 799 struct drm_encoder *encoder, 800 enum drm_bridge_attach_flags flags) 801 { 802 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(encoder); 803 804 return drm_bridge_attach(encoder, ib->next_bridge, 805 &ib->bridge, flags); 806 } 807 808 static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge, 809 struct drm_bridge_state *bridge_state, 810 struct drm_crtc_state *crtc_state, 811 struct drm_connector_state *conn_state) 812 { 813 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 814 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 815 816 ib->bus_cfg = bridge_state->output_bus_cfg; 817 818 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 819 return 0; 820 821 switch (bridge_state->output_bus_cfg.format) { 822 case MEDIA_BUS_FMT_RGB888_3X8: 823 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 824 /* 825 * The LCD controller expects timing values in dot-clock ticks, 826 * which is 3x the timing values in pixels when using a 3x8-bit 827 * display; but it will count the display area size in pixels 828 * either way. Go figure. 829 */ 830 mode->crtc_clock = mode->clock * 3; 831 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 832 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 833 mode->crtc_hdisplay = mode->hdisplay; 834 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 835 return 0; 836 case MEDIA_BUS_FMT_RGB565_1X16: 837 case MEDIA_BUS_FMT_RGB666_1X18: 838 case MEDIA_BUS_FMT_RGB888_1X24: 839 return 0; 840 default: 841 return -EINVAL; 842 } 843 } 844 845 static u32 * 846 ingenic_drm_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 847 struct drm_bridge_state *bridge_state, 848 struct drm_crtc_state *crtc_state, 849 struct drm_connector_state *conn_state, 850 u32 output_fmt, 851 unsigned int *num_input_fmts) 852 { 853 switch (output_fmt) { 854 case MEDIA_BUS_FMT_RGB888_1X24: 855 case MEDIA_BUS_FMT_RGB666_1X18: 856 case MEDIA_BUS_FMT_RGB565_1X16: 857 case MEDIA_BUS_FMT_RGB888_3X8: 858 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 859 break; 860 default: 861 *num_input_fmts = 0; 862 return NULL; 863 } 864 865 return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state, 866 crtc_state, conn_state, 867 output_fmt, 868 num_input_fmts); 869 } 870 871 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 872 { 873 struct ingenic_drm *priv = drm_device_get_priv(arg); 874 unsigned int state; 875 876 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 877 878 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 879 JZ_LCD_STATE_EOF_IRQ, 0); 880 881 if (state & JZ_LCD_STATE_EOF_IRQ) 882 drm_crtc_handle_vblank(&priv->crtc); 883 884 return IRQ_HANDLED; 885 } 886 887 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 888 { 889 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 890 891 if (priv->no_vblank) 892 return -EINVAL; 893 894 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 895 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 896 897 return 0; 898 } 899 900 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 901 { 902 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 903 904 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 905 } 906 907 static struct drm_framebuffer * 908 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, 909 const struct drm_format_info *info, 910 const struct drm_mode_fb_cmd2 *mode_cmd) 911 { 912 struct ingenic_drm *priv = drm_device_get_priv(drm); 913 914 if (priv->soc_info->map_noncoherent) 915 return drm_gem_fb_create_with_dirty(drm, file, info, mode_cmd); 916 917 return drm_gem_fb_create(drm, file, info, mode_cmd); 918 } 919 920 static struct drm_gem_object * 921 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size) 922 { 923 struct ingenic_drm *priv = drm_device_get_priv(drm); 924 struct drm_gem_dma_object *obj; 925 926 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 927 if (!obj) 928 return ERR_PTR(-ENOMEM); 929 930 obj->map_noncoherent = priv->soc_info->map_noncoherent; 931 932 return &obj->base; 933 } 934 935 static struct drm_private_state * 936 ingenic_drm_duplicate_state(struct drm_private_obj *obj) 937 { 938 struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state); 939 940 state = kmemdup(state, sizeof(*state), GFP_KERNEL); 941 if (!state) 942 return NULL; 943 944 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 945 946 return &state->base; 947 } 948 949 static void ingenic_drm_destroy_state(struct drm_private_obj *obj, 950 struct drm_private_state *state) 951 { 952 struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state); 953 954 kfree(priv_state); 955 } 956 957 DEFINE_DRM_GEM_DMA_FOPS(ingenic_drm_fops); 958 959 static const struct drm_driver ingenic_drm_driver_data = { 960 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 961 .name = "ingenic-drm", 962 .desc = "DRM module for Ingenic SoCs", 963 .major = 1, 964 .minor = 1, 965 .patchlevel = 0, 966 967 .fops = &ingenic_drm_fops, 968 .gem_create_object = ingenic_drm_gem_create_object, 969 DRM_GEM_DMA_DRIVER_OPS, 970 DRM_FBDEV_DMA_DRIVER_OPS, 971 }; 972 973 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 974 .update_plane = drm_atomic_helper_update_plane, 975 .disable_plane = drm_atomic_helper_disable_plane, 976 .reset = drm_atomic_helper_plane_reset, 977 .destroy = drm_plane_cleanup, 978 979 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 980 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 981 }; 982 983 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 984 .set_config = drm_atomic_helper_set_config, 985 .page_flip = drm_atomic_helper_page_flip, 986 .reset = drm_atomic_helper_crtc_reset, 987 .destroy = drm_crtc_cleanup, 988 989 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 990 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 991 992 .enable_vblank = ingenic_drm_enable_vblank, 993 .disable_vblank = ingenic_drm_disable_vblank, 994 }; 995 996 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 997 .atomic_update = ingenic_drm_plane_atomic_update, 998 .atomic_check = ingenic_drm_plane_atomic_check, 999 .atomic_disable = ingenic_drm_plane_atomic_disable, 1000 }; 1001 1002 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 1003 .atomic_enable = ingenic_drm_crtc_atomic_enable, 1004 .atomic_disable = ingenic_drm_crtc_atomic_disable, 1005 .atomic_begin = ingenic_drm_crtc_atomic_begin, 1006 .atomic_flush = ingenic_drm_crtc_atomic_flush, 1007 .atomic_check = ingenic_drm_crtc_atomic_check, 1008 .mode_valid = ingenic_drm_crtc_mode_valid, 1009 }; 1010 1011 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 1012 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 1013 }; 1014 1015 static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = { 1016 .attach = ingenic_drm_bridge_attach, 1017 .atomic_enable = ingenic_drm_bridge_atomic_enable, 1018 .atomic_disable = ingenic_drm_bridge_atomic_disable, 1019 .atomic_check = ingenic_drm_bridge_atomic_check, 1020 .atomic_reset = drm_atomic_helper_bridge_reset, 1021 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1022 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1023 .atomic_get_input_bus_fmts = ingenic_drm_bridge_atomic_get_input_bus_fmts, 1024 }; 1025 1026 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 1027 .fb_create = ingenic_drm_gem_fb_create, 1028 .atomic_check = drm_atomic_helper_check, 1029 .atomic_commit = drm_atomic_helper_commit, 1030 }; 1031 1032 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 1033 .atomic_commit_tail = drm_atomic_helper_commit_tail, 1034 }; 1035 1036 static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = { 1037 .atomic_duplicate_state = ingenic_drm_duplicate_state, 1038 .atomic_destroy_state = ingenic_drm_destroy_state, 1039 }; 1040 1041 static void ingenic_drm_unbind_all(void *d) 1042 { 1043 struct ingenic_drm *priv = d; 1044 1045 component_unbind_all(priv->dev, &priv->drm); 1046 } 1047 1048 static void __maybe_unused ingenic_drm_release_rmem(void *d) 1049 { 1050 of_reserved_mem_device_release(d); 1051 } 1052 1053 static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv, 1054 unsigned int hwdesc, 1055 unsigned int next_hwdesc, u32 id) 1056 { 1057 struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc]; 1058 1059 desc->next = dma_hwdesc_addr(priv, next_hwdesc); 1060 desc->id = id; 1061 } 1062 1063 static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv) 1064 { 1065 struct ingenic_dma_hwdesc *desc; 1066 1067 ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0); 1068 1069 desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE]; 1070 desc->addr = priv->dma_hwdescs_phys 1071 + offsetof(struct ingenic_dma_hwdescs, palette); 1072 desc->cmd = JZ_LCD_CMD_ENABLE_PAL 1073 | (sizeof(priv->dma_hwdescs->palette) / 4); 1074 } 1075 1076 static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv, 1077 unsigned int plane) 1078 { 1079 ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane); 1080 } 1081 1082 static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj) 1083 { 1084 drm_atomic_private_obj_fini(private_obj); 1085 } 1086 1087 static int ingenic_drm_bind(struct device *dev, bool has_components) 1088 { 1089 struct platform_device *pdev = to_platform_device(dev); 1090 struct ingenic_drm_private_state *private_state; 1091 const struct jz_soc_info *soc_info; 1092 struct ingenic_drm *priv; 1093 struct clk *parent_clk; 1094 struct drm_plane *primary; 1095 struct drm_bridge *bridge; 1096 struct drm_panel *panel; 1097 struct drm_connector *connector; 1098 struct drm_encoder *encoder; 1099 struct ingenic_drm_bridge *ib; 1100 struct drm_device *drm; 1101 void __iomem *base; 1102 struct resource *res; 1103 struct regmap_config regmap_config; 1104 long parent_rate; 1105 unsigned int i, clone_mask = 0; 1106 int ret, irq; 1107 u32 osdc = 0; 1108 1109 soc_info = of_device_get_match_data(dev); 1110 if (!soc_info) { 1111 dev_err(dev, "Missing platform data\n"); 1112 return -EINVAL; 1113 } 1114 1115 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 1116 ret = of_reserved_mem_device_init(dev); 1117 1118 if (ret && ret != -ENODEV) 1119 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 1120 1121 if (!ret) { 1122 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 1123 if (ret) 1124 return ret; 1125 } 1126 } 1127 1128 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 1129 struct ingenic_drm, drm); 1130 if (IS_ERR(priv)) 1131 return PTR_ERR(priv); 1132 1133 priv->soc_info = soc_info; 1134 priv->dev = dev; 1135 drm = &priv->drm; 1136 1137 platform_set_drvdata(pdev, priv); 1138 1139 ret = drmm_mode_config_init(drm); 1140 if (ret) 1141 goto err_drvdata; 1142 1143 drm->mode_config.min_width = 0; 1144 drm->mode_config.min_height = 0; 1145 drm->mode_config.max_width = soc_info->max_width; 1146 drm->mode_config.max_height = 4095; 1147 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 1148 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 1149 1150 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1151 if (IS_ERR(base)) { 1152 dev_err(dev, "Failed to get memory resource\n"); 1153 ret = PTR_ERR(base); 1154 goto err_drvdata; 1155 } 1156 1157 regmap_config = ingenic_drm_regmap_config; 1158 regmap_config.max_register = res->end - res->start; 1159 priv->map = devm_regmap_init_mmio(dev, base, 1160 ®map_config); 1161 if (IS_ERR(priv->map)) { 1162 dev_err(dev, "Failed to create regmap\n"); 1163 ret = PTR_ERR(priv->map); 1164 goto err_drvdata; 1165 } 1166 1167 irq = platform_get_irq(pdev, 0); 1168 if (irq < 0) { 1169 ret = irq; 1170 goto err_drvdata; 1171 } 1172 1173 if (soc_info->needs_dev_clk) { 1174 priv->lcd_clk = devm_clk_get(dev, "lcd"); 1175 if (IS_ERR(priv->lcd_clk)) { 1176 dev_err(dev, "Failed to get lcd clock\n"); 1177 ret = PTR_ERR(priv->lcd_clk); 1178 goto err_drvdata; 1179 } 1180 } 1181 1182 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 1183 if (IS_ERR(priv->pix_clk)) { 1184 dev_err(dev, "Failed to get pixel clock\n"); 1185 ret = PTR_ERR(priv->pix_clk); 1186 goto err_drvdata; 1187 } 1188 1189 priv->dma_hwdescs = dmam_alloc_coherent(dev, 1190 sizeof(*priv->dma_hwdescs), 1191 &priv->dma_hwdescs_phys, 1192 GFP_KERNEL); 1193 if (!priv->dma_hwdescs) { 1194 ret = -ENOMEM; 1195 goto err_drvdata; 1196 } 1197 1198 /* Configure DMA hwdesc for foreground0 plane */ 1199 ingenic_drm_configure_hwdesc_plane(priv, 0); 1200 1201 /* Configure DMA hwdesc for foreground1 plane */ 1202 ingenic_drm_configure_hwdesc_plane(priv, 1); 1203 1204 /* Configure DMA hwdesc for palette */ 1205 ingenic_drm_configure_hwdesc_palette(priv); 1206 1207 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 1208 1209 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 1210 1211 ret = drm_universal_plane_init(drm, primary, 1, 1212 &ingenic_drm_primary_plane_funcs, 1213 priv->soc_info->formats_f1, 1214 priv->soc_info->num_formats_f1, 1215 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1216 if (ret) { 1217 dev_err(dev, "Failed to register plane: %i\n", ret); 1218 goto err_drvdata; 1219 } 1220 1221 if (soc_info->map_noncoherent) 1222 drm_plane_enable_fb_damage_clips(&priv->f1); 1223 1224 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 1225 1226 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 1227 NULL, &ingenic_drm_crtc_funcs, NULL); 1228 if (ret) { 1229 dev_err(dev, "Failed to init CRTC: %i\n", ret); 1230 goto err_drvdata; 1231 } 1232 1233 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 1234 ARRAY_SIZE(priv->dma_hwdescs->palette)); 1235 1236 if (soc_info->has_osd) { 1237 drm_plane_helper_add(&priv->f0, 1238 &ingenic_drm_plane_helper_funcs); 1239 1240 ret = drm_universal_plane_init(drm, &priv->f0, 1, 1241 &ingenic_drm_primary_plane_funcs, 1242 priv->soc_info->formats_f0, 1243 priv->soc_info->num_formats_f0, 1244 NULL, DRM_PLANE_TYPE_OVERLAY, 1245 NULL); 1246 if (ret) { 1247 dev_err(dev, "Failed to register overlay plane: %i\n", 1248 ret); 1249 goto err_drvdata; 1250 } 1251 1252 if (soc_info->map_noncoherent) 1253 drm_plane_enable_fb_damage_clips(&priv->f0); 1254 1255 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 1256 ret = component_bind_all(dev, drm); 1257 if (ret) { 1258 if (ret != -EPROBE_DEFER) 1259 dev_err(dev, "Failed to bind components: %i\n", ret); 1260 goto err_drvdata; 1261 } 1262 1263 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1264 if (ret) 1265 goto err_drvdata; 1266 1267 priv->ipu_plane = drm_plane_from_index(drm, 2); 1268 if (!priv->ipu_plane) { 1269 dev_err(dev, "Failed to retrieve IPU plane\n"); 1270 ret = -EINVAL; 1271 goto err_drvdata; 1272 } 1273 } 1274 } 1275 1276 for (i = 0; ; i++) { 1277 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1278 if (ret) { 1279 if (ret == -ENODEV) 1280 break; /* we're done */ 1281 if (ret != -EPROBE_DEFER) 1282 dev_err(dev, "Failed to get bridge handle\n"); 1283 goto err_drvdata; 1284 } 1285 1286 if (panel) 1287 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1288 DRM_MODE_CONNECTOR_DPI); 1289 1290 ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder, 1291 NULL, DRM_MODE_ENCODER_DPI, NULL); 1292 if (IS_ERR(ib)) { 1293 ret = PTR_ERR(ib); 1294 dev_err(dev, "Failed to init encoder: %d\n", ret); 1295 goto err_drvdata; 1296 } 1297 1298 encoder = &ib->encoder; 1299 encoder->possible_crtcs = drm_crtc_mask(&priv->crtc); 1300 1301 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1302 1303 ib->bridge.funcs = &ingenic_drm_bridge_funcs; 1304 ib->next_bridge = bridge; 1305 1306 ret = drm_bridge_attach(encoder, &ib->bridge, NULL, 1307 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1308 if (ret) { 1309 dev_err(dev, "Unable to attach bridge\n"); 1310 goto err_drvdata; 1311 } 1312 1313 connector = drm_bridge_connector_init(drm, encoder); 1314 if (IS_ERR(connector)) { 1315 dev_err(dev, "Unable to init connector\n"); 1316 ret = PTR_ERR(connector); 1317 goto err_drvdata; 1318 } 1319 1320 drm_connector_attach_encoder(connector, encoder); 1321 } 1322 1323 drm_for_each_encoder(encoder, drm) { 1324 clone_mask |= BIT(drm_encoder_index(encoder)); 1325 } 1326 1327 drm_for_each_encoder(encoder, drm) { 1328 encoder->possible_clones = clone_mask; 1329 } 1330 1331 ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm); 1332 if (ret) { 1333 dev_err(dev, "Unable to install IRQ handler\n"); 1334 goto err_drvdata; 1335 } 1336 1337 ret = drm_vblank_init(drm, 1); 1338 if (ret) { 1339 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1340 goto err_drvdata; 1341 } 1342 1343 drm_mode_config_reset(drm); 1344 1345 ret = clk_prepare_enable(priv->pix_clk); 1346 if (ret) { 1347 dev_err(dev, "Unable to start pixel clock\n"); 1348 goto err_drvdata; 1349 } 1350 1351 if (priv->lcd_clk) { 1352 parent_clk = clk_get_parent(priv->lcd_clk); 1353 parent_rate = clk_get_rate(parent_clk); 1354 1355 /* LCD Device clock must be 3x the pixel clock for STN panels, 1356 * or 1.5x the pixel clock for TFT panels. To avoid having to 1357 * check for the LCD device clock everytime we do a mode change, 1358 * we set the LCD device clock to the highest rate possible. 1359 */ 1360 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1361 if (ret) { 1362 dev_err(dev, "Unable to set LCD clock rate\n"); 1363 goto err_pixclk_disable; 1364 } 1365 1366 ret = clk_prepare_enable(priv->lcd_clk); 1367 if (ret) { 1368 dev_err(dev, "Unable to start lcd clock\n"); 1369 goto err_pixclk_disable; 1370 } 1371 } 1372 1373 /* Enable OSD if available */ 1374 if (soc_info->has_osd) 1375 osdc |= JZ_LCD_OSDC_OSDEN; 1376 if (soc_info->has_alpha) 1377 osdc |= JZ_LCD_OSDC_ALPHAEN; 1378 regmap_write(priv->map, JZ_REG_LCD_OSDC, osdc); 1379 1380 mutex_init(&priv->clk_mutex); 1381 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1382 1383 parent_clk = clk_get_parent(priv->pix_clk); 1384 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1385 if (ret) { 1386 dev_err(dev, "Unable to register clock notifier\n"); 1387 goto err_devclk_disable; 1388 } 1389 1390 private_state = kzalloc(sizeof(*private_state), GFP_KERNEL); 1391 if (!private_state) { 1392 ret = -ENOMEM; 1393 goto err_clk_notifier_unregister; 1394 } 1395 1396 drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base, 1397 &ingenic_drm_private_state_funcs); 1398 1399 ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini, 1400 &priv->private_obj); 1401 if (ret) 1402 goto err_private_state_free; 1403 1404 ret = drm_dev_register(drm, 0); 1405 if (ret) { 1406 dev_err(dev, "Failed to register DRM driver\n"); 1407 goto err_clk_notifier_unregister; 1408 } 1409 1410 drm_client_setup(drm, NULL); 1411 1412 return 0; 1413 1414 err_private_state_free: 1415 kfree(private_state); 1416 err_clk_notifier_unregister: 1417 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1418 err_devclk_disable: 1419 if (priv->lcd_clk) 1420 clk_disable_unprepare(priv->lcd_clk); 1421 err_pixclk_disable: 1422 clk_disable_unprepare(priv->pix_clk); 1423 err_drvdata: 1424 platform_set_drvdata(pdev, NULL); 1425 return ret; 1426 } 1427 1428 static int ingenic_drm_bind_with_components(struct device *dev) 1429 { 1430 return ingenic_drm_bind(dev, true); 1431 } 1432 1433 static void ingenic_drm_unbind(struct device *dev) 1434 { 1435 struct ingenic_drm *priv = dev_get_drvdata(dev); 1436 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1437 1438 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1439 if (priv->lcd_clk) 1440 clk_disable_unprepare(priv->lcd_clk); 1441 clk_disable_unprepare(priv->pix_clk); 1442 1443 drm_dev_unregister(&priv->drm); 1444 drm_atomic_helper_shutdown(&priv->drm); 1445 dev_set_drvdata(dev, NULL); 1446 } 1447 1448 static const struct component_master_ops ingenic_master_ops = { 1449 .bind = ingenic_drm_bind_with_components, 1450 .unbind = ingenic_drm_unbind, 1451 }; 1452 1453 static int ingenic_drm_probe(struct platform_device *pdev) 1454 { 1455 struct device *dev = &pdev->dev; 1456 struct component_match *match = NULL; 1457 struct device_node *np; 1458 1459 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1460 return ingenic_drm_bind(dev, false); 1461 1462 /* IPU is at port address 8 */ 1463 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1464 if (!np) 1465 return ingenic_drm_bind(dev, false); 1466 1467 drm_of_component_match_add(dev, &match, component_compare_of, np); 1468 of_node_put(np); 1469 1470 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1471 } 1472 1473 static void ingenic_drm_remove(struct platform_device *pdev) 1474 { 1475 struct device *dev = &pdev->dev; 1476 1477 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1478 ingenic_drm_unbind(dev); 1479 else 1480 component_master_del(dev, &ingenic_master_ops); 1481 } 1482 1483 static void ingenic_drm_shutdown(struct platform_device *pdev) 1484 { 1485 struct ingenic_drm *priv = platform_get_drvdata(pdev); 1486 1487 if (priv) 1488 drm_atomic_helper_shutdown(&priv->drm); 1489 } 1490 1491 static int ingenic_drm_suspend(struct device *dev) 1492 { 1493 struct ingenic_drm *priv = dev_get_drvdata(dev); 1494 1495 return drm_mode_config_helper_suspend(&priv->drm); 1496 } 1497 1498 static int ingenic_drm_resume(struct device *dev) 1499 { 1500 struct ingenic_drm *priv = dev_get_drvdata(dev); 1501 1502 return drm_mode_config_helper_resume(&priv->drm); 1503 } 1504 1505 static DEFINE_SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, 1506 ingenic_drm_suspend, ingenic_drm_resume); 1507 1508 static const u32 jz4740_formats[] = { 1509 DRM_FORMAT_XRGB1555, 1510 DRM_FORMAT_RGB565, 1511 DRM_FORMAT_XRGB8888, 1512 }; 1513 1514 static const u32 jz4725b_formats_f1[] = { 1515 DRM_FORMAT_XRGB1555, 1516 DRM_FORMAT_RGB565, 1517 DRM_FORMAT_XRGB8888, 1518 }; 1519 1520 static const u32 jz4725b_formats_f0[] = { 1521 DRM_FORMAT_C8, 1522 DRM_FORMAT_XRGB1555, 1523 DRM_FORMAT_RGB565, 1524 DRM_FORMAT_XRGB8888, 1525 }; 1526 1527 static const u32 jz4770_formats_f1[] = { 1528 DRM_FORMAT_XRGB1555, 1529 DRM_FORMAT_RGB565, 1530 DRM_FORMAT_RGB888, 1531 DRM_FORMAT_XRGB8888, 1532 DRM_FORMAT_XRGB2101010, 1533 }; 1534 1535 static const u32 jz4770_formats_f0[] = { 1536 DRM_FORMAT_C8, 1537 DRM_FORMAT_XRGB1555, 1538 DRM_FORMAT_RGB565, 1539 DRM_FORMAT_RGB888, 1540 DRM_FORMAT_XRGB8888, 1541 DRM_FORMAT_XRGB2101010, 1542 }; 1543 1544 static const struct jz_soc_info jz4740_soc_info = { 1545 .needs_dev_clk = true, 1546 .has_osd = false, 1547 .map_noncoherent = false, 1548 .max_width = 800, 1549 .max_height = 600, 1550 .max_burst = JZ_LCD_CTRL_BURST_16, 1551 .formats_f1 = jz4740_formats, 1552 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1553 /* JZ4740 has only one plane */ 1554 }; 1555 1556 static const struct jz_soc_info jz4725b_soc_info = { 1557 .needs_dev_clk = false, 1558 .has_osd = true, 1559 .map_noncoherent = false, 1560 .max_width = 800, 1561 .max_height = 600, 1562 .max_burst = JZ_LCD_CTRL_BURST_16, 1563 .formats_f1 = jz4725b_formats_f1, 1564 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1565 .formats_f0 = jz4725b_formats_f0, 1566 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1567 }; 1568 1569 static const struct jz_soc_info jz4760_soc_info = { 1570 .needs_dev_clk = false, 1571 .has_osd = true, 1572 .map_noncoherent = false, 1573 .max_width = 1280, 1574 .max_height = 720, 1575 .max_burst = JZ_LCD_CTRL_BURST_32, 1576 .formats_f1 = jz4770_formats_f1, 1577 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1578 .formats_f0 = jz4770_formats_f0, 1579 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1580 }; 1581 1582 static const struct jz_soc_info jz4760b_soc_info = { 1583 .needs_dev_clk = false, 1584 .has_osd = true, 1585 .map_noncoherent = false, 1586 .max_width = 1280, 1587 .max_height = 720, 1588 .max_burst = JZ_LCD_CTRL_BURST_64, 1589 .formats_f1 = jz4770_formats_f1, 1590 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1591 .formats_f0 = jz4770_formats_f0, 1592 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1593 }; 1594 1595 static const struct jz_soc_info jz4770_soc_info = { 1596 .needs_dev_clk = false, 1597 .has_osd = true, 1598 .map_noncoherent = true, 1599 .max_width = 1280, 1600 .max_height = 720, 1601 .max_burst = JZ_LCD_CTRL_BURST_64, 1602 .formats_f1 = jz4770_formats_f1, 1603 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1604 .formats_f0 = jz4770_formats_f0, 1605 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1606 }; 1607 1608 static const struct jz_soc_info jz4780_soc_info = { 1609 .needs_dev_clk = true, 1610 .has_osd = true, 1611 .has_alpha = true, 1612 .use_extended_hwdesc = true, 1613 .plane_f0_not_working = true, /* REVISIT */ 1614 .max_width = 4096, 1615 .max_height = 2048, 1616 .max_burst = JZ_LCD_CTRL_BURST_64, 1617 .formats_f1 = jz4770_formats_f1, 1618 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1619 .formats_f0 = jz4770_formats_f0, 1620 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1621 }; 1622 1623 static const struct of_device_id ingenic_drm_of_match[] = { 1624 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1625 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1626 { .compatible = "ingenic,jz4760-lcd", .data = &jz4760_soc_info }, 1627 { .compatible = "ingenic,jz4760b-lcd", .data = &jz4760b_soc_info }, 1628 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1629 { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, 1630 { /* sentinel */ }, 1631 }; 1632 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1633 1634 static struct platform_driver ingenic_drm_driver = { 1635 .driver = { 1636 .name = "ingenic-drm", 1637 .pm = pm_sleep_ptr(&ingenic_drm_pm_ops), 1638 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1639 }, 1640 .probe = ingenic_drm_probe, 1641 .remove = ingenic_drm_remove, 1642 .shutdown = ingenic_drm_shutdown, 1643 }; 1644 1645 static int ingenic_drm_init(void) 1646 { 1647 int err; 1648 1649 if (drm_firmware_drivers_only()) 1650 return -ENODEV; 1651 1652 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1653 err = platform_driver_register(ingenic_ipu_driver_ptr); 1654 if (err) 1655 return err; 1656 } 1657 1658 err = platform_driver_register(&ingenic_drm_driver); 1659 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && err) 1660 platform_driver_unregister(ingenic_ipu_driver_ptr); 1661 1662 return err; 1663 } 1664 module_init(ingenic_drm_init); 1665 1666 static void ingenic_drm_exit(void) 1667 { 1668 platform_driver_unregister(&ingenic_drm_driver); 1669 1670 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1671 platform_driver_unregister(ingenic_ipu_driver_ptr); 1672 } 1673 module_exit(ingenic_drm_exit); 1674 1675 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1676 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1677 MODULE_LICENSE("GPL"); 1678