1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 #include <linux/xarray.h> 48 49 #include <drm/ttm/ttm_bo.h> 50 #include <drm/ttm/ttm_placement.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_gem.h> 54 #include <drm/drm_ioctl.h> 55 56 #include <kgd_kfd_interface.h> 57 #include "dm_pp_interface.h" 58 #include "kgd_pp_interface.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_utils.h" 62 #include "amdgpu_mode.h" 63 #include "amdgpu_ih.h" 64 #include "amdgpu_irq.h" 65 #include "amdgpu_ucode.h" 66 #include "amdgpu_ttm.h" 67 #include "amdgpu_psp.h" 68 #include "amdgpu_gds.h" 69 #include "amdgpu_sync.h" 70 #include "amdgpu_ring.h" 71 #include "amdgpu_vm.h" 72 #include "amdgpu_dpm.h" 73 #include "amdgpu_acp.h" 74 #include "amdgpu_uvd.h" 75 #include "amdgpu_vce.h" 76 #include "amdgpu_vcn.h" 77 #include "amdgpu_jpeg.h" 78 #include "amdgpu_vpe.h" 79 #include "amdgpu_umsch_mm.h" 80 #include "amdgpu_gmc.h" 81 #include "amdgpu_gfx.h" 82 #include "amdgpu_sdma_types.h" 83 #include "amdgpu_lsdma.h" 84 #include "amdgpu_nbio.h" 85 #include "amdgpu_reg_access.h" 86 #include "amdgpu_hdp.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_mes_ctx.h" 91 #include "amdgpu_gart.h" 92 #include "amdgpu_debugfs.h" 93 #include "amdgpu_job.h" 94 #include "amdgpu_bo_list.h" 95 #include "amdgpu_gem.h" 96 #include "amdgpu_doorbell.h" 97 #include "amdgpu_amdkfd.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_umc.h" 100 #include "amdgpu_mmhub.h" 101 #include "amdgpu_gfxhub.h" 102 #include "amdgpu_df.h" 103 #include "amdgpu_smuio.h" 104 #include "amdgpu_fdinfo.h" 105 #include "amdgpu_mca.h" 106 #include "amdgpu_ras.h" 107 #include "amdgpu_lockdep.h" 108 #include "amdgpu_cper.h" 109 #include "amdgpu_xcp.h" 110 #include "amdgpu_seq64.h" 111 #include "amdgpu_reg_state.h" 112 #include "amdgpu_userq.h" 113 #include "amdgpu_eviction_fence.h" 114 #include "amdgpu_wb.h" 115 #include "amdgpu_ip.h" 116 #include "amdgpu_mes.h" 117 #include "amdgpu_sa.h" 118 #include "amdgpu_acpi.h" 119 #include "amdgpu_ualink.h" 120 #if defined(CONFIG_DRM_AMD_ISP) 121 #include "amdgpu_isp.h" 122 #endif 123 124 #define MAX_GPU_INSTANCE 64 125 126 #define GFX_SLICE_PERIOD_MS 250 127 128 struct amdgpu_gpu_instance { 129 struct amdgpu_device *adev; 130 int mgpu_fan_enabled; 131 }; 132 133 struct amdgpu_mgpu_info { 134 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 135 struct mutex mutex; 136 uint32_t num_gpu; 137 uint32_t num_dgpu; 138 uint32_t num_apu; 139 }; 140 141 struct amdgpu_hwip_reg_entry { 142 u32 hwip; 143 u32 inst; 144 u32 seg; 145 u32 reg_offset; 146 const char *reg_name; 147 }; 148 149 struct amdgpu_watchdog_timer { 150 bool timeout_fatal_disable; 151 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 152 }; 153 154 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 155 156 /* 157 * Modules parameters. 158 */ 159 extern int amdgpu_modeset; 160 extern int amdgpu_iommu_perfopt; 161 extern unsigned int amdgpu_vram_limit; 162 extern int amdgpu_vis_vram_limit; 163 extern int amdgpu_gart_size; 164 extern int amdgpu_gtt_size; 165 extern int amdgpu_moverate; 166 extern int amdgpu_audio; 167 extern int amdgpu_disp_priority; 168 extern int amdgpu_hw_i2c; 169 extern int amdgpu_pcie_gen2; 170 extern int amdgpu_msi; 171 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 172 extern int amdgpu_dpm; 173 extern int amdgpu_fw_load_type; 174 extern int amdgpu_aspm; 175 extern int amdgpu_runtime_pm; 176 extern uint amdgpu_ip_block_mask; 177 extern int amdgpu_bapm; 178 extern int amdgpu_deep_color; 179 extern int amdgpu_vm_size; 180 extern int amdgpu_vm_block_size; 181 extern int amdgpu_vm_fragment_size; 182 extern int amdgpu_vm_fault_stop; 183 extern int amdgpu_vm_debug; 184 extern int amdgpu_vm_update_mode; 185 extern int amdgpu_exp_hw_support; 186 extern int amdgpu_dc; 187 extern int amdgpu_sched_jobs; 188 extern int amdgpu_sched_hw_submission; 189 extern uint amdgpu_pcie_gen_cap; 190 extern uint amdgpu_pcie_lane_cap; 191 extern u64 amdgpu_cg_mask; 192 extern uint amdgpu_pg_mask; 193 extern uint amdgpu_sdma_phase_quantum; 194 extern char *amdgpu_disable_cu; 195 extern char *amdgpu_virtual_display; 196 extern uint amdgpu_pp_feature_mask; 197 extern uint amdgpu_force_long_training; 198 extern int amdgpu_lbpw; 199 extern int amdgpu_compute_multipipe; 200 extern int amdgpu_gpu_recovery; 201 extern int amdgpu_emu_mode; 202 extern uint amdgpu_smu_memory_pool_size; 203 extern int amdgpu_smu_pptable_id; 204 extern uint amdgpu_dc_feature_mask; 205 extern uint amdgpu_freesync_vid_mode; 206 extern uint amdgpu_dc_debug_mask; 207 extern uint amdgpu_dc_visual_confirm; 208 extern int amdgpu_dm_abm_level; 209 extern int amdgpu_backlight; 210 extern int amdgpu_damage_clips; 211 extern struct amdgpu_mgpu_info mgpu_info; 212 extern int amdgpu_ras_enable; 213 extern u64 amdgpu_ras_mask; 214 extern int amdgpu_bad_page_threshold; 215 extern bool amdgpu_ignore_bad_page_threshold; 216 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 217 extern int amdgpu_async_gfx_ring; 218 extern int amdgpu_mcbp; 219 extern int amdgpu_discovery; 220 extern int amdgpu_mes_log_enable; 221 extern int amdgpu_mes_dbgext_buffer_size; 222 extern int amdgpu_mes_dbgext_options; 223 extern int amdgpu_uni_mes; 224 extern int amdgpu_noretry; 225 extern int amdgpu_force_asic_type; 226 extern int amdgpu_smartshift_bias; 227 extern int amdgpu_use_xgmi_p2p; 228 extern int amdgpu_mtype_local; 229 extern int amdgpu_mtype_remote; 230 extern int amdgpu_enforce_isolation; 231 extern uint amdgpu_debug_mask; 232 #ifdef CONFIG_HSA_AMD 233 extern int sched_policy; 234 extern bool debug_evictions; 235 extern bool no_system_mem_limit; 236 extern int halt_if_hws_hang; 237 extern uint amdgpu_svm_default_granularity; 238 #else 239 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 240 static const bool __maybe_unused debug_evictions; /* = false */ 241 static const bool __maybe_unused no_system_mem_limit; 242 static const int __maybe_unused halt_if_hws_hang; 243 #endif 244 #ifdef CONFIG_HSA_AMD_P2P 245 extern bool pcie_p2p; 246 #endif 247 248 extern int amdgpu_tmz; 249 extern int amdgpu_reset_method; 250 251 #ifdef CONFIG_DRM_AMDGPU_SI 252 extern int amdgpu_si_support; 253 #endif 254 #ifdef CONFIG_DRM_AMDGPU_CIK 255 extern int amdgpu_cik_support; 256 #endif 257 extern int amdgpu_num_kcq; 258 259 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 260 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 261 extern int amdgpu_vcnfw_log; 262 extern int amdgpu_sg_display; 263 extern int amdgpu_umsch_mm; 264 extern int amdgpu_seamless; 265 extern int amdgpu_umsch_mm_fwlog; 266 267 extern int amdgpu_user_partt_mode; 268 extern int amdgpu_agp; 269 extern int amdgpu_rebar; 270 271 extern int amdgpu_wbrf; 272 extern int amdgpu_user_queue; 273 extern int amdgpu_ptl; 274 275 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 276 277 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 278 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 279 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 280 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 281 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 282 #define AMDGPUFB_CONN_LIMIT 4 283 #define AMDGPU_BIOS_NUM_SCRATCH 16 284 285 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 286 287 /* hard reset data */ 288 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 289 290 /* reset flags */ 291 #define AMDGPU_RESET_GFX (1 << 0) 292 #define AMDGPU_RESET_COMPUTE (1 << 1) 293 #define AMDGPU_RESET_DMA (1 << 2) 294 #define AMDGPU_RESET_CP (1 << 3) 295 #define AMDGPU_RESET_GRBM (1 << 4) 296 #define AMDGPU_RESET_DMA1 (1 << 5) 297 #define AMDGPU_RESET_RLC (1 << 6) 298 #define AMDGPU_RESET_SEM (1 << 7) 299 #define AMDGPU_RESET_IH (1 << 8) 300 #define AMDGPU_RESET_VMC (1 << 9) 301 #define AMDGPU_RESET_MC (1 << 10) 302 #define AMDGPU_RESET_DISPLAY (1 << 11) 303 #define AMDGPU_RESET_UVD (1 << 12) 304 #define AMDGPU_RESET_VCE (1 << 13) 305 #define AMDGPU_RESET_VCE1 (1 << 14) 306 307 /* reset mask */ 308 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 309 #define AMDGPU_RESET_TYPE_SOFT_RECOVERY (1 << 1) /* soft recovery, eg. kill shaders */ 310 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 311 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 312 #define AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET (1 << 4) /* soft-resets an IP block */ 313 314 /* max cursor sizes (in pixels) */ 315 #define CIK_CURSOR_WIDTH 128 316 #define CIK_CURSOR_HEIGHT 128 317 318 /* smart shift bias level limits */ 319 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 320 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 321 322 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 323 #define AMDGPU_SWCTF_EXTRA_DELAY 50 324 325 struct amdgpu_xcp_mgr; 326 struct amdgpu_device; 327 struct amdgpu_irq_src; 328 struct amdgpu_fpriv; 329 struct amdgpu_bo_va_mapping; 330 struct kfd_vm_fault_info; 331 struct amdgpu_hive_info; 332 struct amdgpu_reset_context; 333 struct amdgpu_reset_control; 334 struct amdgpu_coredump_info; 335 struct amdgpu_video_codecs; 336 337 enum amdgpu_cp_irq { 338 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 339 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 345 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 346 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 347 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 348 349 AMDGPU_CP_IRQ_LAST 350 }; 351 352 enum amdgpu_thermal_irq { 353 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 354 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 355 356 AMDGPU_THERMAL_IRQ_LAST 357 }; 358 359 enum amdgpu_kiq_irq { 360 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 361 AMDGPU_CP_KIQ_IRQ_LAST 362 }; 363 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 364 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 365 #define MAX_KIQ_REG_TRY 1000 366 367 /* 368 * BIOS. 369 */ 370 bool amdgpu_get_bios(struct amdgpu_device *adev); 371 bool amdgpu_read_bios(struct amdgpu_device *adev); 372 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 373 u8 *bios, u32 length_bytes); 374 void amdgpu_bios_release(struct amdgpu_device *adev); 375 /* 376 * Clocks 377 */ 378 379 #define AMDGPU_MAX_PPLL 3 380 381 struct amdgpu_clock { 382 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 383 struct amdgpu_pll spll; 384 struct amdgpu_pll mpll; 385 /* 10 Khz units */ 386 uint32_t default_mclk; 387 uint32_t default_sclk; 388 uint32_t default_dispclk; 389 uint32_t dp_extclk; 390 uint32_t max_pixel_clock; 391 }; 392 393 /* 394 * IRQS. 395 */ 396 397 struct amdgpu_flip_work { 398 struct delayed_work flip_work; 399 struct work_struct unpin_work; 400 struct amdgpu_device *adev; 401 int crtc_id; 402 u32 target_vblank; 403 uint64_t base; 404 struct drm_pending_vblank_event *event; 405 struct amdgpu_bo *old_abo; 406 unsigned shared_count; 407 struct dma_fence **shared; 408 struct dma_fence_cb cb; 409 bool async; 410 }; 411 412 /* 413 * file private structure 414 */ 415 416 struct amdgpu_fpriv { 417 struct amdgpu_vm vm; 418 struct amdgpu_bo_va *prt_va; 419 struct amdgpu_bo_va *csa_va; 420 struct amdgpu_bo_va *seq64_va; 421 struct xarray bo_list_handles; 422 struct amdgpu_ctx_mgr ctx_mgr; 423 struct amdgpu_userq_mgr userq_mgr; 424 425 /* Eviction fence infra */ 426 struct amdgpu_eviction_fence_mgr evf_mgr; 427 428 /** GPU partition selection */ 429 uint32_t xcp_id; 430 }; 431 432 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 433 434 /* 435 * Benchmarking 436 */ 437 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 438 439 /* 440 * ASIC specific functions. 441 */ 442 struct amdgpu_asic_funcs { 443 bool (*read_disabled_bios)(struct amdgpu_device *adev); 444 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 445 u8 *bios, u32 length_bytes); 446 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 447 u32 sh_num, u32 reg_offset, u32 *value); 448 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 449 int (*reset)(struct amdgpu_device *adev); 450 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 451 /* get the reference clock */ 452 u32 (*get_xclk)(struct amdgpu_device *adev); 453 /* MM block clocks */ 454 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 455 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 456 /* static power management */ 457 int (*get_pcie_lanes)(struct amdgpu_device *adev); 458 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 459 /* get config memsize register */ 460 u32 (*get_config_memsize)(struct amdgpu_device *adev); 461 /* flush hdp write queue */ 462 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 463 /* invalidate hdp read cache */ 464 void (*invalidate_hdp)(struct amdgpu_device *adev, 465 struct amdgpu_ring *ring); 466 /* initialize doorbell layout for specific asic*/ 467 void (*init_doorbell_index)(struct amdgpu_device *adev); 468 /* PCIe bandwidth usage */ 469 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 470 uint64_t *count1); 471 /* do we need to reset the asic at init time (e.g., kexec) */ 472 bool (*need_reset_on_init)(struct amdgpu_device *adev); 473 /* PCIe replay counter */ 474 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 475 /* device supports BACO */ 476 int (*supports_baco)(struct amdgpu_device *adev); 477 /* pre asic_init quirks */ 478 void (*pre_asic_init)(struct amdgpu_device *adev); 479 /* enter/exit umd stable pstate */ 480 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 481 /* query video codecs */ 482 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 483 const struct amdgpu_video_codecs **codecs); 484 /* encode "> 32bits" smn addressing */ 485 u64 (*encode_ext_smn_addressing)(int ext_id); 486 487 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 488 enum amdgpu_reg_state reg_state, void *buf, 489 size_t max_size); 490 /* query FW reserved region (size/offset) from discovery */ 491 void (*get_fw_reserved_info)(struct amdgpu_device *adev, 492 u64 *reserve_size, u64 *offset); 493 }; 494 495 /* 496 * IOCTL. 497 */ 498 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 499 struct drm_file *filp); 500 501 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 502 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 503 struct drm_file *filp); 504 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 505 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 506 struct drm_file *filp); 507 508 /* VRAM scratch page for HDP bug, default vram page */ 509 struct amdgpu_mem_scratch { 510 struct amdgpu_bo *robj; 511 uint32_t *ptr; 512 u64 gpu_addr; 513 }; 514 515 /* 516 * CGS 517 */ 518 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 519 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 520 521 /* 522 * Core structure, functions and helpers. 523 */ 524 struct amdgpu_mmio_remap { 525 u32 reg_offset; 526 resource_size_t bus_addr; 527 struct amdgpu_bo *bo; 528 }; 529 530 enum amdgpu_uid_type { 531 AMDGPU_UID_TYPE_XCD, 532 AMDGPU_UID_TYPE_AID, 533 AMDGPU_UID_TYPE_SOC, 534 AMDGPU_UID_TYPE_MID, 535 AMDGPU_UID_TYPE_MAX 536 }; 537 538 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 539 540 struct amdgpu_uid { 541 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 542 struct amdgpu_device *adev; 543 }; 544 545 struct amd_powerplay { 546 void *pp_handle; 547 const struct amd_pm_funcs *pp_funcs; 548 }; 549 550 /* polaris10 kickers */ 551 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 552 ((rid == 0xE3) || \ 553 (rid == 0xE4) || \ 554 (rid == 0xE5) || \ 555 (rid == 0xE7) || \ 556 (rid == 0xEF))) || \ 557 ((did == 0x6FDF) && \ 558 ((rid == 0xE7) || \ 559 (rid == 0xEF) || \ 560 (rid == 0xFF)))) 561 562 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 563 ((rid == 0xE1) || \ 564 (rid == 0xF7))) 565 566 /* polaris11 kickers */ 567 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 568 ((rid == 0xE0) || \ 569 (rid == 0xE5))) || \ 570 ((did == 0x67FF) && \ 571 ((rid == 0xCF) || \ 572 (rid == 0xEF) || \ 573 (rid == 0xFF)))) 574 575 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 576 ((rid == 0xE2))) 577 578 /* polaris12 kickers */ 579 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 580 ((rid == 0xC0) || \ 581 (rid == 0xC1) || \ 582 (rid == 0xC3) || \ 583 (rid == 0xC7))) || \ 584 ((did == 0x6981) && \ 585 ((rid == 0x00) || \ 586 (rid == 0x01) || \ 587 (rid == 0x10)))) 588 589 struct amdgpu_pcie_reset_ctx { 590 bool in_link_reset; 591 bool occurs_dpc; 592 bool audio_suspended; 593 struct pci_dev *swus; 594 struct pci_saved_state *swus_pcistate; 595 struct pci_saved_state *swds_pcistate; 596 }; 597 598 /* 599 * Custom Init levels could be defined for different situations where a full 600 * initialization of all hardware blocks are not expected. Sample cases are 601 * custom init sequences after resume after S0i3/S3, reset on initialization, 602 * partial reset of blocks etc. Presently, this defines only two levels. Levels 603 * are described in corresponding struct definitions - amdgpu_init_default, 604 * amdgpu_init_minimal_xgmi. 605 */ 606 enum amdgpu_init_lvl_id { 607 AMDGPU_INIT_LEVEL_DEFAULT, 608 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 609 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 610 }; 611 612 struct amdgpu_init_level { 613 enum amdgpu_init_lvl_id level; 614 uint32_t hwini_ip_block_mask; 615 }; 616 617 #define AMDGPU_RESET_MAGIC_NUM 64 618 #define AMDGPU_MAX_DF_PERFMONS 4 619 struct amdgpu_reset_domain; 620 struct amdgpu_fru_info; 621 622 enum amdgpu_enforce_isolation_mode { 623 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 624 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 625 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 626 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 627 }; 628 629 struct amdgpu_device { 630 struct device *dev; 631 struct pci_dev *pdev; 632 /* The two ends of the physical PCIe link outside the device. */ 633 struct pci_dev *link_dev; 634 struct pci_dev *link_partner; 635 struct drm_device ddev; 636 637 #ifdef CONFIG_DRM_AMD_ACP 638 struct amdgpu_acp acp; 639 #endif 640 struct amdgpu_hive_info *hive; 641 struct amdgpu_xcp_mgr *xcp_mgr; 642 /* ASIC */ 643 enum amd_asic_type asic_type; 644 uint32_t family; 645 uint32_t rev_id; 646 uint32_t external_rev_id; 647 unsigned long flags; 648 unsigned long apu_flags; 649 int usec_timeout; 650 const struct amdgpu_asic_funcs *asic_funcs; 651 bool shutdown; 652 bool need_swiotlb; 653 bool accel_working; 654 struct notifier_block acpi_nb; 655 struct notifier_block pm_nb; 656 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 657 struct debugfs_blob_wrapper debugfs_vbios_blob; 658 struct mutex srbm_mutex; 659 /* GRBM index mutex. Protects concurrent access to GRBM index */ 660 struct mutex grbm_idx_mutex; 661 struct dev_pm_domain vga_pm_domain; 662 bool have_disp_power_ref; 663 bool have_atomics_support; 664 bool is_sw_smu; 665 666 /* BIOS */ 667 bool is_atom_fw; 668 uint8_t *bios; 669 uint32_t bios_size; 670 uint32_t bios_scratch_reg_offset; 671 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 672 673 /* Register/doorbell mmio */ 674 resource_size_t rmmio_base; 675 resource_size_t rmmio_size; 676 void __iomem *rmmio; 677 /* protects concurrent MM_INDEX/DATA based register access */ 678 spinlock_t mmio_idx_lock; 679 struct amdgpu_mmio_remap rmmio_remap; 680 /* Indirect register access blocks */ 681 struct amdgpu_reg_access reg; 682 struct amdgpu_doorbell doorbell; 683 684 /* clock/pll info */ 685 struct amdgpu_clock clock; 686 687 /* MC */ 688 struct amdgpu_gmc gmc; 689 struct amdgpu_gart gart; 690 dma_addr_t dummy_page_addr; 691 struct amdgpu_vm_manager vm_manager; 692 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 693 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 694 695 /* memory management */ 696 struct amdgpu_mman mman; 697 struct amdgpu_mem_scratch mem_scratch; 698 struct amdgpu_wb wb; 699 atomic64_t num_bytes_moved; 700 atomic64_t num_evictions; 701 atomic64_t num_vram_cpu_page_faults; 702 atomic_t gpu_reset_counter; 703 atomic_t vram_lost_counter; 704 705 /* data for buffer migration throttling */ 706 struct { 707 spinlock_t lock; 708 s64 last_update_us; 709 s64 accum_us; /* accumulated microseconds */ 710 s64 accum_us_vis; /* for visible VRAM */ 711 u32 log2_max_MBps; 712 } mm_stats; 713 714 /* discovery*/ 715 struct amdgpu_discovery_info discovery; 716 717 /* display */ 718 bool enable_virtual_display; 719 struct amdgpu_vkms_output *amdgpu_vkms_output; 720 struct amdgpu_mode_info mode_info; 721 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 722 struct delayed_work hotplug_work; 723 struct amdgpu_irq_src crtc_irq; 724 struct amdgpu_irq_src vline0_irq; 725 struct amdgpu_irq_src vupdate_irq; 726 struct amdgpu_irq_src pageflip_irq; 727 struct amdgpu_irq_src hpd_irq; 728 struct amdgpu_irq_src dmub_trace_irq; 729 struct amdgpu_irq_src dmub_outbox_irq; 730 731 /* rings */ 732 u64 fence_context; 733 unsigned num_rings; 734 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 735 struct dma_fence __rcu *gang_submit; 736 bool ib_pool_ready; 737 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 738 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 739 740 /* interrupts */ 741 struct amdgpu_irq irq; 742 743 /* powerplay */ 744 struct amd_powerplay powerplay; 745 struct amdgpu_pm pm; 746 u64 cg_flags; 747 u32 pg_flags; 748 749 /* nbio */ 750 struct amdgpu_nbio nbio; 751 752 /* hdp */ 753 struct amdgpu_hdp hdp; 754 755 /* smuio */ 756 struct amdgpu_smuio smuio; 757 758 /* mmhub */ 759 struct amdgpu_mmhub mmhub; 760 761 /* gfxhub */ 762 struct amdgpu_gfxhub gfxhub; 763 764 /* gfx */ 765 struct amdgpu_gfx gfx; 766 767 /* sdma */ 768 struct amdgpu_sdma sdma; 769 770 /* lsdma */ 771 struct amdgpu_lsdma lsdma; 772 773 /* uvd */ 774 struct amdgpu_uvd uvd; 775 776 /* vce */ 777 struct amdgpu_vce vce; 778 779 /* vcn */ 780 struct amdgpu_vcn vcn; 781 782 /* jpeg */ 783 struct amdgpu_jpeg jpeg; 784 785 /* vpe */ 786 struct amdgpu_vpe vpe; 787 788 /* umsch */ 789 struct amdgpu_umsch_mm umsch_mm; 790 bool enable_umsch_mm; 791 792 /* firmwares */ 793 struct amdgpu_firmware firmware; 794 795 /* PSP */ 796 struct psp_context psp; 797 798 /* GDS */ 799 struct amdgpu_gds gds; 800 801 /* for userq and VM fences */ 802 struct amdgpu_seq64 seq64; 803 804 /* UMC */ 805 struct amdgpu_umc umc; 806 807 /* display related functionality */ 808 struct amdgpu_display_manager dm; 809 810 /* UALink manager */ 811 struct amdgpu_ualink_mgr ualink; 812 813 #if defined(CONFIG_DRM_AMD_ISP) 814 /* isp */ 815 struct amdgpu_isp isp; 816 #endif 817 818 /* mes */ 819 bool enable_mes; 820 bool enable_mes_kiq; 821 bool enable_uni_mes; 822 struct amdgpu_mes mes; 823 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 824 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 825 826 /** 827 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 828 * Key: doorbell_index (unique global identifier for the queue) 829 * Value: struct amdgpu_usermode_queue 830 */ 831 struct xarray userq_doorbell_xa; 832 833 /* df */ 834 struct amdgpu_df df; 835 836 /* MCA */ 837 struct amdgpu_mca mca; 838 839 /* CPER */ 840 struct amdgpu_cper cper; 841 842 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 843 uint32_t harvest_ip_mask; 844 int num_ip_blocks; 845 struct mutex mn_lock; 846 DECLARE_HASHTABLE(mn_hash, 7); 847 848 /* tracking pinned memory 849 * 850 * vram_pin_size = sum(vram_pin_size_xcp[]) + vram_pin_size_common 851 * 852 * vram_pin_size total pin size in device 853 * vram_pin_size_xcp[i] pins owned by partition i (bo->xcp_id = i, i >= 0) 854 * vram_pin_size_common pins not owned by any partition, bo->xcp_id = -1 855 */ 856 atomic64_t vram_pin_size; 857 atomic64_t vram_pin_size_xcp[MAX_XCP]; 858 atomic64_t vram_pin_size_common; 859 atomic64_t visible_pin_size; 860 atomic64_t gart_pin_size; 861 862 /* soc15 register offset based on ip, instance and segment */ 863 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 864 struct amdgpu_ip_map_info ip_map; 865 866 /* delayed work_func for deferring clockgating during resume */ 867 struct delayed_work delayed_init_work; 868 869 struct amdgpu_virt virt; 870 871 /* record hw reset is performed */ 872 bool has_hw_reset; 873 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 874 875 /* s3/s4 mask */ 876 bool in_suspend; 877 bool in_s3; 878 bool in_s4; 879 bool in_s0ix; 880 suspend_state_t last_suspend_state; 881 882 enum pp_mp1_state mp1_state; 883 struct amdgpu_doorbell_index doorbell_index; 884 885 struct mutex notifier_lock; 886 887 int asic_reset_res; 888 struct work_struct xgmi_reset_work; 889 struct list_head reset_list; 890 891 long gfx_timeout; 892 long sdma_timeout; 893 long video_timeout; 894 long compute_timeout; 895 long psp_timeout; 896 897 uint64_t unique_id; 898 uint8_t unitid; 899 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 900 901 /* enable runtime pm on the device */ 902 bool in_runpm; 903 bool has_pr3; 904 905 bool ucode_sysfs_en; 906 907 struct amdgpu_fru_info *fru_info; 908 atomic_t throttling_logging_enabled; 909 struct ratelimit_state throttling_logging_rs; 910 uint32_t ras_hw_enabled; 911 uint32_t ras_enabled; 912 bool ras_default_ecc_enabled; 913 914 bool no_hw_access; 915 struct pci_saved_state *pci_state; 916 pci_channel_state_t pci_channel_state; 917 918 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 919 920 /* Track auto wait count on s_barrier settings */ 921 bool barrier_has_auto_waitcnt; 922 923 struct amdgpu_reset_control *reset_cntl; 924 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 925 926 bool ram_is_direct_mapped; 927 928 struct list_head ras_list; 929 930 struct amdgpu_reset_domain *reset_domain; 931 932 #ifdef CONFIG_DEV_COREDUMP 933 struct amdgpu_coredump_info *coredump; 934 struct work_struct coredump_work; 935 #endif 936 937 struct mutex benchmark_mutex; 938 939 bool scpm_enabled; 940 uint32_t scpm_status; 941 942 struct work_struct reset_work; 943 944 bool dc_enabled; 945 /* Mask of active clusters */ 946 uint32_t aid_mask; 947 948 /* Debug */ 949 bool debug_vm; 950 bool debug_largebar; 951 bool debug_disable_soft_recovery; 952 bool debug_use_vram_fw_buf; 953 bool debug_exp_resets; 954 bool debug_disable_gpu_ring_reset; 955 bool debug_vm_userptr; 956 bool debug_disable_ce_logs; 957 bool debug_enable_ce_cs; 958 bool debug_hibernation_thaw_resume_gpu; 959 bool debug_disable_ip_block_soft_reset; 960 961 /* Protection for the following isolation structure */ 962 struct mutex enforce_isolation_mutex; 963 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 964 struct amdgpu_isolation { 965 void *owner; 966 struct dma_fence *spearhead; 967 struct amdgpu_sync active; 968 struct amdgpu_sync prev; 969 } isolation[MAX_XCP]; 970 971 struct amdgpu_init_level *init_lvl; 972 973 /* This flag is used to determine how VRAM allocations are handled for APUs 974 * in KFD: VRAM or GTT. 975 */ 976 bool apu_prefer_gtt; 977 978 bool userq_halt_for_enforce_isolation; 979 struct amdgpu_uid *uid_info; 980 981 struct amdgpu_uma_carveout_info uma_info; 982 983 /* KFD 984 * Must be last --ends in a flexible-array member. 985 */ 986 struct amdgpu_kfd_dev kfd; 987 }; 988 989 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 990 uint8_t ip, uint8_t inst) 991 { 992 /* This considers only major/minor/rev and ignores 993 * subrevision/variant fields. 994 */ 995 return adev->ip_versions[ip][inst] & ~0xFFU; 996 } 997 998 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 999 uint8_t ip, uint8_t inst) 1000 { 1001 /* This returns full version - major/minor/rev/variant/subrevision */ 1002 return adev->ip_versions[ip][inst]; 1003 } 1004 1005 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1006 { 1007 return container_of(ddev, struct amdgpu_device, ddev); 1008 } 1009 1010 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1011 { 1012 return &adev->ddev; 1013 } 1014 1015 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1016 { 1017 return container_of(bdev, struct amdgpu_device, mman.bdev); 1018 } 1019 1020 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1021 { 1022 return !!adev->aid_mask; 1023 } 1024 1025 int amdgpu_device_init(struct amdgpu_device *adev, 1026 uint32_t flags); 1027 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1028 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1029 1030 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1031 1032 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1033 void *buf, size_t size, bool write); 1034 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1035 void *buf, size_t size, bool write); 1036 1037 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1038 void *buf, size_t size, bool write); 1039 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1040 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1041 enum amd_asic_type asic_type); 1042 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1043 1044 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1045 1046 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1047 struct amdgpu_reset_context *reset_context); 1048 1049 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1050 struct amdgpu_reset_context *reset_context); 1051 1052 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1053 1054 int emu_soc_asic_init(struct amdgpu_device *adev); 1055 1056 /* 1057 * Registers read & write functions. 1058 */ 1059 #define AMDGPU_REGS_NO_KIQ (1<<1) 1060 #define AMDGPU_REGS_RLC (1<<2) 1061 1062 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1063 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1064 1065 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1066 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1067 1068 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1069 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1070 1071 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1072 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1073 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1074 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1075 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1076 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1077 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1078 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1079 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1080 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1081 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1082 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1083 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1084 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1085 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1086 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1087 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1088 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1089 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1090 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1091 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1092 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1093 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1094 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1095 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1096 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1097 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1098 #define RREG32_AUDIO_ENDPT(block, reg) \ 1099 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1100 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1101 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1102 #define WREG32_P(reg, val, mask) \ 1103 do { \ 1104 uint32_t tmp_ = RREG32(reg); \ 1105 tmp_ &= (mask); \ 1106 tmp_ |= ((val) & ~(mask)); \ 1107 WREG32(reg, tmp_); \ 1108 } while (0) 1109 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1110 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1111 #define WREG32_PLL_P(reg, val, mask) \ 1112 do { \ 1113 uint32_t tmp_ = RREG32_PLL(reg); \ 1114 tmp_ &= (mask); \ 1115 tmp_ |= ((val) & ~(mask)); \ 1116 WREG32_PLL(reg, tmp_); \ 1117 } while (0) 1118 1119 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1120 do { \ 1121 u32 tmp = RREG32_SMC(_Reg); \ 1122 tmp &= (_Mask); \ 1123 tmp |= ((_Val) & ~(_Mask)); \ 1124 WREG32_SMC(_Reg, tmp); \ 1125 } while (0) 1126 1127 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1128 1129 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1130 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1131 1132 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1133 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1134 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1135 1136 #define REG_GET_FIELD(value, reg, field) \ 1137 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1138 1139 #define WREG32_FIELD(reg, field, val) \ 1140 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1141 1142 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1143 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1144 1145 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1146 /* 1147 * BIOS helpers. 1148 */ 1149 #define RBIOS8(i) (adev->bios[i]) 1150 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1151 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1152 1153 #include "amdgpu_reset.h" 1154 1155 /* 1156 * ASICs macro. 1157 */ 1158 #define amdgpu_asic_set_vga_state(adev, state) \ 1159 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1160 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1161 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1162 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1163 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1164 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1165 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1166 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1167 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1168 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1169 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1170 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1171 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1172 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1173 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1174 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1175 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1176 #define amdgpu_asic_supports_baco(adev) \ 1177 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1178 #define amdgpu_asic_pre_asic_init(adev) \ 1179 { \ 1180 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1181 (adev)->asic_funcs->pre_asic_init((adev)); \ 1182 } 1183 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1184 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1185 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1186 1187 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1188 1189 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1190 #define for_each_inst(i, inst_mask) \ 1191 for (i = ffs(inst_mask); i-- != 0; \ 1192 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1193 1194 /* Common functions */ 1195 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1196 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1197 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1198 struct amdgpu_job *job, 1199 struct amdgpu_reset_context *reset_context); 1200 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1201 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1202 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1203 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1204 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1205 1206 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1207 u64 num_vis_bytes); 1208 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1209 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1210 const u32 *registers, 1211 const u32 array_size); 1212 1213 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1214 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1215 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1216 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1217 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1218 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1219 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1220 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1221 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1222 struct amdgpu_device *peer_adev); 1223 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1224 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1225 1226 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1227 struct amdgpu_ring *ring); 1228 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1229 struct amdgpu_ring *ring); 1230 1231 void amdgpu_device_halt(struct amdgpu_device *adev); 1232 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1233 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1234 struct dma_fence *gang); 1235 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1236 struct amdgpu_ring *ring, 1237 struct amdgpu_job *job); 1238 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1239 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1240 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1241 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1242 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1243 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1244 const struct amdgpu_buffer_funcs *buffer_funcs); 1245 1246 /* atpx handler */ 1247 #if defined(CONFIG_VGA_SWITCHEROO) 1248 void amdgpu_register_atpx_handler(void); 1249 void amdgpu_unregister_atpx_handler(void); 1250 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1251 bool amdgpu_is_atpx_hybrid(void); 1252 bool amdgpu_has_atpx(void); 1253 #else 1254 static inline void amdgpu_register_atpx_handler(void) {} 1255 static inline void amdgpu_unregister_atpx_handler(void) {} 1256 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1257 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1258 static inline bool amdgpu_has_atpx(void) { return false; } 1259 #endif 1260 1261 /* 1262 * KMS 1263 */ 1264 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1265 extern const int amdgpu_max_kms_ioctl; 1266 1267 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1268 void amdgpu_driver_unload_kms(struct drm_device *dev); 1269 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1270 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1271 struct drm_file *file_priv); 1272 void amdgpu_driver_release_kms(struct drm_device *dev); 1273 1274 int amdgpu_device_prepare(struct drm_device *dev); 1275 void amdgpu_device_complete(struct drm_device *dev); 1276 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1277 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1278 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1279 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1280 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1281 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1282 struct drm_file *filp); 1283 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1284 struct drm_file *filp); 1285 1286 /* 1287 * functions used by amdgpu_encoder.c 1288 */ 1289 struct amdgpu_afmt_acr { 1290 u32 clock; 1291 1292 int n_32khz; 1293 int cts_32khz; 1294 1295 int n_44_1khz; 1296 int cts_44_1khz; 1297 1298 int n_48khz; 1299 int cts_48khz; 1300 1301 }; 1302 1303 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1304 1305 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1306 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1307 1308 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1309 pci_channel_state_t state); 1310 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1311 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1312 void amdgpu_pci_resume(struct pci_dev *pdev); 1313 1314 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1315 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1316 1317 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1318 1319 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1320 enum amd_clockgating_state state); 1321 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1322 enum amd_powergating_state state); 1323 1324 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1325 { 1326 return amdgpu_gpu_recovery != 0 && 1327 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1328 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1329 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1330 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1331 } 1332 1333 #include "amdgpu_object.h" 1334 1335 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1336 { 1337 return adev->gmc.tmz_enabled; 1338 } 1339 1340 int amdgpu_in_reset(struct amdgpu_device *adev); 1341 1342 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1343 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1344 extern const struct attribute_group amdgpu_flash_attr_group; 1345 1346 void amdgpu_set_init_level(struct amdgpu_device *adev, 1347 enum amdgpu_init_lvl_id lvl); 1348 1349 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1350 { 1351 u32 status; 1352 int r; 1353 1354 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1355 if (r || PCI_POSSIBLE_ERROR(status)) { 1356 dev_err(adev->dev, "device lost from bus!"); 1357 return -ENODEV; 1358 } 1359 1360 return 0; 1361 } 1362 1363 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1364 enum amdgpu_uid_type type, uint8_t inst, 1365 uint64_t uid); 1366 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1367 enum amdgpu_uid_type type, uint8_t inst); 1368 #endif 1369