1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
26
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo.h>
33 #include <linux/sched/mm.h>
34
35 #include "amdgpu_sync.h"
36 #include "amdgpu_ring.h"
37 #include "amdgpu_ids.h"
38 #include "amdgpu_ttm.h"
39
40 struct drm_exec;
41
42 struct amdgpu_bo_va;
43 struct amdgpu_job;
44 struct amdgpu_bo_list_entry;
45 struct amdgpu_bo_vm;
46
47 /*
48 * GPUVM handling
49 */
50
51 /* Maximum number of PTEs the hardware can write with one command */
52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
53
54 /* number of entries in page table */
55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
56
57 #define AMDGPU_PTE_VALID (1ULL << 0)
58 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
59 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
60
61 /* RV+ */
62 #define AMDGPU_PTE_TMZ (1ULL << 3)
63
64 /* VI only */
65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
66
67 #define AMDGPU_PTE_READABLE (1ULL << 5)
68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
69
70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
71
72 /* TILED for VEGA10, reserved for older ASICs */
73 #define AMDGPU_PTE_PRT (1ULL << 51)
74
75 /* PDE is handled as PTE for VEGA10 */
76 #define AMDGPU_PDE_PTE (1ULL << 54)
77
78 #define AMDGPU_PTE_LOG (1ULL << 55)
79
80 /* PTE is handled as PDE for VEGA10 (Translate Further) */
81 #define AMDGPU_PTE_TF (1ULL << 56)
82
83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */
84 #define AMDGPU_PTE_NOALLOC (1ULL << 58)
85
86 /* PDE Block Fragment Size for VEGA10 */
87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
88
89 /* Flag combination to set no-retry with TF disabled */
90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \
91 AMDGPU_PTE_TF)
92
93 /* Flag combination to set no-retry with TF enabled */
94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \
95 AMDGPU_PTE_PRT)
96 /* For GFX9 */
97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57)
98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL)
99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \
100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \
101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
102
103 #define AMDGPU_MTYPE_NC 0
104 #define AMDGPU_MTYPE_CC 2
105
106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
107 | AMDGPU_PTE_SNOOPED \
108 | AMDGPU_PTE_EXECUTABLE \
109 | AMDGPU_PTE_READABLE \
110 | AMDGPU_PTE_WRITEABLE \
111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
112
113 /* gfx10 */
114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48)
115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL)
116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \
117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \
118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype))
119
120 /* gfx12 */
121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56)
122 #define AMDGPU_PTE_PRT_FLAG(adev) \
123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)
124
125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54)
126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL)
127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \
128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \
129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype))
130
131 #define AMDGPU_PTE_DCC (1ULL << 58)
132 #define AMDGPU_PTE_IS_PTE (1ULL << 63)
133
134 /* PDE Block Fragment Size for gfx v12 */
135 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58)
136 #define AMDGPU_PDE_BFS_FLAG(adev, a) \
137 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a))
138 /* PDE is handled as PTE for gfx v12 */
139 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63)
140 #define AMDGPU_PDE_PTE_FLAG(adev) \
141 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE)
142
143 /* How to program VM fault handling */
144 #define AMDGPU_VM_FAULT_STOP_NEVER 0
145 #define AMDGPU_VM_FAULT_STOP_FIRST 1
146 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
147
148 /* How much VRAM be reserved for page tables */
149 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
150
151 /*
152 * max number of VMHUB
153 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1
154 */
155 #define AMDGPU_MAX_VMHUBS 13
156 #define AMDGPU_GFXHUB_START 0
157 #define AMDGPU_MMHUB0_START 8
158 #define AMDGPU_MMHUB1_START 12
159 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x))
160 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x))
161 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x))
162
163 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START)
164 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START)
165 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS)
166
167 /* Reserve space at top/bottom of address space for kernel use */
168 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20)
169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
170 << AMDGPU_GPU_PAGE_SHIFT) \
171 - AMDGPU_VA_RESERVED_CSA_SIZE)
172 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20)
173 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \
174 - AMDGPU_VA_RESERVED_SEQ64_SIZE)
175 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12)
176 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \
177 - AMDGPU_VA_RESERVED_TRAP_SIZE)
178 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16)
179 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \
180 AMDGPU_VA_RESERVED_SEQ64_SIZE + \
181 AMDGPU_VA_RESERVED_CSA_SIZE)
182
183 /* See vm_update_mode */
184 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
185 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
186
187 /* VMPT level enumerate, and the hiberachy is:
188 * PDB2->PDB1->PDB0->PTB
189 */
190 enum amdgpu_vm_level {
191 AMDGPU_VM_PDB2,
192 AMDGPU_VM_PDB1,
193 AMDGPU_VM_PDB0,
194 AMDGPU_VM_PTB
195 };
196
197 /* base structure for tracking BO usage in a VM */
198 struct amdgpu_vm_bo_base {
199 /* constant after initialization */
200 struct amdgpu_vm *vm;
201 struct amdgpu_bo *bo;
202
203 /* protected by bo being reserved */
204 struct amdgpu_vm_bo_base *next;
205
206 /* protected by vm status_lock */
207 struct list_head vm_status;
208
209 /* if the bo is counted as shared in mem stats
210 * protected by vm status_lock */
211 bool shared;
212
213 /* protected by the BO being reserved */
214 bool moved;
215 };
216
217 /* provided by hw blocks that can write ptes, e.g., sdma */
218 struct amdgpu_vm_pte_funcs {
219 /* number of dw to reserve per operation */
220 unsigned copy_pte_num_dw;
221
222 /* copy pte entries from GART */
223 void (*copy_pte)(struct amdgpu_ib *ib,
224 uint64_t pe, uint64_t src,
225 unsigned count);
226
227 /* write pte one entry at a time with addr mapping */
228 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
229 uint64_t value, unsigned count,
230 uint32_t incr);
231 /* for linear pte/pde updates without addr mapping */
232 void (*set_pte_pde)(struct amdgpu_ib *ib,
233 uint64_t pe,
234 uint64_t addr, unsigned count,
235 uint32_t incr, uint64_t flags);
236 };
237
238 struct amdgpu_task_info {
239 char process_name[TASK_COMM_LEN];
240 char task_name[TASK_COMM_LEN];
241 pid_t pid;
242 pid_t tgid;
243 struct kref refcount;
244 };
245
246 /**
247 * struct amdgpu_vm_update_params
248 *
249 * Encapsulate some VM table update parameters to reduce
250 * the number of function parameters
251 *
252 */
253 struct amdgpu_vm_update_params {
254
255 /**
256 * @adev: amdgpu device we do this update for
257 */
258 struct amdgpu_device *adev;
259
260 /**
261 * @vm: optional amdgpu_vm we do this update for
262 */
263 struct amdgpu_vm *vm;
264
265 /**
266 * @immediate: if changes should be made immediately
267 */
268 bool immediate;
269
270 /**
271 * @unlocked: true if the root BO is not locked
272 */
273 bool unlocked;
274
275 /**
276 * @pages_addr:
277 *
278 * DMA addresses to use for mapping
279 */
280 dma_addr_t *pages_addr;
281
282 /**
283 * @job: job to used for hw submission
284 */
285 struct amdgpu_job *job;
286
287 /**
288 * @num_dw_left: number of dw left for the IB
289 */
290 unsigned int num_dw_left;
291
292 /**
293 * @needs_flush: true whenever we need to invalidate the TLB
294 */
295 bool needs_flush;
296
297 /**
298 * @allow_override: true for memory that is not uncached: allows MTYPE
299 * to be overridden for NUMA local memory.
300 */
301 bool allow_override;
302
303 /**
304 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush
305 */
306 struct list_head tlb_flush_waitlist;
307 };
308
309 struct amdgpu_vm_update_funcs {
310 int (*map_table)(struct amdgpu_bo_vm *bo);
311 int (*prepare)(struct amdgpu_vm_update_params *p,
312 struct amdgpu_sync *sync);
313 int (*update)(struct amdgpu_vm_update_params *p,
314 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
315 unsigned count, uint32_t incr, uint64_t flags);
316 int (*commit)(struct amdgpu_vm_update_params *p,
317 struct dma_fence **fence);
318 };
319
320 struct amdgpu_vm_fault_info {
321 /* fault address */
322 uint64_t addr;
323 /* fault status register */
324 uint32_t status;
325 /* which vmhub? gfxhub, mmhub, etc. */
326 unsigned int vmhub;
327 };
328
329 struct amdgpu_mem_stats {
330 struct drm_memory_stats drm;
331
332 /* buffers that requested this placement but are currently evicted */
333 uint64_t evicted;
334 };
335
336 struct amdgpu_vm {
337 /* tree of virtual addresses mapped */
338 struct rb_root_cached va;
339
340 /* Lock to prevent eviction while we are updating page tables
341 * use vm_eviction_lock/unlock(vm)
342 */
343 struct mutex eviction_lock;
344 bool evicting;
345 unsigned int saved_flags;
346
347 /* Lock to protect vm_bo add/del/move on all lists of vm */
348 spinlock_t status_lock;
349
350 /* Memory statistics for this vm, protected by status_lock */
351 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM];
352
353 /* Per-VM and PT BOs who needs a validation */
354 struct list_head evicted;
355
356 /* BOs for user mode queues that need a validation */
357 struct list_head evicted_user;
358
359 /* PT BOs which relocated and their parent need an update */
360 struct list_head relocated;
361
362 /* per VM BOs moved, but not yet updated in the PT */
363 struct list_head moved;
364
365 /* All BOs of this VM not currently in the state machine */
366 struct list_head idle;
367
368 /* regular invalidated BOs, but not yet updated in the PT */
369 struct list_head invalidated;
370
371 /* BO mappings freed, but not yet updated in the PT */
372 struct list_head freed;
373
374 /* BOs which are invalidated, has been updated in the PTs */
375 struct list_head done;
376
377 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
378 struct list_head pt_freed;
379 struct work_struct pt_free_work;
380
381 /* contains the page directory */
382 struct amdgpu_vm_bo_base root;
383 struct dma_fence *last_update;
384
385 /* Scheduler entities for page table updates */
386 struct drm_sched_entity immediate;
387 struct drm_sched_entity delayed;
388
389 /* Last finished delayed update */
390 atomic64_t tlb_seq;
391 struct dma_fence *last_tlb_flush;
392 atomic64_t kfd_last_flushed_seq;
393 uint64_t tlb_fence_context;
394
395 /* How many times we had to re-generate the page tables */
396 uint64_t generation;
397
398 /* Last unlocked submission to the scheduler entities */
399 struct dma_fence *last_unlocked;
400
401 unsigned int pasid;
402 bool reserved_vmid[AMDGPU_MAX_VMHUBS];
403
404 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
405 bool use_cpu_for_update;
406
407 /* Functions to use for VM table updates */
408 const struct amdgpu_vm_update_funcs *update_funcs;
409
410 /* Up to 128 pending retry page faults */
411 DECLARE_KFIFO(faults, u64, 128);
412
413 /* Points to the KFD process VM info */
414 struct amdkfd_process_info *process_info;
415
416 /* List node in amdkfd_process_info.vm_list_head */
417 struct list_head vm_list_node;
418
419 /* Valid while the PD is reserved or fenced */
420 uint64_t pd_phys_addr;
421
422 /* Some basic info about the task */
423 struct amdgpu_task_info *task_info;
424
425 /* Store positions of group of BOs */
426 struct ttm_lru_bulk_move lru_bulk_move;
427 /* Flag to indicate if VM is used for compute */
428 bool is_compute_context;
429
430 /* Memory partition number, -1 means any partition */
431 int8_t mem_id;
432
433 /* cached fault info */
434 struct amdgpu_vm_fault_info fault_info;
435 };
436
437 struct amdgpu_vm_manager {
438 /* Handling of VMIDs */
439 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
440 unsigned int first_kfd_vmid;
441 bool concurrent_flush;
442
443 /* Handling of VM fences */
444 u64 fence_context;
445 unsigned seqno[AMDGPU_MAX_RINGS];
446
447 uint64_t max_pfn;
448 uint32_t num_level;
449 uint32_t block_size;
450 uint32_t fragment_size;
451 enum amdgpu_vm_level root_level;
452 /* vram base address for page table entry */
453 u64 vram_base_offset;
454 /* vm pte handling */
455 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
456 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
457 unsigned vm_pte_num_scheds;
458 struct amdgpu_ring *page_fault;
459
460 /* partial resident texture handling */
461 spinlock_t prt_lock;
462 atomic_t num_prt_users;
463
464 /* controls how VM page tables are updated for Graphics and Compute.
465 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
466 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
467 */
468 int vm_update_mode;
469
470 /* PASID to VM mapping, will be used in interrupt context to
471 * look up VM of a page fault
472 */
473 struct xarray pasids;
474 /* Global registration of recent page fault information */
475 struct amdgpu_vm_fault_info fault_info;
476 };
477
478 struct amdgpu_bo_va_mapping;
479
480 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
481 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
482 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
483
484 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
485 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
486
487 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
488 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
489
490 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
491 u32 pasid);
492
493 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
494 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id);
495 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
496 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
497 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
498 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
499 unsigned int num_fences);
500 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
501 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);
502 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
503 struct ww_acquire_ctx *ticket,
504 int (*callback)(void *p, struct amdgpu_bo *bo),
505 void *param);
506 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
507 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
508 struct amdgpu_vm *vm, bool immediate);
509 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
510 struct amdgpu_vm *vm,
511 struct dma_fence **fence);
512 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
513 struct amdgpu_vm *vm,
514 struct ww_acquire_ctx *ticket);
515 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
516 struct amdgpu_vm *vm,
517 uint32_t flush_type,
518 uint32_t xcc_mask);
519 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
520 struct amdgpu_vm *vm, struct amdgpu_bo *bo);
521 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
522 bool immediate, bool unlocked, bool flush_tlb,
523 bool allow_override, struct amdgpu_sync *sync,
524 uint64_t start, uint64_t last, uint64_t flags,
525 uint64_t offset, uint64_t vram_base,
526 struct ttm_resource *res, dma_addr_t *pages_addr,
527 struct dma_fence **fence);
528 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
529 struct amdgpu_bo_va *bo_va,
530 bool clear);
531 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
532 void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted);
533 void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base,
534 struct ttm_resource *new_res, int sign);
535 void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo);
536 void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem,
537 bool evicted);
538 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
539 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
540 struct amdgpu_bo *bo);
541 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
542 struct amdgpu_vm *vm,
543 struct amdgpu_bo *bo);
544 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
545 struct amdgpu_bo_va *bo_va,
546 uint64_t addr, uint64_t offset,
547 uint64_t size, uint64_t flags);
548 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
549 struct amdgpu_bo_va *bo_va,
550 uint64_t addr, uint64_t offset,
551 uint64_t size, uint64_t flags);
552 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
553 struct amdgpu_bo_va *bo_va,
554 uint64_t addr);
555 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
556 struct amdgpu_vm *vm,
557 uint64_t saddr, uint64_t size);
558 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
559 uint64_t addr);
560 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
561 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
562 struct amdgpu_bo_va *bo_va);
563 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
564 uint32_t fragment_size_default, unsigned max_level,
565 unsigned max_bits);
566 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
567 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
568 struct amdgpu_job *job);
569 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
570
571 struct amdgpu_task_info *
572 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid);
573
574 struct amdgpu_task_info *
575 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm);
576
577 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info);
578
579 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
580 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,
581 bool write_fault);
582
583 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
584
585 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
586 struct amdgpu_vm *vm);
587 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
588 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]);
589
590 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
591 struct amdgpu_bo_vm *vmbo, bool immediate);
592 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
593 int level, bool immediate, struct amdgpu_bo_vm **vmbo,
594 int32_t xcp_id);
595 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm);
596
597 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,
598 struct amdgpu_vm_bo_base *entry);
599 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
600 uint64_t start, uint64_t end,
601 uint64_t dst, uint64_t flags);
602 void amdgpu_vm_pt_free_work(struct work_struct *work);
603 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev,
604 struct amdgpu_vm_update_params *params);
605
606 #if defined(CONFIG_DEBUG_FS)
607 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
608 #endif
609
610 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm);
611
612 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo);
613
614 /**
615 * amdgpu_vm_tlb_seq - return tlb flush sequence number
616 * @vm: the amdgpu_vm structure to query
617 *
618 * Returns the tlb flush sequence number which indicates that the VM TLBs needs
619 * to be invalidated whenever the sequence number change.
620 */
amdgpu_vm_tlb_seq(struct amdgpu_vm * vm)621 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
622 {
623 unsigned long flags;
624 spinlock_t *lock;
625
626 /*
627 * Workaround to stop racing between the fence signaling and handling
628 * the cb. The lock is static after initially setting it up, just make
629 * sure that the dma_fence structure isn't freed up.
630 */
631 rcu_read_lock();
632 lock = vm->last_tlb_flush->lock;
633 rcu_read_unlock();
634
635 spin_lock_irqsave(lock, flags);
636 spin_unlock_irqrestore(lock, flags);
637
638 return atomic64_read(&vm->tlb_seq);
639 }
640
641 /*
642 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
643 * happens while holding this lock anywhere to prevent deadlocks when
644 * an MMU notifier runs in reclaim-FS context.
645 */
amdgpu_vm_eviction_lock(struct amdgpu_vm * vm)646 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
647 {
648 mutex_lock(&vm->eviction_lock);
649 vm->saved_flags = memalloc_noreclaim_save();
650 }
651
amdgpu_vm_eviction_trylock(struct amdgpu_vm * vm)652 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
653 {
654 if (mutex_trylock(&vm->eviction_lock)) {
655 vm->saved_flags = memalloc_noreclaim_save();
656 return true;
657 }
658 return false;
659 }
660
amdgpu_vm_eviction_unlock(struct amdgpu_vm * vm)661 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
662 {
663 memalloc_noreclaim_restore(vm->saved_flags);
664 mutex_unlock(&vm->eviction_lock);
665 }
666
667 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
668 unsigned int pasid,
669 uint64_t addr,
670 uint32_t status,
671 unsigned int vmhub);
672 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
673 struct amdgpu_vm *vm,
674 struct dma_fence **fence);
675
676 #endif
677