1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/blk-integrity.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kstrtox.h>
18 #include <linux/memremap.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/once.h>
23 #include <linux/pci.h>
24 #include <linux/suspend.h>
25 #include <linux/t10-pi.h>
26 #include <linux/types.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
31
32 #include "trace.h"
33 #include "nvme.h"
34
35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
37
38 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39
40 /*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44 #define NVME_MAX_KB_SZ 8192
45 #define NVME_MAX_SEGS 128
46 #define NVME_MAX_NR_ALLOCATIONS 5
47
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0444);
50
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0444);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59
60 static unsigned int sgl_threshold = SZ_32K;
61 module_param(sgl_threshold, uint, 0644);
62 MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
66 #define NVME_PCI_MIN_QUEUE_SIZE 2
67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_uint,
72 };
73
74 static unsigned int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77
io_queue_count_set(const char * val,const struct kernel_param * kp)78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79 {
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87 }
88
89 static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92 };
93
94 static unsigned int write_queues;
95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96 MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
100 static unsigned int poll_queues;
101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
104 static bool noacpi;
105 module_param(noacpi, bool, 0444);
106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
108 struct nvme_dev;
109 struct nvme_queue;
110
111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112 static void nvme_delete_io_queues(struct nvme_dev *dev);
113 static void nvme_update_attrs(struct nvme_dev *dev);
114
115 /*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118 struct nvme_dev {
119 struct nvme_queue *queues;
120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
126 unsigned online_queues;
127 unsigned max_qid;
128 unsigned io_queues[HCTX_MAX_TYPES];
129 unsigned int num_vecs;
130 u32 q_depth;
131 int io_sqes;
132 u32 db_stride;
133 void __iomem *bar;
134 unsigned long bar_mapped_size;
135 struct mutex shutdown_lock;
136 bool subsystem;
137 u64 cmb_size;
138 bool cmb_use_sqes;
139 u32 cmbsz;
140 u32 cmbloc;
141 struct nvme_ctrl ctrl;
142 u32 last_ps;
143 bool hmb;
144
145 mempool_t *iod_mempool;
146
147 /* shadow doorbell buffer support: */
148 __le32 *dbbuf_dbs;
149 dma_addr_t dbbuf_dbs_dma_addr;
150 __le32 *dbbuf_eis;
151 dma_addr_t dbbuf_eis_dma_addr;
152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
156 dma_addr_t host_mem_descs_dma;
157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
162 };
163
io_queue_depth_set(const char * val,const struct kernel_param * kp)164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165 {
166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
168 }
169
sq_idx(unsigned int qid,u32 stride)170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 {
172 return qid * 2 * stride;
173 }
174
cq_idx(unsigned int qid,u32 stride)175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 {
177 return (qid * 2 + 1) * stride;
178 }
179
to_nvme_dev(struct nvme_ctrl * ctrl)180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 {
182 return container_of(ctrl, struct nvme_dev, ctrl);
183 }
184
185 /*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189 struct nvme_queue {
190 struct nvme_dev *dev;
191 spinlock_t sq_lock;
192 void *sq_cmds;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
198 u32 __iomem *q_db;
199 u32 q_depth;
200 u16 cq_vector;
201 u16 sq_tail;
202 u16 last_sq_tail;
203 u16 cq_head;
204 u16 qid;
205 u8 cq_phase;
206 u8 sqes;
207 unsigned long flags;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
216 struct completion delete_done;
217 };
218
219 union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222 };
223
224 /*
225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
229 */
230 struct nvme_iod {
231 struct nvme_request req;
232 struct nvme_command cmd;
233 bool aborted;
234 s8 nr_allocations; /* PRP list pool allocations. 0 means small
235 pool in use */
236 unsigned int dma_len; /* length of single DMA segment mapping */
237 dma_addr_t first_dma;
238 dma_addr_t meta_dma;
239 struct sg_table sgt;
240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
241 };
242
nvme_dbbuf_size(struct nvme_dev * dev)243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
244 {
245 return dev->nr_allocated_queues * 8 * dev->db_stride;
246 }
247
nvme_dbbuf_dma_alloc(struct nvme_dev * dev)248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
249 {
250 unsigned int mem_size = nvme_dbbuf_size(dev);
251
252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253 return;
254
255 if (dev->dbbuf_dbs) {
256 /*
257 * Clear the dbbuf memory so the driver doesn't observe stale
258 * values from the previous instantiation.
259 */
260 memset(dev->dbbuf_dbs, 0, mem_size);
261 memset(dev->dbbuf_eis, 0, mem_size);
262 return;
263 }
264
265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
266 &dev->dbbuf_dbs_dma_addr,
267 GFP_KERNEL);
268 if (!dev->dbbuf_dbs)
269 goto fail;
270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
271 &dev->dbbuf_eis_dma_addr,
272 GFP_KERNEL);
273 if (!dev->dbbuf_eis)
274 goto fail_free_dbbuf_dbs;
275 return;
276
277 fail_free_dbbuf_dbs:
278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
279 dev->dbbuf_dbs_dma_addr);
280 dev->dbbuf_dbs = NULL;
281 fail:
282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
283 }
284
nvme_dbbuf_dma_free(struct nvme_dev * dev)285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286 {
287 unsigned int mem_size = nvme_dbbuf_size(dev);
288
289 if (dev->dbbuf_dbs) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 }
294 if (dev->dbbuf_eis) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
297 dev->dbbuf_eis = NULL;
298 }
299 }
300
nvme_dbbuf_init(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)301 static void nvme_dbbuf_init(struct nvme_dev *dev,
302 struct nvme_queue *nvmeq, int qid)
303 {
304 if (!dev->dbbuf_dbs || !qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
311 }
312
nvme_dbbuf_free(struct nvme_queue * nvmeq)313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314 {
315 if (!nvmeq->qid)
316 return;
317
318 nvmeq->dbbuf_sq_db = NULL;
319 nvmeq->dbbuf_cq_db = NULL;
320 nvmeq->dbbuf_sq_ei = NULL;
321 nvmeq->dbbuf_cq_ei = NULL;
322 }
323
nvme_dbbuf_set(struct nvme_dev * dev)324 static void nvme_dbbuf_set(struct nvme_dev *dev)
325 {
326 struct nvme_command c = { };
327 unsigned int i;
328
329 if (!dev->dbbuf_dbs)
330 return;
331
332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
340
341 for (i = 1; i <= dev->online_queues; i++)
342 nvme_dbbuf_free(&dev->queues[i]);
343 }
344 }
345
nvme_dbbuf_need_event(u16 event_idx,u16 new_idx,u16 old)346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347 {
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349 }
350
351 /* Update dbbuf and return true if an MMIO is required */
nvme_dbbuf_update_and_check_event(u16 value,__le32 * dbbuf_db,volatile __le32 * dbbuf_ei)352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353 volatile __le32 *dbbuf_ei)
354 {
355 if (dbbuf_db) {
356 u16 old_value, event_idx;
357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
364 old_value = le32_to_cpu(*dbbuf_db);
365 *dbbuf_db = cpu_to_le32(value);
366
367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
375 event_idx = le32_to_cpu(*dbbuf_ei);
376 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
377 return false;
378 }
379
380 return true;
381 }
382
383 /*
384 * Will slightly overestimate the number of pages needed. This is OK
385 * as it only leads to a small amount of wasted memory for the lifetime of
386 * the I/O.
387 */
nvme_pci_npages_prp(void)388 static int nvme_pci_npages_prp(void)
389 {
390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
393 }
394
nvme_admin_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
397 {
398 struct nvme_dev *dev = to_nvme_dev(data);
399 struct nvme_queue *nvmeq = &dev->queues[0];
400
401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
403
404 hctx->driver_data = nvmeq;
405 return 0;
406 }
407
nvme_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
410 {
411 struct nvme_dev *dev = to_nvme_dev(data);
412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
413
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
416 return 0;
417 }
418
nvme_pci_init_request(struct blk_mq_tag_set * set,struct request * req,unsigned int hctx_idx,unsigned int numa_node)419 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420 struct request *req, unsigned int hctx_idx,
421 unsigned int numa_node)
422 {
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424
425 nvme_req(req)->ctrl = set->driver_data;
426 nvme_req(req)->cmd = &iod->cmd;
427 return 0;
428 }
429
queue_irq_offset(struct nvme_dev * dev)430 static int queue_irq_offset(struct nvme_dev *dev)
431 {
432 /* if we have more than 1 vec, admin queue offsets us by 1 */
433 if (dev->num_vecs > 1)
434 return 1;
435
436 return 0;
437 }
438
nvme_pci_map_queues(struct blk_mq_tag_set * set)439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
440 {
441 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
442 int i, qoff, offset;
443
444 offset = queue_irq_offset(dev);
445 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446 struct blk_mq_queue_map *map = &set->map[i];
447
448 map->nr_queues = dev->io_queues[i];
449 if (!map->nr_queues) {
450 BUG_ON(i == HCTX_TYPE_DEFAULT);
451 continue;
452 }
453
454 /*
455 * The poll queue(s) doesn't have an IRQ (and hence IRQ
456 * affinity), so use the regular blk-mq cpu mapping
457 */
458 map->queue_offset = qoff;
459 if (i != HCTX_TYPE_POLL && offset)
460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 else
462 blk_mq_map_queues(map);
463 qoff += map->nr_queues;
464 offset += map->nr_queues;
465 }
466 }
467
468 /*
469 * Write sq tail if we are asked to, or if the next command would wrap.
470 */
nvme_write_sq_db(struct nvme_queue * nvmeq,bool write_sq)471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
472 {
473 if (!write_sq) {
474 u16 next_tail = nvmeq->sq_tail + 1;
475
476 if (next_tail == nvmeq->q_depth)
477 next_tail = 0;
478 if (next_tail != nvmeq->last_sq_tail)
479 return;
480 }
481
482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
484 writel(nvmeq->sq_tail, nvmeq->q_db);
485 nvmeq->last_sq_tail = nvmeq->sq_tail;
486 }
487
nvme_sq_copy_cmd(struct nvme_queue * nvmeq,struct nvme_command * cmd)488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489 struct nvme_command *cmd)
490 {
491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
492 absolute_pointer(cmd), sizeof(*cmd));
493 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvmeq->sq_tail = 0;
495 }
496
nvme_commit_rqs(struct blk_mq_hw_ctx * hctx)497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498 {
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
504 spin_unlock(&nvmeq->sq_lock);
505 }
506
nvme_pci_use_sgls(struct nvme_dev * dev,struct request * req,int nseg)507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508 int nseg)
509 {
510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
511 unsigned int avg_seg_size;
512
513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
514
515 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
516 return false;
517 if (!nvmeq->qid)
518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522 }
523
nvme_free_prps(struct nvme_dev * dev,struct request * req)524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
525 {
526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 dma_addr_t dma_addr = iod->first_dma;
529 int i;
530
531 for (i = 0; i < iod->nr_allocations; i++) {
532 __le64 *prp_list = iod->list[i].prp_list;
533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
536 dma_addr = next_dma_addr;
537 }
538 }
539
nvme_unmap_data(struct nvme_dev * dev,struct request * req)540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541 {
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543
544 if (iod->dma_len) {
545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546 rq_dma_dir(req));
547 return;
548 }
549
550 WARN_ON_ONCE(!iod->sgt.nents);
551
552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
553
554 if (iod->nr_allocations == 0)
555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
556 iod->first_dma);
557 else if (iod->nr_allocations == 1)
558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
559 iod->first_dma);
560 else
561 nvme_free_prps(dev, req);
562 mempool_free(iod->sgt.sgl, dev->iod_mempool);
563 }
564
nvme_print_sgl(struct scatterlist * sgl,int nents)565 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566 {
567 int i;
568 struct scatterlist *sg;
569
570 for_each_sg(sgl, sg, nents, i) {
571 dma_addr_t phys = sg_phys(sg);
572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573 "dma_address:%pad dma_length:%d\n",
574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575 sg_dma_len(sg));
576 }
577 }
578
nvme_pci_setup_prps(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd)579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580 struct request *req, struct nvme_rw_command *cmnd)
581 {
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
583 struct dma_pool *pool;
584 int length = blk_rq_payload_bytes(req);
585 struct scatterlist *sg = iod->sgt.sgl;
586 int dma_len = sg_dma_len(sg);
587 u64 dma_addr = sg_dma_address(sg);
588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
589 __le64 *prp_list;
590 dma_addr_t prp_dma;
591 int nprps, i;
592
593 length -= (NVME_CTRL_PAGE_SIZE - offset);
594 if (length <= 0) {
595 iod->first_dma = 0;
596 goto done;
597 }
598
599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
600 if (dma_len) {
601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
602 } else {
603 sg = sg_next(sg);
604 dma_addr = sg_dma_address(sg);
605 dma_len = sg_dma_len(sg);
606 }
607
608 if (length <= NVME_CTRL_PAGE_SIZE) {
609 iod->first_dma = dma_addr;
610 goto done;
611 }
612
613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
614 if (nprps <= (256 / 8)) {
615 pool = dev->prp_small_pool;
616 iod->nr_allocations = 0;
617 } else {
618 pool = dev->prp_page_pool;
619 iod->nr_allocations = 1;
620 }
621
622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
623 if (!prp_list) {
624 iod->nr_allocations = -1;
625 return BLK_STS_RESOURCE;
626 }
627 iod->list[0].prp_list = prp_list;
628 iod->first_dma = prp_dma;
629 i = 0;
630 for (;;) {
631 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
632 __le64 *old_prp_list = prp_list;
633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
634 if (!prp_list)
635 goto free_prps;
636 iod->list[iod->nr_allocations++].prp_list = prp_list;
637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
642 dma_len -= NVME_CTRL_PAGE_SIZE;
643 dma_addr += NVME_CTRL_PAGE_SIZE;
644 length -= NVME_CTRL_PAGE_SIZE;
645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655 done:
656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
658 return BLK_STS_OK;
659 free_prps:
660 nvme_free_prps(dev, req);
661 return BLK_STS_RESOURCE;
662 bad_sgl:
663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->sgt.nents);
666 return BLK_STS_IOERR;
667 }
668
nvme_pci_sgl_set_data(struct nvme_sgl_desc * sge,struct scatterlist * sg)669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671 {
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675 }
676
nvme_pci_sgl_set_seg(struct nvme_sgl_desc * sge,dma_addr_t dma_addr,int entries)677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679 {
680 sge->addr = cpu_to_le64(dma_addr);
681 sge->length = cpu_to_le32(entries * sizeof(*sge));
682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
683 }
684
nvme_pci_setup_sgls(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmd)685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
686 struct request *req, struct nvme_rw_command *cmd)
687 {
688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
689 struct dma_pool *pool;
690 struct nvme_sgl_desc *sg_list;
691 struct scatterlist *sg = iod->sgt.sgl;
692 unsigned int entries = iod->sgt.nents;
693 dma_addr_t sgl_dma;
694 int i = 0;
695
696 /* setting the transfer type as SGL */
697 cmd->flags = NVME_CMD_SGL_METABUF;
698
699 if (entries == 1) {
700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
701 return BLK_STS_OK;
702 }
703
704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705 pool = dev->prp_small_pool;
706 iod->nr_allocations = 0;
707 } else {
708 pool = dev->prp_page_pool;
709 iod->nr_allocations = 1;
710 }
711
712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
713 if (!sg_list) {
714 iod->nr_allocations = -1;
715 return BLK_STS_RESOURCE;
716 }
717
718 iod->list[0].sg_list = sg_list;
719 iod->first_dma = sgl_dma;
720
721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
722 do {
723 nvme_pci_sgl_set_data(&sg_list[i++], sg);
724 sg = sg_next(sg);
725 } while (--entries > 0);
726
727 return BLK_STS_OK;
728 }
729
nvme_setup_prp_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmnd,
732 struct bio_vec *bv)
733 {
734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
737
738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739 if (dma_mapping_error(dev->dev, iod->first_dma))
740 return BLK_STS_RESOURCE;
741 iod->dma_len = bv->bv_len;
742
743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744 if (bv->bv_len > first_prp_len)
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
746 else
747 cmnd->dptr.prp2 = 0;
748 return BLK_STS_OK;
749 }
750
nvme_setup_sgl_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754 {
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
762 cmnd->flags = NVME_CMD_SGL_METABUF;
763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
766 return BLK_STS_OK;
767 }
768
nvme_map_data(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
770 struct nvme_command *cmnd)
771 {
772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
773 blk_status_t ret = BLK_STS_RESOURCE;
774 int rc;
775
776 if (blk_rq_nr_phys_segments(req) == 1) {
777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
778 struct bio_vec bv = req_bvec(req);
779
780 if (!is_pci_p2pdma_page(bv.bv_page)) {
781 if ((bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) +
782 bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
783 return nvme_setup_prp_simple(dev, req,
784 &cmnd->rw, &bv);
785
786 if (nvmeq->qid && sgl_threshold &&
787 nvme_ctrl_sgl_supported(&dev->ctrl))
788 return nvme_setup_sgl_simple(dev, req,
789 &cmnd->rw, &bv);
790 }
791 }
792
793 iod->dma_len = 0;
794 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
795 if (!iod->sgt.sgl)
796 return BLK_STS_RESOURCE;
797 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
798 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
799 if (!iod->sgt.orig_nents)
800 goto out_free_sg;
801
802 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
803 DMA_ATTR_NO_WARN);
804 if (rc) {
805 if (rc == -EREMOTEIO)
806 ret = BLK_STS_TARGET;
807 goto out_free_sg;
808 }
809
810 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
812 else
813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814 if (ret != BLK_STS_OK)
815 goto out_unmap_sg;
816 return BLK_STS_OK;
817
818 out_unmap_sg:
819 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
820 out_free_sg:
821 mempool_free(iod->sgt.sgl, dev->iod_mempool);
822 return ret;
823 }
824
nvme_map_metadata(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)825 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
826 struct nvme_command *cmnd)
827 {
828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
829 struct bio_vec bv = rq_integrity_vec(req);
830
831 iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0);
832 if (dma_mapping_error(dev->dev, iod->meta_dma))
833 return BLK_STS_IOERR;
834 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
835 return BLK_STS_OK;
836 }
837
nvme_prep_rq(struct nvme_dev * dev,struct request * req)838 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
839 {
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
841 blk_status_t ret;
842
843 iod->aborted = false;
844 iod->nr_allocations = -1;
845 iod->sgt.nents = 0;
846
847 ret = nvme_setup_cmd(req->q->queuedata, req);
848 if (ret)
849 return ret;
850
851 if (blk_rq_nr_phys_segments(req)) {
852 ret = nvme_map_data(dev, req, &iod->cmd);
853 if (ret)
854 goto out_free_cmd;
855 }
856
857 if (blk_integrity_rq(req)) {
858 ret = nvme_map_metadata(dev, req, &iod->cmd);
859 if (ret)
860 goto out_unmap_data;
861 }
862
863 nvme_start_request(req);
864 return BLK_STS_OK;
865 out_unmap_data:
866 if (blk_rq_nr_phys_segments(req))
867 nvme_unmap_data(dev, req);
868 out_free_cmd:
869 nvme_cleanup_cmd(req);
870 return ret;
871 }
872
873 /*
874 * NOTE: ns is NULL when called on the admin queue.
875 */
nvme_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)876 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
877 const struct blk_mq_queue_data *bd)
878 {
879 struct nvme_queue *nvmeq = hctx->driver_data;
880 struct nvme_dev *dev = nvmeq->dev;
881 struct request *req = bd->rq;
882 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
883 blk_status_t ret;
884
885 /*
886 * We should not need to do this, but we're still using this to
887 * ensure we can drain requests on a dying queue.
888 */
889 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
890 return BLK_STS_IOERR;
891
892 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
893 return nvme_fail_nonready_command(&dev->ctrl, req);
894
895 ret = nvme_prep_rq(dev, req);
896 if (unlikely(ret))
897 return ret;
898 spin_lock(&nvmeq->sq_lock);
899 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
900 nvme_write_sq_db(nvmeq, bd->last);
901 spin_unlock(&nvmeq->sq_lock);
902 return BLK_STS_OK;
903 }
904
nvme_submit_cmds(struct nvme_queue * nvmeq,struct request ** rqlist)905 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
906 {
907 spin_lock(&nvmeq->sq_lock);
908 while (!rq_list_empty(*rqlist)) {
909 struct request *req = rq_list_pop(rqlist);
910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
911
912 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
913 }
914 nvme_write_sq_db(nvmeq, true);
915 spin_unlock(&nvmeq->sq_lock);
916 }
917
nvme_prep_rq_batch(struct nvme_queue * nvmeq,struct request * req)918 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
919 {
920 /*
921 * We should not need to do this, but we're still using this to
922 * ensure we can drain requests on a dying queue.
923 */
924 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
925 return false;
926 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
927 return false;
928
929 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
930 }
931
nvme_queue_rqs(struct request ** rqlist)932 static void nvme_queue_rqs(struct request **rqlist)
933 {
934 struct request *req, *next, *prev = NULL;
935 struct request *requeue_list = NULL;
936
937 rq_list_for_each_safe(rqlist, req, next) {
938 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
939
940 if (!nvme_prep_rq_batch(nvmeq, req)) {
941 /* detach 'req' and add to remainder list */
942 rq_list_move(rqlist, &requeue_list, req, prev);
943
944 req = prev;
945 if (!req)
946 continue;
947 }
948
949 if (!next || req->mq_hctx != next->mq_hctx) {
950 /* detach rest of list, and submit */
951 req->rq_next = NULL;
952 nvme_submit_cmds(nvmeq, rqlist);
953 *rqlist = next;
954 prev = NULL;
955 } else
956 prev = req;
957 }
958
959 *rqlist = requeue_list;
960 }
961
nvme_pci_unmap_rq(struct request * req)962 static __always_inline void nvme_pci_unmap_rq(struct request *req)
963 {
964 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
965 struct nvme_dev *dev = nvmeq->dev;
966
967 if (blk_integrity_rq(req)) {
968 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
969
970 dma_unmap_page(dev->dev, iod->meta_dma,
971 rq_integrity_vec(req).bv_len, rq_dma_dir(req));
972 }
973
974 if (blk_rq_nr_phys_segments(req))
975 nvme_unmap_data(dev, req);
976 }
977
nvme_pci_complete_rq(struct request * req)978 static void nvme_pci_complete_rq(struct request *req)
979 {
980 nvme_pci_unmap_rq(req);
981 nvme_complete_rq(req);
982 }
983
nvme_pci_complete_batch(struct io_comp_batch * iob)984 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
985 {
986 nvme_complete_batch(iob, nvme_pci_unmap_rq);
987 }
988
989 /* We read the CQE phase first to check if the rest of the entry is valid */
nvme_cqe_pending(struct nvme_queue * nvmeq)990 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
991 {
992 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
993
994 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
995 }
996
nvme_ring_cq_doorbell(struct nvme_queue * nvmeq)997 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
998 {
999 u16 head = nvmeq->cq_head;
1000
1001 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1002 nvmeq->dbbuf_cq_ei))
1003 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1004 }
1005
nvme_queue_tagset(struct nvme_queue * nvmeq)1006 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1007 {
1008 if (!nvmeq->qid)
1009 return nvmeq->dev->admin_tagset.tags[0];
1010 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1011 }
1012
nvme_handle_cqe(struct nvme_queue * nvmeq,struct io_comp_batch * iob,u16 idx)1013 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1014 struct io_comp_batch *iob, u16 idx)
1015 {
1016 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1017 __u16 command_id = READ_ONCE(cqe->command_id);
1018 struct request *req;
1019
1020 /*
1021 * AEN requests are special as they don't time out and can
1022 * survive any kind of queue freeze and often don't respond to
1023 * aborts. We don't even bother to allocate a struct request
1024 * for them but rather special case them here.
1025 */
1026 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1027 nvme_complete_async_event(&nvmeq->dev->ctrl,
1028 cqe->status, &cqe->result);
1029 return;
1030 }
1031
1032 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1033 if (unlikely(!req)) {
1034 dev_warn(nvmeq->dev->ctrl.device,
1035 "invalid id %d completed on queue %d\n",
1036 command_id, le16_to_cpu(cqe->sq_id));
1037 return;
1038 }
1039
1040 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1041 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1042 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1043 nvme_pci_complete_batch))
1044 nvme_pci_complete_rq(req);
1045 }
1046
nvme_update_cq_head(struct nvme_queue * nvmeq)1047 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1048 {
1049 u32 tmp = nvmeq->cq_head + 1;
1050
1051 if (tmp == nvmeq->q_depth) {
1052 nvmeq->cq_head = 0;
1053 nvmeq->cq_phase ^= 1;
1054 } else {
1055 nvmeq->cq_head = tmp;
1056 }
1057 }
1058
nvme_poll_cq(struct nvme_queue * nvmeq,struct io_comp_batch * iob)1059 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1060 struct io_comp_batch *iob)
1061 {
1062 int found = 0;
1063
1064 while (nvme_cqe_pending(nvmeq)) {
1065 found++;
1066 /*
1067 * load-load control dependency between phase and the rest of
1068 * the cqe requires a full read memory barrier
1069 */
1070 dma_rmb();
1071 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1072 nvme_update_cq_head(nvmeq);
1073 }
1074
1075 if (found)
1076 nvme_ring_cq_doorbell(nvmeq);
1077 return found;
1078 }
1079
nvme_irq(int irq,void * data)1080 static irqreturn_t nvme_irq(int irq, void *data)
1081 {
1082 struct nvme_queue *nvmeq = data;
1083 DEFINE_IO_COMP_BATCH(iob);
1084
1085 if (nvme_poll_cq(nvmeq, &iob)) {
1086 if (!rq_list_empty(iob.req_list))
1087 nvme_pci_complete_batch(&iob);
1088 return IRQ_HANDLED;
1089 }
1090 return IRQ_NONE;
1091 }
1092
nvme_irq_check(int irq,void * data)1093 static irqreturn_t nvme_irq_check(int irq, void *data)
1094 {
1095 struct nvme_queue *nvmeq = data;
1096
1097 if (nvme_cqe_pending(nvmeq))
1098 return IRQ_WAKE_THREAD;
1099 return IRQ_NONE;
1100 }
1101
1102 /*
1103 * Poll for completions for any interrupt driven queue
1104 * Can be called from any context.
1105 */
nvme_poll_irqdisable(struct nvme_queue * nvmeq)1106 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1107 {
1108 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1109
1110 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1111
1112 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1113 nvme_poll_cq(nvmeq, NULL);
1114 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1115 }
1116
nvme_poll(struct blk_mq_hw_ctx * hctx,struct io_comp_batch * iob)1117 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1118 {
1119 struct nvme_queue *nvmeq = hctx->driver_data;
1120 bool found;
1121
1122 if (!nvme_cqe_pending(nvmeq))
1123 return 0;
1124
1125 spin_lock(&nvmeq->cq_poll_lock);
1126 found = nvme_poll_cq(nvmeq, iob);
1127 spin_unlock(&nvmeq->cq_poll_lock);
1128
1129 return found;
1130 }
1131
nvme_pci_submit_async_event(struct nvme_ctrl * ctrl)1132 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1133 {
1134 struct nvme_dev *dev = to_nvme_dev(ctrl);
1135 struct nvme_queue *nvmeq = &dev->queues[0];
1136 struct nvme_command c = { };
1137
1138 c.common.opcode = nvme_admin_async_event;
1139 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1140
1141 spin_lock(&nvmeq->sq_lock);
1142 nvme_sq_copy_cmd(nvmeq, &c);
1143 nvme_write_sq_db(nvmeq, true);
1144 spin_unlock(&nvmeq->sq_lock);
1145 }
1146
nvme_pci_subsystem_reset(struct nvme_ctrl * ctrl)1147 static int nvme_pci_subsystem_reset(struct nvme_ctrl *ctrl)
1148 {
1149 struct nvme_dev *dev = to_nvme_dev(ctrl);
1150 int ret = 0;
1151
1152 /*
1153 * Taking the shutdown_lock ensures the BAR mapping is not being
1154 * altered by reset_work. Holding this lock before the RESETTING state
1155 * change, if successful, also ensures nvme_remove won't be able to
1156 * proceed to iounmap until we're done.
1157 */
1158 mutex_lock(&dev->shutdown_lock);
1159 if (!dev->bar_mapped_size) {
1160 ret = -ENODEV;
1161 goto unlock;
1162 }
1163
1164 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
1165 ret = -EBUSY;
1166 goto unlock;
1167 }
1168
1169 writel(NVME_SUBSYS_RESET, dev->bar + NVME_REG_NSSR);
1170 nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE);
1171
1172 /*
1173 * Read controller status to flush the previous write and trigger a
1174 * pcie read error.
1175 */
1176 readl(dev->bar + NVME_REG_CSTS);
1177 unlock:
1178 mutex_unlock(&dev->shutdown_lock);
1179 return ret;
1180 }
1181
adapter_delete_queue(struct nvme_dev * dev,u8 opcode,u16 id)1182 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1183 {
1184 struct nvme_command c = { };
1185
1186 c.delete_queue.opcode = opcode;
1187 c.delete_queue.qid = cpu_to_le16(id);
1188
1189 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1190 }
1191
adapter_alloc_cq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq,s16 vector)1192 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1193 struct nvme_queue *nvmeq, s16 vector)
1194 {
1195 struct nvme_command c = { };
1196 int flags = NVME_QUEUE_PHYS_CONTIG;
1197
1198 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1199 flags |= NVME_CQ_IRQ_ENABLED;
1200
1201 /*
1202 * Note: we (ab)use the fact that the prp fields survive if no data
1203 * is attached to the request.
1204 */
1205 c.create_cq.opcode = nvme_admin_create_cq;
1206 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1207 c.create_cq.cqid = cpu_to_le16(qid);
1208 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1209 c.create_cq.cq_flags = cpu_to_le16(flags);
1210 c.create_cq.irq_vector = cpu_to_le16(vector);
1211
1212 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1213 }
1214
adapter_alloc_sq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq)1215 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1216 struct nvme_queue *nvmeq)
1217 {
1218 struct nvme_ctrl *ctrl = &dev->ctrl;
1219 struct nvme_command c = { };
1220 int flags = NVME_QUEUE_PHYS_CONTIG;
1221
1222 /*
1223 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1224 * set. Since URGENT priority is zeroes, it makes all queues
1225 * URGENT.
1226 */
1227 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1228 flags |= NVME_SQ_PRIO_MEDIUM;
1229
1230 /*
1231 * Note: we (ab)use the fact that the prp fields survive if no data
1232 * is attached to the request.
1233 */
1234 c.create_sq.opcode = nvme_admin_create_sq;
1235 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1236 c.create_sq.sqid = cpu_to_le16(qid);
1237 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1238 c.create_sq.sq_flags = cpu_to_le16(flags);
1239 c.create_sq.cqid = cpu_to_le16(qid);
1240
1241 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1242 }
1243
adapter_delete_cq(struct nvme_dev * dev,u16 cqid)1244 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1245 {
1246 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1247 }
1248
adapter_delete_sq(struct nvme_dev * dev,u16 sqid)1249 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1250 {
1251 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1252 }
1253
abort_endio(struct request * req,blk_status_t error)1254 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1255 {
1256 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1257
1258 dev_warn(nvmeq->dev->ctrl.device,
1259 "Abort status: 0x%x", nvme_req(req)->status);
1260 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1261 blk_mq_free_request(req);
1262 return RQ_END_IO_NONE;
1263 }
1264
nvme_should_reset(struct nvme_dev * dev,u32 csts)1265 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1266 {
1267 /* If true, indicates loss of adapter communication, possibly by a
1268 * NVMe Subsystem reset.
1269 */
1270 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1271
1272 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1273 switch (nvme_ctrl_state(&dev->ctrl)) {
1274 case NVME_CTRL_RESETTING:
1275 case NVME_CTRL_CONNECTING:
1276 return false;
1277 default:
1278 break;
1279 }
1280
1281 /* We shouldn't reset unless the controller is on fatal error state
1282 * _or_ if we lost the communication with it.
1283 */
1284 if (!(csts & NVME_CSTS_CFS) && !nssro)
1285 return false;
1286
1287 return true;
1288 }
1289
nvme_warn_reset(struct nvme_dev * dev,u32 csts)1290 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1291 {
1292 /* Read a config register to help see what died. */
1293 u16 pci_status;
1294 int result;
1295
1296 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1297 &pci_status);
1298 if (result == PCIBIOS_SUCCESSFUL)
1299 dev_warn(dev->ctrl.device,
1300 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1301 csts, pci_status);
1302 else
1303 dev_warn(dev->ctrl.device,
1304 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1305 csts, result);
1306
1307 if (csts != ~0)
1308 return;
1309
1310 dev_warn(dev->ctrl.device,
1311 "Does your device have a faulty power saving mode enabled?\n");
1312 dev_warn(dev->ctrl.device,
1313 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off\" and report a bug\n");
1314 }
1315
nvme_timeout(struct request * req)1316 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1317 {
1318 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1319 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1320 struct nvme_dev *dev = nvmeq->dev;
1321 struct request *abort_req;
1322 struct nvme_command cmd = { };
1323 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1324 u8 opcode;
1325
1326 if (nvme_state_terminal(&dev->ctrl))
1327 goto disable;
1328
1329 /* If PCI error recovery process is happening, we cannot reset or
1330 * the recovery mechanism will surely fail.
1331 */
1332 mb();
1333 if (pci_channel_offline(to_pci_dev(dev->dev)))
1334 return BLK_EH_RESET_TIMER;
1335
1336 /*
1337 * Reset immediately if the controller is failed
1338 */
1339 if (nvme_should_reset(dev, csts)) {
1340 nvme_warn_reset(dev, csts);
1341 goto disable;
1342 }
1343
1344 /*
1345 * Did we miss an interrupt?
1346 */
1347 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1348 nvme_poll(req->mq_hctx, NULL);
1349 else
1350 nvme_poll_irqdisable(nvmeq);
1351
1352 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1353 dev_warn(dev->ctrl.device,
1354 "I/O tag %d (%04x) QID %d timeout, completion polled\n",
1355 req->tag, nvme_cid(req), nvmeq->qid);
1356 return BLK_EH_DONE;
1357 }
1358
1359 /*
1360 * Shutdown immediately if controller times out while starting. The
1361 * reset work will see the pci device disabled when it gets the forced
1362 * cancellation error. All outstanding requests are completed on
1363 * shutdown, so we return BLK_EH_DONE.
1364 */
1365 switch (nvme_ctrl_state(&dev->ctrl)) {
1366 case NVME_CTRL_CONNECTING:
1367 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1368 fallthrough;
1369 case NVME_CTRL_DELETING:
1370 dev_warn_ratelimited(dev->ctrl.device,
1371 "I/O tag %d (%04x) QID %d timeout, disable controller\n",
1372 req->tag, nvme_cid(req), nvmeq->qid);
1373 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1374 nvme_dev_disable(dev, true);
1375 return BLK_EH_DONE;
1376 case NVME_CTRL_RESETTING:
1377 return BLK_EH_RESET_TIMER;
1378 default:
1379 break;
1380 }
1381
1382 /*
1383 * Shutdown the controller immediately and schedule a reset if the
1384 * command was already aborted once before and still hasn't been
1385 * returned to the driver, or if this is the admin queue.
1386 */
1387 opcode = nvme_req(req)->cmd->common.opcode;
1388 if (!nvmeq->qid || iod->aborted) {
1389 dev_warn(dev->ctrl.device,
1390 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n",
1391 req->tag, nvme_cid(req), opcode,
1392 nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid);
1393 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1394 goto disable;
1395 }
1396
1397 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1398 atomic_inc(&dev->ctrl.abort_limit);
1399 return BLK_EH_RESET_TIMER;
1400 }
1401 iod->aborted = true;
1402
1403 cmd.abort.opcode = nvme_admin_abort_cmd;
1404 cmd.abort.cid = nvme_cid(req);
1405 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1406
1407 dev_warn(nvmeq->dev->ctrl.device,
1408 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n",
1409 req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode),
1410 nvmeq->qid, blk_op_str(req_op(req)), req_op(req),
1411 blk_rq_bytes(req));
1412
1413 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1414 BLK_MQ_REQ_NOWAIT);
1415 if (IS_ERR(abort_req)) {
1416 atomic_inc(&dev->ctrl.abort_limit);
1417 return BLK_EH_RESET_TIMER;
1418 }
1419 nvme_init_request(abort_req, &cmd);
1420
1421 abort_req->end_io = abort_endio;
1422 abort_req->end_io_data = NULL;
1423 blk_execute_rq_nowait(abort_req, false);
1424
1425 /*
1426 * The aborted req will be completed on receiving the abort req.
1427 * We enable the timer again. If hit twice, it'll cause a device reset,
1428 * as the device then is in a faulty state.
1429 */
1430 return BLK_EH_RESET_TIMER;
1431
1432 disable:
1433 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1434 if (nvme_state_terminal(&dev->ctrl))
1435 nvme_dev_disable(dev, true);
1436 return BLK_EH_DONE;
1437 }
1438
1439 nvme_dev_disable(dev, false);
1440 if (nvme_try_sched_reset(&dev->ctrl))
1441 nvme_unquiesce_io_queues(&dev->ctrl);
1442 return BLK_EH_DONE;
1443 }
1444
nvme_free_queue(struct nvme_queue * nvmeq)1445 static void nvme_free_queue(struct nvme_queue *nvmeq)
1446 {
1447 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1448 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1449 if (!nvmeq->sq_cmds)
1450 return;
1451
1452 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1453 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1454 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1455 } else {
1456 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1457 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1458 }
1459 }
1460
nvme_free_queues(struct nvme_dev * dev,int lowest)1461 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1462 {
1463 int i;
1464
1465 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1466 dev->ctrl.queue_count--;
1467 nvme_free_queue(&dev->queues[i]);
1468 }
1469 }
1470
nvme_suspend_queue(struct nvme_dev * dev,unsigned int qid)1471 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1472 {
1473 struct nvme_queue *nvmeq = &dev->queues[qid];
1474
1475 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1476 return;
1477
1478 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1479 mb();
1480
1481 nvmeq->dev->online_queues--;
1482 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1483 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1484 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1485 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1486 }
1487
nvme_suspend_io_queues(struct nvme_dev * dev)1488 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1489 {
1490 int i;
1491
1492 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1493 nvme_suspend_queue(dev, i);
1494 }
1495
1496 /*
1497 * Called only on a device that has been disabled and after all other threads
1498 * that can check this device's completion queues have synced, except
1499 * nvme_poll(). This is the last chance for the driver to see a natural
1500 * completion before nvme_cancel_request() terminates all incomplete requests.
1501 */
nvme_reap_pending_cqes(struct nvme_dev * dev)1502 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1503 {
1504 int i;
1505
1506 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1507 spin_lock(&dev->queues[i].cq_poll_lock);
1508 nvme_poll_cq(&dev->queues[i], NULL);
1509 spin_unlock(&dev->queues[i].cq_poll_lock);
1510 }
1511 }
1512
nvme_cmb_qdepth(struct nvme_dev * dev,int nr_io_queues,int entry_size)1513 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1514 int entry_size)
1515 {
1516 int q_depth = dev->q_depth;
1517 unsigned q_size_aligned = roundup(q_depth * entry_size,
1518 NVME_CTRL_PAGE_SIZE);
1519
1520 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1521 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1522
1523 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1524 q_depth = div_u64(mem_per_q, entry_size);
1525
1526 /*
1527 * Ensure the reduced q_depth is above some threshold where it
1528 * would be better to map queues in system memory with the
1529 * original depth
1530 */
1531 if (q_depth < 64)
1532 return -ENOMEM;
1533 }
1534
1535 return q_depth;
1536 }
1537
nvme_alloc_sq_cmds(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)1538 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1539 int qid)
1540 {
1541 struct pci_dev *pdev = to_pci_dev(dev->dev);
1542
1543 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1544 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1545 if (nvmeq->sq_cmds) {
1546 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1547 nvmeq->sq_cmds);
1548 if (nvmeq->sq_dma_addr) {
1549 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1550 return 0;
1551 }
1552
1553 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1554 }
1555 }
1556
1557 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1558 &nvmeq->sq_dma_addr, GFP_KERNEL);
1559 if (!nvmeq->sq_cmds)
1560 return -ENOMEM;
1561 return 0;
1562 }
1563
nvme_alloc_queue(struct nvme_dev * dev,int qid,int depth)1564 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1565 {
1566 struct nvme_queue *nvmeq = &dev->queues[qid];
1567
1568 if (dev->ctrl.queue_count > qid)
1569 return 0;
1570
1571 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1572 nvmeq->q_depth = depth;
1573 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1574 &nvmeq->cq_dma_addr, GFP_KERNEL);
1575 if (!nvmeq->cqes)
1576 goto free_nvmeq;
1577
1578 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1579 goto free_cqdma;
1580
1581 nvmeq->dev = dev;
1582 spin_lock_init(&nvmeq->sq_lock);
1583 spin_lock_init(&nvmeq->cq_poll_lock);
1584 nvmeq->cq_head = 0;
1585 nvmeq->cq_phase = 1;
1586 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1587 nvmeq->qid = qid;
1588 dev->ctrl.queue_count++;
1589
1590 return 0;
1591
1592 free_cqdma:
1593 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1594 nvmeq->cq_dma_addr);
1595 free_nvmeq:
1596 return -ENOMEM;
1597 }
1598
queue_request_irq(struct nvme_queue * nvmeq)1599 static int queue_request_irq(struct nvme_queue *nvmeq)
1600 {
1601 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1602 int nr = nvmeq->dev->ctrl.instance;
1603
1604 if (use_threaded_interrupts) {
1605 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1606 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1607 } else {
1608 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1609 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1610 }
1611 }
1612
nvme_init_queue(struct nvme_queue * nvmeq,u16 qid)1613 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1614 {
1615 struct nvme_dev *dev = nvmeq->dev;
1616
1617 nvmeq->sq_tail = 0;
1618 nvmeq->last_sq_tail = 0;
1619 nvmeq->cq_head = 0;
1620 nvmeq->cq_phase = 1;
1621 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1622 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1623 nvme_dbbuf_init(dev, nvmeq, qid);
1624 dev->online_queues++;
1625 wmb(); /* ensure the first interrupt sees the initialization */
1626 }
1627
1628 /*
1629 * Try getting shutdown_lock while setting up IO queues.
1630 */
nvme_setup_io_queues_trylock(struct nvme_dev * dev)1631 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1632 {
1633 /*
1634 * Give up if the lock is being held by nvme_dev_disable.
1635 */
1636 if (!mutex_trylock(&dev->shutdown_lock))
1637 return -ENODEV;
1638
1639 /*
1640 * Controller is in wrong state, fail early.
1641 */
1642 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
1643 mutex_unlock(&dev->shutdown_lock);
1644 return -ENODEV;
1645 }
1646
1647 return 0;
1648 }
1649
nvme_create_queue(struct nvme_queue * nvmeq,int qid,bool polled)1650 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1651 {
1652 struct nvme_dev *dev = nvmeq->dev;
1653 int result;
1654 u16 vector = 0;
1655
1656 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1657
1658 /*
1659 * A queue's vector matches the queue identifier unless the controller
1660 * has only one vector available.
1661 */
1662 if (!polled)
1663 vector = dev->num_vecs == 1 ? 0 : qid;
1664 else
1665 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1666
1667 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1668 if (result)
1669 return result;
1670
1671 result = adapter_alloc_sq(dev, qid, nvmeq);
1672 if (result < 0)
1673 return result;
1674 if (result)
1675 goto release_cq;
1676
1677 nvmeq->cq_vector = vector;
1678
1679 result = nvme_setup_io_queues_trylock(dev);
1680 if (result)
1681 return result;
1682 nvme_init_queue(nvmeq, qid);
1683 if (!polled) {
1684 result = queue_request_irq(nvmeq);
1685 if (result < 0)
1686 goto release_sq;
1687 }
1688
1689 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1690 mutex_unlock(&dev->shutdown_lock);
1691 return result;
1692
1693 release_sq:
1694 dev->online_queues--;
1695 mutex_unlock(&dev->shutdown_lock);
1696 adapter_delete_sq(dev, qid);
1697 release_cq:
1698 adapter_delete_cq(dev, qid);
1699 return result;
1700 }
1701
1702 static const struct blk_mq_ops nvme_mq_admin_ops = {
1703 .queue_rq = nvme_queue_rq,
1704 .complete = nvme_pci_complete_rq,
1705 .init_hctx = nvme_admin_init_hctx,
1706 .init_request = nvme_pci_init_request,
1707 .timeout = nvme_timeout,
1708 };
1709
1710 static const struct blk_mq_ops nvme_mq_ops = {
1711 .queue_rq = nvme_queue_rq,
1712 .queue_rqs = nvme_queue_rqs,
1713 .complete = nvme_pci_complete_rq,
1714 .commit_rqs = nvme_commit_rqs,
1715 .init_hctx = nvme_init_hctx,
1716 .init_request = nvme_pci_init_request,
1717 .map_queues = nvme_pci_map_queues,
1718 .timeout = nvme_timeout,
1719 .poll = nvme_poll,
1720 };
1721
nvme_dev_remove_admin(struct nvme_dev * dev)1722 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1723 {
1724 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1725 /*
1726 * If the controller was reset during removal, it's possible
1727 * user requests may be waiting on a stopped queue. Start the
1728 * queue to flush these to completion.
1729 */
1730 nvme_unquiesce_admin_queue(&dev->ctrl);
1731 nvme_remove_admin_tag_set(&dev->ctrl);
1732 }
1733 }
1734
db_bar_size(struct nvme_dev * dev,unsigned nr_io_queues)1735 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1736 {
1737 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1738 }
1739
nvme_remap_bar(struct nvme_dev * dev,unsigned long size)1740 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1741 {
1742 struct pci_dev *pdev = to_pci_dev(dev->dev);
1743
1744 if (size <= dev->bar_mapped_size)
1745 return 0;
1746 if (size > pci_resource_len(pdev, 0))
1747 return -ENOMEM;
1748 if (dev->bar)
1749 iounmap(dev->bar);
1750 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1751 if (!dev->bar) {
1752 dev->bar_mapped_size = 0;
1753 return -ENOMEM;
1754 }
1755 dev->bar_mapped_size = size;
1756 dev->dbs = dev->bar + NVME_REG_DBS;
1757
1758 return 0;
1759 }
1760
nvme_pci_configure_admin_queue(struct nvme_dev * dev)1761 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1762 {
1763 int result;
1764 u32 aqa;
1765 struct nvme_queue *nvmeq;
1766
1767 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1768 if (result < 0)
1769 return result;
1770
1771 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1772 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1773
1774 if (dev->subsystem &&
1775 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1776 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1777
1778 /*
1779 * If the device has been passed off to us in an enabled state, just
1780 * clear the enabled bit. The spec says we should set the 'shutdown
1781 * notification bits', but doing so may cause the device to complete
1782 * commands to the admin queue ... and we don't know what memory that
1783 * might be pointing at!
1784 */
1785 result = nvme_disable_ctrl(&dev->ctrl, false);
1786 if (result < 0)
1787 return result;
1788
1789 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1790 if (result)
1791 return result;
1792
1793 dev->ctrl.numa_node = dev_to_node(dev->dev);
1794
1795 nvmeq = &dev->queues[0];
1796 aqa = nvmeq->q_depth - 1;
1797 aqa |= aqa << 16;
1798
1799 writel(aqa, dev->bar + NVME_REG_AQA);
1800 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1801 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1802
1803 result = nvme_enable_ctrl(&dev->ctrl);
1804 if (result)
1805 return result;
1806
1807 nvmeq->cq_vector = 0;
1808 nvme_init_queue(nvmeq, 0);
1809 result = queue_request_irq(nvmeq);
1810 if (result) {
1811 dev->online_queues--;
1812 return result;
1813 }
1814
1815 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1816 return result;
1817 }
1818
nvme_create_io_queues(struct nvme_dev * dev)1819 static int nvme_create_io_queues(struct nvme_dev *dev)
1820 {
1821 unsigned i, max, rw_queues;
1822 int ret = 0;
1823
1824 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1825 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1826 ret = -ENOMEM;
1827 break;
1828 }
1829 }
1830
1831 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1832 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1833 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1834 dev->io_queues[HCTX_TYPE_READ];
1835 } else {
1836 rw_queues = max;
1837 }
1838
1839 for (i = dev->online_queues; i <= max; i++) {
1840 bool polled = i > rw_queues;
1841
1842 ret = nvme_create_queue(&dev->queues[i], i, polled);
1843 if (ret)
1844 break;
1845 }
1846
1847 /*
1848 * Ignore failing Create SQ/CQ commands, we can continue with less
1849 * than the desired amount of queues, and even a controller without
1850 * I/O queues can still be used to issue admin commands. This might
1851 * be useful to upgrade a buggy firmware for example.
1852 */
1853 return ret >= 0 ? 0 : ret;
1854 }
1855
nvme_cmb_size_unit(struct nvme_dev * dev)1856 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1857 {
1858 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1859
1860 return 1ULL << (12 + 4 * szu);
1861 }
1862
nvme_cmb_size(struct nvme_dev * dev)1863 static u32 nvme_cmb_size(struct nvme_dev *dev)
1864 {
1865 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1866 }
1867
nvme_map_cmb(struct nvme_dev * dev)1868 static void nvme_map_cmb(struct nvme_dev *dev)
1869 {
1870 u64 size, offset;
1871 resource_size_t bar_size;
1872 struct pci_dev *pdev = to_pci_dev(dev->dev);
1873 int bar;
1874
1875 if (dev->cmb_size)
1876 return;
1877
1878 if (NVME_CAP_CMBS(dev->ctrl.cap))
1879 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1880
1881 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1882 if (!dev->cmbsz)
1883 return;
1884 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1885
1886 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1887 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1888 bar = NVME_CMB_BIR(dev->cmbloc);
1889 bar_size = pci_resource_len(pdev, bar);
1890
1891 if (offset > bar_size)
1892 return;
1893
1894 /*
1895 * Tell the controller about the host side address mapping the CMB,
1896 * and enable CMB decoding for the NVMe 1.4+ scheme:
1897 */
1898 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1899 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1900 (pci_bus_address(pdev, bar) + offset),
1901 dev->bar + NVME_REG_CMBMSC);
1902 }
1903
1904 /*
1905 * Controllers may support a CMB size larger than their BAR,
1906 * for example, due to being behind a bridge. Reduce the CMB to
1907 * the reported size of the BAR
1908 */
1909 if (size > bar_size - offset)
1910 size = bar_size - offset;
1911
1912 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1913 dev_warn(dev->ctrl.device,
1914 "failed to register the CMB\n");
1915 return;
1916 }
1917
1918 dev->cmb_size = size;
1919 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1920
1921 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1922 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1923 pci_p2pmem_publish(pdev, true);
1924
1925 nvme_update_attrs(dev);
1926 }
1927
nvme_set_host_mem(struct nvme_dev * dev,u32 bits)1928 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1929 {
1930 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1931 u64 dma_addr = dev->host_mem_descs_dma;
1932 struct nvme_command c = { };
1933 int ret;
1934
1935 c.features.opcode = nvme_admin_set_features;
1936 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1937 c.features.dword11 = cpu_to_le32(bits);
1938 c.features.dword12 = cpu_to_le32(host_mem_size);
1939 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1940 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1941 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1942
1943 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1944 if (ret) {
1945 dev_warn(dev->ctrl.device,
1946 "failed to set host mem (err %d, flags %#x).\n",
1947 ret, bits);
1948 } else
1949 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1950
1951 return ret;
1952 }
1953
nvme_free_host_mem(struct nvme_dev * dev)1954 static void nvme_free_host_mem(struct nvme_dev *dev)
1955 {
1956 int i;
1957
1958 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1959 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1960 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1961
1962 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1963 le64_to_cpu(desc->addr),
1964 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1965 }
1966
1967 kfree(dev->host_mem_desc_bufs);
1968 dev->host_mem_desc_bufs = NULL;
1969 dma_free_coherent(dev->dev,
1970 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1971 dev->host_mem_descs, dev->host_mem_descs_dma);
1972 dev->host_mem_descs = NULL;
1973 dev->nr_host_mem_descs = 0;
1974 }
1975
__nvme_alloc_host_mem(struct nvme_dev * dev,u64 preferred,u32 chunk_size)1976 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1977 u32 chunk_size)
1978 {
1979 struct nvme_host_mem_buf_desc *descs;
1980 u32 max_entries, len;
1981 dma_addr_t descs_dma;
1982 int i = 0;
1983 void **bufs;
1984 u64 size, tmp;
1985
1986 tmp = (preferred + chunk_size - 1);
1987 do_div(tmp, chunk_size);
1988 max_entries = tmp;
1989
1990 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1991 max_entries = dev->ctrl.hmmaxd;
1992
1993 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1994 &descs_dma, GFP_KERNEL);
1995 if (!descs)
1996 goto out;
1997
1998 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1999 if (!bufs)
2000 goto out_free_descs;
2001
2002 for (size = 0; size < preferred && i < max_entries; size += len) {
2003 dma_addr_t dma_addr;
2004
2005 len = min_t(u64, chunk_size, preferred - size);
2006 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2007 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2008 if (!bufs[i])
2009 break;
2010
2011 descs[i].addr = cpu_to_le64(dma_addr);
2012 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2013 i++;
2014 }
2015
2016 if (!size)
2017 goto out_free_bufs;
2018
2019 dev->nr_host_mem_descs = i;
2020 dev->host_mem_size = size;
2021 dev->host_mem_descs = descs;
2022 dev->host_mem_descs_dma = descs_dma;
2023 dev->host_mem_desc_bufs = bufs;
2024 return 0;
2025
2026 out_free_bufs:
2027 while (--i >= 0) {
2028 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2029
2030 dma_free_attrs(dev->dev, size, bufs[i],
2031 le64_to_cpu(descs[i].addr),
2032 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2033 }
2034
2035 kfree(bufs);
2036 out_free_descs:
2037 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2038 descs_dma);
2039 out:
2040 dev->host_mem_descs = NULL;
2041 return -ENOMEM;
2042 }
2043
nvme_alloc_host_mem(struct nvme_dev * dev,u64 min,u64 preferred)2044 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2045 {
2046 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2047 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2048 u64 chunk_size;
2049
2050 /* start big and work our way down */
2051 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2052 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2053 if (!min || dev->host_mem_size >= min)
2054 return 0;
2055 nvme_free_host_mem(dev);
2056 }
2057 }
2058
2059 return -ENOMEM;
2060 }
2061
nvme_setup_host_mem(struct nvme_dev * dev)2062 static int nvme_setup_host_mem(struct nvme_dev *dev)
2063 {
2064 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2065 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2066 u64 min = (u64)dev->ctrl.hmmin * 4096;
2067 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2068 int ret;
2069
2070 if (!dev->ctrl.hmpre)
2071 return 0;
2072
2073 preferred = min(preferred, max);
2074 if (min > max) {
2075 dev_warn(dev->ctrl.device,
2076 "min host memory (%lld MiB) above limit (%d MiB).\n",
2077 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2078 nvme_free_host_mem(dev);
2079 return 0;
2080 }
2081
2082 /*
2083 * If we already have a buffer allocated check if we can reuse it.
2084 */
2085 if (dev->host_mem_descs) {
2086 if (dev->host_mem_size >= min)
2087 enable_bits |= NVME_HOST_MEM_RETURN;
2088 else
2089 nvme_free_host_mem(dev);
2090 }
2091
2092 if (!dev->host_mem_descs) {
2093 if (nvme_alloc_host_mem(dev, min, preferred)) {
2094 dev_warn(dev->ctrl.device,
2095 "failed to allocate host memory buffer.\n");
2096 return 0; /* controller must work without HMB */
2097 }
2098
2099 dev_info(dev->ctrl.device,
2100 "allocated %lld MiB host memory buffer.\n",
2101 dev->host_mem_size >> ilog2(SZ_1M));
2102 }
2103
2104 ret = nvme_set_host_mem(dev, enable_bits);
2105 if (ret)
2106 nvme_free_host_mem(dev);
2107 return ret;
2108 }
2109
cmb_show(struct device * dev,struct device_attribute * attr,char * buf)2110 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2111 char *buf)
2112 {
2113 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2114
2115 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2116 ndev->cmbloc, ndev->cmbsz);
2117 }
2118 static DEVICE_ATTR_RO(cmb);
2119
cmbloc_show(struct device * dev,struct device_attribute * attr,char * buf)2120 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2121 char *buf)
2122 {
2123 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2124
2125 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2126 }
2127 static DEVICE_ATTR_RO(cmbloc);
2128
cmbsz_show(struct device * dev,struct device_attribute * attr,char * buf)2129 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2130 char *buf)
2131 {
2132 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2133
2134 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2135 }
2136 static DEVICE_ATTR_RO(cmbsz);
2137
hmb_show(struct device * dev,struct device_attribute * attr,char * buf)2138 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2139 char *buf)
2140 {
2141 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2142
2143 return sysfs_emit(buf, "%d\n", ndev->hmb);
2144 }
2145
hmb_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2146 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2147 const char *buf, size_t count)
2148 {
2149 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2150 bool new;
2151 int ret;
2152
2153 if (kstrtobool(buf, &new) < 0)
2154 return -EINVAL;
2155
2156 if (new == ndev->hmb)
2157 return count;
2158
2159 if (new) {
2160 ret = nvme_setup_host_mem(ndev);
2161 } else {
2162 ret = nvme_set_host_mem(ndev, 0);
2163 if (!ret)
2164 nvme_free_host_mem(ndev);
2165 }
2166
2167 if (ret < 0)
2168 return ret;
2169
2170 return count;
2171 }
2172 static DEVICE_ATTR_RW(hmb);
2173
nvme_pci_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)2174 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2175 struct attribute *a, int n)
2176 {
2177 struct nvme_ctrl *ctrl =
2178 dev_get_drvdata(container_of(kobj, struct device, kobj));
2179 struct nvme_dev *dev = to_nvme_dev(ctrl);
2180
2181 if (a == &dev_attr_cmb.attr ||
2182 a == &dev_attr_cmbloc.attr ||
2183 a == &dev_attr_cmbsz.attr) {
2184 if (!dev->cmbsz)
2185 return 0;
2186 }
2187 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2188 return 0;
2189
2190 return a->mode;
2191 }
2192
2193 static struct attribute *nvme_pci_attrs[] = {
2194 &dev_attr_cmb.attr,
2195 &dev_attr_cmbloc.attr,
2196 &dev_attr_cmbsz.attr,
2197 &dev_attr_hmb.attr,
2198 NULL,
2199 };
2200
2201 static const struct attribute_group nvme_pci_dev_attrs_group = {
2202 .attrs = nvme_pci_attrs,
2203 .is_visible = nvme_pci_attrs_are_visible,
2204 };
2205
2206 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2207 &nvme_dev_attrs_group,
2208 &nvme_pci_dev_attrs_group,
2209 NULL,
2210 };
2211
nvme_update_attrs(struct nvme_dev * dev)2212 static void nvme_update_attrs(struct nvme_dev *dev)
2213 {
2214 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2215 }
2216
2217 /*
2218 * nirqs is the number of interrupts available for write and read
2219 * queues. The core already reserved an interrupt for the admin queue.
2220 */
nvme_calc_irq_sets(struct irq_affinity * affd,unsigned int nrirqs)2221 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2222 {
2223 struct nvme_dev *dev = affd->priv;
2224 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2225
2226 /*
2227 * If there is no interrupt available for queues, ensure that
2228 * the default queue is set to 1. The affinity set size is
2229 * also set to one, but the irq core ignores it for this case.
2230 *
2231 * If only one interrupt is available or 'write_queue' == 0, combine
2232 * write and read queues.
2233 *
2234 * If 'write_queues' > 0, ensure it leaves room for at least one read
2235 * queue.
2236 */
2237 if (!nrirqs) {
2238 nrirqs = 1;
2239 nr_read_queues = 0;
2240 } else if (nrirqs == 1 || !nr_write_queues) {
2241 nr_read_queues = 0;
2242 } else if (nr_write_queues >= nrirqs) {
2243 nr_read_queues = 1;
2244 } else {
2245 nr_read_queues = nrirqs - nr_write_queues;
2246 }
2247
2248 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2249 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2250 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2251 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2252 affd->nr_sets = nr_read_queues ? 2 : 1;
2253 }
2254
nvme_setup_irqs(struct nvme_dev * dev,unsigned int nr_io_queues)2255 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2256 {
2257 struct pci_dev *pdev = to_pci_dev(dev->dev);
2258 struct irq_affinity affd = {
2259 .pre_vectors = 1,
2260 .calc_sets = nvme_calc_irq_sets,
2261 .priv = dev,
2262 };
2263 unsigned int irq_queues, poll_queues;
2264 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2265
2266 /*
2267 * Poll queues don't need interrupts, but we need at least one I/O queue
2268 * left over for non-polled I/O.
2269 */
2270 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2271 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2272
2273 /*
2274 * Initialize for the single interrupt case, will be updated in
2275 * nvme_calc_irq_sets().
2276 */
2277 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2278 dev->io_queues[HCTX_TYPE_READ] = 0;
2279
2280 /*
2281 * We need interrupts for the admin queue and each non-polled I/O queue,
2282 * but some Apple controllers require all queues to use the first
2283 * vector.
2284 */
2285 irq_queues = 1;
2286 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2287 irq_queues += (nr_io_queues - poll_queues);
2288 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2289 flags &= ~PCI_IRQ_MSI;
2290 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2291 &affd);
2292 }
2293
nvme_max_io_queues(struct nvme_dev * dev)2294 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2295 {
2296 /*
2297 * If tags are shared with admin queue (Apple bug), then
2298 * make sure we only use one IO queue.
2299 */
2300 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2301 return 1;
2302 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2303 }
2304
nvme_setup_io_queues(struct nvme_dev * dev)2305 static int nvme_setup_io_queues(struct nvme_dev *dev)
2306 {
2307 struct nvme_queue *adminq = &dev->queues[0];
2308 struct pci_dev *pdev = to_pci_dev(dev->dev);
2309 unsigned int nr_io_queues;
2310 unsigned long size;
2311 int result;
2312
2313 /*
2314 * Sample the module parameters once at reset time so that we have
2315 * stable values to work with.
2316 */
2317 dev->nr_write_queues = write_queues;
2318 dev->nr_poll_queues = poll_queues;
2319
2320 nr_io_queues = dev->nr_allocated_queues - 1;
2321 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2322 if (result < 0)
2323 return result;
2324
2325 if (nr_io_queues == 0)
2326 return 0;
2327
2328 /*
2329 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2330 * from set to unset. If there is a window to it is truely freed,
2331 * pci_free_irq_vectors() jumping into this window will crash.
2332 * And take lock to avoid racing with pci_free_irq_vectors() in
2333 * nvme_dev_disable() path.
2334 */
2335 result = nvme_setup_io_queues_trylock(dev);
2336 if (result)
2337 return result;
2338 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2339 pci_free_irq(pdev, 0, adminq);
2340
2341 if (dev->cmb_use_sqes) {
2342 result = nvme_cmb_qdepth(dev, nr_io_queues,
2343 sizeof(struct nvme_command));
2344 if (result > 0) {
2345 dev->q_depth = result;
2346 dev->ctrl.sqsize = result - 1;
2347 } else {
2348 dev->cmb_use_sqes = false;
2349 }
2350 }
2351
2352 do {
2353 size = db_bar_size(dev, nr_io_queues);
2354 result = nvme_remap_bar(dev, size);
2355 if (!result)
2356 break;
2357 if (!--nr_io_queues) {
2358 result = -ENOMEM;
2359 goto out_unlock;
2360 }
2361 } while (1);
2362 adminq->q_db = dev->dbs;
2363
2364 retry:
2365 /* Deregister the admin queue's interrupt */
2366 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2367 pci_free_irq(pdev, 0, adminq);
2368
2369 /*
2370 * If we enable msix early due to not intx, disable it again before
2371 * setting up the full range we need.
2372 */
2373 pci_free_irq_vectors(pdev);
2374
2375 result = nvme_setup_irqs(dev, nr_io_queues);
2376 if (result <= 0) {
2377 result = -EIO;
2378 goto out_unlock;
2379 }
2380
2381 dev->num_vecs = result;
2382 result = max(result - 1, 1);
2383 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2384
2385 /*
2386 * Should investigate if there's a performance win from allocating
2387 * more queues than interrupt vectors; it might allow the submission
2388 * path to scale better, even if the receive path is limited by the
2389 * number of interrupts.
2390 */
2391 result = queue_request_irq(adminq);
2392 if (result)
2393 goto out_unlock;
2394 set_bit(NVMEQ_ENABLED, &adminq->flags);
2395 mutex_unlock(&dev->shutdown_lock);
2396
2397 result = nvme_create_io_queues(dev);
2398 if (result || dev->online_queues < 2)
2399 return result;
2400
2401 if (dev->online_queues - 1 < dev->max_qid) {
2402 nr_io_queues = dev->online_queues - 1;
2403 nvme_delete_io_queues(dev);
2404 result = nvme_setup_io_queues_trylock(dev);
2405 if (result)
2406 return result;
2407 nvme_suspend_io_queues(dev);
2408 goto retry;
2409 }
2410 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2411 dev->io_queues[HCTX_TYPE_DEFAULT],
2412 dev->io_queues[HCTX_TYPE_READ],
2413 dev->io_queues[HCTX_TYPE_POLL]);
2414 return 0;
2415 out_unlock:
2416 mutex_unlock(&dev->shutdown_lock);
2417 return result;
2418 }
2419
nvme_del_queue_end(struct request * req,blk_status_t error)2420 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2421 blk_status_t error)
2422 {
2423 struct nvme_queue *nvmeq = req->end_io_data;
2424
2425 blk_mq_free_request(req);
2426 complete(&nvmeq->delete_done);
2427 return RQ_END_IO_NONE;
2428 }
2429
nvme_del_cq_end(struct request * req,blk_status_t error)2430 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2431 blk_status_t error)
2432 {
2433 struct nvme_queue *nvmeq = req->end_io_data;
2434
2435 if (error)
2436 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2437
2438 return nvme_del_queue_end(req, error);
2439 }
2440
nvme_delete_queue(struct nvme_queue * nvmeq,u8 opcode)2441 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2442 {
2443 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2444 struct request *req;
2445 struct nvme_command cmd = { };
2446
2447 cmd.delete_queue.opcode = opcode;
2448 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2449
2450 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2451 if (IS_ERR(req))
2452 return PTR_ERR(req);
2453 nvme_init_request(req, &cmd);
2454
2455 if (opcode == nvme_admin_delete_cq)
2456 req->end_io = nvme_del_cq_end;
2457 else
2458 req->end_io = nvme_del_queue_end;
2459 req->end_io_data = nvmeq;
2460
2461 init_completion(&nvmeq->delete_done);
2462 blk_execute_rq_nowait(req, false);
2463 return 0;
2464 }
2465
__nvme_delete_io_queues(struct nvme_dev * dev,u8 opcode)2466 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2467 {
2468 int nr_queues = dev->online_queues - 1, sent = 0;
2469 unsigned long timeout;
2470
2471 retry:
2472 timeout = NVME_ADMIN_TIMEOUT;
2473 while (nr_queues > 0) {
2474 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2475 break;
2476 nr_queues--;
2477 sent++;
2478 }
2479 while (sent) {
2480 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2481
2482 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2483 timeout);
2484 if (timeout == 0)
2485 return false;
2486
2487 sent--;
2488 if (nr_queues)
2489 goto retry;
2490 }
2491 return true;
2492 }
2493
nvme_delete_io_queues(struct nvme_dev * dev)2494 static void nvme_delete_io_queues(struct nvme_dev *dev)
2495 {
2496 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2497 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2498 }
2499
nvme_pci_nr_maps(struct nvme_dev * dev)2500 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2501 {
2502 if (dev->io_queues[HCTX_TYPE_POLL])
2503 return 3;
2504 if (dev->io_queues[HCTX_TYPE_READ])
2505 return 2;
2506 return 1;
2507 }
2508
nvme_pci_update_nr_queues(struct nvme_dev * dev)2509 static bool nvme_pci_update_nr_queues(struct nvme_dev *dev)
2510 {
2511 if (!dev->ctrl.tagset) {
2512 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
2513 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
2514 return true;
2515 }
2516
2517 /* Give up if we are racing with nvme_dev_disable() */
2518 if (!mutex_trylock(&dev->shutdown_lock))
2519 return false;
2520
2521 /* Check if nvme_dev_disable() has been executed already */
2522 if (!dev->online_queues) {
2523 mutex_unlock(&dev->shutdown_lock);
2524 return false;
2525 }
2526
2527 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2528 /* free previously allocated queues that are no longer usable */
2529 nvme_free_queues(dev, dev->online_queues);
2530 mutex_unlock(&dev->shutdown_lock);
2531 return true;
2532 }
2533
nvme_pci_enable(struct nvme_dev * dev)2534 static int nvme_pci_enable(struct nvme_dev *dev)
2535 {
2536 int result = -ENOMEM;
2537 struct pci_dev *pdev = to_pci_dev(dev->dev);
2538 unsigned int flags = PCI_IRQ_ALL_TYPES;
2539
2540 if (pci_enable_device_mem(pdev))
2541 return result;
2542
2543 pci_set_master(pdev);
2544
2545 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2546 result = -ENODEV;
2547 goto disable;
2548 }
2549
2550 /*
2551 * Some devices and/or platforms don't advertise or work with INTx
2552 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2553 * adjust this later.
2554 */
2555 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2556 flags &= ~PCI_IRQ_MSI;
2557 result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
2558 if (result < 0)
2559 goto disable;
2560
2561 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2562
2563 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2564 io_queue_depth);
2565 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2566 dev->dbs = dev->bar + 4096;
2567
2568 /*
2569 * Some Apple controllers require a non-standard SQE size.
2570 * Interestingly they also seem to ignore the CC:IOSQES register
2571 * so we don't bother updating it here.
2572 */
2573 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2574 dev->io_sqes = 7;
2575 else
2576 dev->io_sqes = NVME_NVM_IOSQES;
2577
2578 if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) {
2579 dev->q_depth = 2;
2580 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2581 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2582 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2583 dev->q_depth = 64;
2584 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2585 "set queue depth=%u\n", dev->q_depth);
2586 }
2587
2588 /*
2589 * Controllers with the shared tags quirk need the IO queue to be
2590 * big enough so that we get 32 tags for the admin queue
2591 */
2592 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2593 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2594 dev->q_depth = NVME_AQ_DEPTH + 2;
2595 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2596 dev->q_depth);
2597 }
2598 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2599
2600 nvme_map_cmb(dev);
2601
2602 pci_save_state(pdev);
2603
2604 result = nvme_pci_configure_admin_queue(dev);
2605 if (result)
2606 goto free_irq;
2607 return result;
2608
2609 free_irq:
2610 pci_free_irq_vectors(pdev);
2611 disable:
2612 pci_disable_device(pdev);
2613 return result;
2614 }
2615
nvme_dev_unmap(struct nvme_dev * dev)2616 static void nvme_dev_unmap(struct nvme_dev *dev)
2617 {
2618 if (dev->bar)
2619 iounmap(dev->bar);
2620 pci_release_mem_regions(to_pci_dev(dev->dev));
2621 }
2622
nvme_pci_ctrl_is_dead(struct nvme_dev * dev)2623 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2624 {
2625 struct pci_dev *pdev = to_pci_dev(dev->dev);
2626 u32 csts;
2627
2628 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2629 return true;
2630 if (pdev->error_state != pci_channel_io_normal)
2631 return true;
2632
2633 csts = readl(dev->bar + NVME_REG_CSTS);
2634 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2635 }
2636
nvme_dev_disable(struct nvme_dev * dev,bool shutdown)2637 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2638 {
2639 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
2640 struct pci_dev *pdev = to_pci_dev(dev->dev);
2641 bool dead;
2642
2643 mutex_lock(&dev->shutdown_lock);
2644 dead = nvme_pci_ctrl_is_dead(dev);
2645 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
2646 if (pci_is_enabled(pdev))
2647 nvme_start_freeze(&dev->ctrl);
2648 /*
2649 * Give the controller a chance to complete all entered requests
2650 * if doing a safe shutdown.
2651 */
2652 if (!dead && shutdown)
2653 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2654 }
2655
2656 nvme_quiesce_io_queues(&dev->ctrl);
2657
2658 if (!dead && dev->ctrl.queue_count > 0) {
2659 nvme_delete_io_queues(dev);
2660 nvme_disable_ctrl(&dev->ctrl, shutdown);
2661 nvme_poll_irqdisable(&dev->queues[0]);
2662 }
2663 nvme_suspend_io_queues(dev);
2664 nvme_suspend_queue(dev, 0);
2665 pci_free_irq_vectors(pdev);
2666 if (pci_is_enabled(pdev))
2667 pci_disable_device(pdev);
2668 nvme_reap_pending_cqes(dev);
2669
2670 nvme_cancel_tagset(&dev->ctrl);
2671 nvme_cancel_admin_tagset(&dev->ctrl);
2672
2673 /*
2674 * The driver will not be starting up queues again if shutting down so
2675 * must flush all entered requests to their failed completion to avoid
2676 * deadlocking blk-mq hot-cpu notifier.
2677 */
2678 if (shutdown) {
2679 nvme_unquiesce_io_queues(&dev->ctrl);
2680 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2681 nvme_unquiesce_admin_queue(&dev->ctrl);
2682 }
2683 mutex_unlock(&dev->shutdown_lock);
2684 }
2685
nvme_disable_prepare_reset(struct nvme_dev * dev,bool shutdown)2686 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2687 {
2688 if (!nvme_wait_reset(&dev->ctrl))
2689 return -EBUSY;
2690 nvme_dev_disable(dev, shutdown);
2691 return 0;
2692 }
2693
nvme_setup_prp_pools(struct nvme_dev * dev)2694 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2695 {
2696 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2697 NVME_CTRL_PAGE_SIZE,
2698 NVME_CTRL_PAGE_SIZE, 0);
2699 if (!dev->prp_page_pool)
2700 return -ENOMEM;
2701
2702 /* Optimisation for I/Os between 4k and 128k */
2703 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2704 256, 256, 0);
2705 if (!dev->prp_small_pool) {
2706 dma_pool_destroy(dev->prp_page_pool);
2707 return -ENOMEM;
2708 }
2709 return 0;
2710 }
2711
nvme_release_prp_pools(struct nvme_dev * dev)2712 static void nvme_release_prp_pools(struct nvme_dev *dev)
2713 {
2714 dma_pool_destroy(dev->prp_page_pool);
2715 dma_pool_destroy(dev->prp_small_pool);
2716 }
2717
nvme_pci_alloc_iod_mempool(struct nvme_dev * dev)2718 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2719 {
2720 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2721
2722 dev->iod_mempool = mempool_create_node(1,
2723 mempool_kmalloc, mempool_kfree,
2724 (void *)alloc_size, GFP_KERNEL,
2725 dev_to_node(dev->dev));
2726 if (!dev->iod_mempool)
2727 return -ENOMEM;
2728 return 0;
2729 }
2730
nvme_free_tagset(struct nvme_dev * dev)2731 static void nvme_free_tagset(struct nvme_dev *dev)
2732 {
2733 if (dev->tagset.tags)
2734 nvme_remove_io_tag_set(&dev->ctrl);
2735 dev->ctrl.tagset = NULL;
2736 }
2737
2738 /* pairs with nvme_pci_alloc_dev */
nvme_pci_free_ctrl(struct nvme_ctrl * ctrl)2739 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2740 {
2741 struct nvme_dev *dev = to_nvme_dev(ctrl);
2742
2743 nvme_free_tagset(dev);
2744 put_device(dev->dev);
2745 kfree(dev->queues);
2746 kfree(dev);
2747 }
2748
nvme_reset_work(struct work_struct * work)2749 static void nvme_reset_work(struct work_struct *work)
2750 {
2751 struct nvme_dev *dev =
2752 container_of(work, struct nvme_dev, ctrl.reset_work);
2753 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2754 int result;
2755
2756 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
2757 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2758 dev->ctrl.state);
2759 result = -ENODEV;
2760 goto out;
2761 }
2762
2763 /*
2764 * If we're called to reset a live controller first shut it down before
2765 * moving on.
2766 */
2767 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2768 nvme_dev_disable(dev, false);
2769 nvme_sync_queues(&dev->ctrl);
2770
2771 mutex_lock(&dev->shutdown_lock);
2772 result = nvme_pci_enable(dev);
2773 if (result)
2774 goto out_unlock;
2775 nvme_unquiesce_admin_queue(&dev->ctrl);
2776 mutex_unlock(&dev->shutdown_lock);
2777
2778 /*
2779 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2780 * initializing procedure here.
2781 */
2782 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2783 dev_warn(dev->ctrl.device,
2784 "failed to mark controller CONNECTING\n");
2785 result = -EBUSY;
2786 goto out;
2787 }
2788
2789 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2790 if (result)
2791 goto out;
2792
2793 nvme_dbbuf_dma_alloc(dev);
2794
2795 result = nvme_setup_host_mem(dev);
2796 if (result < 0)
2797 goto out;
2798
2799 result = nvme_setup_io_queues(dev);
2800 if (result)
2801 goto out;
2802
2803 /*
2804 * Freeze and update the number of I/O queues as thos might have
2805 * changed. If there are no I/O queues left after this reset, keep the
2806 * controller around but remove all namespaces.
2807 */
2808 if (dev->online_queues > 1) {
2809 nvme_dbbuf_set(dev);
2810 nvme_unquiesce_io_queues(&dev->ctrl);
2811 nvme_wait_freeze(&dev->ctrl);
2812 if (!nvme_pci_update_nr_queues(dev))
2813 goto out;
2814 nvme_unfreeze(&dev->ctrl);
2815 } else {
2816 dev_warn(dev->ctrl.device, "IO queues lost\n");
2817 nvme_mark_namespaces_dead(&dev->ctrl);
2818 nvme_unquiesce_io_queues(&dev->ctrl);
2819 nvme_remove_namespaces(&dev->ctrl);
2820 nvme_free_tagset(dev);
2821 }
2822
2823 /*
2824 * If only admin queue live, keep it to do further investigation or
2825 * recovery.
2826 */
2827 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2828 dev_warn(dev->ctrl.device,
2829 "failed to mark controller live state\n");
2830 result = -ENODEV;
2831 goto out;
2832 }
2833
2834 nvme_start_ctrl(&dev->ctrl);
2835 return;
2836
2837 out_unlock:
2838 mutex_unlock(&dev->shutdown_lock);
2839 out:
2840 /*
2841 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2842 * may be holding this pci_dev's device lock.
2843 */
2844 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2845 result);
2846 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2847 nvme_dev_disable(dev, true);
2848 nvme_sync_queues(&dev->ctrl);
2849 nvme_mark_namespaces_dead(&dev->ctrl);
2850 nvme_unquiesce_io_queues(&dev->ctrl);
2851 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2852 }
2853
nvme_pci_reg_read32(struct nvme_ctrl * ctrl,u32 off,u32 * val)2854 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2855 {
2856 *val = readl(to_nvme_dev(ctrl)->bar + off);
2857 return 0;
2858 }
2859
nvme_pci_reg_write32(struct nvme_ctrl * ctrl,u32 off,u32 val)2860 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2861 {
2862 writel(val, to_nvme_dev(ctrl)->bar + off);
2863 return 0;
2864 }
2865
nvme_pci_reg_read64(struct nvme_ctrl * ctrl,u32 off,u64 * val)2866 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2867 {
2868 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2869 return 0;
2870 }
2871
nvme_pci_get_address(struct nvme_ctrl * ctrl,char * buf,int size)2872 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2873 {
2874 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2875
2876 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2877 }
2878
nvme_pci_print_device_info(struct nvme_ctrl * ctrl)2879 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2880 {
2881 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2882 struct nvme_subsystem *subsys = ctrl->subsys;
2883
2884 dev_err(ctrl->device,
2885 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2886 pdev->vendor, pdev->device,
2887 nvme_strlen(subsys->model, sizeof(subsys->model)),
2888 subsys->model, nvme_strlen(subsys->firmware_rev,
2889 sizeof(subsys->firmware_rev)),
2890 subsys->firmware_rev);
2891 }
2892
nvme_pci_supports_pci_p2pdma(struct nvme_ctrl * ctrl)2893 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2894 {
2895 struct nvme_dev *dev = to_nvme_dev(ctrl);
2896
2897 return dma_pci_p2pdma_supported(dev->dev);
2898 }
2899
2900 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2901 .name = "pcie",
2902 .module = THIS_MODULE,
2903 .flags = NVME_F_METADATA_SUPPORTED,
2904 .dev_attr_groups = nvme_pci_dev_attr_groups,
2905 .reg_read32 = nvme_pci_reg_read32,
2906 .reg_write32 = nvme_pci_reg_write32,
2907 .reg_read64 = nvme_pci_reg_read64,
2908 .free_ctrl = nvme_pci_free_ctrl,
2909 .submit_async_event = nvme_pci_submit_async_event,
2910 .subsystem_reset = nvme_pci_subsystem_reset,
2911 .get_address = nvme_pci_get_address,
2912 .print_device_info = nvme_pci_print_device_info,
2913 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
2914 };
2915
nvme_dev_map(struct nvme_dev * dev)2916 static int nvme_dev_map(struct nvme_dev *dev)
2917 {
2918 struct pci_dev *pdev = to_pci_dev(dev->dev);
2919
2920 if (pci_request_mem_regions(pdev, "nvme"))
2921 return -ENODEV;
2922
2923 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2924 goto release;
2925
2926 return 0;
2927 release:
2928 pci_release_mem_regions(pdev);
2929 return -ENODEV;
2930 }
2931
check_vendor_combination_bug(struct pci_dev * pdev)2932 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2933 {
2934 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2935 /*
2936 * Several Samsung devices seem to drop off the PCIe bus
2937 * randomly when APST is on and uses the deepest sleep state.
2938 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2939 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2940 * 950 PRO 256GB", but it seems to be restricted to two Dell
2941 * laptops.
2942 */
2943 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2944 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2945 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2946 return NVME_QUIRK_NO_DEEPEST_PS;
2947 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2948 /*
2949 * Samsung SSD 960 EVO drops off the PCIe bus after system
2950 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2951 * within few minutes after bootup on a Coffee Lake board -
2952 * ASUS PRIME Z370-A
2953 */
2954 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2955 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2956 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2957 return NVME_QUIRK_NO_APST;
2958 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2959 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2960 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2961 /*
2962 * Forcing to use host managed nvme power settings for
2963 * lowest idle power with quick resume latency on
2964 * Samsung and Toshiba SSDs based on suspend behavior
2965 * on Coffee Lake board for LENOVO C640
2966 */
2967 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2968 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2969 return NVME_QUIRK_SIMPLE_SUSPEND;
2970 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
2971 pdev->device == 0x500f)) {
2972 /*
2973 * Exclude some Kingston NV1 and A2000 devices from
2974 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
2975 * lot fo energy with s2idle sleep on some TUXEDO platforms.
2976 */
2977 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
2978 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
2979 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
2980 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
2981 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2982 } else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) {
2983 /*
2984 * Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND
2985 * because of high power consumption (> 2 Watt) in s2idle
2986 * sleep. Only some boards with Intel CPU are affected.
2987 */
2988 if (dmi_match(DMI_BOARD_NAME, "GMxPXxx") ||
2989 dmi_match(DMI_BOARD_NAME, "PH4PG31") ||
2990 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1") ||
2991 dmi_match(DMI_BOARD_NAME, "PH6PG01_PH6PG71"))
2992 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2993 }
2994
2995 /*
2996 * NVMe SSD drops off the PCIe bus after system idle
2997 * for 10 hours on a Lenovo N60z board.
2998 */
2999 if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6"))
3000 return NVME_QUIRK_NO_APST;
3001
3002 return 0;
3003 }
3004
nvme_pci_alloc_dev(struct pci_dev * pdev,const struct pci_device_id * id)3005 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
3006 const struct pci_device_id *id)
3007 {
3008 unsigned long quirks = id->driver_data;
3009 int node = dev_to_node(&pdev->dev);
3010 struct nvme_dev *dev;
3011 int ret = -ENOMEM;
3012
3013 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3014 if (!dev)
3015 return ERR_PTR(-ENOMEM);
3016 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3017 mutex_init(&dev->shutdown_lock);
3018
3019 dev->nr_write_queues = write_queues;
3020 dev->nr_poll_queues = poll_queues;
3021 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3022 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3023 sizeof(struct nvme_queue), GFP_KERNEL, node);
3024 if (!dev->queues)
3025 goto out_free_dev;
3026
3027 dev->dev = get_device(&pdev->dev);
3028
3029 quirks |= check_vendor_combination_bug(pdev);
3030 if (!noacpi &&
3031 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
3032 acpi_storage_d3(&pdev->dev)) {
3033 /*
3034 * Some systems use a bios work around to ask for D3 on
3035 * platforms that support kernel managed suspend.
3036 */
3037 dev_info(&pdev->dev,
3038 "platform quirk: setting simple suspend\n");
3039 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3040 }
3041 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3042 quirks);
3043 if (ret)
3044 goto out_put_device;
3045
3046 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
3047 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
3048 else
3049 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3050 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3051 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
3052
3053 /*
3054 * Limit the max command size to prevent iod->sg allocations going
3055 * over a single page.
3056 */
3057 dev->ctrl.max_hw_sectors = min_t(u32,
3058 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
3059 dev->ctrl.max_segments = NVME_MAX_SEGS;
3060
3061 /*
3062 * There is no support for SGLs for metadata (yet), so we are limited to
3063 * a single integrity segment for the separate metadata pointer.
3064 */
3065 dev->ctrl.max_integrity_segments = 1;
3066 return dev;
3067
3068 out_put_device:
3069 put_device(dev->dev);
3070 kfree(dev->queues);
3071 out_free_dev:
3072 kfree(dev);
3073 return ERR_PTR(ret);
3074 }
3075
nvme_probe(struct pci_dev * pdev,const struct pci_device_id * id)3076 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3077 {
3078 struct nvme_dev *dev;
3079 int result = -ENOMEM;
3080
3081 dev = nvme_pci_alloc_dev(pdev, id);
3082 if (IS_ERR(dev))
3083 return PTR_ERR(dev);
3084
3085 result = nvme_add_ctrl(&dev->ctrl);
3086 if (result)
3087 goto out_put_ctrl;
3088
3089 result = nvme_dev_map(dev);
3090 if (result)
3091 goto out_uninit_ctrl;
3092
3093 result = nvme_setup_prp_pools(dev);
3094 if (result)
3095 goto out_dev_unmap;
3096
3097 result = nvme_pci_alloc_iod_mempool(dev);
3098 if (result)
3099 goto out_release_prp_pools;
3100
3101 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3102
3103 result = nvme_pci_enable(dev);
3104 if (result)
3105 goto out_release_iod_mempool;
3106
3107 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3108 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3109 if (result)
3110 goto out_disable;
3111
3112 /*
3113 * Mark the controller as connecting before sending admin commands to
3114 * allow the timeout handler to do the right thing.
3115 */
3116 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3117 dev_warn(dev->ctrl.device,
3118 "failed to mark controller CONNECTING\n");
3119 result = -EBUSY;
3120 goto out_disable;
3121 }
3122
3123 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3124 if (result)
3125 goto out_disable;
3126
3127 nvme_dbbuf_dma_alloc(dev);
3128
3129 result = nvme_setup_host_mem(dev);
3130 if (result < 0)
3131 goto out_disable;
3132
3133 result = nvme_setup_io_queues(dev);
3134 if (result)
3135 goto out_disable;
3136
3137 if (dev->online_queues > 1) {
3138 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3139 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3140 nvme_dbbuf_set(dev);
3141 }
3142
3143 if (!dev->ctrl.tagset)
3144 dev_warn(dev->ctrl.device, "IO queues not created\n");
3145
3146 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3147 dev_warn(dev->ctrl.device,
3148 "failed to mark controller live state\n");
3149 result = -ENODEV;
3150 goto out_disable;
3151 }
3152
3153 pci_set_drvdata(pdev, dev);
3154
3155 nvme_start_ctrl(&dev->ctrl);
3156 nvme_put_ctrl(&dev->ctrl);
3157 flush_work(&dev->ctrl.scan_work);
3158 return 0;
3159
3160 out_disable:
3161 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3162 nvme_dev_disable(dev, true);
3163 nvme_free_host_mem(dev);
3164 nvme_dev_remove_admin(dev);
3165 nvme_dbbuf_dma_free(dev);
3166 nvme_free_queues(dev, 0);
3167 out_release_iod_mempool:
3168 mempool_destroy(dev->iod_mempool);
3169 out_release_prp_pools:
3170 nvme_release_prp_pools(dev);
3171 out_dev_unmap:
3172 nvme_dev_unmap(dev);
3173 out_uninit_ctrl:
3174 nvme_uninit_ctrl(&dev->ctrl);
3175 out_put_ctrl:
3176 nvme_put_ctrl(&dev->ctrl);
3177 return result;
3178 }
3179
nvme_reset_prepare(struct pci_dev * pdev)3180 static void nvme_reset_prepare(struct pci_dev *pdev)
3181 {
3182 struct nvme_dev *dev = pci_get_drvdata(pdev);
3183
3184 /*
3185 * We don't need to check the return value from waiting for the reset
3186 * state as pci_dev device lock is held, making it impossible to race
3187 * with ->remove().
3188 */
3189 nvme_disable_prepare_reset(dev, false);
3190 nvme_sync_queues(&dev->ctrl);
3191 }
3192
nvme_reset_done(struct pci_dev * pdev)3193 static void nvme_reset_done(struct pci_dev *pdev)
3194 {
3195 struct nvme_dev *dev = pci_get_drvdata(pdev);
3196
3197 if (!nvme_try_sched_reset(&dev->ctrl))
3198 flush_work(&dev->ctrl.reset_work);
3199 }
3200
nvme_shutdown(struct pci_dev * pdev)3201 static void nvme_shutdown(struct pci_dev *pdev)
3202 {
3203 struct nvme_dev *dev = pci_get_drvdata(pdev);
3204
3205 nvme_disable_prepare_reset(dev, true);
3206 }
3207
3208 /*
3209 * The driver's remove may be called on a device in a partially initialized
3210 * state. This function must not have any dependencies on the device state in
3211 * order to proceed.
3212 */
nvme_remove(struct pci_dev * pdev)3213 static void nvme_remove(struct pci_dev *pdev)
3214 {
3215 struct nvme_dev *dev = pci_get_drvdata(pdev);
3216
3217 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3218 pci_set_drvdata(pdev, NULL);
3219
3220 if (!pci_device_is_present(pdev)) {
3221 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3222 nvme_dev_disable(dev, true);
3223 }
3224
3225 flush_work(&dev->ctrl.reset_work);
3226 nvme_stop_ctrl(&dev->ctrl);
3227 nvme_remove_namespaces(&dev->ctrl);
3228 nvme_dev_disable(dev, true);
3229 nvme_free_host_mem(dev);
3230 nvme_dev_remove_admin(dev);
3231 nvme_dbbuf_dma_free(dev);
3232 nvme_free_queues(dev, 0);
3233 mempool_destroy(dev->iod_mempool);
3234 nvme_release_prp_pools(dev);
3235 nvme_dev_unmap(dev);
3236 nvme_uninit_ctrl(&dev->ctrl);
3237 }
3238
3239 #ifdef CONFIG_PM_SLEEP
nvme_get_power_state(struct nvme_ctrl * ctrl,u32 * ps)3240 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3241 {
3242 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3243 }
3244
nvme_set_power_state(struct nvme_ctrl * ctrl,u32 ps)3245 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3246 {
3247 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3248 }
3249
nvme_resume(struct device * dev)3250 static int nvme_resume(struct device *dev)
3251 {
3252 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3253 struct nvme_ctrl *ctrl = &ndev->ctrl;
3254
3255 if (ndev->last_ps == U32_MAX ||
3256 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3257 goto reset;
3258 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3259 goto reset;
3260
3261 return 0;
3262 reset:
3263 return nvme_try_sched_reset(ctrl);
3264 }
3265
nvme_suspend(struct device * dev)3266 static int nvme_suspend(struct device *dev)
3267 {
3268 struct pci_dev *pdev = to_pci_dev(dev);
3269 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3270 struct nvme_ctrl *ctrl = &ndev->ctrl;
3271 int ret = -EBUSY;
3272
3273 ndev->last_ps = U32_MAX;
3274
3275 /*
3276 * The platform does not remove power for a kernel managed suspend so
3277 * use host managed nvme power settings for lowest idle power if
3278 * possible. This should have quicker resume latency than a full device
3279 * shutdown. But if the firmware is involved after the suspend or the
3280 * device does not support any non-default power states, shut down the
3281 * device fully.
3282 *
3283 * If ASPM is not enabled for the device, shut down the device and allow
3284 * the PCI bus layer to put it into D3 in order to take the PCIe link
3285 * down, so as to allow the platform to achieve its minimum low-power
3286 * state (which may not be possible if the link is up).
3287 */
3288 if (pm_suspend_via_firmware() || !ctrl->npss ||
3289 !pcie_aspm_enabled(pdev) ||
3290 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3291 return nvme_disable_prepare_reset(ndev, true);
3292
3293 nvme_start_freeze(ctrl);
3294 nvme_wait_freeze(ctrl);
3295 nvme_sync_queues(ctrl);
3296
3297 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3298 goto unfreeze;
3299
3300 /*
3301 * Host memory access may not be successful in a system suspend state,
3302 * but the specification allows the controller to access memory in a
3303 * non-operational power state.
3304 */
3305 if (ndev->hmb) {
3306 ret = nvme_set_host_mem(ndev, 0);
3307 if (ret < 0)
3308 goto unfreeze;
3309 }
3310
3311 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3312 if (ret < 0)
3313 goto unfreeze;
3314
3315 /*
3316 * A saved state prevents pci pm from generically controlling the
3317 * device's power. If we're using protocol specific settings, we don't
3318 * want pci interfering.
3319 */
3320 pci_save_state(pdev);
3321
3322 ret = nvme_set_power_state(ctrl, ctrl->npss);
3323 if (ret < 0)
3324 goto unfreeze;
3325
3326 if (ret) {
3327 /* discard the saved state */
3328 pci_load_saved_state(pdev, NULL);
3329
3330 /*
3331 * Clearing npss forces a controller reset on resume. The
3332 * correct value will be rediscovered then.
3333 */
3334 ret = nvme_disable_prepare_reset(ndev, true);
3335 ctrl->npss = 0;
3336 }
3337 unfreeze:
3338 nvme_unfreeze(ctrl);
3339 return ret;
3340 }
3341
nvme_simple_suspend(struct device * dev)3342 static int nvme_simple_suspend(struct device *dev)
3343 {
3344 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3345
3346 return nvme_disable_prepare_reset(ndev, true);
3347 }
3348
nvme_simple_resume(struct device * dev)3349 static int nvme_simple_resume(struct device *dev)
3350 {
3351 struct pci_dev *pdev = to_pci_dev(dev);
3352 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3353
3354 return nvme_try_sched_reset(&ndev->ctrl);
3355 }
3356
3357 static const struct dev_pm_ops nvme_dev_pm_ops = {
3358 .suspend = nvme_suspend,
3359 .resume = nvme_resume,
3360 .freeze = nvme_simple_suspend,
3361 .thaw = nvme_simple_resume,
3362 .poweroff = nvme_simple_suspend,
3363 .restore = nvme_simple_resume,
3364 };
3365 #endif /* CONFIG_PM_SLEEP */
3366
nvme_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3367 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3368 pci_channel_state_t state)
3369 {
3370 struct nvme_dev *dev = pci_get_drvdata(pdev);
3371
3372 /*
3373 * A frozen channel requires a reset. When detected, this method will
3374 * shutdown the controller to quiesce. The controller will be restarted
3375 * after the slot reset through driver's slot_reset callback.
3376 */
3377 switch (state) {
3378 case pci_channel_io_normal:
3379 return PCI_ERS_RESULT_CAN_RECOVER;
3380 case pci_channel_io_frozen:
3381 dev_warn(dev->ctrl.device,
3382 "frozen state error detected, reset controller\n");
3383 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3384 nvme_dev_disable(dev, true);
3385 return PCI_ERS_RESULT_DISCONNECT;
3386 }
3387 nvme_dev_disable(dev, false);
3388 return PCI_ERS_RESULT_NEED_RESET;
3389 case pci_channel_io_perm_failure:
3390 dev_warn(dev->ctrl.device,
3391 "failure state error detected, request disconnect\n");
3392 return PCI_ERS_RESULT_DISCONNECT;
3393 }
3394 return PCI_ERS_RESULT_NEED_RESET;
3395 }
3396
nvme_slot_reset(struct pci_dev * pdev)3397 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3398 {
3399 struct nvme_dev *dev = pci_get_drvdata(pdev);
3400
3401 dev_info(dev->ctrl.device, "restart after slot reset\n");
3402 pci_restore_state(pdev);
3403 if (!nvme_try_sched_reset(&dev->ctrl))
3404 nvme_unquiesce_io_queues(&dev->ctrl);
3405 return PCI_ERS_RESULT_RECOVERED;
3406 }
3407
nvme_error_resume(struct pci_dev * pdev)3408 static void nvme_error_resume(struct pci_dev *pdev)
3409 {
3410 struct nvme_dev *dev = pci_get_drvdata(pdev);
3411
3412 flush_work(&dev->ctrl.reset_work);
3413 }
3414
3415 static const struct pci_error_handlers nvme_err_handler = {
3416 .error_detected = nvme_error_detected,
3417 .slot_reset = nvme_slot_reset,
3418 .resume = nvme_error_resume,
3419 .reset_prepare = nvme_reset_prepare,
3420 .reset_done = nvme_reset_done,
3421 };
3422
3423 static const struct pci_device_id nvme_id_table[] = {
3424 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3425 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3426 NVME_QUIRK_DEALLOCATE_ZEROES, },
3427 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3428 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3429 NVME_QUIRK_DEALLOCATE_ZEROES, },
3430 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3431 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3432 NVME_QUIRK_DEALLOCATE_ZEROES |
3433 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3434 NVME_QUIRK_BOGUS_NID, },
3435 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3436 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3437 NVME_QUIRK_DEALLOCATE_ZEROES, },
3438 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3439 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3440 NVME_QUIRK_MEDIUM_PRIO_SQ |
3441 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3442 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3443 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3444 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3445 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3446 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3447 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3448 NVME_QUIRK_BOGUS_NID, },
3449 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3450 .driver_data = NVME_QUIRK_BOGUS_NID, },
3451 { PCI_DEVICE(0x1217, 0x8760), /* O2 Micro 64GB Steam Deck */
3452 .driver_data = NVME_QUIRK_QDEPTH_ONE },
3453 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3454 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3455 NVME_QUIRK_BOGUS_NID, },
3456 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3457 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3458 NVME_QUIRK_BOGUS_NID, },
3459 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3460 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3461 NVME_QUIRK_NO_NS_DESC_LIST, },
3462 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3463 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3464 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3465 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3466 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3467 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3468 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3469 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3470 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3471 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3472 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3473 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3474 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
3475 .driver_data = NVME_QUIRK_BROKEN_MSI },
3476 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3477 .driver_data = NVME_QUIRK_BOGUS_NID, },
3478 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3479 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3480 NVME_QUIRK_BOGUS_NID, },
3481 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3482 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3483 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3484 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3485 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3486 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3487 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3488 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3489 .driver_data = NVME_QUIRK_BOGUS_NID, },
3490 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3491 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3492 NVME_QUIRK_BOGUS_NID, },
3493 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3494 .driver_data = NVME_QUIRK_BOGUS_NID, },
3495 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3496 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3497 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3498 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3499 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3500 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3501 .driver_data = NVME_QUIRK_BOGUS_NID, },
3502 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3504 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3505 .driver_data = NVME_QUIRK_BOGUS_NID, },
3506 { PCI_DEVICE(0x1c5c, 0x1D59), /* SK Hynix BC901 */
3507 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3508 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3509 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3510 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3511 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3512 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3513 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3514 NVME_QUIRK_BOGUS_NID, },
3515 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3516 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3517 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3518 .driver_data = NVME_QUIRK_BOGUS_NID, },
3519 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3520 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3521 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3522 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3523 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3524 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3525 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3526 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3527 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3528 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3529 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3530 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3531 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3532 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3533 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3534 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3535 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3536 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3537 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3538 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3539 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3540 .driver_data = NVME_QUIRK_BOGUS_NID, },
3541 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3542 .driver_data = NVME_QUIRK_BOGUS_NID, },
3543 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3544 .driver_data = NVME_QUIRK_BOGUS_NID, },
3545 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3546 .driver_data = NVME_QUIRK_BOGUS_NID, },
3547 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3548 .driver_data = NVME_QUIRK_BOGUS_NID, },
3549 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3550 .driver_data = NVME_QUIRK_BOGUS_NID, },
3551 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3552 .driver_data = NVME_QUIRK_BOGUS_NID, },
3553 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3554 .driver_data = NVME_QUIRK_BOGUS_NID, },
3555 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3556 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3557 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3558 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3559 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3560 .driver_data = NVME_QUIRK_BOGUS_NID, },
3561 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3562 .driver_data = NVME_QUIRK_BOGUS_NID, },
3563 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3564 .driver_data = NVME_QUIRK_BOGUS_NID, },
3565 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3566 .driver_data = NVME_QUIRK_BOGUS_NID |
3567 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3568 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3569 .driver_data = NVME_QUIRK_BOGUS_NID, },
3570 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3571 .driver_data = NVME_QUIRK_BOGUS_NID, },
3572 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3573 .driver_data = NVME_QUIRK_BOGUS_NID, },
3574 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3575 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3576 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3577 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3578 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3579 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3580 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3581 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3582 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3583 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3584 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3585 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3586 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3587 /*
3588 * Fix for the Apple controller found in the MacBook8,1 and
3589 * some MacBook7,1 to avoid controller resets and data loss.
3590 */
3591 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3592 NVME_QUIRK_QDEPTH_ONE },
3593 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3594 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3595 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3596 NVME_QUIRK_128_BYTES_SQES |
3597 NVME_QUIRK_SHARED_TAGS |
3598 NVME_QUIRK_SKIP_CID_GEN |
3599 NVME_QUIRK_IDENTIFY_CNS },
3600 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3601 { 0, }
3602 };
3603 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3604
3605 static struct pci_driver nvme_driver = {
3606 .name = "nvme",
3607 .id_table = nvme_id_table,
3608 .probe = nvme_probe,
3609 .remove = nvme_remove,
3610 .shutdown = nvme_shutdown,
3611 .driver = {
3612 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3613 #ifdef CONFIG_PM_SLEEP
3614 .pm = &nvme_dev_pm_ops,
3615 #endif
3616 },
3617 .sriov_configure = pci_sriov_configure_simple,
3618 .err_handler = &nvme_err_handler,
3619 };
3620
nvme_init(void)3621 static int __init nvme_init(void)
3622 {
3623 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3624 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3625 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3626 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3627 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3628 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3629 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3630
3631 return pci_register_driver(&nvme_driver);
3632 }
3633
nvme_exit(void)3634 static void __exit nvme_exit(void)
3635 {
3636 pci_unregister_driver(&nvme_driver);
3637 flush_workqueue(nvme_wq);
3638 }
3639
3640 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3641 MODULE_LICENSE("GPL");
3642 MODULE_VERSION("1.0");
3643 MODULE_DESCRIPTION("NVMe host PCIe transport driver");
3644 module_init(nvme_init);
3645 module_exit(nvme_exit);
3646