1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_clock.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18
19 #include <dt-bindings/clock/qcom,ipq5424-nsscc.h>
20 #include <dt-bindings/interconnect/qcom,ipq5424.h>
21 #include <dt-bindings/reset/qcom,ipq5424-nsscc.h>
22
23 #include "clk-branch.h"
24 #include "clk-rcg.h"
25 #include "clk-regmap.h"
26 #include "clk-regmap-divider.h"
27 #include "common.h"
28 #include "reset.h"
29
30 /* Need to match the order of clocks in DT binding */
31 enum {
32 DT_CMN_PLL_XO_CLK,
33 DT_CMN_PLL_NSS_300M_CLK,
34 DT_CMN_PLL_NSS_375M_CLK,
35 DT_GCC_GPLL0_OUT_AUX,
36 DT_UNIPHY0_NSS_RX_CLK,
37 DT_UNIPHY0_NSS_TX_CLK,
38 DT_UNIPHY1_NSS_RX_CLK,
39 DT_UNIPHY1_NSS_TX_CLK,
40 DT_UNIPHY2_NSS_RX_CLK,
41 DT_UNIPHY2_NSS_TX_CLK,
42 };
43
44 enum {
45 P_CMN_PLL_XO_CLK,
46 P_CMN_PLL_NSS_300M_CLK,
47 P_CMN_PLL_NSS_375M_CLK,
48 P_GCC_GPLL0_OUT_AUX,
49 P_UNIPHY0_NSS_RX_CLK,
50 P_UNIPHY0_NSS_TX_CLK,
51 P_UNIPHY1_NSS_RX_CLK,
52 P_UNIPHY1_NSS_TX_CLK,
53 P_UNIPHY2_NSS_RX_CLK,
54 P_UNIPHY2_NSS_TX_CLK,
55 };
56
57 static const struct parent_map nss_cc_parent_map_0[] = {
58 { P_CMN_PLL_XO_CLK, 0 },
59 { P_GCC_GPLL0_OUT_AUX, 2 },
60 { P_CMN_PLL_NSS_300M_CLK, 5 },
61 { P_CMN_PLL_NSS_375M_CLK, 6 },
62 };
63
64 static const struct clk_parent_data nss_cc_parent_data_0[] = {
65 { .index = DT_CMN_PLL_XO_CLK },
66 { .index = DT_GCC_GPLL0_OUT_AUX },
67 { .index = DT_CMN_PLL_NSS_300M_CLK },
68 { .index = DT_CMN_PLL_NSS_375M_CLK },
69 };
70
71 static const struct parent_map nss_cc_parent_map_1[] = {
72 { P_CMN_PLL_XO_CLK, 0 },
73 { P_GCC_GPLL0_OUT_AUX, 2 },
74 { P_UNIPHY0_NSS_RX_CLK, 3 },
75 { P_UNIPHY0_NSS_TX_CLK, 4 },
76 { P_CMN_PLL_NSS_300M_CLK, 5 },
77 { P_CMN_PLL_NSS_375M_CLK, 6 },
78 };
79
80 static const struct clk_parent_data nss_cc_parent_data_1[] = {
81 { .index = DT_CMN_PLL_XO_CLK },
82 { .index = DT_GCC_GPLL0_OUT_AUX },
83 { .index = DT_UNIPHY0_NSS_RX_CLK },
84 { .index = DT_UNIPHY0_NSS_TX_CLK },
85 { .index = DT_CMN_PLL_NSS_300M_CLK },
86 { .index = DT_CMN_PLL_NSS_375M_CLK },
87 };
88
89 static const struct parent_map nss_cc_parent_map_2[] = {
90 { P_CMN_PLL_XO_CLK, 0 },
91 { P_GCC_GPLL0_OUT_AUX, 2 },
92 { P_UNIPHY1_NSS_RX_CLK, 3 },
93 { P_UNIPHY1_NSS_TX_CLK, 4 },
94 { P_CMN_PLL_NSS_300M_CLK, 5 },
95 { P_CMN_PLL_NSS_375M_CLK, 6 },
96 };
97
98 static const struct clk_parent_data nss_cc_parent_data_2[] = {
99 { .index = DT_CMN_PLL_XO_CLK },
100 { .index = DT_GCC_GPLL0_OUT_AUX },
101 { .index = DT_UNIPHY1_NSS_RX_CLK },
102 { .index = DT_UNIPHY1_NSS_TX_CLK },
103 { .index = DT_CMN_PLL_NSS_300M_CLK },
104 { .index = DT_CMN_PLL_NSS_375M_CLK },
105 };
106
107 static const struct parent_map nss_cc_parent_map_3[] = {
108 { P_CMN_PLL_XO_CLK, 0 },
109 { P_GCC_GPLL0_OUT_AUX, 2 },
110 { P_UNIPHY2_NSS_RX_CLK, 3 },
111 { P_UNIPHY2_NSS_TX_CLK, 4 },
112 { P_CMN_PLL_NSS_300M_CLK, 5 },
113 { P_CMN_PLL_NSS_375M_CLK, 6 },
114 };
115
116 static const struct clk_parent_data nss_cc_parent_data_3[] = {
117 { .index = DT_CMN_PLL_XO_CLK },
118 { .index = DT_GCC_GPLL0_OUT_AUX },
119 { .index = DT_UNIPHY2_NSS_RX_CLK },
120 { .index = DT_UNIPHY2_NSS_TX_CLK },
121 { .index = DT_CMN_PLL_NSS_300M_CLK },
122 { .index = DT_CMN_PLL_NSS_375M_CLK },
123 };
124
125 static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
126 F(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
127 F(375000000, P_CMN_PLL_NSS_375M_CLK, 1, 0, 0),
128 { }
129 };
130
131 static struct clk_rcg2 nss_cc_ce_clk_src = {
132 .cmd_rcgr = 0x5e0,
133 .mnd_width = 0,
134 .hid_width = 5,
135 .parent_map = nss_cc_parent_map_0,
136 .freq_tbl = ftbl_nss_cc_ce_clk_src,
137 .clkr.hw.init = &(const struct clk_init_data){
138 .name = "nss_cc_ce_clk_src",
139 .parent_data = nss_cc_parent_data_0,
140 .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
141 .flags = CLK_SET_RATE_PARENT,
142 .ops = &clk_rcg2_ops,
143 },
144 };
145
146 static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
147 F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
148 { }
149 };
150
151 static struct clk_rcg2 nss_cc_cfg_clk_src = {
152 .cmd_rcgr = 0x6a8,
153 .mnd_width = 0,
154 .hid_width = 5,
155 .parent_map = nss_cc_parent_map_0,
156 .freq_tbl = ftbl_nss_cc_cfg_clk_src,
157 .clkr.hw.init = &(const struct clk_init_data){
158 .name = "nss_cc_cfg_clk_src",
159 .parent_data = nss_cc_parent_data_0,
160 .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
161 .flags = CLK_SET_RATE_PARENT,
162 .ops = &clk_rcg2_ops,
163 },
164 };
165
166 static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] = {
167 F(300000000, P_CMN_PLL_NSS_300M_CLK, 1, 0, 0),
168 F(375000000, P_CMN_PLL_NSS_375M_CLK, 1, 0, 0),
169 { }
170 };
171
172 static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src = {
173 .cmd_rcgr = 0x644,
174 .mnd_width = 0,
175 .hid_width = 5,
176 .parent_map = nss_cc_parent_map_0,
177 .freq_tbl = ftbl_nss_cc_eip_bfdcd_clk_src,
178 .clkr.hw.init = &(const struct clk_init_data){
179 .name = "nss_cc_eip_bfdcd_clk_src",
180 .parent_data = nss_cc_parent_data_0,
181 .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
182 .flags = CLK_SET_RATE_PARENT,
183 .ops = &clk_rcg2_ops,
184 },
185 };
186
187 static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
188 C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
189 C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
190 };
191
192 static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
193 C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
194 C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
195 };
196
197 static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
198 FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
199 FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
200 FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
201 FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
202 FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0),
203 FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
204 { }
205 };
206
207 static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
208 .cmd_rcgr = 0x4b4,
209 .mnd_width = 0,
210 .hid_width = 5,
211 .parent_map = nss_cc_parent_map_1,
212 .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
213 .clkr.hw.init = &(const struct clk_init_data){
214 .name = "nss_cc_port1_rx_clk_src",
215 .parent_data = nss_cc_parent_data_1,
216 .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
217 .ops = &clk_rcg2_fm_ops,
218 },
219 };
220
221 static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
222 C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
223 C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
224 };
225
226 static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
227 C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
228 C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
229 };
230
231 static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
232 FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
233 FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
234 FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
235 FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
236 FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0),
237 FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
238 { }
239 };
240
241 static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
242 .cmd_rcgr = 0x4c0,
243 .mnd_width = 0,
244 .hid_width = 5,
245 .parent_map = nss_cc_parent_map_1,
246 .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
247 .clkr.hw.init = &(const struct clk_init_data){
248 .name = "nss_cc_port1_tx_clk_src",
249 .parent_data = nss_cc_parent_data_1,
250 .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
251 .ops = &clk_rcg2_fm_ops,
252 },
253 };
254
255 static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = {
256 C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
257 C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
258 };
259
260 static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = {
261 C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
262 C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
263 };
264
265 static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = {
266 FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
267 FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25),
268 FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
269 FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125),
270 FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
271 FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
272 { }
273 };
274
275 static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
276 .cmd_rcgr = 0x4cc,
277 .mnd_width = 0,
278 .hid_width = 5,
279 .parent_map = nss_cc_parent_map_2,
280 .freq_multi_tbl = ftbl_nss_cc_port2_rx_clk_src,
281 .clkr.hw.init = &(const struct clk_init_data){
282 .name = "nss_cc_port2_rx_clk_src",
283 .parent_data = nss_cc_parent_data_2,
284 .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
285 .ops = &clk_rcg2_fm_ops,
286 },
287 };
288
289 static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = {
290 C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
291 C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
292 };
293
294 static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = {
295 C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
296 C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
297 };
298
299 static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = {
300 FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
301 FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25),
302 FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
303 FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125),
304 FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
305 FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
306 { }
307 };
308
309 static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
310 .cmd_rcgr = 0x4d8,
311 .mnd_width = 0,
312 .hid_width = 5,
313 .parent_map = nss_cc_parent_map_2,
314 .freq_multi_tbl = ftbl_nss_cc_port2_tx_clk_src,
315 .clkr.hw.init = &(const struct clk_init_data){
316 .name = "nss_cc_port2_tx_clk_src",
317 .parent_data = nss_cc_parent_data_2,
318 .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
319 .ops = &clk_rcg2_fm_ops,
320 },
321 };
322
323 static const struct freq_conf ftbl_nss_cc_port3_rx_clk_src_25[] = {
324 C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
325 C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
326 };
327
328 static const struct freq_conf ftbl_nss_cc_port3_rx_clk_src_125[] = {
329 C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
330 C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
331 };
332
333 static const struct freq_multi_tbl ftbl_nss_cc_port3_rx_clk_src[] = {
334 FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
335 FM(25000000, ftbl_nss_cc_port3_rx_clk_src_25),
336 FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
337 FM(125000000, ftbl_nss_cc_port3_rx_clk_src_125),
338 FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
339 FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
340 { }
341 };
342
343 static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
344 .cmd_rcgr = 0x4e4,
345 .mnd_width = 0,
346 .hid_width = 5,
347 .parent_map = nss_cc_parent_map_3,
348 .freq_multi_tbl = ftbl_nss_cc_port3_rx_clk_src,
349 .clkr.hw.init = &(const struct clk_init_data){
350 .name = "nss_cc_port3_rx_clk_src",
351 .parent_data = nss_cc_parent_data_3,
352 .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
353 .ops = &clk_rcg2_fm_ops,
354 },
355 };
356
357 static const struct freq_conf ftbl_nss_cc_port3_tx_clk_src_25[] = {
358 C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
359 C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
360 };
361
362 static const struct freq_conf ftbl_nss_cc_port3_tx_clk_src_125[] = {
363 C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
364 C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
365 };
366
367 static const struct freq_multi_tbl ftbl_nss_cc_port3_tx_clk_src[] = {
368 FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
369 FM(25000000, ftbl_nss_cc_port3_tx_clk_src_25),
370 FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
371 FM(125000000, ftbl_nss_cc_port3_tx_clk_src_125),
372 FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
373 FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
374 { }
375 };
376
377 static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
378 .cmd_rcgr = 0x4f0,
379 .mnd_width = 0,
380 .hid_width = 5,
381 .parent_map = nss_cc_parent_map_3,
382 .freq_multi_tbl = ftbl_nss_cc_port3_tx_clk_src,
383 .clkr.hw.init = &(const struct clk_init_data){
384 .name = "nss_cc_port3_tx_clk_src",
385 .parent_data = nss_cc_parent_data_3,
386 .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
387 .ops = &clk_rcg2_fm_ops,
388 },
389 };
390
391 static struct clk_rcg2 nss_cc_ppe_clk_src = {
392 .cmd_rcgr = 0x3ec,
393 .mnd_width = 0,
394 .hid_width = 5,
395 .parent_map = nss_cc_parent_map_0,
396 .freq_tbl = ftbl_nss_cc_ce_clk_src,
397 .clkr.hw.init = &(const struct clk_init_data){
398 .name = "nss_cc_ppe_clk_src",
399 .parent_data = nss_cc_parent_data_0,
400 .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
401 .flags = CLK_SET_RATE_PARENT,
402 .ops = &clk_rcg2_ops,
403 },
404 };
405
406 static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
407 .reg = 0x4bc,
408 .shift = 0,
409 .width = 9,
410 .clkr.hw.init = &(const struct clk_init_data) {
411 .name = "nss_cc_port1_rx_div_clk_src",
412 .parent_hws = (const struct clk_hw*[]){
413 &nss_cc_port1_rx_clk_src.clkr.hw,
414 },
415 .num_parents = 1,
416 .flags = CLK_SET_RATE_PARENT,
417 .ops = &clk_regmap_div_ops,
418 },
419 };
420
421 static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
422 .reg = 0x4c8,
423 .shift = 0,
424 .width = 9,
425 .clkr.hw.init = &(const struct clk_init_data) {
426 .name = "nss_cc_port1_tx_div_clk_src",
427 .parent_hws = (const struct clk_hw*[]){
428 &nss_cc_port1_tx_clk_src.clkr.hw,
429 },
430 .num_parents = 1,
431 .flags = CLK_SET_RATE_PARENT,
432 .ops = &clk_regmap_div_ops,
433 },
434 };
435
436 static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
437 .reg = 0x4d4,
438 .shift = 0,
439 .width = 9,
440 .clkr.hw.init = &(const struct clk_init_data) {
441 .name = "nss_cc_port2_rx_div_clk_src",
442 .parent_hws = (const struct clk_hw*[]){
443 &nss_cc_port2_rx_clk_src.clkr.hw,
444 },
445 .num_parents = 1,
446 .flags = CLK_SET_RATE_PARENT,
447 .ops = &clk_regmap_div_ops,
448 },
449 };
450
451 static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
452 .reg = 0x4e0,
453 .shift = 0,
454 .width = 9,
455 .clkr.hw.init = &(const struct clk_init_data) {
456 .name = "nss_cc_port2_tx_div_clk_src",
457 .parent_hws = (const struct clk_hw*[]){
458 &nss_cc_port2_tx_clk_src.clkr.hw,
459 },
460 .num_parents = 1,
461 .flags = CLK_SET_RATE_PARENT,
462 .ops = &clk_regmap_div_ops,
463 },
464 };
465
466 static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
467 .reg = 0x4ec,
468 .shift = 0,
469 .width = 9,
470 .clkr.hw.init = &(const struct clk_init_data) {
471 .name = "nss_cc_port3_rx_div_clk_src",
472 .parent_hws = (const struct clk_hw*[]){
473 &nss_cc_port3_rx_clk_src.clkr.hw,
474 },
475 .num_parents = 1,
476 .flags = CLK_SET_RATE_PARENT,
477 .ops = &clk_regmap_div_ops,
478 },
479 };
480
481 static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
482 .reg = 0x4f8,
483 .shift = 0,
484 .width = 9,
485 .clkr.hw.init = &(const struct clk_init_data) {
486 .name = "nss_cc_port3_tx_div_clk_src",
487 .parent_hws = (const struct clk_hw*[]){
488 &nss_cc_port3_tx_clk_src.clkr.hw,
489 },
490 .num_parents = 1,
491 .flags = CLK_SET_RATE_PARENT,
492 .ops = &clk_regmap_div_ops,
493 },
494 };
495
496 static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
497 .reg = 0x3f4,
498 .shift = 0,
499 .width = 4,
500 .clkr.hw.init = &(const struct clk_init_data) {
501 .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
502 .parent_hws = (const struct clk_hw*[]){
503 &nss_cc_ppe_clk_src.clkr.hw,
504 },
505 .num_parents = 1,
506 .flags = CLK_SET_RATE_PARENT,
507 .ops = &clk_regmap_div_ro_ops,
508 },
509 };
510
511 static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
512 .reg = 0x3f8,
513 .shift = 0,
514 .width = 4,
515 .clkr.hw.init = &(const struct clk_init_data) {
516 .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
517 .parent_hws = (const struct clk_hw*[]){
518 &nss_cc_ppe_clk_src.clkr.hw,
519 },
520 .num_parents = 1,
521 .flags = CLK_SET_RATE_PARENT,
522 .ops = &clk_regmap_div_ro_ops,
523 },
524 };
525
526 static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
527 .reg = 0x3fc,
528 .shift = 0,
529 .width = 4,
530 .clkr.hw.init = &(const struct clk_init_data) {
531 .name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
532 .parent_hws = (const struct clk_hw*[]){
533 &nss_cc_ppe_clk_src.clkr.hw,
534 },
535 .num_parents = 1,
536 .flags = CLK_SET_RATE_PARENT,
537 .ops = &clk_regmap_div_ro_ops,
538 },
539 };
540
541 static struct clk_branch nss_cc_ce_apb_clk = {
542 .halt_reg = 0x5e8,
543 .halt_check = BRANCH_HALT,
544 .clkr = {
545 .enable_reg = 0x5e8,
546 .enable_mask = BIT(0),
547 .hw.init = &(const struct clk_init_data){
548 .name = "nss_cc_ce_apb_clk",
549 .parent_hws = (const struct clk_hw*[]){
550 &nss_cc_ce_clk_src.clkr.hw,
551 },
552 .num_parents = 1,
553 .flags = CLK_SET_RATE_PARENT,
554 .ops = &clk_branch2_ops,
555 },
556 },
557 };
558
559 static struct clk_branch nss_cc_ce_axi_clk = {
560 .halt_reg = 0x5ec,
561 .halt_check = BRANCH_HALT,
562 .clkr = {
563 .enable_reg = 0x5ec,
564 .enable_mask = BIT(0),
565 .hw.init = &(const struct clk_init_data){
566 .name = "nss_cc_ce_axi_clk",
567 .parent_hws = (const struct clk_hw*[]){
568 &nss_cc_ce_clk_src.clkr.hw,
569 },
570 .num_parents = 1,
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_branch2_ops,
573 },
574 },
575 };
576
577 static struct clk_branch nss_cc_debug_clk = {
578 .halt_reg = 0x70c,
579 .halt_check = BRANCH_HALT,
580 .clkr = {
581 .enable_reg = 0x70c,
582 .enable_mask = BIT(0),
583 .hw.init = &(const struct clk_init_data){
584 .name = "nss_cc_debug_clk",
585 .ops = &clk_branch2_ops,
586 },
587 },
588 };
589
590 static struct clk_branch nss_cc_eip_clk = {
591 .halt_reg = 0x658,
592 .halt_check = BRANCH_HALT,
593 .clkr = {
594 .enable_reg = 0x658,
595 .enable_mask = BIT(0),
596 .hw.init = &(const struct clk_init_data){
597 .name = "nss_cc_eip_clk",
598 .parent_hws = (const struct clk_hw*[]){
599 &nss_cc_eip_bfdcd_clk_src.clkr.hw,
600 },
601 .num_parents = 1,
602 .flags = CLK_SET_RATE_PARENT,
603 .ops = &clk_branch2_ops,
604 },
605 },
606 };
607
608 static struct clk_branch nss_cc_nss_csr_clk = {
609 .halt_reg = 0x6b0,
610 .halt_check = BRANCH_HALT,
611 .clkr = {
612 .enable_reg = 0x6b0,
613 .enable_mask = BIT(0),
614 .hw.init = &(const struct clk_init_data){
615 .name = "nss_cc_nss_csr_clk",
616 .parent_hws = (const struct clk_hw*[]){
617 &nss_cc_cfg_clk_src.clkr.hw,
618 },
619 .num_parents = 1,
620 .flags = CLK_SET_RATE_PARENT,
621 .ops = &clk_branch2_ops,
622 },
623 },
624 };
625
626 static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
627 .halt_reg = 0x5f4,
628 .halt_check = BRANCH_HALT,
629 .clkr = {
630 .enable_reg = 0x5f4,
631 .enable_mask = BIT(0),
632 .hw.init = &(const struct clk_init_data){
633 .name = "nss_cc_nssnoc_ce_apb_clk",
634 .parent_hws = (const struct clk_hw*[]){
635 &nss_cc_ce_clk_src.clkr.hw,
636 },
637 .num_parents = 1,
638 .flags = CLK_SET_RATE_PARENT,
639 .ops = &clk_branch2_ops,
640 },
641 },
642 };
643
644 static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
645 .halt_reg = 0x5f8,
646 .halt_check = BRANCH_HALT,
647 .clkr = {
648 .enable_reg = 0x5f8,
649 .enable_mask = BIT(0),
650 .hw.init = &(const struct clk_init_data){
651 .name = "nss_cc_nssnoc_ce_axi_clk",
652 .parent_hws = (const struct clk_hw*[]){
653 &nss_cc_ce_clk_src.clkr.hw,
654 },
655 .num_parents = 1,
656 .flags = CLK_SET_RATE_PARENT,
657 .ops = &clk_branch2_ops,
658 },
659 },
660 };
661
662 static struct clk_branch nss_cc_nssnoc_eip_clk = {
663 .halt_reg = 0x660,
664 .halt_check = BRANCH_HALT,
665 .clkr = {
666 .enable_reg = 0x660,
667 .enable_mask = BIT(0),
668 .hw.init = &(const struct clk_init_data){
669 .name = "nss_cc_nssnoc_eip_clk",
670 .parent_hws = (const struct clk_hw*[]){
671 &nss_cc_eip_bfdcd_clk_src.clkr.hw,
672 },
673 .num_parents = 1,
674 .flags = CLK_SET_RATE_PARENT,
675 .ops = &clk_branch2_ops,
676 },
677 },
678 };
679
680 static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
681 .halt_reg = 0x6b4,
682 .halt_check = BRANCH_HALT,
683 .clkr = {
684 .enable_reg = 0x6b4,
685 .enable_mask = BIT(0),
686 .hw.init = &(const struct clk_init_data){
687 .name = "nss_cc_nssnoc_nss_csr_clk",
688 .parent_hws = (const struct clk_hw*[]){
689 &nss_cc_cfg_clk_src.clkr.hw,
690 },
691 .num_parents = 1,
692 .flags = CLK_SET_RATE_PARENT,
693 .ops = &clk_branch2_ops,
694 },
695 },
696 };
697
698 static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
699 .halt_reg = 0x444,
700 .halt_check = BRANCH_HALT,
701 .clkr = {
702 .enable_reg = 0x444,
703 .enable_mask = BIT(0),
704 .hw.init = &(const struct clk_init_data){
705 .name = "nss_cc_nssnoc_ppe_cfg_clk",
706 .parent_hws = (const struct clk_hw*[]){
707 &nss_cc_ppe_clk_src.clkr.hw,
708 },
709 .num_parents = 1,
710 .flags = CLK_SET_RATE_PARENT,
711 .ops = &clk_branch2_ops,
712 },
713 },
714 };
715
716 static struct clk_branch nss_cc_nssnoc_ppe_clk = {
717 .halt_reg = 0x440,
718 .halt_check = BRANCH_HALT,
719 .clkr = {
720 .enable_reg = 0x440,
721 .enable_mask = BIT(0),
722 .hw.init = &(const struct clk_init_data){
723 .name = "nss_cc_nssnoc_ppe_clk",
724 .parent_hws = (const struct clk_hw*[]){
725 &nss_cc_ppe_clk_src.clkr.hw,
726 },
727 .num_parents = 1,
728 .flags = CLK_SET_RATE_PARENT,
729 .ops = &clk_branch2_ops,
730 },
731 },
732 };
733
734 static struct clk_branch nss_cc_port1_mac_clk = {
735 .halt_reg = 0x428,
736 .halt_check = BRANCH_HALT,
737 .clkr = {
738 .enable_reg = 0x428,
739 .enable_mask = BIT(0),
740 .hw.init = &(const struct clk_init_data){
741 .name = "nss_cc_port1_mac_clk",
742 .parent_hws = (const struct clk_hw*[]){
743 &nss_cc_ppe_clk_src.clkr.hw,
744 },
745 .num_parents = 1,
746 .flags = CLK_SET_RATE_PARENT,
747 .ops = &clk_branch2_ops,
748 },
749 },
750 };
751
752 static struct clk_branch nss_cc_port1_rx_clk = {
753 .halt_reg = 0x4fc,
754 .halt_check = BRANCH_HALT,
755 .clkr = {
756 .enable_reg = 0x4fc,
757 .enable_mask = BIT(0),
758 .hw.init = &(const struct clk_init_data){
759 .name = "nss_cc_port1_rx_clk",
760 .parent_hws = (const struct clk_hw*[]){
761 &nss_cc_port1_rx_div_clk_src.clkr.hw,
762 },
763 .num_parents = 1,
764 .flags = CLK_SET_RATE_PARENT,
765 .ops = &clk_branch2_ops,
766 },
767 },
768 };
769
770 static struct clk_branch nss_cc_port1_tx_clk = {
771 .halt_reg = 0x504,
772 .halt_check = BRANCH_HALT,
773 .clkr = {
774 .enable_reg = 0x504,
775 .enable_mask = BIT(0),
776 .hw.init = &(const struct clk_init_data){
777 .name = "nss_cc_port1_tx_clk",
778 .parent_hws = (const struct clk_hw*[]){
779 &nss_cc_port1_tx_div_clk_src.clkr.hw,
780 },
781 .num_parents = 1,
782 .flags = CLK_SET_RATE_PARENT,
783 .ops = &clk_branch2_ops,
784 },
785 },
786 };
787
788 static struct clk_branch nss_cc_port2_mac_clk = {
789 .halt_reg = 0x430,
790 .halt_check = BRANCH_HALT,
791 .clkr = {
792 .enable_reg = 0x430,
793 .enable_mask = BIT(0),
794 .hw.init = &(const struct clk_init_data){
795 .name = "nss_cc_port2_mac_clk",
796 .parent_hws = (const struct clk_hw*[]){
797 &nss_cc_ppe_clk_src.clkr.hw,
798 },
799 .num_parents = 1,
800 .flags = CLK_SET_RATE_PARENT,
801 .ops = &clk_branch2_ops,
802 },
803 },
804 };
805
806 static struct clk_branch nss_cc_port2_rx_clk = {
807 .halt_reg = 0x50c,
808 .halt_check = BRANCH_HALT,
809 .clkr = {
810 .enable_reg = 0x50c,
811 .enable_mask = BIT(0),
812 .hw.init = &(const struct clk_init_data){
813 .name = "nss_cc_port2_rx_clk",
814 .parent_hws = (const struct clk_hw*[]){
815 &nss_cc_port2_rx_div_clk_src.clkr.hw,
816 },
817 .num_parents = 1,
818 .flags = CLK_SET_RATE_PARENT,
819 .ops = &clk_branch2_ops,
820 },
821 },
822 };
823
824 static struct clk_branch nss_cc_port2_tx_clk = {
825 .halt_reg = 0x514,
826 .halt_check = BRANCH_HALT,
827 .clkr = {
828 .enable_reg = 0x514,
829 .enable_mask = BIT(0),
830 .hw.init = &(const struct clk_init_data){
831 .name = "nss_cc_port2_tx_clk",
832 .parent_hws = (const struct clk_hw*[]){
833 &nss_cc_port2_tx_div_clk_src.clkr.hw,
834 },
835 .num_parents = 1,
836 .flags = CLK_SET_RATE_PARENT,
837 .ops = &clk_branch2_ops,
838 },
839 },
840 };
841
842 static struct clk_branch nss_cc_port3_mac_clk = {
843 .halt_reg = 0x438,
844 .halt_check = BRANCH_HALT,
845 .clkr = {
846 .enable_reg = 0x438,
847 .enable_mask = BIT(0),
848 .hw.init = &(const struct clk_init_data){
849 .name = "nss_cc_port3_mac_clk",
850 .parent_hws = (const struct clk_hw*[]){
851 &nss_cc_ppe_clk_src.clkr.hw,
852 },
853 .num_parents = 1,
854 .flags = CLK_SET_RATE_PARENT,
855 .ops = &clk_branch2_ops,
856 },
857 },
858 };
859
860 static struct clk_branch nss_cc_port3_rx_clk = {
861 .halt_reg = 0x51c,
862 .halt_check = BRANCH_HALT,
863 .clkr = {
864 .enable_reg = 0x51c,
865 .enable_mask = BIT(0),
866 .hw.init = &(const struct clk_init_data){
867 .name = "nss_cc_port3_rx_clk",
868 .parent_hws = (const struct clk_hw*[]){
869 &nss_cc_port3_rx_div_clk_src.clkr.hw,
870 },
871 .num_parents = 1,
872 .flags = CLK_SET_RATE_PARENT,
873 .ops = &clk_branch2_ops,
874 },
875 },
876 };
877
878 static struct clk_branch nss_cc_port3_tx_clk = {
879 .halt_reg = 0x524,
880 .halt_check = BRANCH_HALT,
881 .clkr = {
882 .enable_reg = 0x524,
883 .enable_mask = BIT(0),
884 .hw.init = &(const struct clk_init_data){
885 .name = "nss_cc_port3_tx_clk",
886 .parent_hws = (const struct clk_hw*[]){
887 &nss_cc_port3_tx_div_clk_src.clkr.hw,
888 },
889 .num_parents = 1,
890 .flags = CLK_SET_RATE_PARENT,
891 .ops = &clk_branch2_ops,
892 },
893 },
894 };
895
896 static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
897 .halt_reg = 0x424,
898 .halt_check = BRANCH_HALT,
899 .clkr = {
900 .enable_reg = 0x424,
901 .enable_mask = BIT(0),
902 .hw.init = &(const struct clk_init_data){
903 .name = "nss_cc_ppe_edma_cfg_clk",
904 .parent_hws = (const struct clk_hw*[]){
905 &nss_cc_ppe_clk_src.clkr.hw,
906 },
907 .num_parents = 1,
908 .flags = CLK_SET_RATE_PARENT,
909 .ops = &clk_branch2_ops,
910 },
911 },
912 };
913
914 static struct clk_branch nss_cc_ppe_edma_clk = {
915 .halt_reg = 0x41c,
916 .halt_check = BRANCH_HALT,
917 .clkr = {
918 .enable_reg = 0x41c,
919 .enable_mask = BIT(0),
920 .hw.init = &(const struct clk_init_data){
921 .name = "nss_cc_ppe_edma_clk",
922 .parent_hws = (const struct clk_hw*[]){
923 &nss_cc_ppe_clk_src.clkr.hw,
924 },
925 .num_parents = 1,
926 .flags = CLK_SET_RATE_PARENT,
927 .ops = &clk_branch2_ops,
928 },
929 },
930 };
931
932 static struct clk_branch nss_cc_ppe_switch_btq_clk = {
933 .halt_reg = 0x408,
934 .halt_check = BRANCH_HALT,
935 .clkr = {
936 .enable_reg = 0x408,
937 .enable_mask = BIT(0),
938 .hw.init = &(const struct clk_init_data){
939 .name = "nss_cc_ppe_switch_btq_clk",
940 .parent_hws = (const struct clk_hw*[]){
941 &nss_cc_ppe_clk_src.clkr.hw,
942 },
943 .num_parents = 1,
944 .flags = CLK_SET_RATE_PARENT,
945 .ops = &clk_branch2_ops,
946 },
947 },
948 };
949
950 static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
951 .halt_reg = 0x418,
952 .halt_check = BRANCH_HALT,
953 .clkr = {
954 .enable_reg = 0x418,
955 .enable_mask = BIT(0),
956 .hw.init = &(const struct clk_init_data){
957 .name = "nss_cc_ppe_switch_cfg_clk",
958 .parent_hws = (const struct clk_hw*[]){
959 &nss_cc_ppe_clk_src.clkr.hw,
960 },
961 .num_parents = 1,
962 .flags = CLK_SET_RATE_PARENT,
963 .ops = &clk_branch2_ops,
964 },
965 },
966 };
967
968 static struct clk_branch nss_cc_ppe_switch_clk = {
969 .halt_reg = 0x410,
970 .halt_check = BRANCH_HALT,
971 .clkr = {
972 .enable_reg = 0x410,
973 .enable_mask = BIT(0),
974 .hw.init = &(const struct clk_init_data){
975 .name = "nss_cc_ppe_switch_clk",
976 .parent_hws = (const struct clk_hw*[]){
977 &nss_cc_ppe_clk_src.clkr.hw,
978 },
979 .num_parents = 1,
980 .flags = CLK_SET_RATE_PARENT,
981 .ops = &clk_branch2_ops,
982 },
983 },
984 };
985
986 static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
987 .halt_reg = 0x400,
988 .halt_check = BRANCH_HALT,
989 .clkr = {
990 .enable_reg = 0x400,
991 .enable_mask = BIT(0),
992 .hw.init = &(const struct clk_init_data){
993 .name = "nss_cc_ppe_switch_ipe_clk",
994 .parent_hws = (const struct clk_hw*[]){
995 &nss_cc_ppe_clk_src.clkr.hw,
996 },
997 .num_parents = 1,
998 .flags = CLK_SET_RATE_PARENT,
999 .ops = &clk_branch2_ops,
1000 },
1001 },
1002 };
1003
1004 static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
1005 .halt_reg = 0x57c,
1006 .halt_check = BRANCH_HALT,
1007 .clkr = {
1008 .enable_reg = 0x57c,
1009 .enable_mask = BIT(0),
1010 .hw.init = &(const struct clk_init_data){
1011 .name = "nss_cc_uniphy_port1_rx_clk",
1012 .parent_hws = (const struct clk_hw*[]){
1013 &nss_cc_port1_rx_div_clk_src.clkr.hw,
1014 },
1015 .num_parents = 1,
1016 .flags = CLK_SET_RATE_PARENT,
1017 .ops = &clk_branch2_ops,
1018 },
1019 },
1020 };
1021
1022 static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
1023 .halt_reg = 0x580,
1024 .halt_check = BRANCH_HALT,
1025 .clkr = {
1026 .enable_reg = 0x580,
1027 .enable_mask = BIT(0),
1028 .hw.init = &(const struct clk_init_data){
1029 .name = "nss_cc_uniphy_port1_tx_clk",
1030 .parent_hws = (const struct clk_hw*[]){
1031 &nss_cc_port1_tx_div_clk_src.clkr.hw,
1032 },
1033 .num_parents = 1,
1034 .flags = CLK_SET_RATE_PARENT,
1035 .ops = &clk_branch2_ops,
1036 },
1037 },
1038 };
1039
1040 static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
1041 .halt_reg = 0x584,
1042 .halt_check = BRANCH_HALT,
1043 .clkr = {
1044 .enable_reg = 0x584,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(const struct clk_init_data){
1047 .name = "nss_cc_uniphy_port2_rx_clk",
1048 .parent_hws = (const struct clk_hw*[]){
1049 &nss_cc_port2_rx_div_clk_src.clkr.hw,
1050 },
1051 .num_parents = 1,
1052 .flags = CLK_SET_RATE_PARENT,
1053 .ops = &clk_branch2_ops,
1054 },
1055 },
1056 };
1057
1058 static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
1059 .halt_reg = 0x588,
1060 .halt_check = BRANCH_HALT,
1061 .clkr = {
1062 .enable_reg = 0x588,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(const struct clk_init_data){
1065 .name = "nss_cc_uniphy_port2_tx_clk",
1066 .parent_hws = (const struct clk_hw*[]){
1067 &nss_cc_port2_tx_div_clk_src.clkr.hw,
1068 },
1069 .num_parents = 1,
1070 .flags = CLK_SET_RATE_PARENT,
1071 .ops = &clk_branch2_ops,
1072 },
1073 },
1074 };
1075
1076 static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
1077 .halt_reg = 0x58c,
1078 .halt_check = BRANCH_HALT,
1079 .clkr = {
1080 .enable_reg = 0x58c,
1081 .enable_mask = BIT(0),
1082 .hw.init = &(const struct clk_init_data){
1083 .name = "nss_cc_uniphy_port3_rx_clk",
1084 .parent_hws = (const struct clk_hw*[]){
1085 &nss_cc_port3_rx_div_clk_src.clkr.hw,
1086 },
1087 .num_parents = 1,
1088 .flags = CLK_SET_RATE_PARENT,
1089 .ops = &clk_branch2_ops,
1090 },
1091 },
1092 };
1093
1094 static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
1095 .halt_reg = 0x590,
1096 .halt_check = BRANCH_HALT,
1097 .clkr = {
1098 .enable_reg = 0x590,
1099 .enable_mask = BIT(0),
1100 .hw.init = &(const struct clk_init_data){
1101 .name = "nss_cc_uniphy_port3_tx_clk",
1102 .parent_hws = (const struct clk_hw*[]){
1103 &nss_cc_port3_tx_div_clk_src.clkr.hw,
1104 },
1105 .num_parents = 1,
1106 .flags = CLK_SET_RATE_PARENT,
1107 .ops = &clk_branch2_ops,
1108 },
1109 },
1110 };
1111
1112 static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
1113 .halt_reg = 0x448,
1114 .halt_check = BRANCH_HALT,
1115 .clkr = {
1116 .enable_reg = 0x448,
1117 .enable_mask = BIT(0),
1118 .hw.init = &(const struct clk_init_data){
1119 .name = "nss_cc_xgmac0_ptp_ref_clk",
1120 .parent_hws = (const struct clk_hw*[]){
1121 &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
1122 },
1123 .num_parents = 1,
1124 .flags = CLK_SET_RATE_PARENT,
1125 .ops = &clk_branch2_ops,
1126 },
1127 },
1128 };
1129
1130 static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
1131 .halt_reg = 0x44c,
1132 .halt_check = BRANCH_HALT,
1133 .clkr = {
1134 .enable_reg = 0x44c,
1135 .enable_mask = BIT(0),
1136 .hw.init = &(const struct clk_init_data){
1137 .name = "nss_cc_xgmac1_ptp_ref_clk",
1138 .parent_hws = (const struct clk_hw*[]){
1139 &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
1140 },
1141 .num_parents = 1,
1142 .flags = CLK_SET_RATE_PARENT,
1143 .ops = &clk_branch2_ops,
1144 },
1145 },
1146 };
1147
1148 static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
1149 .halt_reg = 0x450,
1150 .halt_check = BRANCH_HALT,
1151 .clkr = {
1152 .enable_reg = 0x450,
1153 .enable_mask = BIT(0),
1154 .hw.init = &(const struct clk_init_data){
1155 .name = "nss_cc_xgmac2_ptp_ref_clk",
1156 .parent_hws = (const struct clk_hw*[]){
1157 &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
1158 },
1159 .num_parents = 1,
1160 .flags = CLK_SET_RATE_PARENT,
1161 .ops = &clk_branch2_ops,
1162 },
1163 },
1164 };
1165
1166 static struct clk_regmap *nss_cc_ipq5424_clocks[] = {
1167 [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
1168 [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
1169 [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
1170 [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
1171 [NSS_CC_DEBUG_CLK] = &nss_cc_debug_clk.clkr,
1172 [NSS_CC_EIP_BFDCD_CLK_SRC] = &nss_cc_eip_bfdcd_clk_src.clkr,
1173 [NSS_CC_EIP_CLK] = &nss_cc_eip_clk.clkr,
1174 [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
1175 [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
1176 [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
1177 [NSS_CC_NSSNOC_EIP_CLK] = &nss_cc_nssnoc_eip_clk.clkr,
1178 [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
1179 [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
1180 [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
1181 [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
1182 [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
1183 [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
1184 [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
1185 [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
1186 [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
1187 [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
1188 [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
1189 [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
1190 [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
1191 [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
1192 [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
1193 [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
1194 [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
1195 [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
1196 [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
1197 [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
1198 [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
1199 [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
1200 [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
1201 [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
1202 [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
1203 [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
1204 [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
1205 [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
1206 [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
1207 [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
1208 [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
1209 [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
1210 [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
1211 [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
1212 [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
1213 [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
1214 [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
1215 [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
1216 [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
1217 [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
1218 [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
1219 [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
1220 [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
1221 };
1222
1223 static const struct qcom_reset_map nss_cc_ipq5424_resets[] = {
1224 [NSS_CC_CE_APB_CLK_ARES] = { 0x5e8, 2 },
1225 [NSS_CC_CE_AXI_CLK_ARES] = { 0x5ec, 2 },
1226 [NSS_CC_DEBUG_CLK_ARES] = { 0x70c, 2 },
1227 [NSS_CC_EIP_CLK_ARES] = { 0x658, 2 },
1228 [NSS_CC_NSS_CSR_CLK_ARES] = { 0x6b0, 2 },
1229 [NSS_CC_NSSNOC_CE_APB_CLK_ARES] = { 0x5f4, 2 },
1230 [NSS_CC_NSSNOC_CE_AXI_CLK_ARES] = { 0x5f8, 2 },
1231 [NSS_CC_NSSNOC_EIP_CLK_ARES] = { 0x660, 2 },
1232 [NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] = { 0x6b4, 2 },
1233 [NSS_CC_NSSNOC_PPE_CLK_ARES] = { 0x440, 2 },
1234 [NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] = { 0x444, 2 },
1235 [NSS_CC_PORT1_MAC_CLK_ARES] = { 0x428, 2 },
1236 [NSS_CC_PORT1_RX_CLK_ARES] = { 0x4fc, 2 },
1237 [NSS_CC_PORT1_TX_CLK_ARES] = { 0x504, 2 },
1238 [NSS_CC_PORT2_MAC_CLK_ARES] = { 0x430, 2 },
1239 [NSS_CC_PORT2_RX_CLK_ARES] = { 0x50c, 2 },
1240 [NSS_CC_PORT2_TX_CLK_ARES] = { 0x514, 2 },
1241 [NSS_CC_PORT3_MAC_CLK_ARES] = { 0x438, 2 },
1242 [NSS_CC_PORT3_RX_CLK_ARES] = { 0x51c, 2 },
1243 [NSS_CC_PORT3_TX_CLK_ARES] = { 0x524, 2 },
1244 [NSS_CC_PPE_BCR] = { 0x3e8 },
1245 [NSS_CC_PPE_EDMA_CLK_ARES] = { 0x41c, 2 },
1246 [NSS_CC_PPE_EDMA_CFG_CLK_ARES] = { 0x424, 2 },
1247 [NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] = { 0x408, 2 },
1248 [NSS_CC_PPE_SWITCH_CLK_ARES] = { 0x410, 2 },
1249 [NSS_CC_PPE_SWITCH_CFG_CLK_ARES] = { 0x418, 2 },
1250 [NSS_CC_PPE_SWITCH_IPE_CLK_ARES] = { 0x400, 2 },
1251 [NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] = { 0x57c, 2 },
1252 [NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] = { 0x580, 2 },
1253 [NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] = { 0x584, 2 },
1254 [NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] = { 0x588, 2 },
1255 [NSS_CC_UNIPHY_PORT3_RX_CLK_ARES] = { 0x58c, 2 },
1256 [NSS_CC_UNIPHY_PORT3_TX_CLK_ARES] = { 0x590, 2 },
1257 [NSS_CC_XGMAC0_PTP_REF_CLK_ARES] = { 0x448, 2 },
1258 [NSS_CC_XGMAC1_PTP_REF_CLK_ARES] = { 0x44c, 2 },
1259 [NSS_CC_XGMAC2_PTP_REF_CLK_ARES] = { 0x450, 2 },
1260 };
1261
1262 static const struct regmap_config nss_cc_ipq5424_regmap_config = {
1263 .reg_bits = 32,
1264 .reg_stride = 4,
1265 .val_bits = 32,
1266 .max_register = 0x800,
1267 .fast_io = true,
1268 };
1269
1270 static const struct qcom_icc_hws_data icc_ipq5424_nss_hws[] = {
1271 { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK },
1272 { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK },
1273 { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK },
1274 { MASTER_NSSNOC_CE_AXI, SLAVE_NSSNOC_CE_AXI, NSS_CC_NSSNOC_CE_AXI_CLK},
1275 { MASTER_NSSNOC_CE_APB, SLAVE_NSSNOC_CE_APB, NSS_CC_NSSNOC_CE_APB_CLK},
1276 { MASTER_NSSNOC_EIP, SLAVE_NSSNOC_EIP, NSS_CC_NSSNOC_EIP_CLK},
1277 };
1278
1279 #define IPQ_NSSCC_ID (5424 * 2) /* some unique value */
1280
1281 static const struct qcom_cc_desc nss_cc_ipq5424_desc = {
1282 .config = &nss_cc_ipq5424_regmap_config,
1283 .clks = nss_cc_ipq5424_clocks,
1284 .num_clks = ARRAY_SIZE(nss_cc_ipq5424_clocks),
1285 .resets = nss_cc_ipq5424_resets,
1286 .num_resets = ARRAY_SIZE(nss_cc_ipq5424_resets),
1287 .icc_hws = icc_ipq5424_nss_hws,
1288 .num_icc_hws = ARRAY_SIZE(icc_ipq5424_nss_hws),
1289 .icc_first_node_id = IPQ_NSSCC_ID,
1290 };
1291
1292 static const struct dev_pm_ops nss_cc_ipq5424_pm_ops = {
1293 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
1294 };
1295
1296 static const struct of_device_id nss_cc_ipq5424_match_table[] = {
1297 { .compatible = "qcom,ipq5424-nsscc" },
1298 { }
1299 };
1300 MODULE_DEVICE_TABLE(of, nss_cc_ipq5424_match_table);
1301
nss_cc_ipq5424_probe(struct platform_device * pdev)1302 static int nss_cc_ipq5424_probe(struct platform_device *pdev)
1303 {
1304 int ret;
1305
1306 ret = devm_pm_runtime_enable(&pdev->dev);
1307 if (ret)
1308 return dev_err_probe(&pdev->dev, ret, "Fail to enable runtime PM\n");
1309
1310 ret = devm_pm_clk_create(&pdev->dev);
1311 if (ret)
1312 return dev_err_probe(&pdev->dev, ret, "Fail to create PM clock\n");
1313
1314 ret = pm_clk_add(&pdev->dev, "bus");
1315 if (ret)
1316 return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n");
1317
1318 ret = pm_runtime_resume_and_get(&pdev->dev);
1319 if (ret)
1320 return dev_err_probe(&pdev->dev, ret, "Fail to resume\n");
1321
1322 ret = qcom_cc_probe(pdev, &nss_cc_ipq5424_desc);
1323 pm_runtime_put(&pdev->dev);
1324
1325 return ret;
1326 }
1327
1328 static struct platform_driver nss_cc_ipq5424_driver = {
1329 .probe = nss_cc_ipq5424_probe,
1330 .driver = {
1331 .name = "qcom,ipq5424-nsscc",
1332 .of_match_table = nss_cc_ipq5424_match_table,
1333 .pm = &nss_cc_ipq5424_pm_ops,
1334 .sync_state = icc_sync_state,
1335 },
1336 };
1337 module_platform_driver(nss_cc_ipq5424_driver);
1338
1339 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. NSSCC IPQ5424 Driver");
1340 MODULE_LICENSE("GPL");
1341