1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/timer.h>
13
14 #include <drm/drm_print.h>
15
16 #include "vc4_drv.h"
17 #include "vc4_regs.h"
18
19 static const struct debugfs_reg32 v3d_regs[] = {
20 VC4_REG32(V3D_IDENT0),
21 VC4_REG32(V3D_IDENT1),
22 VC4_REG32(V3D_IDENT2),
23 VC4_REG32(V3D_SCRATCH),
24 VC4_REG32(V3D_L2CACTL),
25 VC4_REG32(V3D_SLCACTL),
26 VC4_REG32(V3D_INTCTL),
27 VC4_REG32(V3D_INTENA),
28 VC4_REG32(V3D_INTDIS),
29 VC4_REG32(V3D_CT0CS),
30 VC4_REG32(V3D_CT1CS),
31 VC4_REG32(V3D_CT0EA),
32 VC4_REG32(V3D_CT1EA),
33 VC4_REG32(V3D_CT0CA),
34 VC4_REG32(V3D_CT1CA),
35 VC4_REG32(V3D_CT00RA0),
36 VC4_REG32(V3D_CT01RA0),
37 VC4_REG32(V3D_CT0LC),
38 VC4_REG32(V3D_CT1LC),
39 VC4_REG32(V3D_CT0PC),
40 VC4_REG32(V3D_CT1PC),
41 VC4_REG32(V3D_PCS),
42 VC4_REG32(V3D_BFC),
43 VC4_REG32(V3D_RFC),
44 VC4_REG32(V3D_BPCA),
45 VC4_REG32(V3D_BPCS),
46 VC4_REG32(V3D_BPOA),
47 VC4_REG32(V3D_BPOS),
48 VC4_REG32(V3D_BXCF),
49 VC4_REG32(V3D_SQRSV0),
50 VC4_REG32(V3D_SQRSV1),
51 VC4_REG32(V3D_SQCNTL),
52 VC4_REG32(V3D_SRQPC),
53 VC4_REG32(V3D_SRQUA),
54 VC4_REG32(V3D_SRQUL),
55 VC4_REG32(V3D_SRQCS),
56 VC4_REG32(V3D_VPACNTL),
57 VC4_REG32(V3D_VPMBASE),
58 VC4_REG32(V3D_PCTRC),
59 VC4_REG32(V3D_PCTRE),
60 VC4_REG32(V3D_PCTR(0)),
61 VC4_REG32(V3D_PCTRS(0)),
62 VC4_REG32(V3D_PCTR(1)),
63 VC4_REG32(V3D_PCTRS(1)),
64 VC4_REG32(V3D_PCTR(2)),
65 VC4_REG32(V3D_PCTRS(2)),
66 VC4_REG32(V3D_PCTR(3)),
67 VC4_REG32(V3D_PCTRS(3)),
68 VC4_REG32(V3D_PCTR(4)),
69 VC4_REG32(V3D_PCTRS(4)),
70 VC4_REG32(V3D_PCTR(5)),
71 VC4_REG32(V3D_PCTRS(5)),
72 VC4_REG32(V3D_PCTR(6)),
73 VC4_REG32(V3D_PCTRS(6)),
74 VC4_REG32(V3D_PCTR(7)),
75 VC4_REG32(V3D_PCTRS(7)),
76 VC4_REG32(V3D_PCTR(8)),
77 VC4_REG32(V3D_PCTRS(8)),
78 VC4_REG32(V3D_PCTR(9)),
79 VC4_REG32(V3D_PCTRS(9)),
80 VC4_REG32(V3D_PCTR(10)),
81 VC4_REG32(V3D_PCTRS(10)),
82 VC4_REG32(V3D_PCTR(11)),
83 VC4_REG32(V3D_PCTRS(11)),
84 VC4_REG32(V3D_PCTR(12)),
85 VC4_REG32(V3D_PCTRS(12)),
86 VC4_REG32(V3D_PCTR(13)),
87 VC4_REG32(V3D_PCTRS(13)),
88 VC4_REG32(V3D_PCTR(14)),
89 VC4_REG32(V3D_PCTRS(14)),
90 VC4_REG32(V3D_PCTR(15)),
91 VC4_REG32(V3D_PCTRS(15)),
92 VC4_REG32(V3D_DBGE),
93 VC4_REG32(V3D_FDBGO),
94 VC4_REG32(V3D_FDBGB),
95 VC4_REG32(V3D_FDBGR),
96 VC4_REG32(V3D_FDBGS),
97 VC4_REG32(V3D_ERRSTAT),
98 };
99
vc4_v3d_debugfs_ident(struct seq_file * m,void * unused)100 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
101 {
102 struct drm_debugfs_entry *entry = m->private;
103 struct drm_device *dev = entry->dev;
104 struct vc4_dev *vc4 = to_vc4_dev(dev);
105 int ret = vc4_v3d_pm_get(vc4);
106
107 if (ret == 0) {
108 uint32_t ident1 = V3D_READ(V3D_IDENT1);
109 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
110 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
111 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
112
113 seq_printf(m, "Revision: %d\n",
114 VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
115 seq_printf(m, "Slices: %d\n", nslc);
116 seq_printf(m, "TMUs: %d\n", nslc * tups);
117 seq_printf(m, "QPUs: %d\n", nslc * qups);
118 seq_printf(m, "Semaphores: %d\n",
119 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
120 vc4_v3d_pm_put(vc4);
121 }
122
123 return 0;
124 }
125
126 /*
127 * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably
128 * get the pm_runtime refcount to 0 in vc4_reset().
129 */
130 int
vc4_v3d_pm_get(struct vc4_dev * vc4)131 vc4_v3d_pm_get(struct vc4_dev *vc4)
132 {
133 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
134 return -ENODEV;
135
136 mutex_lock(&vc4->power_lock);
137 if (vc4->power_refcount++ == 0) {
138 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
139
140 if (ret < 0) {
141 vc4->power_refcount--;
142 mutex_unlock(&vc4->power_lock);
143 return ret;
144 }
145 }
146 mutex_unlock(&vc4->power_lock);
147
148 return 0;
149 }
150
151 void
vc4_v3d_pm_put(struct vc4_dev * vc4)152 vc4_v3d_pm_put(struct vc4_dev *vc4)
153 {
154 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
155 return;
156
157 mutex_lock(&vc4->power_lock);
158 if (--vc4->power_refcount == 0) {
159 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
160 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
161 }
162 mutex_unlock(&vc4->power_lock);
163 }
164
vc4_v3d_init_hw(struct drm_device * dev)165 static void vc4_v3d_init_hw(struct drm_device *dev)
166 {
167 struct vc4_dev *vc4 = to_vc4_dev(dev);
168
169 /* Take all the memory that would have been reserved for user
170 * QPU programs, since we don't have an interface for running
171 * them, anyway.
172 */
173 V3D_WRITE(V3D_VPMBASE, 0);
174 }
175
bin_slot_try_alloc(struct vc4_dev * vc4)176 static int bin_slot_try_alloc(struct vc4_dev *vc4)
177 {
178 int slot;
179
180 guard(spinlock_irqsave)(&vc4->job_lock);
181
182 slot = ffs(~vc4->bin_alloc_used);
183 if (slot != 0) {
184 /* Switch from ffs() bit index to a 0-based index. */
185 slot--;
186 vc4->bin_alloc_used |= BIT(slot);
187 } else {
188 slot = -ENOMEM;
189 }
190
191 return slot;
192 }
193
vc4_v3d_get_bin_slot(struct vc4_dev * vc4,long timeout)194 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4, long timeout)
195 {
196 int slot;
197 long ret;
198
199 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
200 return -ENODEV;
201
202 /* If the pool is full, wait for a job to release its slots. */
203 ret = wait_event_interruptible_timeout(vc4->job_wait_queue,
204 (slot = bin_slot_try_alloc(vc4)) >= 0,
205 timeout);
206 if (ret < 0)
207 return ret;
208 if (ret == 0)
209 return -ENOMEM;
210
211 return slot;
212 }
213
214 /*
215 * bin_bo_alloc() - allocates the memory that will be used for
216 * tile binning.
217 *
218 * The binner has a limitation that the addresses in the tile state
219 * buffer that point into the tile alloc buffer or binner overflow
220 * memory only have 28 bits (256MB), and the top 4 on the bus for
221 * tile alloc references end up coming from the tile state buffer's
222 * address.
223 *
224 * To work around this, we allocate a single large buffer while V3D is
225 * in use, make sure that it has the top 4 bits constant across its
226 * entire extent, and then put the tile state, tile alloc, and binner
227 * overflow memory inside that buffer.
228 *
229 * This creates a limitation where we may not be able to execute a job
230 * if it doesn't fit within the buffer that we allocated up front.
231 * However, it turns out that 16MB is "enough for anybody", and
232 * real-world applications run into allocation failures from the
233 * overall DMA pool before they make scenes complicated enough to run
234 * out of bin space.
235 */
bin_bo_alloc(struct vc4_dev * vc4)236 static int bin_bo_alloc(struct vc4_dev *vc4)
237 {
238 struct vc4_v3d *v3d = vc4->v3d;
239 uint32_t size = 16 * 1024 * 1024;
240 int ret = 0;
241 struct list_head list;
242
243 if (!v3d)
244 return -ENODEV;
245
246 /* We may need to try allocating more than once to get a BO
247 * that doesn't cross 256MB. Track the ones we've allocated
248 * that failed so far, so that we can free them when we've got
249 * one that succeeded (if we freed them right away, our next
250 * allocation would probably be the same chunk of memory).
251 */
252 INIT_LIST_HEAD(&list);
253
254 while (true) {
255 struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true,
256 VC4_BO_TYPE_BIN);
257
258 if (IS_ERR(bo)) {
259 ret = PTR_ERR(bo);
260
261 dev_err(&v3d->pdev->dev,
262 "Failed to allocate memory for tile binning: "
263 "%d. You may need to enable DMA or give it "
264 "more memory.",
265 ret);
266 break;
267 }
268
269 /* Check if this BO won't trigger the addressing bug. */
270 if ((bo->base.dma_addr & 0xf0000000) ==
271 ((bo->base.dma_addr + bo->base.base.size - 1) & 0xf0000000)) {
272 vc4->bin_bo = bo;
273
274 /* Set up for allocating 512KB chunks of
275 * binner memory. The biggest allocation we
276 * need to do is for the initial tile alloc +
277 * tile state buffer. We can render to a
278 * maximum of ((2048*2048) / (32*32) = 4096
279 * tiles in a frame (until we do floating
280 * point rendering, at which point it would be
281 * 8192). Tile state is 48b/tile (rounded to
282 * a page), and tile alloc is 32b/tile
283 * (rounded to a page), plus a page of extra,
284 * for a total of 320kb for our worst-case.
285 * We choose 512kb so that it divides evenly
286 * into our 16MB, and the rest of the 512kb
287 * will be used as storage for the overflow
288 * from the initial 32b CL per bin.
289 */
290 vc4->bin_alloc_size = 512 * 1024;
291 vc4->bin_alloc_used = 0;
292 vc4->bin_alloc_overflow = 0;
293 WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 !=
294 bo->base.base.size / vc4->bin_alloc_size);
295
296 kref_init(&vc4->bin_bo_kref);
297
298 /* Enable the out-of-memory interrupt to set our
299 * newly-allocated binner BO, potentially from an
300 * already-pending-but-masked interrupt.
301 */
302 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
303
304 break;
305 }
306
307 /* Put it on the list to free later, and try again. */
308 list_add(&bo->unref_head, &list);
309 }
310
311 /* Free all the BOs we allocated but didn't choose. */
312 while (!list_empty(&list)) {
313 struct vc4_bo *bo = list_last_entry(&list,
314 struct vc4_bo, unref_head);
315
316 list_del(&bo->unref_head);
317 drm_gem_object_put(&bo->base.base);
318 }
319
320 return ret;
321 }
322
vc4_v3d_bin_bo_get(struct vc4_dev * vc4,bool * used)323 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used)
324 {
325 int ret = 0;
326
327 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
328 return -ENODEV;
329
330 mutex_lock(&vc4->bin_bo_lock);
331
332 if (used && *used)
333 goto complete;
334
335 if (vc4->bin_bo)
336 kref_get(&vc4->bin_bo_kref);
337 else
338 ret = bin_bo_alloc(vc4);
339
340 if (ret == 0 && used)
341 *used = true;
342
343 complete:
344 mutex_unlock(&vc4->bin_bo_lock);
345
346 return ret;
347 }
348
bin_bo_release(struct kref * ref)349 static void bin_bo_release(struct kref *ref)
350 {
351 struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref);
352
353 if (WARN_ON_ONCE(!vc4->bin_bo))
354 return;
355
356 drm_gem_object_put(&vc4->bin_bo->base.base);
357 vc4->bin_bo = NULL;
358 }
359
vc4_v3d_bin_bo_put(struct vc4_dev * vc4)360 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
361 {
362 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
363 return;
364
365 mutex_lock(&vc4->bin_bo_lock);
366 kref_put(&vc4->bin_bo_kref, bin_bo_release);
367 mutex_unlock(&vc4->bin_bo_lock);
368 }
369
370 #ifdef CONFIG_PM
vc4_v3d_runtime_suspend(struct device * dev)371 static int vc4_v3d_runtime_suspend(struct device *dev)
372 {
373 struct vc4_v3d *v3d = dev_get_drvdata(dev);
374 struct vc4_dev *vc4 = v3d->vc4;
375
376 vc4_irq_disable(&vc4->base);
377
378 clk_disable_unprepare(v3d->clk);
379
380 return 0;
381 }
382
vc4_v3d_runtime_resume(struct device * dev)383 static int vc4_v3d_runtime_resume(struct device *dev)
384 {
385 struct vc4_v3d *v3d = dev_get_drvdata(dev);
386 struct vc4_dev *vc4 = v3d->vc4;
387 int ret;
388
389 ret = clk_prepare_enable(v3d->clk);
390 if (ret != 0)
391 return ret;
392
393 vc4_v3d_init_hw(&vc4->base);
394
395 vc4_irq_enable(&vc4->base);
396 enable_irq(vc4->irq);
397
398 return 0;
399 }
400 #endif
401
vc4_v3d_debugfs_init(struct drm_minor * minor)402 int vc4_v3d_debugfs_init(struct drm_minor *minor)
403 {
404 struct drm_device *drm = minor->dev;
405 struct vc4_dev *vc4 = to_vc4_dev(drm);
406 struct vc4_v3d *v3d = vc4->v3d;
407
408 if (!vc4->v3d)
409 return -ENODEV;
410
411 drm_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL);
412
413 vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset);
414
415 return 0;
416 }
417
vc4_v3d_bind(struct device * dev,struct device * master,void * data)418 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
419 {
420 struct platform_device *pdev = to_platform_device(dev);
421 struct drm_device *drm = dev_get_drvdata(master);
422 struct vc4_dev *vc4 = to_vc4_dev(drm);
423 struct vc4_v3d *v3d = NULL;
424 int ret;
425
426 v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);
427 if (!v3d)
428 return -ENOMEM;
429
430 dev_set_drvdata(dev, v3d);
431
432 v3d->pdev = pdev;
433
434 v3d->regs = vc4_ioremap_regs(pdev, 0);
435 if (IS_ERR(v3d->regs))
436 return PTR_ERR(v3d->regs);
437 v3d->regset.base = v3d->regs;
438 v3d->regset.regs = v3d_regs;
439 v3d->regset.nregs = ARRAY_SIZE(v3d_regs);
440
441 vc4->v3d = v3d;
442 v3d->vc4 = vc4;
443
444 v3d->clk = devm_clk_get_optional(dev, NULL);
445 if (IS_ERR(v3d->clk))
446 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
447
448 ret = platform_get_irq(pdev, 0);
449 if (ret < 0)
450 return ret;
451 vc4->irq = ret;
452
453 ret = vc4_irq_install(drm, vc4->irq);
454 if (ret) {
455 drm_err(drm, "Failed to install IRQ handler\n");
456 return ret;
457 }
458
459 ret = devm_pm_runtime_enable(dev);
460 if (ret)
461 return ret;
462
463 ret = pm_runtime_resume_and_get(dev);
464 if (ret)
465 return ret;
466
467 if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
468 drm_err(drm, "V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
469 V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
470 ret = -EINVAL;
471 goto err_put_runtime_pm;
472 }
473
474 /* Reset the binner overflow address/size at setup, to be sure
475 * we don't reuse an old one.
476 */
477 V3D_WRITE(V3D_BPOA, 0);
478 V3D_WRITE(V3D_BPOS, 0);
479
480 pm_runtime_use_autosuspend(dev);
481 pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
482 pm_runtime_put_autosuspend(dev);
483
484 return 0;
485
486 err_put_runtime_pm:
487 pm_runtime_put(dev);
488
489 return ret;
490 }
491
vc4_v3d_unbind(struct device * dev,struct device * master,void * data)492 static void vc4_v3d_unbind(struct device *dev, struct device *master,
493 void *data)
494 {
495 struct drm_device *drm = data;
496 struct vc4_dev *vc4 = to_vc4_dev(drm);
497
498 /* A straggler vc4_reset() re-enables the interrupt. */
499 timer_shutdown_sync(&vc4->hangcheck.timer);
500 cancel_work_sync(&vc4->hangcheck.reset_work);
501
502 vc4_irq_uninstall(drm);
503
504 /* Flush rather than cancel, so queued completions release their jobs. */
505 flush_work(&vc4->job_done_work);
506
507 /* Disable the binner's overflow memory address, so the next
508 * driver probe (if any) doesn't try to reuse our old
509 * allocation.
510 */
511 V3D_WRITE(V3D_BPOA, 0);
512 V3D_WRITE(V3D_BPOS, 0);
513
514 vc4->v3d = NULL;
515 }
516
517 static const struct dev_pm_ops vc4_v3d_pm_ops = {
518 SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL)
519 };
520
521 static const struct component_ops vc4_v3d_ops = {
522 .bind = vc4_v3d_bind,
523 .unbind = vc4_v3d_unbind,
524 };
525
vc4_v3d_dev_probe(struct platform_device * pdev)526 static int vc4_v3d_dev_probe(struct platform_device *pdev)
527 {
528 return component_add(&pdev->dev, &vc4_v3d_ops);
529 }
530
vc4_v3d_dev_remove(struct platform_device * pdev)531 static void vc4_v3d_dev_remove(struct platform_device *pdev)
532 {
533 component_del(&pdev->dev, &vc4_v3d_ops);
534 }
535
536 const struct of_device_id vc4_v3d_dt_match[] = {
537 { .compatible = "brcm,bcm2835-v3d" },
538 { .compatible = "brcm,cygnus-v3d" },
539 { .compatible = "brcm,vc4-v3d" },
540 {}
541 };
542
543 struct platform_driver vc4_v3d_driver = {
544 .probe = vc4_v3d_dev_probe,
545 .remove = vc4_v3d_dev_remove,
546 .driver = {
547 .name = "vc4_v3d",
548 .of_match_table = vc4_v3d_dt_match,
549 .pm = &vc4_v3d_pm_ops,
550 },
551 };
552