1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // CS42L43 SPI Controller Driver
4 //
5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/acpi.h>
9 #include <linux/array_size.h>
10 #include <linux/bits.h>
11 #include <linux/bitfield.h>
12 #include <linux/cleanup.h>
13 #include <linux/device.h>
14 #include <linux/errno.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/gpio/machine.h>
17 #include <linux/gpio/property.h>
18 #include <linux/mfd/cs42l43.h>
19 #include <linux/mfd/cs42l43-regs.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/property.h>
26 #include <linux/regmap.h>
27 #include <linux/spi/spi.h>
28 #include <linux/units.h>
29
30 #define CS42L43_FIFO_SIZE 16
31 #define CS42L43_SPI_ROOT_HZ 49152000
32 #define CS42L43_SPI_MAX_LENGTH 65532
33
34 enum cs42l43_spi_cmd {
35 CS42L43_WRITE,
36 CS42L43_READ
37 };
38
39 struct cs42l43_spi {
40 struct device *dev;
41 struct regmap *regmap;
42 struct spi_controller *ctlr;
43 };
44
45 static const unsigned int cs42l43_clock_divs[] = {
46 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
47 };
48
49 static struct spi_board_info amp_info_template = {
50 .modalias = "cs35l56",
51 .max_speed_hz = 11 * HZ_PER_MHZ,
52 .mode = SPI_MODE_0,
53 };
54
55 static const struct software_node cs42l43_gpiochip_swnode = {
56 .name = "cs42l43-pinctrl",
57 };
58
59 static const struct software_node_ref_args cs42l43_cs_refs[] = {
60 SOFTWARE_NODE_REFERENCE(&cs42l43_gpiochip_swnode, 0, GPIO_ACTIVE_LOW),
61 SOFTWARE_NODE_REFERENCE(&swnode_gpio_undefined),
62 };
63
64 static const struct property_entry cs42l43_cs_props[] = {
65 PROPERTY_ENTRY_REF_ARRAY("cs-gpios", cs42l43_cs_refs),
66 {}
67 };
68
cs42l43_spi_tx(struct regmap * regmap,const u8 * buf,unsigned int len)69 static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)
70 {
71 const u8 *end = buf + len;
72 u32 val = 0;
73 int ret;
74
75 while (buf < end) {
76 const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
77
78 while (buf < block) {
79 const u8 *word = min(buf + sizeof(u32), block);
80 int pad = (buf + sizeof(u32)) - word;
81
82 while (buf < word) {
83 val >>= BITS_PER_BYTE;
84 val |= FIELD_PREP(GENMASK(31, 24), *buf);
85
86 buf++;
87 }
88
89 val >>= pad * BITS_PER_BYTE;
90
91 regmap_write(regmap, CS42L43_TX_DATA, val);
92 }
93
94 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);
95
96 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
97 val, (val & CS42L43_SPI_TX_REQUEST_MASK),
98 1000, 5000);
99 if (ret)
100 return ret;
101 }
102
103 return 0;
104 }
105
cs42l43_spi_rx(struct regmap * regmap,u8 * buf,unsigned int len)106 static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)
107 {
108 u8 *end = buf + len;
109 u32 val;
110 int ret;
111
112 while (buf < end) {
113 u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
114
115 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
116 val, (val & CS42L43_SPI_RX_REQUEST_MASK),
117 1000, 5000);
118 if (ret)
119 return ret;
120
121 while (buf < block) {
122 u8 *word = min(buf + sizeof(u32), block);
123
124 ret = regmap_read(regmap, CS42L43_RX_DATA, &val);
125 if (ret)
126 return ret;
127
128 while (buf < word) {
129 *buf = FIELD_GET(GENMASK(7, 0), val);
130
131 val >>= BITS_PER_BYTE;
132 buf++;
133 }
134 }
135
136 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);
137 }
138
139 return 0;
140 }
141
cs42l43_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr)142 static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
143 struct spi_transfer *tfr)
144 {
145 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
146 int i, ret = -EINVAL;
147
148 for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {
149 if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)
150 break;
151 }
152
153 if (i == ARRAY_SIZE(cs42l43_clock_divs))
154 return -EINVAL;
155
156 regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);
157
158 if (tfr->tx_buf) {
159 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);
160 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);
161 } else if (tfr->rx_buf) {
162 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);
163 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);
164 }
165
166 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);
167
168 if (tfr->tx_buf)
169 ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);
170 else if (tfr->rx_buf)
171 ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);
172
173 return ret;
174 }
175
cs42l43_set_cs(struct spi_device * spi,bool is_high)176 static void cs42l43_set_cs(struct spi_device *spi, bool is_high)
177 {
178 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
179
180 regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);
181 }
182
cs42l43_prepare_message(struct spi_controller * ctlr,struct spi_message * msg)183 static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
184 {
185 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
186 struct spi_device *spi = msg->spi;
187 unsigned int spi_config1 = 0;
188
189 /* select another internal CS, which doesn't exist, so CS 0 is not used */
190 if (spi_get_csgpiod(spi, 0))
191 spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;
192 if (spi->mode & SPI_CPOL)
193 spi_config1 |= CS42L43_SPI_CPOL_MASK;
194 if (spi->mode & SPI_CPHA)
195 spi_config1 |= CS42L43_SPI_CPHA_MASK;
196 if (spi->mode & SPI_3WIRE)
197 spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;
198
199 regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);
200
201 return 0;
202 }
203
cs42l43_prepare_transfer_hardware(struct spi_controller * ctlr)204 static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
205 {
206 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
207 int ret;
208
209 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);
210 if (ret)
211 dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);
212
213 return ret;
214 }
215
cs42l43_unprepare_transfer_hardware(struct spi_controller * ctlr)216 static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
217 {
218 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
219 int ret;
220
221 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);
222 if (ret)
223 dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);
224
225 return ret;
226 }
227
cs42l43_spi_max_length(struct spi_device * spi)228 static size_t cs42l43_spi_max_length(struct spi_device *spi)
229 {
230 return CS42L43_SPI_MAX_LENGTH;
231 }
232
cs42l43_get_speaker_id_gpios(struct cs42l43_spi * priv,int * result)233 static int cs42l43_get_speaker_id_gpios(struct cs42l43_spi *priv, int *result)
234 {
235 struct gpio_descs *descs;
236 u32 spkid;
237 int i, ret;
238
239 descs = gpiod_get_array_optional(priv->dev, "spk-id", GPIOD_IN);
240 if (IS_ERR_OR_NULL(descs))
241 return PTR_ERR(descs);
242
243 spkid = 0;
244 for (i = 0; i < descs->ndescs; i++) {
245 ret = gpiod_get_value_cansleep(descs->desc[i]);
246 if (ret < 0)
247 goto err;
248
249 spkid |= (ret << i);
250 }
251
252 dev_dbg(priv->dev, "spk-id-gpios = %d\n", spkid);
253 *result = spkid;
254 err:
255 gpiod_put_array(descs);
256
257 return ret;
258 }
259
cs42l43_find_xu_node(struct fwnode_handle * fwnode)260 static struct fwnode_handle *cs42l43_find_xu_node(struct fwnode_handle *fwnode)
261 {
262 static const u32 func_smart_amp = 0x1;
263 struct fwnode_handle *child_fwnode, *ext_fwnode;
264 u32 function;
265 int ret;
266
267 fwnode_for_each_child_node(fwnode, child_fwnode) {
268 acpi_handle handle = ACPI_HANDLE_FWNODE(child_fwnode);
269
270 ret = acpi_get_local_address(handle, &function);
271 if (ret || function != func_smart_amp)
272 continue;
273
274 ext_fwnode = fwnode_get_named_child_node(child_fwnode,
275 "mipi-sdca-function-expansion-subproperties");
276 if (!ext_fwnode)
277 continue;
278
279 fwnode_handle_put(child_fwnode);
280
281 return ext_fwnode;
282 }
283
284 return NULL;
285 }
286
cs42l43_create_bridge_amp(struct cs42l43_spi * priv,const char * const name,int cs,int spkid)287 static struct spi_board_info *cs42l43_create_bridge_amp(struct cs42l43_spi *priv,
288 const char * const name,
289 int cs, int spkid)
290 {
291 struct property_entry *props = NULL;
292 struct software_node *swnode;
293 struct spi_board_info *info;
294
295 if (spkid >= 0) {
296 props = devm_kmalloc(priv->dev, sizeof(*props), GFP_KERNEL);
297 if (!props)
298 return NULL;
299
300 *props = PROPERTY_ENTRY_U32("cirrus,speaker-id", spkid);
301 }
302
303 swnode = devm_kmalloc(priv->dev, sizeof(*swnode), GFP_KERNEL);
304 if (!swnode)
305 return NULL;
306
307 *swnode = SOFTWARE_NODE(name, props, NULL);
308
309 info = devm_kmemdup(priv->dev, &_info_template,
310 sizeof(amp_info_template), GFP_KERNEL);
311 if (!info)
312 return NULL;
313
314 info->chip_select = cs;
315 info->swnode = swnode;
316
317 return info;
318 }
319
cs42l43_release_of_node(void * data)320 static void cs42l43_release_of_node(void *data)
321 {
322 fwnode_handle_put(data);
323 }
324
cs42l43_release_sw_node(void * data)325 static void cs42l43_release_sw_node(void *data)
326 {
327 software_node_unregister(&cs42l43_gpiochip_swnode);
328 }
329
cs42l43_spi_probe(struct platform_device * pdev)330 static int cs42l43_spi_probe(struct platform_device *pdev)
331 {
332 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
333 struct cs42l43_spi *priv;
334 struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
335 struct fwnode_handle *xu_fwnode __free(fwnode_handle) = cs42l43_find_xu_node(fwnode);
336 int nsidecars = 0;
337 int spkid = -EINVAL;
338 int ret;
339
340 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
341 if (!priv)
342 return -ENOMEM;
343
344 priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr));
345 if (!priv->ctlr)
346 return -ENOMEM;
347
348 spi_controller_set_devdata(priv->ctlr, priv);
349
350 priv->dev = &pdev->dev;
351 priv->regmap = cs42l43->regmap;
352
353 priv->ctlr->prepare_message = cs42l43_prepare_message;
354 priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
355 priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
356 priv->ctlr->transfer_one = cs42l43_transfer_one;
357 priv->ctlr->set_cs = cs42l43_set_cs;
358 priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
359 priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
360 priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
361 priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
362 SPI_BPW_MASK(32);
363 priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
364 cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];
365 priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
366 priv->ctlr->use_gpio_descriptors = true;
367 priv->ctlr->auto_runtime_pm = true;
368
369 ret = devm_pm_runtime_enable(priv->dev);
370 if (ret)
371 return ret;
372
373 pm_runtime_idle(priv->dev);
374
375 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);
376 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);
377
378 // Disable Watchdog timer and enable stall
379 regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);
380 regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);
381
382 if (is_of_node(fwnode)) {
383 fwnode = fwnode_get_named_child_node(fwnode, "spi");
384 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_of_node, fwnode);
385 if (ret)
386 return ret;
387 }
388
389 fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars);
390
391 if (nsidecars) {
392 ret = fwnode_property_read_u32(xu_fwnode, "01fa-spk-id-val", &spkid);
393 if (!ret) {
394 dev_dbg(priv->dev, "01fa-spk-id-val = %d\n", spkid);
395 } else if (ret != -EINVAL) {
396 return dev_err_probe(priv->dev, ret, "Failed to get spk-id-val\n");
397 } else {
398 ret = cs42l43_get_speaker_id_gpios(priv, &spkid);
399 if (ret < 0)
400 return dev_err_probe(priv->dev, ret,
401 "Failed to get spk-id-gpios\n");
402 }
403
404 ret = software_node_register(&cs42l43_gpiochip_swnode);
405 if (ret)
406 return dev_err_probe(priv->dev, ret,
407 "Failed to register gpio swnode\n");
408
409 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_sw_node, NULL);
410 if (ret)
411 return ret;
412
413 ret = device_create_managed_software_node(&priv->ctlr->dev,
414 cs42l43_cs_props, NULL);
415 if (ret)
416 return dev_err_probe(priv->dev, ret, "Failed to add swnode\n");
417 } else {
418 device_set_node(&priv->ctlr->dev, fwnode);
419 }
420
421 ret = devm_spi_register_controller(priv->dev, priv->ctlr);
422 if (ret)
423 return dev_err_probe(priv->dev, ret,
424 "Failed to register SPI controller\n");
425
426 if (nsidecars) {
427 struct spi_board_info *ampl_info;
428 struct spi_board_info *ampr_info;
429
430 ampl_info = cs42l43_create_bridge_amp(priv, "cs35l56-left", 0, spkid);
431 if (!ampl_info)
432 return -ENOMEM;
433
434 ampr_info = cs42l43_create_bridge_amp(priv, "cs35l56-right", 1, spkid);
435 if (!ampr_info)
436 return -ENOMEM;
437
438 if (!spi_new_device(priv->ctlr, ampl_info))
439 return dev_err_probe(priv->dev, -ENODEV,
440 "Failed to create left amp slave\n");
441
442 if (!spi_new_device(priv->ctlr, ampr_info))
443 return dev_err_probe(priv->dev, -ENODEV,
444 "Failed to create right amp slave\n");
445 }
446
447 return 0;
448 }
449
450 static const struct platform_device_id cs42l43_spi_id_table[] = {
451 { "cs42l43-spi", },
452 {}
453 };
454 MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);
455
456 static struct platform_driver cs42l43_spi_driver = {
457 .driver = {
458 .name = "cs42l43-spi",
459 },
460 .probe = cs42l43_spi_probe,
461 .id_table = cs42l43_spi_id_table,
462 };
463 module_platform_driver(cs42l43_spi_driver);
464
465 MODULE_IMPORT_NS("GPIO_SWNODE");
466 MODULE_DESCRIPTION("CS42L43 SPI Driver");
467 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
468 MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");
469 MODULE_LICENSE("GPL");
470