1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include <linux/bitfield.h> 8 9 #include "rvu_struct.h" 10 #include "rvu_reg.h" 11 #include "rvu.h" 12 #include "npc.h" 13 #include "rvu_npc_fs.h" 14 #include "rvu_npc_hash.h" 15 #include "cn20k/reg.h" 16 #include "cn20k/npc.h" 17 18 static const char * const npc_flow_names[] = { 19 [NPC_DMAC] = "dmac", 20 [NPC_SMAC] = "smac", 21 [NPC_ETYPE] = "ether type", 22 [NPC_VLAN_ETYPE_CTAG] = "vlan ether type ctag", 23 [NPC_VLAN_ETYPE_STAG] = "vlan ether type stag", 24 [NPC_OUTER_VID] = "outer vlan id", 25 [NPC_INNER_VID] = "inner vlan id", 26 [NPC_TOS] = "tos", 27 [NPC_IPFRAG_IPV4] = "fragmented IPv4 header ", 28 [NPC_SIP_IPV4] = "ipv4 source ip", 29 [NPC_DIP_IPV4] = "ipv4 destination ip", 30 [NPC_IPFRAG_IPV6] = "fragmented IPv6 header ", 31 [NPC_SIP_IPV6] = "ipv6 source ip", 32 [NPC_DIP_IPV6] = "ipv6 destination ip", 33 [NPC_IPPROTO_TCP] = "ip proto tcp", 34 [NPC_IPPROTO_UDP] = "ip proto udp", 35 [NPC_IPPROTO_SCTP] = "ip proto sctp", 36 [NPC_IPPROTO_ICMP] = "ip proto icmp", 37 [NPC_IPPROTO_ICMP6] = "ip proto icmp6", 38 [NPC_IPPROTO_AH] = "ip proto AH", 39 [NPC_IPPROTO_ESP] = "ip proto ESP", 40 [NPC_SPORT_TCP] = "tcp source port", 41 [NPC_DPORT_TCP] = "tcp destination port", 42 [NPC_SPORT_UDP] = "udp source port", 43 [NPC_DPORT_UDP] = "udp destination port", 44 [NPC_SPORT_SCTP] = "sctp source port", 45 [NPC_DPORT_SCTP] = "sctp destination port", 46 [NPC_LXMB] = "Mcast/Bcast header ", 47 [NPC_IPSEC_SPI] = "SPI ", 48 [NPC_MPLS1_LBTCBOS] = "lse depth 1 label tc bos", 49 [NPC_MPLS1_TTL] = "lse depth 1 ttl", 50 [NPC_MPLS2_LBTCBOS] = "lse depth 2 label tc bos", 51 [NPC_MPLS2_TTL] = "lse depth 2 ttl", 52 [NPC_MPLS3_LBTCBOS] = "lse depth 3 label tc bos", 53 [NPC_MPLS3_TTL] = "lse depth 3 ttl", 54 [NPC_MPLS4_LBTCBOS] = "lse depth 4 label tc bos", 55 [NPC_MPLS4_TTL] = "lse depth 4", 56 [NPC_TYPE_ICMP] = "icmp type", 57 [NPC_CODE_ICMP] = "icmp code", 58 [NPC_TCP_FLAGS] = "tcp flags", 59 [NPC_UNKNOWN] = "unknown", 60 }; 61 62 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf) 63 { 64 struct npc_mcam *mcam = &rvu->hw->mcam; 65 u64 mcam_features; 66 u64 unsupported; 67 68 mcam_features = is_npc_intf_tx(intf) ? mcam->tx_features : mcam->rx_features; 69 unsupported = (mcam_features ^ features) & ~mcam_features; 70 71 /* Return false if at least one of the input flows is not extracted */ 72 return !unsupported; 73 } 74 75 const char *npc_get_field_name(u8 hdr) 76 { 77 if (hdr >= ARRAY_SIZE(npc_flow_names)) 78 return npc_flow_names[NPC_UNKNOWN]; 79 80 return npc_flow_names[hdr]; 81 } 82 83 /* Compute keyword masks and figure out the number of keywords a field 84 * spans in the key. 85 */ 86 static void npc_set_kw_masks(struct rvu *rvu, struct npc_mcam *mcam, u8 type, 87 u8 nr_bits, int start_kwi, int offset, u8 intf) 88 { 89 struct npc_key_field *field = &mcam->rx_key_fields[type]; 90 u8 bits_in_kw; 91 int max_kwi; 92 93 if (is_cn20k(rvu->pdev)) { 94 if (mcam->banks_per_entry == 1) 95 max_kwi = 3; /* NPC_MCAM_KEY_X2 */ 96 else 97 max_kwi = 7; /* NPC_MCAM_KEY_X4 */ 98 } else { 99 if (mcam->banks_per_entry == 1) 100 max_kwi = 1; /* NPC_MCAM_KEY_X1 */ 101 else if (mcam->banks_per_entry == 2) 102 max_kwi = 3; /* NPC_MCAM_KEY_X2 */ 103 else 104 max_kwi = 6; /* NPC_MCAM_KEY_X4 */ 105 } 106 107 if (is_npc_intf_tx(intf)) 108 field = &mcam->tx_key_fields[type]; 109 110 if (offset + nr_bits <= 64) { 111 /* one KW only */ 112 if (start_kwi > max_kwi) 113 return; 114 field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0) 115 << offset; 116 field->nr_kws = 1; 117 } else if (offset + nr_bits > 64 && 118 offset + nr_bits <= 128) { 119 /* two KWs */ 120 if (start_kwi + 1 > max_kwi) 121 return; 122 /* first KW mask */ 123 bits_in_kw = 64 - offset; 124 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 125 << offset; 126 /* second KW mask i.e. mask for rest of bits */ 127 bits_in_kw = nr_bits + offset - 64; 128 field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0); 129 field->nr_kws = 2; 130 } else { 131 /* three KWs */ 132 if (start_kwi + 2 > max_kwi) 133 return; 134 /* first KW mask */ 135 bits_in_kw = 64 - offset; 136 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 137 << offset; 138 /* second KW mask */ 139 field->kw_mask[start_kwi + 1] = ~0ULL; 140 /* third KW mask i.e. mask for rest of bits */ 141 bits_in_kw = nr_bits + offset - 128; 142 field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0); 143 field->nr_kws = 3; 144 } 145 } 146 147 /* Helper function to figure out whether field exists in the key */ 148 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf) 149 { 150 struct npc_mcam *mcam = &rvu->hw->mcam; 151 struct npc_key_field *input; 152 153 input = &mcam->rx_key_fields[type]; 154 if (is_npc_intf_tx(intf)) 155 input = &mcam->tx_key_fields[type]; 156 157 return input->nr_kws > 0; 158 } 159 160 static bool npc_is_same(struct npc_key_field *input, 161 struct npc_key_field *field) 162 { 163 return memcmp(&input->layer_mdata, &field->layer_mdata, 164 sizeof(struct npc_layer_mdata)) == 0; 165 } 166 167 static void npc_set_layer_mdata(struct rvu *rvu, 168 struct npc_mcam *mcam, enum key_fields type, 169 u64 cfg, u8 lid, u8 lt, u8 intf) 170 { 171 struct npc_key_field *input = &mcam->rx_key_fields[type]; 172 173 if (is_npc_intf_tx(intf)) 174 input = &mcam->tx_key_fields[type]; 175 176 input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 177 input->layer_mdata.key = FIELD_GET(NPC_KEY_OFFSET, cfg); 178 if (is_cn20k(rvu->pdev)) 179 input->layer_mdata.len = FIELD_GET(NPC_CN20K_BYTESM, cfg) + 1; 180 else 181 input->layer_mdata.len = FIELD_GET(NPC_BYTESM, cfg) + 1; 182 input->layer_mdata.ltype = lt; 183 input->layer_mdata.lid = lid; 184 } 185 186 static bool npc_check_overlap_fields(struct npc_key_field *input1, 187 struct npc_key_field *input2, 188 int max_kw) 189 { 190 int kwi; 191 192 /* Fields with same layer id and different ltypes are mutually 193 * exclusive hence they can be overlapped 194 */ 195 if (input1->layer_mdata.lid == input2->layer_mdata.lid && 196 input1->layer_mdata.ltype != input2->layer_mdata.ltype) 197 return false; 198 199 for (kwi = 0; kwi < max_kw; kwi++) { 200 if (input1->kw_mask[kwi] & input2->kw_mask[kwi]) 201 return true; 202 } 203 204 return false; 205 } 206 207 /* Helper function to check whether given field overlaps with any other fields 208 * in the key. Due to limitations on key size and the key extraction profile in 209 * use higher layers can overwrite lower layer's header fields. Hence overlap 210 * needs to be checked. 211 */ 212 static bool npc_check_overlap(struct rvu *rvu, int blkaddr, 213 enum key_fields type, u8 start_lid, u8 intf) 214 { 215 struct npc_mcam *mcam = &rvu->hw->mcam; 216 struct npc_key_field *dummy, *input; 217 int start_kwi, offset; 218 u8 nr_bits, lid, lt, ld; 219 int extr, kws; 220 u64 cfg; 221 222 dummy = &mcam->rx_key_fields[NPC_UNKNOWN]; 223 input = &mcam->rx_key_fields[type]; 224 225 if (is_npc_intf_tx(intf)) { 226 dummy = &mcam->tx_key_fields[NPC_UNKNOWN]; 227 input = &mcam->tx_key_fields[type]; 228 } 229 230 kws = NPC_KWS_IN_KEY_SZ_7; 231 232 if (is_cn20k(rvu->pdev)) 233 goto skip_cn10k_config; 234 235 for (lid = start_lid; lid < NPC_MAX_LID; lid++) { 236 for (lt = 0; lt < NPC_MAX_LT; lt++) { 237 for (ld = 0; ld < NPC_MAX_LD; ld++) { 238 cfg = rvu_read64(rvu, blkaddr, 239 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 240 (intf, lid, lt, ld)); 241 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 242 continue; 243 memset(dummy, 0, sizeof(struct npc_key_field)); 244 npc_set_layer_mdata(rvu, mcam, NPC_UNKNOWN, 245 cfg, lid, lt, intf); 246 /* exclude input */ 247 if (npc_is_same(input, dummy)) 248 continue; 249 start_kwi = dummy->layer_mdata.key / 8; 250 offset = (dummy->layer_mdata.key * 8) % 64; 251 nr_bits = dummy->layer_mdata.len * 8; 252 /* form KW masks */ 253 npc_set_kw_masks(rvu, mcam, NPC_UNKNOWN, 254 nr_bits, start_kwi, 255 offset, intf); 256 /* check any input field bits falls in any 257 * other field bits. 258 */ 259 if (npc_check_overlap_fields(dummy, input, kws)) 260 return true; 261 } 262 } 263 } 264 return false; 265 266 skip_cn10k_config: 267 for (extr = 0 ; extr < rvu->hw->npc_kex_extr; extr++) { 268 lid = CN20K_GET_EXTR_LID(intf, extr); 269 if (lid < start_lid) 270 continue; 271 for (lt = 0; lt < NPC_MAX_LT; lt++) { 272 cfg = CN20K_GET_EXTR_LT(intf, extr, lt); 273 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 274 continue; 275 276 memset(dummy, 0, sizeof(struct npc_key_field)); 277 npc_set_layer_mdata(rvu, mcam, NPC_UNKNOWN, cfg, 278 lid, lt, intf); 279 /* exclude input */ 280 if (npc_is_same(input, dummy)) 281 continue; 282 start_kwi = dummy->layer_mdata.key / 8; 283 offset = (dummy->layer_mdata.key * 8) % 64; 284 nr_bits = dummy->layer_mdata.len * 8; 285 /* form KW masks */ 286 npc_set_kw_masks(rvu, mcam, NPC_UNKNOWN, nr_bits, 287 start_kwi, offset, intf); 288 /* check any input field bits falls in any other 289 * field bits 290 */ 291 if (npc_check_overlap_fields(dummy, input, 292 NPC_KWS_IN_KEY_SZ_8)) 293 return true; 294 } 295 } 296 297 return false; 298 } 299 300 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, 301 u8 intf) 302 { 303 if (!npc_is_field_present(rvu, type, intf) || 304 npc_check_overlap(rvu, blkaddr, type, 0, intf)) 305 return false; 306 return true; 307 } 308 309 static void npc_scan_exact_result(struct rvu *rvu, 310 struct npc_mcam *mcam, u8 bit_number, 311 u8 key_nibble, u8 intf) 312 { 313 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 314 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 315 u8 nr_bits = 4; /* bits in a nibble */ 316 u8 type; 317 318 switch (bit_number) { 319 case 40 ... 43: 320 type = NPC_EXACT_RESULT; 321 break; 322 323 default: 324 return; 325 } 326 npc_set_kw_masks(rvu, mcam, type, nr_bits, kwi, offset, intf); 327 } 328 329 static void npc_cn20k_scan_parse_result(struct rvu *rvu, struct npc_mcam *mcam, 330 u8 bit_number, u8 key_nibble, u8 intf) 331 { 332 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 333 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 334 u8 nr_bits = 4; /* bits in a nibble */ 335 u8 type; 336 337 switch (bit_number) { 338 case 0 ... 2: 339 type = NPC_CHAN; 340 break; 341 case 3: 342 type = NPC_ERRLEV; 343 break; 344 case 4 ... 5: 345 type = NPC_ERRCODE; 346 break; 347 case 6: 348 type = NPC_LXMB; 349 break; 350 case 8: 351 type = NPC_LA; 352 break; 353 case 10: 354 type = NPC_LB; 355 break; 356 case 12: 357 type = NPC_LC; 358 break; 359 case 14: 360 type = NPC_LD; 361 break; 362 case 16: 363 type = NPC_LE; 364 break; 365 case 18: 366 type = NPC_LF; 367 break; 368 case 20: 369 type = NPC_LG; 370 break; 371 case 22: 372 type = NPC_LH; 373 break; 374 default: 375 return; 376 } 377 378 npc_set_kw_masks(rvu, mcam, type, nr_bits, kwi, offset, intf); 379 } 380 381 static void npc_scan_parse_result(struct rvu *rvu, 382 struct npc_mcam *mcam, u8 bit_number, 383 u8 key_nibble, u8 intf) 384 { 385 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 386 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 387 u8 nr_bits = 4; /* bits in a nibble */ 388 u8 type; 389 390 if (is_cn20k(rvu->pdev)) { 391 npc_cn20k_scan_parse_result(rvu, mcam, bit_number, 392 key_nibble, intf); 393 return; 394 } 395 396 switch (bit_number) { 397 case 0 ... 2: 398 type = NPC_CHAN; 399 break; 400 case 3: 401 type = NPC_ERRLEV; 402 break; 403 case 4 ... 5: 404 type = NPC_ERRCODE; 405 break; 406 case 6: 407 type = NPC_LXMB; 408 break; 409 /* check for LTYPE only as of now */ 410 case 9: 411 type = NPC_LA; 412 break; 413 case 12: 414 type = NPC_LB; 415 break; 416 case 15: 417 type = NPC_LC; 418 break; 419 case 18: 420 type = NPC_LD; 421 break; 422 case 21: 423 type = NPC_LE; 424 break; 425 case 24: 426 type = NPC_LF; 427 break; 428 case 27: 429 type = NPC_LG; 430 break; 431 case 30: 432 type = NPC_LH; 433 break; 434 default: 435 return; 436 } 437 438 npc_set_kw_masks(rvu, mcam, type, nr_bits, kwi, offset, intf); 439 } 440 441 static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf) 442 { 443 struct npc_mcam *mcam = &rvu->hw->mcam; 444 struct npc_key_field *key_fields; 445 /* Ether type can come from three layers 446 * (ethernet, single tagged, double tagged) 447 */ 448 struct npc_key_field *etype_ether; 449 struct npc_key_field *etype_tag1; 450 struct npc_key_field *etype_tag2; 451 /* Outer VLAN TCI can come from two layers 452 * (single tagged, double tagged) 453 */ 454 struct npc_key_field *vlan_tag1; 455 struct npc_key_field *vlan_tag2; 456 /* Inner VLAN TCI for double tagged frames */ 457 struct npc_key_field *vlan_tag3; 458 u64 *features; 459 int i, max_kw; 460 u8 start_lid; 461 462 if (is_cn20k(rvu->pdev)) 463 max_kw = NPC_KWS_IN_KEY_SZ_8; 464 else 465 max_kw = NPC_KWS_IN_KEY_SZ_7; 466 467 key_fields = mcam->rx_key_fields; 468 features = &mcam->rx_features; 469 470 if (is_npc_intf_tx(intf)) { 471 key_fields = mcam->tx_key_fields; 472 features = &mcam->tx_features; 473 } 474 475 /* Handle header fields which can come from multiple layers like 476 * etype, outer vlan tci. These fields should have same position in 477 * the key otherwise to install a mcam rule more than one entry is 478 * needed which complicates mcam space management. 479 */ 480 etype_ether = &key_fields[NPC_ETYPE_ETHER]; 481 etype_tag1 = &key_fields[NPC_ETYPE_TAG1]; 482 etype_tag2 = &key_fields[NPC_ETYPE_TAG2]; 483 vlan_tag1 = &key_fields[NPC_VLAN_TAG1]; 484 vlan_tag2 = &key_fields[NPC_VLAN_TAG2]; 485 vlan_tag3 = &key_fields[NPC_VLAN_TAG3]; 486 487 /* if key profile programmed does not extract Ethertype at all */ 488 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) { 489 dev_err(rvu->dev, "mkex: Ethertype is not extracted.\n"); 490 goto vlan_tci; 491 } 492 493 /* if key profile programmed extracts Ethertype from one layer */ 494 if (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) 495 key_fields[NPC_ETYPE] = *etype_ether; 496 if (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws) 497 key_fields[NPC_ETYPE] = *etype_tag1; 498 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws) 499 key_fields[NPC_ETYPE] = *etype_tag2; 500 501 /* if key profile programmed extracts Ethertype from multiple layers */ 502 if (etype_ether->nr_kws && etype_tag1->nr_kws) { 503 for (i = 0; i < max_kw; i++) { 504 if (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i]) { 505 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and tagged pkts.\n"); 506 goto vlan_tci; 507 } 508 } 509 key_fields[NPC_ETYPE] = *etype_tag1; 510 } 511 if (etype_ether->nr_kws && etype_tag2->nr_kws) { 512 for (i = 0; i < max_kw; i++) { 513 if (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i]) { 514 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and double tagged pkts.\n"); 515 goto vlan_tci; 516 } 517 } 518 key_fields[NPC_ETYPE] = *etype_tag2; 519 } 520 if (etype_tag1->nr_kws && etype_tag2->nr_kws) { 521 for (i = 0; i < max_kw; i++) { 522 if (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i]) { 523 dev_err(rvu->dev, "mkex: Etype pos is different for tagged and double tagged pkts.\n"); 524 goto vlan_tci; 525 } 526 } 527 key_fields[NPC_ETYPE] = *etype_tag2; 528 } 529 530 /* check none of higher layers overwrite Ethertype */ 531 start_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1; 532 if (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf)) { 533 dev_err(rvu->dev, "mkex: Ethertype is overwritten by higher layers.\n"); 534 goto vlan_tci; 535 } 536 *features |= BIT_ULL(NPC_ETYPE); 537 vlan_tci: 538 /* if key profile does not extract outer vlan tci at all */ 539 if (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws) { 540 dev_err(rvu->dev, "mkex: Outer vlan tci is not extracted.\n"); 541 goto done; 542 } 543 544 /* if key profile extracts outer vlan tci from one layer */ 545 if (vlan_tag1->nr_kws && !vlan_tag2->nr_kws) 546 key_fields[NPC_OUTER_VID] = *vlan_tag1; 547 if (!vlan_tag1->nr_kws && vlan_tag2->nr_kws) 548 key_fields[NPC_OUTER_VID] = *vlan_tag2; 549 550 /* if key profile extracts outer vlan tci from multiple layers */ 551 if (vlan_tag1->nr_kws && vlan_tag2->nr_kws) { 552 for (i = 0; i < max_kw; i++) { 553 if (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i]) { 554 dev_err(rvu->dev, "mkex: Out vlan tci pos is different for tagged and double tagged pkts.\n"); 555 goto done; 556 } 557 } 558 key_fields[NPC_OUTER_VID] = *vlan_tag2; 559 } 560 /* check none of higher layers overwrite outer vlan tci */ 561 start_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1; 562 if (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf)) { 563 dev_err(rvu->dev, "mkex: Outer vlan tci is overwritten by higher layers.\n"); 564 goto done; 565 } 566 *features |= BIT_ULL(NPC_OUTER_VID); 567 568 /* If key profile extracts inner vlan tci */ 569 if (vlan_tag3->nr_kws) { 570 key_fields[NPC_INNER_VID] = *vlan_tag3; 571 *features |= BIT_ULL(NPC_INNER_VID); 572 } 573 done: 574 return; 575 } 576 577 static void npc_scan_ldata(struct rvu *rvu, int blkaddr, u8 lid, 578 u8 lt, u64 cfg, u8 intf) 579 { 580 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash; 581 struct npc_mcam *mcam = &rvu->hw->mcam; 582 u8 hdr, key, nr_bytes, bit_offset; 583 u8 la_ltype, la_start; 584 /* starting KW index and starting bit position */ 585 int start_kwi, offset; 586 587 if (is_cn20k(rvu->pdev)) 588 nr_bytes = FIELD_GET(NPC_CN20K_BYTESM, cfg) + 1; 589 else 590 nr_bytes = FIELD_GET(NPC_BYTESM, cfg) + 1; 591 592 hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 593 key = FIELD_GET(NPC_KEY_OFFSET, cfg); 594 595 /* For Tx, Layer A has NIX_INST_HDR_S(64 bytes) preceding 596 * ethernet header. 597 */ 598 if (is_npc_intf_tx(intf)) { 599 la_ltype = NPC_LT_LA_IH_NIX_ETHER; 600 la_start = 8; 601 } else { 602 la_ltype = NPC_LT_LA_ETHER; 603 la_start = 0; 604 } 605 606 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \ 607 do { \ 608 start_kwi = key / 8; \ 609 offset = (key * 8) % 64; \ 610 if (lid == (hlid) && lt == (hlt)) { \ 611 if ((hstart) >= hdr && \ 612 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \ 613 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \ 614 npc_set_layer_mdata(rvu, mcam, (name), cfg, lid, lt, \ 615 intf); \ 616 offset += bit_offset; \ 617 start_kwi += offset / 64; \ 618 offset %= 64; \ 619 npc_set_kw_masks(rvu, mcam, (name), (hlen) * 8, \ 620 start_kwi, offset, intf); \ 621 } \ 622 } \ 623 } while (0) 624 625 /* List LID, LTYPE, start offset from layer and length(in bytes) of 626 * packet header fields below. 627 * Example: Source IP is 4 bytes and starts at 12th byte of IP header 628 */ 629 NPC_SCAN_HDR(NPC_TOS, NPC_LID_LC, NPC_LT_LC_IP, 1, 1); 630 NPC_SCAN_HDR(NPC_IPFRAG_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 6, 1); 631 NPC_SCAN_HDR(NPC_SIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 12, 4); 632 NPC_SCAN_HDR(NPC_DIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 16, 4); 633 NPC_SCAN_HDR(NPC_IPFRAG_IPV6, NPC_LID_LC, NPC_LT_LC_IP6_EXT, 6, 1); 634 if (rvu->hw->cap.npc_hash_extract) { 635 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][0]) 636 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 4); 637 else 638 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 639 640 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][1]) 641 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 4); 642 else 643 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 644 } else { 645 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 646 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 647 } 648 649 NPC_SCAN_HDR(NPC_SPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 0, 2); 650 NPC_SCAN_HDR(NPC_DPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 2, 2); 651 NPC_SCAN_HDR(NPC_SPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 0, 2); 652 NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2); 653 NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2); 654 NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2); 655 NPC_SCAN_HDR(NPC_TYPE_ICMP, NPC_LID_LD, NPC_LT_LD_ICMP, 0, 1); 656 NPC_SCAN_HDR(NPC_CODE_ICMP, NPC_LID_LD, NPC_LT_LD_ICMP, 1, 1); 657 NPC_SCAN_HDR(NPC_TCP_FLAGS, NPC_LID_LD, NPC_LT_LD_TCP, 12, 2); 658 NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2); 659 NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2); 660 NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2); 661 NPC_SCAN_HDR(NPC_VLAN_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 2, 2); 662 NPC_SCAN_HDR(NPC_VLAN_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 2, 2); 663 NPC_SCAN_HDR(NPC_VLAN_TAG3, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 6, 2); 664 NPC_SCAN_HDR(NPC_DMAC, NPC_LID_LA, la_ltype, la_start, 6); 665 666 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LD, NPC_LT_LD_AH, 4, 4); 667 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LE, NPC_LT_LE_ESP, 0, 4); 668 NPC_SCAN_HDR(NPC_MPLS1_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 0, 3); 669 NPC_SCAN_HDR(NPC_MPLS1_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 3, 1); 670 NPC_SCAN_HDR(NPC_MPLS2_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 4, 3); 671 NPC_SCAN_HDR(NPC_MPLS2_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 7, 1); 672 NPC_SCAN_HDR(NPC_MPLS3_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 8, 3); 673 NPC_SCAN_HDR(NPC_MPLS3_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 11, 1); 674 NPC_SCAN_HDR(NPC_MPLS4_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 12, 3); 675 NPC_SCAN_HDR(NPC_MPLS4_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 15, 1); 676 677 /* SMAC follows the DMAC(which is 6 bytes) */ 678 NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6); 679 /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */ 680 NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2); 681 } 682 683 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf) 684 { 685 struct npc_mcam *mcam = &rvu->hw->mcam; 686 u64 *features = &mcam->rx_features; 687 u64 proto_flags; 688 int hdr; 689 690 if (is_npc_intf_tx(intf)) 691 features = &mcam->tx_features; 692 693 for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) { 694 if (npc_check_field(rvu, blkaddr, hdr, intf)) 695 *features |= BIT_ULL(hdr); 696 } 697 698 proto_flags = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) | 699 BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) | 700 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) | 701 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) | 702 BIT_ULL(NPC_TYPE_ICMP) | BIT_ULL(NPC_CODE_ICMP) | 703 BIT_ULL(NPC_TCP_FLAGS); 704 705 /* for tcp/udp/sctp corresponding layer type should be in the key */ 706 if (*features & proto_flags) { 707 if (!npc_check_field(rvu, blkaddr, NPC_LD, intf)) 708 *features &= ~proto_flags; 709 else 710 *features |= BIT_ULL(NPC_IPPROTO_TCP) | 711 BIT_ULL(NPC_IPPROTO_UDP) | 712 BIT_ULL(NPC_IPPROTO_SCTP) | 713 BIT_ULL(NPC_IPPROTO_ICMP); 714 } 715 716 /* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */ 717 if (npc_check_field(rvu, blkaddr, NPC_LD, intf)) { 718 *features |= BIT_ULL(NPC_IPPROTO_AH); 719 *features |= BIT_ULL(NPC_IPPROTO_ICMP); 720 *features |= BIT_ULL(NPC_IPPROTO_ICMP6); 721 } 722 723 /* for ESP, check if corresponding layer type is present in the key */ 724 if (npc_check_field(rvu, blkaddr, NPC_LE, intf)) 725 *features |= BIT_ULL(NPC_IPPROTO_ESP); 726 727 /* for vlan corresponding layer type should be in the key */ 728 if (*features & BIT_ULL(NPC_OUTER_VID)) 729 if (!npc_check_field(rvu, blkaddr, NPC_LB, intf)) 730 *features &= ~BIT_ULL(NPC_OUTER_VID); 731 732 /* Allow extracting SPI field from AH and ESP headers at same offset */ 733 if (npc_is_field_present(rvu, NPC_IPSEC_SPI, intf) && 734 (*features & (BIT_ULL(NPC_IPPROTO_ESP) | BIT_ULL(NPC_IPPROTO_AH)))) 735 *features |= BIT_ULL(NPC_IPSEC_SPI); 736 737 /* for vlan ethertypes corresponding layer type should be in the key */ 738 if (npc_check_field(rvu, blkaddr, NPC_LB, intf)) 739 *features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) | 740 BIT_ULL(NPC_VLAN_ETYPE_STAG); 741 742 /* for L2M/L2B/L3M/L3B, check if the type is present in the key */ 743 if (npc_check_field(rvu, blkaddr, NPC_LXMB, intf)) 744 *features |= BIT_ULL(NPC_LXMB); 745 746 for (hdr = NPC_MPLS1_LBTCBOS; hdr <= NPC_MPLS4_TTL; hdr++) { 747 if (npc_check_field(rvu, blkaddr, hdr, intf)) 748 *features |= BIT_ULL(hdr); 749 } 750 } 751 752 /* Scan key extraction profile and record how fields of our interest 753 * fill the key structure. Also verify Channel and DMAC exists in 754 * key and not overwritten by other header fields. 755 */ 756 static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf) 757 { 758 struct npc_mcam *mcam = &rvu->hw->mcam; 759 u8 lid, lt, ld, bitnr; 760 u64 cfg, masked_cfg; 761 u8 key_nibble = 0; 762 int extr; 763 764 /* Scan and note how parse result is going to be in key. 765 * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from 766 * parse result in the key. The enabled nibbles from parse result 767 * will be concatenated in key. 768 */ 769 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf)); 770 if (is_cn20k(rvu->pdev)) { 771 masked_cfg = cfg & NPC_CN20K_PARSE_NIBBLE; 772 for_each_set_bit(bitnr, (unsigned long *)&masked_cfg, 773 NPC_CN20K_TOTAL_NIBBLE) { 774 npc_scan_parse_result(rvu, mcam, bitnr, 775 key_nibble, intf); 776 key_nibble++; 777 } 778 } else { 779 masked_cfg = cfg & NPC_PARSE_NIBBLE; 780 for_each_set_bit(bitnr, (unsigned long *)&masked_cfg, 781 NPC_TOTAL_NIBBLE) { 782 npc_scan_parse_result(rvu, mcam, bitnr, 783 key_nibble, intf); 784 key_nibble++; 785 } 786 } 787 788 /* Ignore exact match bits for mcam entries except the first rule 789 * which is drop on hit. This first rule is configured explitcitly by 790 * exact match code. 791 */ 792 masked_cfg = cfg & NPC_EXACT_NIBBLE; 793 bitnr = NPC_EXACT_NIBBLE_START; 794 for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) { 795 npc_scan_exact_result(rvu, mcam, bitnr, key_nibble, intf); 796 key_nibble++; 797 } 798 799 if (is_cn20k(rvu->pdev)) 800 goto skip_cn10k_config; 801 802 /* Scan and note how layer data is going to be in key */ 803 for (lid = 0; lid < NPC_MAX_LID; lid++) { 804 for (lt = 0; lt < NPC_MAX_LT; lt++) { 805 for (ld = 0; ld < NPC_MAX_LD; ld++) { 806 cfg = rvu_read64(rvu, blkaddr, 807 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 808 (intf, lid, lt, ld)); 809 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 810 continue; 811 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg, 812 intf); 813 } 814 } 815 } 816 817 return 0; 818 819 skip_cn10k_config: 820 for (extr = 0 ; extr < rvu->hw->npc_kex_extr; extr++) { 821 lid = CN20K_GET_EXTR_LID(intf, extr); 822 for (lt = 0; lt < NPC_MAX_LT; lt++) { 823 cfg = CN20K_GET_EXTR_LT(intf, extr, lt); 824 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 825 continue; 826 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg, 827 intf); 828 } 829 } 830 return 0; 831 } 832 833 static int npc_scan_verify_kex(struct rvu *rvu, int blkaddr) 834 { 835 int err; 836 837 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_RX); 838 if (err) 839 return err; 840 841 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_TX); 842 if (err) 843 return err; 844 845 /* Channel is mandatory */ 846 if (!npc_is_field_present(rvu, NPC_CHAN, NIX_INTF_RX)) { 847 dev_err(rvu->dev, "Channel not present in Key\n"); 848 return -EINVAL; 849 } 850 /* check that none of the fields overwrite channel */ 851 if (npc_check_overlap(rvu, blkaddr, NPC_CHAN, 0, NIX_INTF_RX)) { 852 dev_err(rvu->dev, "Channel cannot be overwritten\n"); 853 return -EINVAL; 854 } 855 856 npc_set_features(rvu, blkaddr, NIX_INTF_TX); 857 npc_set_features(rvu, blkaddr, NIX_INTF_RX); 858 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_TX); 859 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_RX); 860 861 return 0; 862 } 863 864 int npc_flow_steering_init(struct rvu *rvu, int blkaddr) 865 { 866 struct npc_mcam *mcam = &rvu->hw->mcam; 867 868 INIT_LIST_HEAD(&mcam->mcam_rules); 869 870 return npc_scan_verify_kex(rvu, blkaddr); 871 } 872 873 static int npc_check_unsupported_flows(struct rvu *rvu, u64 features, u8 intf) 874 { 875 struct npc_mcam *mcam = &rvu->hw->mcam; 876 u64 *mcam_features = &mcam->rx_features; 877 u64 unsupported; 878 u8 bit; 879 880 if (is_npc_intf_tx(intf)) 881 mcam_features = &mcam->tx_features; 882 883 unsupported = (*mcam_features ^ features) & ~(*mcam_features); 884 if (unsupported) { 885 dev_warn(rvu->dev, "Unsupported flow(s):\n"); 886 for_each_set_bit(bit, (unsigned long *)&unsupported, 64) 887 dev_warn(rvu->dev, "%s ", npc_get_field_name(bit)); 888 return -EOPNOTSUPP; 889 } 890 891 return 0; 892 } 893 894 /* npc_update_entry - Based on the masks generated during 895 * the key scanning, updates the given entry with value and 896 * masks for the field of interest. Maximum 16 bytes of a packet 897 * header can be extracted by HW hence lo and hi are sufficient. 898 * When field bytes are less than or equal to 8 then hi should be 899 * 0 for value and mask. 900 * 901 * If exact match of value is required then mask should be all 1's. 902 * If any bits in mask are 0 then corresponding bits in value are 903 * dont care. 904 */ 905 void npc_update_entry(struct rvu *rvu, enum key_fields type, 906 struct mcam_entry_mdata *mdata, u64 val_lo, 907 u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf) 908 { 909 u64 kw_mask[NPC_KWS_IN_KEY_SZ_MAX] = { 0 }; 910 u64 kw[NPC_KWS_IN_KEY_SZ_MAX] = { 0 }; 911 struct npc_mcam *mcam = &rvu->hw->mcam; 912 struct npc_key_field *field; 913 u64 kw1, kw2, kw3; 914 u64 *val, *mask; 915 int i, max_kw; 916 u8 shift; 917 918 field = &mcam->rx_key_fields[type]; 919 if (is_npc_intf_tx(intf)) 920 field = &mcam->tx_key_fields[type]; 921 922 if (!field->nr_kws) 923 return; 924 925 if (is_cn20k(rvu->pdev)) 926 max_kw = NPC_KWS_IN_KEY_SZ_8; 927 else 928 max_kw = NPC_KWS_IN_KEY_SZ_7; 929 930 for (i = 0; i < max_kw; i++) { 931 if (!field->kw_mask[i]) 932 continue; 933 /* place key value in kw[x] */ 934 shift = __ffs64(field->kw_mask[i]); 935 /* update entry value */ 936 kw1 = (val_lo << shift) & field->kw_mask[i]; 937 kw[i] = kw1; 938 /* update entry mask */ 939 kw1 = (mask_lo << shift) & field->kw_mask[i]; 940 kw_mask[i] = kw1; 941 942 if (field->nr_kws == 1) 943 break; 944 /* place remaining bits of key value in kw[x + 1] */ 945 if (field->nr_kws == 2) { 946 /* update entry value */ 947 kw2 = shift ? val_lo >> (64 - shift) : 0; 948 kw2 |= (val_hi << shift); 949 kw2 &= field->kw_mask[i + 1]; 950 kw[i + 1] = kw2; 951 /* update entry mask */ 952 kw2 = shift ? mask_lo >> (64 - shift) : 0; 953 kw2 |= (mask_hi << shift); 954 kw2 &= field->kw_mask[i + 1]; 955 kw_mask[i + 1] = kw2; 956 break; 957 } 958 /* place remaining bits of key value in kw[x + 1], kw[x + 2] */ 959 if (field->nr_kws == 3) { 960 /* update entry value */ 961 kw2 = shift ? val_lo >> (64 - shift) : 0; 962 kw2 |= (val_hi << shift); 963 kw2 &= field->kw_mask[i + 1]; 964 kw3 = shift ? val_hi >> (64 - shift) : 0; 965 kw3 &= field->kw_mask[i + 2]; 966 kw[i + 1] = kw2; 967 kw[i + 2] = kw3; 968 /* update entry mask */ 969 kw2 = shift ? mask_lo >> (64 - shift) : 0; 970 kw2 |= (mask_hi << shift); 971 kw2 &= field->kw_mask[i + 1]; 972 kw3 = shift ? mask_hi >> (64 - shift) : 0; 973 kw3 &= field->kw_mask[i + 2]; 974 kw_mask[i + 1] = kw2; 975 kw_mask[i + 2] = kw3; 976 break; 977 } 978 } 979 /* dummy is ready with values and masks for given key 980 * field now clear and update input entry with those 981 */ 982 983 val = mdata->kw; 984 mask = mdata->kw_mask; 985 986 for (i = 0; i < max_kw; i++, val++, mask++) { 987 if (!field->kw_mask[i]) 988 continue; 989 990 *val &= ~field->kw_mask[i]; 991 *mask &= ~field->kw_mask[i]; 992 993 *val |= kw[i]; 994 *mask |= kw_mask[i]; 995 } 996 } 997 998 static void npc_update_ipv6_flow(struct rvu *rvu, 999 struct mcam_entry_mdata *mdata, 1000 u64 features, struct flow_msg *pkt, 1001 struct flow_msg *mask, 1002 struct rvu_npc_mcam_rule *output, u8 intf) 1003 { 1004 u32 src_ip[IPV6_WORDS], src_ip_mask[IPV6_WORDS]; 1005 u32 dst_ip[IPV6_WORDS], dst_ip_mask[IPV6_WORDS]; 1006 struct flow_msg *opkt = &output->packet; 1007 struct flow_msg *omask = &output->mask; 1008 u64 mask_lo, mask_hi; 1009 u64 val_lo, val_hi; 1010 1011 /* For an ipv6 address fe80::2c68:63ff:fe5e:2d0a the packet 1012 * values to be programmed in MCAM should as below: 1013 * val_high: 0xfe80000000000000 1014 * val_low: 0x2c6863fffe5e2d0a 1015 */ 1016 if (features & BIT_ULL(NPC_SIP_IPV6)) { 1017 be32_to_cpu_array(src_ip_mask, mask->ip6src, IPV6_WORDS); 1018 be32_to_cpu_array(src_ip, pkt->ip6src, IPV6_WORDS); 1019 1020 mask_hi = (u64)src_ip_mask[0] << 32 | src_ip_mask[1]; 1021 mask_lo = (u64)src_ip_mask[2] << 32 | src_ip_mask[3]; 1022 val_hi = (u64)src_ip[0] << 32 | src_ip[1]; 1023 val_lo = (u64)src_ip[2] << 32 | src_ip[3]; 1024 1025 npc_update_entry(rvu, NPC_SIP_IPV6, mdata, val_lo, val_hi, 1026 mask_lo, mask_hi, intf); 1027 memcpy(opkt->ip6src, pkt->ip6src, sizeof(opkt->ip6src)); 1028 memcpy(omask->ip6src, mask->ip6src, sizeof(omask->ip6src)); 1029 } 1030 if (features & BIT_ULL(NPC_DIP_IPV6)) { 1031 be32_to_cpu_array(dst_ip_mask, mask->ip6dst, IPV6_WORDS); 1032 be32_to_cpu_array(dst_ip, pkt->ip6dst, IPV6_WORDS); 1033 1034 mask_hi = (u64)dst_ip_mask[0] << 32 | dst_ip_mask[1]; 1035 mask_lo = (u64)dst_ip_mask[2] << 32 | dst_ip_mask[3]; 1036 val_hi = (u64)dst_ip[0] << 32 | dst_ip[1]; 1037 val_lo = (u64)dst_ip[2] << 32 | dst_ip[3]; 1038 1039 npc_update_entry(rvu, NPC_DIP_IPV6, mdata, val_lo, val_hi, 1040 mask_lo, mask_hi, intf); 1041 memcpy(opkt->ip6dst, pkt->ip6dst, sizeof(opkt->ip6dst)); 1042 memcpy(omask->ip6dst, mask->ip6dst, sizeof(omask->ip6dst)); 1043 } 1044 } 1045 1046 static void npc_update_vlan_features(struct rvu *rvu, 1047 struct mcam_entry_mdata *mdata, 1048 u64 features, u8 intf) 1049 { 1050 bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG)); 1051 bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG)); 1052 bool vid = !!(features & BIT_ULL(NPC_OUTER_VID)); 1053 1054 /* If only VLAN id is given then always match outer VLAN id */ 1055 if (vid && !ctag && !stag) { 1056 npc_update_entry(rvu, NPC_LB, mdata, 1057 NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG, 0, 1058 NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG, 0, intf); 1059 return; 1060 } 1061 if (ctag) 1062 npc_update_entry(rvu, NPC_LB, mdata, NPC_LT_LB_CTAG, 0, 1063 ~0ULL, 0, intf); 1064 if (stag) 1065 npc_update_entry(rvu, NPC_LB, mdata, NPC_LT_LB_STAG_QINQ, 0, 1066 ~0ULL, 0, intf); 1067 } 1068 1069 void npc_update_flow(struct rvu *rvu, struct mcam_entry_mdata *mdata, 1070 u64 features, struct flow_msg *pkt, 1071 struct flow_msg *mask, 1072 struct rvu_npc_mcam_rule *output, u8 intf, 1073 int blkaddr) 1074 { 1075 u64 dmac_mask = ether_addr_to_u64(mask->dmac); 1076 u64 smac_mask = ether_addr_to_u64(mask->smac); 1077 u64 dmac_val = ether_addr_to_u64(pkt->dmac); 1078 u64 smac_val = ether_addr_to_u64(pkt->smac); 1079 struct flow_msg *opkt = &output->packet; 1080 struct flow_msg *omask = &output->mask; 1081 1082 if (!features) 1083 return; 1084 1085 /* For tcp/udp/sctp LTYPE should be present in entry */ 1086 if (features & BIT_ULL(NPC_IPPROTO_TCP)) 1087 npc_update_entry(rvu, NPC_LD, mdata, NPC_LT_LD_TCP, 1088 0, ~0ULL, 0, intf); 1089 if (features & BIT_ULL(NPC_IPPROTO_UDP)) 1090 npc_update_entry(rvu, NPC_LD, mdata, NPC_LT_LD_UDP, 1091 0, ~0ULL, 0, intf); 1092 if (features & BIT_ULL(NPC_IPPROTO_SCTP)) 1093 npc_update_entry(rvu, NPC_LD, mdata, NPC_LT_LD_SCTP, 1094 0, ~0ULL, 0, intf); 1095 if (features & BIT_ULL(NPC_IPPROTO_ICMP)) 1096 npc_update_entry(rvu, NPC_LD, mdata, NPC_LT_LD_ICMP, 1097 0, ~0ULL, 0, intf); 1098 if (features & BIT_ULL(NPC_IPPROTO_ICMP6)) 1099 npc_update_entry(rvu, NPC_LD, mdata, NPC_LT_LD_ICMP6, 1100 0, ~0ULL, 0, intf); 1101 1102 /* For AH, LTYPE should be present in entry */ 1103 if (features & BIT_ULL(NPC_IPPROTO_AH)) 1104 npc_update_entry(rvu, NPC_LD, mdata, NPC_LT_LD_AH, 1105 0, ~0ULL, 0, intf); 1106 /* For ESP, LTYPE should be present in entry */ 1107 if (features & BIT_ULL(NPC_IPPROTO_ESP)) 1108 npc_update_entry(rvu, NPC_LE, mdata, NPC_LT_LE_ESP, 1109 0, ~0ULL, 0, intf); 1110 1111 if (features & BIT_ULL(NPC_LXMB)) { 1112 output->lxmb = is_broadcast_ether_addr(pkt->dmac) ? 2 : 1; 1113 npc_update_entry(rvu, NPC_LXMB, mdata, output->lxmb, 0, 1114 output->lxmb, 0, intf); 1115 } 1116 #define NPC_WRITE_FLOW(field, member, val_lo, val_hi, mask_lo, mask_hi) \ 1117 do { \ 1118 if (features & BIT_ULL((field))) { \ 1119 npc_update_entry(rvu, (field), mdata, (val_lo), (val_hi), \ 1120 (mask_lo), (mask_hi), intf); \ 1121 memcpy(&opkt->member, &pkt->member, sizeof(pkt->member)); \ 1122 memcpy(&omask->member, &mask->member, sizeof(mask->member)); \ 1123 } \ 1124 } while (0) 1125 1126 NPC_WRITE_FLOW(NPC_DMAC, dmac, dmac_val, 0, dmac_mask, 0); 1127 1128 NPC_WRITE_FLOW(NPC_SMAC, smac, smac_val, 0, smac_mask, 0); 1129 NPC_WRITE_FLOW(NPC_ETYPE, etype, ntohs(pkt->etype), 0, 1130 ntohs(mask->etype), 0); 1131 NPC_WRITE_FLOW(NPC_TOS, tos, pkt->tos, 0, mask->tos, 0); 1132 NPC_WRITE_FLOW(NPC_IPFRAG_IPV4, ip_flag, pkt->ip_flag, 0, 1133 mask->ip_flag, 0); 1134 NPC_WRITE_FLOW(NPC_SIP_IPV4, ip4src, ntohl(pkt->ip4src), 0, 1135 ntohl(mask->ip4src), 0); 1136 NPC_WRITE_FLOW(NPC_DIP_IPV4, ip4dst, ntohl(pkt->ip4dst), 0, 1137 ntohl(mask->ip4dst), 0); 1138 NPC_WRITE_FLOW(NPC_SPORT_TCP, sport, ntohs(pkt->sport), 0, 1139 ntohs(mask->sport), 0); 1140 NPC_WRITE_FLOW(NPC_SPORT_UDP, sport, ntohs(pkt->sport), 0, 1141 ntohs(mask->sport), 0); 1142 NPC_WRITE_FLOW(NPC_DPORT_TCP, dport, ntohs(pkt->dport), 0, 1143 ntohs(mask->dport), 0); 1144 NPC_WRITE_FLOW(NPC_DPORT_UDP, dport, ntohs(pkt->dport), 0, 1145 ntohs(mask->dport), 0); 1146 NPC_WRITE_FLOW(NPC_SPORT_SCTP, sport, ntohs(pkt->sport), 0, 1147 ntohs(mask->sport), 0); 1148 NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt->dport), 0, 1149 ntohs(mask->dport), 0); 1150 NPC_WRITE_FLOW(NPC_TYPE_ICMP, icmp_type, pkt->icmp_type, 0, 1151 mask->icmp_type, 0); 1152 NPC_WRITE_FLOW(NPC_CODE_ICMP, icmp_code, pkt->icmp_code, 0, 1153 mask->icmp_code, 0); 1154 NPC_WRITE_FLOW(NPC_TCP_FLAGS, tcp_flags, ntohs(pkt->tcp_flags), 0, 1155 ntohs(mask->tcp_flags), 0); 1156 NPC_WRITE_FLOW(NPC_IPSEC_SPI, spi, ntohl(pkt->spi), 0, 1157 ntohl(mask->spi), 0); 1158 1159 NPC_WRITE_FLOW(NPC_OUTER_VID, vlan_tci, ntohs(pkt->vlan_tci), 0, 1160 ntohs(mask->vlan_tci), 0); 1161 NPC_WRITE_FLOW(NPC_INNER_VID, vlan_itci, ntohs(pkt->vlan_itci), 0, 1162 ntohs(mask->vlan_itci), 0); 1163 1164 NPC_WRITE_FLOW(NPC_MPLS1_LBTCBOS, mpls_lse, 1165 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1166 pkt->mpls_lse[0]), 0, 1167 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1168 mask->mpls_lse[0]), 0); 1169 NPC_WRITE_FLOW(NPC_MPLS1_TTL, mpls_lse, 1170 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1171 pkt->mpls_lse[0]), 0, 1172 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1173 mask->mpls_lse[0]), 0); 1174 NPC_WRITE_FLOW(NPC_MPLS2_LBTCBOS, mpls_lse, 1175 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1176 pkt->mpls_lse[1]), 0, 1177 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1178 mask->mpls_lse[1]), 0); 1179 NPC_WRITE_FLOW(NPC_MPLS2_TTL, mpls_lse, 1180 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1181 pkt->mpls_lse[1]), 0, 1182 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1183 mask->mpls_lse[1]), 0); 1184 NPC_WRITE_FLOW(NPC_MPLS3_LBTCBOS, mpls_lse, 1185 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1186 pkt->mpls_lse[2]), 0, 1187 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1188 mask->mpls_lse[2]), 0); 1189 NPC_WRITE_FLOW(NPC_MPLS3_TTL, mpls_lse, 1190 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1191 pkt->mpls_lse[2]), 0, 1192 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1193 mask->mpls_lse[2]), 0); 1194 NPC_WRITE_FLOW(NPC_MPLS4_LBTCBOS, mpls_lse, 1195 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1196 pkt->mpls_lse[3]), 0, 1197 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1198 mask->mpls_lse[3]), 0); 1199 NPC_WRITE_FLOW(NPC_MPLS4_TTL, mpls_lse, 1200 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1201 pkt->mpls_lse[3]), 0, 1202 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1203 mask->mpls_lse[3]), 0); 1204 1205 NPC_WRITE_FLOW(NPC_IPFRAG_IPV6, next_header, pkt->next_header, 0, 1206 mask->next_header, 0); 1207 npc_update_ipv6_flow(rvu, mdata, features, pkt, mask, output, intf); 1208 npc_update_vlan_features(rvu, mdata, features, intf); 1209 1210 npc_update_field_hash(rvu, intf, mdata, blkaddr, features, 1211 pkt, mask, opkt, omask); 1212 } 1213 1214 static struct rvu_npc_mcam_rule *rvu_mcam_find_rule(struct npc_mcam *mcam, u16 entry) 1215 { 1216 struct rvu_npc_mcam_rule *iter; 1217 1218 mutex_lock(&mcam->lock); 1219 list_for_each_entry(iter, &mcam->mcam_rules, list) { 1220 if (iter->entry == entry) { 1221 mutex_unlock(&mcam->lock); 1222 return iter; 1223 } 1224 } 1225 mutex_unlock(&mcam->lock); 1226 1227 return NULL; 1228 } 1229 1230 static void rvu_mcam_add_rule(struct npc_mcam *mcam, 1231 struct rvu_npc_mcam_rule *rule) 1232 { 1233 struct list_head *head = &mcam->mcam_rules; 1234 struct rvu_npc_mcam_rule *iter; 1235 1236 mutex_lock(&mcam->lock); 1237 list_for_each_entry(iter, &mcam->mcam_rules, list) { 1238 if (iter->entry > rule->entry) 1239 break; 1240 head = &iter->list; 1241 } 1242 1243 list_add(&rule->list, head); 1244 mutex_unlock(&mcam->lock); 1245 } 1246 1247 static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 1248 struct rvu_npc_mcam_rule *rule) 1249 { 1250 struct npc_mcam *mcam = &rvu->hw->mcam; 1251 1252 /* There is no counter allotted for cn20k */ 1253 if (is_cn20k(rvu->pdev)) 1254 return; 1255 1256 mutex_lock(&mcam->lock); 1257 1258 __rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); 1259 1260 mutex_unlock(&mcam->lock); 1261 } 1262 1263 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 1264 struct rvu_npc_mcam_rule *rule, 1265 struct npc_install_flow_rsp *rsp) 1266 { 1267 struct npc_mcam *mcam = &rvu->hw->mcam; 1268 1269 mutex_lock(&mcam->lock); 1270 1271 __rvu_mcam_add_counter_to_rule(rvu, pcifunc, rule, rsp); 1272 1273 mutex_unlock(&mcam->lock); 1274 } 1275 1276 static int npc_mcast_update_action_index(struct rvu *rvu, struct npc_install_flow_req *req, 1277 u64 op, void *action) 1278 { 1279 int mce_index; 1280 1281 /* If a PF/VF is installing a multicast rule then it is expected 1282 * that the PF/VF should have created a group for the multicast/mirror 1283 * list. Otherwise reject the configuration. 1284 * During this scenario, req->index is set as multicast/mirror 1285 * group index. 1286 */ 1287 if (req->hdr.pcifunc && 1288 (op == NIX_RX_ACTIONOP_MCAST || op == NIX_TX_ACTIONOP_MCAST)) { 1289 mce_index = rvu_nix_mcast_get_mce_index(rvu, req->hdr.pcifunc, req->index); 1290 if (mce_index < 0) 1291 return mce_index; 1292 1293 if (op == NIX_RX_ACTIONOP_MCAST) 1294 ((struct nix_rx_action *)action)->index = mce_index; 1295 else 1296 ((struct nix_tx_action *)action)->index = mce_index; 1297 } 1298 1299 return 0; 1300 } 1301 1302 void 1303 npc_populate_mcam_mdata(struct rvu *rvu, 1304 struct mcam_entry_mdata *mdata, 1305 struct cn20k_mcam_entry *cn20k_entry, 1306 struct mcam_entry *entry) 1307 { 1308 if (is_cn20k(rvu->pdev)) { 1309 mdata->kw = cn20k_entry->kw; 1310 mdata->kw_mask = cn20k_entry->kw_mask; 1311 mdata->action = &cn20k_entry->action; 1312 mdata->vtag_action = &cn20k_entry->vtag_action; 1313 mdata->max_kw = NPC_KWS_IN_KEY_SZ_8; 1314 return; 1315 } 1316 mdata->kw = entry->kw; 1317 mdata->kw_mask = entry->kw_mask; 1318 mdata->action = &entry->action; 1319 mdata->vtag_action = &entry->vtag_action; 1320 mdata->max_kw = NPC_KWS_IN_KEY_SZ_7; 1321 } 1322 1323 static int npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1324 struct mcam_entry_mdata *mdata, 1325 struct npc_install_flow_req *req, 1326 u16 target, bool pf_set_vfs_mac) 1327 { 1328 struct rvu_switch *rswitch = &rvu->rswitch; 1329 struct nix_rx_action action; 1330 int ret; 1331 1332 if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac) 1333 req->chan_mask = 0x0; /* Do not care channel */ 1334 1335 npc_update_entry(rvu, NPC_CHAN, mdata, req->channel, 0, req->chan_mask, 1336 0, NIX_INTF_RX); 1337 1338 *(u64 *)&action = 0x00; 1339 action.pf_func = target; 1340 action.op = req->op; 1341 action.index = req->index; 1342 1343 ret = npc_mcast_update_action_index(rvu, req, action.op, (void *)&action); 1344 if (ret) 1345 return ret; 1346 1347 action.match_id = req->match_id; 1348 action.flow_key_alg = req->flow_key_alg; 1349 1350 if (req->op == NIX_RX_ACTION_DEFAULT) { 1351 if (pfvf->def_ucast_rule) { 1352 action = pfvf->def_ucast_rule->rx_action; 1353 } else { 1354 /* For profiles which do not extract DMAC, the default 1355 * unicast entry is unused. Hence modify action for the 1356 * requests which use same action as default unicast 1357 * entry 1358 */ 1359 *(u64 *)&action = 0; 1360 action.pf_func = target; 1361 action.op = NIX_RX_ACTIONOP_UCAST; 1362 } 1363 if (req->match_id) 1364 action.match_id = req->match_id; 1365 } 1366 1367 *mdata->action = *(u64 *)&action; 1368 1369 /* VTAG0 starts at 0th byte of LID_B. 1370 * VTAG1 starts at 4th byte of LID_B. 1371 */ 1372 *mdata->vtag_action = FIELD_PREP(RX_VTAG0_VALID_BIT, req->vtag0_valid) | 1373 FIELD_PREP(RX_VTAG0_TYPE_MASK, req->vtag0_type) | 1374 FIELD_PREP(RX_VTAG0_LID_MASK, NPC_LID_LB) | 1375 FIELD_PREP(RX_VTAG0_RELPTR_MASK, 0) | 1376 FIELD_PREP(RX_VTAG1_VALID_BIT, req->vtag1_valid) | 1377 FIELD_PREP(RX_VTAG1_TYPE_MASK, req->vtag1_type) | 1378 FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) | 1379 FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4); 1380 1381 return 0; 1382 } 1383 1384 static int npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1385 struct mcam_entry_mdata *mdata, 1386 struct npc_install_flow_req *req, u16 target) 1387 { 1388 struct nix_tx_action action; 1389 u64 mask = ~0ULL; 1390 int ret; 1391 1392 /* If AF is installing then do not care about 1393 * PF_FUNC in Send Descriptor 1394 */ 1395 if (is_pffunc_af(req->hdr.pcifunc)) 1396 mask = 0; 1397 1398 npc_update_entry(rvu, NPC_PF_FUNC, mdata, (__force u16)htons(target), 1399 0, mask, 0, NIX_INTF_TX); 1400 1401 *(u64 *)&action = 0x00; 1402 action.op = req->op; 1403 action.index = req->index; 1404 1405 ret = npc_mcast_update_action_index(rvu, req, action.op, (void *)&action); 1406 if (ret) 1407 return ret; 1408 1409 action.match_id = req->match_id; 1410 1411 *mdata->action = *(u64 *)&action; 1412 1413 /* VTAG0 starts at 0th byte of LID_B. 1414 * VTAG1 starts at 4th byte of LID_B. 1415 */ 1416 *mdata->vtag_action = FIELD_PREP(TX_VTAG0_DEF_MASK, req->vtag0_def) | 1417 FIELD_PREP(TX_VTAG0_OP_MASK, req->vtag0_op) | 1418 FIELD_PREP(TX_VTAG0_LID_MASK, NPC_LID_LA) | 1419 FIELD_PREP(TX_VTAG0_RELPTR_MASK, 20) | 1420 FIELD_PREP(TX_VTAG1_DEF_MASK, req->vtag1_def) | 1421 FIELD_PREP(TX_VTAG1_OP_MASK, req->vtag1_op) | 1422 FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) | 1423 FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24); 1424 1425 return 0; 1426 } 1427 1428 static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target, 1429 int nixlf, struct rvu_pfvf *pfvf, 1430 struct npc_install_flow_req *req, 1431 struct npc_install_flow_rsp *rsp, bool enable, 1432 bool pf_set_vfs_mac) 1433 { 1434 struct rvu_npc_mcam_rule *def_ucast_rule = pfvf->def_ucast_rule; 1435 struct npc_cn20k_mcam_write_entry_req cn20k_wreq = { 0 }; 1436 u64 features, installed_features, missing_features = 0; 1437 struct npc_mcam_write_entry_req write_req = { 0 }; 1438 struct npc_mcam *mcam = &rvu->hw->mcam; 1439 struct cn20k_mcam_entry *cn20k_entry; 1440 struct mcam_entry_mdata mdata = { }; 1441 struct rvu_npc_mcam_rule dummy = { 0 }; 1442 struct rvu_npc_mcam_rule *rule; 1443 u16 owner = req->hdr.pcifunc; 1444 struct msg_rsp write_rsp; 1445 struct mcam_entry *entry; 1446 bool new = false; 1447 int entry_index; 1448 int err; 1449 1450 installed_features = req->features; 1451 features = req->features; 1452 entry_index = req->entry; 1453 1454 cn20k_entry = &cn20k_wreq.entry_data; 1455 entry = &write_req.entry_data; 1456 1457 npc_populate_mcam_mdata(rvu, &mdata, cn20k_entry, entry); 1458 1459 npc_update_flow(rvu, &mdata, features, &req->packet, &req->mask, &dummy, 1460 req->intf, blkaddr); 1461 1462 if (is_npc_intf_rx(req->intf)) { 1463 err = npc_update_rx_entry(rvu, pfvf, &mdata, req, target, 1464 pf_set_vfs_mac); 1465 if (err) 1466 return err; 1467 } else { 1468 err = npc_update_tx_entry(rvu, pfvf, &mdata, req, target); 1469 if (err) 1470 return err; 1471 } 1472 1473 /* Default unicast rules do not exist for TX */ 1474 if (is_npc_intf_tx(req->intf)) 1475 goto find_rule; 1476 1477 if (req->default_rule) { 1478 entry_index = npc_get_nixlf_mcam_index(mcam, target, nixlf, 1479 NIXLF_UCAST_ENTRY); 1480 1481 if (entry_index < 0) { 1482 dev_err(rvu->dev, 1483 "%s: Error to get ucast entry for target=%#x\n", 1484 __func__, target); 1485 return -EINVAL; 1486 } 1487 1488 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, entry_index); 1489 } 1490 1491 /* update mcam entry with default unicast rule attributes */ 1492 if (def_ucast_rule && (req->default_rule && req->append)) { 1493 missing_features = (def_ucast_rule->features ^ features) & 1494 def_ucast_rule->features; 1495 if (missing_features) 1496 npc_update_flow(rvu, &mdata, missing_features, 1497 &def_ucast_rule->packet, 1498 &def_ucast_rule->mask, 1499 &dummy, req->intf, 1500 blkaddr); 1501 installed_features = req->features | missing_features; 1502 } 1503 1504 find_rule: 1505 rule = rvu_mcam_find_rule(mcam, entry_index); 1506 if (!rule) { 1507 rule = kzalloc_obj(*rule); 1508 if (!rule) 1509 return -ENOMEM; 1510 new = true; 1511 } 1512 1513 if (!is_cn20k(rvu->pdev)) { 1514 write_req.hdr.pcifunc = owner; 1515 1516 /* allocate new counter if rule has no counter */ 1517 if (!req->default_rule && req->set_cntr && !rule->has_cntr) 1518 rvu_mcam_add_counter_to_rule(rvu, owner, rule, rsp); 1519 1520 /* if user wants to delete an existing counter for a rule then 1521 * free the counter 1522 */ 1523 if (!req->set_cntr && rule->has_cntr) 1524 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1525 1526 /* AF owns the default rules so change the owner just to relax 1527 * the checks in rvu_mbox_handler_npc_mcam_write_entry 1528 */ 1529 if (req->default_rule) 1530 write_req.hdr.pcifunc = 0; 1531 1532 write_req.entry = entry_index; 1533 write_req.intf = req->intf; 1534 write_req.enable_entry = (u8)enable; 1535 /* if counter is available then clear and use it */ 1536 if (req->set_cntr && rule->has_cntr) { 1537 rvu_write64(rvu, blkaddr, 1538 NPC_AF_MATCH_STATX(rule->cntr), 1539 req->cntr_val); 1540 write_req.set_cntr = 1; 1541 write_req.cntr = rule->cntr; 1542 } 1543 goto update_rule; 1544 } 1545 1546 cn20k_wreq.hdr.pcifunc = owner; 1547 1548 if (req->default_rule) 1549 cn20k_wreq.hdr.pcifunc = 0; 1550 1551 cn20k_wreq.entry = entry_index; 1552 cn20k_wreq.intf = req->intf; 1553 cn20k_wreq.enable_entry = (u8)enable; 1554 cn20k_wreq.hw_prio = req->hw_prio; 1555 cn20k_wreq.req_kw_type = req->req_kw_type; 1556 1557 update_rule: 1558 1559 /* update rule */ 1560 memcpy(&rule->packet, &dummy.packet, sizeof(rule->packet)); 1561 memcpy(&rule->mask, &dummy.mask, sizeof(rule->mask)); 1562 rule->entry = entry_index; 1563 if (is_cn20k(rvu->pdev)) { 1564 memcpy(&rule->rx_action, &cn20k_entry->action, 1565 sizeof(struct nix_rx_action)); 1566 if (is_npc_intf_tx(req->intf)) 1567 memcpy(&rule->tx_action, &cn20k_entry->action, 1568 sizeof(struct nix_tx_action)); 1569 rule->vtag_action = cn20k_entry->vtag_action; 1570 } else { 1571 memcpy(&rule->rx_action, &entry->action, 1572 sizeof(struct nix_rx_action)); 1573 if (is_npc_intf_tx(req->intf)) 1574 memcpy(&rule->tx_action, &entry->action, 1575 sizeof(struct nix_tx_action)); 1576 rule->vtag_action = entry->vtag_action; 1577 } 1578 1579 rule->features = installed_features; 1580 rule->default_rule = req->default_rule; 1581 rule->owner = owner; 1582 rule->enable = enable; 1583 1584 if (is_cn20k(rvu->pdev)) { 1585 rule->chan_mask = cn20k_wreq.entry_data.kw_mask[0] & 1586 NPC_KEX_CHAN_MASK; 1587 rule->chan = cn20k_wreq.entry_data.kw[0] & 1588 NPC_KEX_CHAN_MASK; 1589 } else { 1590 rule->chan_mask = write_req.entry_data.kw_mask[0] & 1591 NPC_KEX_CHAN_MASK; 1592 rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK; 1593 } 1594 1595 rule->chan &= rule->chan_mask; 1596 rule->lxmb = dummy.lxmb; 1597 rule->hw_prio = req->hw_prio; 1598 if (is_npc_intf_tx(req->intf)) 1599 rule->intf = pfvf->nix_tx_intf; 1600 else 1601 rule->intf = pfvf->nix_rx_intf; 1602 1603 if (new) 1604 rvu_mcam_add_rule(mcam, rule); 1605 if (req->default_rule) 1606 pfvf->def_ucast_rule = rule; 1607 1608 /* write to mcam entry registers */ 1609 if (is_cn20k(rvu->pdev)) 1610 err = rvu_mbox_handler_npc_cn20k_mcam_write_entry(rvu, 1611 &cn20k_wreq, 1612 &write_rsp); 1613 else 1614 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, 1615 &write_rsp); 1616 1617 if (err) { 1618 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1619 if (new) { 1620 list_del(&rule->list); 1621 kfree(rule); 1622 } 1623 return err; 1624 } 1625 1626 /* VF's MAC address is being changed via PF */ 1627 if (pf_set_vfs_mac) { 1628 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1629 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1630 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1631 } 1632 1633 if (test_bit(PF_SET_VF_CFG, &pfvf->flags) && 1634 req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7) 1635 rule->vfvlan_cfg = true; 1636 1637 if (is_npc_intf_rx(req->intf) && req->match_id && 1638 (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS)) 1639 return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc, 1640 req->index, req->match_id); 1641 1642 if (owner && req->op == NIX_RX_ACTIONOP_MCAST) 1643 return rvu_nix_mcast_update_mcam_entry(rvu, req->hdr.pcifunc, 1644 req->index, entry_index); 1645 1646 return 0; 1647 } 1648 1649 static int 1650 rvu_npc_free_entry_for_flow_install(struct rvu *rvu, u16 pcifunc, 1651 bool free_entry, int mcam_idx) 1652 { 1653 struct npc_mcam_free_entry_req free_req = { 0 }; 1654 struct msg_rsp rsp; 1655 int rc; 1656 1657 if (!free_entry) 1658 return 0; 1659 1660 free_req.hdr.pcifunc = pcifunc; 1661 free_req.entry = mcam_idx; 1662 rc = rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp); 1663 return rc; 1664 } 1665 1666 static int 1667 rvu_npc_alloc_entry_for_flow_install(struct rvu *rvu, 1668 struct npc_install_flow_req *fl_req, 1669 u16 *mcam_idx, u8 *kw_type, 1670 bool *allocated) 1671 { 1672 struct npc_mcam_alloc_entry_req entry_req; 1673 struct npc_mcam_alloc_entry_rsp entry_rsp; 1674 struct npc_get_num_kws_req kws_req; 1675 struct npc_get_num_kws_rsp kws_rsp; 1676 int off, kw_bits, rc; 1677 u8 *src, *dst; 1678 1679 if (!is_cn20k(rvu->pdev)) { 1680 *kw_type = -1; 1681 return 0; 1682 } 1683 1684 if (!fl_req->alloc_entry) { 1685 *kw_type = -1; 1686 return 0; 1687 } 1688 1689 off = offsetof(struct npc_install_flow_req, packet); 1690 dst = (u8 *)&kws_req.fl + off; 1691 src = (u8 *)fl_req + off; 1692 memcpy(dst, src, sizeof(struct npc_install_flow_req) - off); 1693 rc = rvu_mbox_handler_npc_get_num_kws(rvu, &kws_req, &kws_rsp); 1694 if (rc) 1695 return rc; 1696 1697 kw_bits = kws_rsp.kws * 64; 1698 1699 *kw_type = NPC_MCAM_KEY_X2; 1700 if (kw_bits > 256) 1701 *kw_type = NPC_MCAM_KEY_X4; 1702 1703 memset(&entry_req, 0, sizeof(entry_req)); 1704 memset(&entry_rsp, 0, sizeof(entry_rsp)); 1705 1706 entry_req.hdr.pcifunc = fl_req->hdr.pcifunc; 1707 entry_req.ref_prio = fl_req->ref_prio; 1708 entry_req.ref_entry = fl_req->ref_entry; 1709 entry_req.kw_type = *kw_type; 1710 entry_req.count = 1; 1711 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, 1712 &entry_req, 1713 &entry_rsp); 1714 if (rc) 1715 return rc; 1716 1717 *mcam_idx = entry_rsp.entry_list[0]; 1718 *allocated = true; 1719 return 0; 1720 } 1721 1722 int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, 1723 struct npc_install_flow_req *req, 1724 struct npc_install_flow_rsp *rsp) 1725 { 1726 bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK); 1727 bool from_rep_dev = !!is_rep_dev(rvu, req->hdr.pcifunc); 1728 struct rvu_switch *rswitch = &rvu->rswitch; 1729 int blkaddr, nixlf, err; 1730 struct rvu_pfvf *pfvf; 1731 bool pf_set_vfs_mac = false; 1732 bool allocated = false; 1733 bool enable = true; 1734 u8 kw_type; 1735 u16 target; 1736 1737 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1738 if (blkaddr < 0) { 1739 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1740 return NPC_MCAM_INVALID_REQ; 1741 } 1742 1743 if (!is_npc_interface_valid(rvu, req->intf)) 1744 return NPC_FLOW_INTF_INVALID; 1745 1746 err = rvu_npc_alloc_entry_for_flow_install(rvu, req, &req->entry, 1747 &kw_type, &allocated); 1748 if (err) { 1749 dev_err(rvu->dev, 1750 "%s: Error to alloc mcam entry for pcifunc=%#x\n", 1751 __func__, req->hdr.pcifunc); 1752 return err; 1753 } 1754 1755 req->entry = npc_cn20k_vidx2idx(req->entry); 1756 1757 /* If DMAC is not extracted in MKEX, rules installed by AF 1758 * can rely on L2MB bit set by hardware protocol checker for 1759 * broadcast and multicast addresses. 1760 */ 1761 if (npc_check_field(rvu, blkaddr, NPC_DMAC, req->intf)) 1762 goto process_flow; 1763 1764 if (is_pffunc_af(req->hdr.pcifunc) && 1765 req->features & BIT_ULL(NPC_DMAC)) { 1766 if (is_unicast_ether_addr(req->packet.dmac)) { 1767 dev_warn(rvu->dev, 1768 "%s: mkex profile does not support ucast flow\n", 1769 __func__); 1770 rvu_npc_free_entry_for_flow_install(rvu, 1771 req->hdr.pcifunc, 1772 allocated, 1773 req->entry); 1774 return NPC_FLOW_NOT_SUPPORTED; 1775 } 1776 1777 if (!npc_is_field_present(rvu, NPC_LXMB, req->intf)) { 1778 dev_warn(rvu->dev, 1779 "%s: mkex profile does not support bcast/mcast flow", 1780 __func__); 1781 rvu_npc_free_entry_for_flow_install(rvu, 1782 req->hdr.pcifunc, 1783 allocated, 1784 req->entry); 1785 return NPC_FLOW_NOT_SUPPORTED; 1786 } 1787 1788 /* Modify feature to use LXMB instead of DMAC */ 1789 req->features &= ~BIT_ULL(NPC_DMAC); 1790 req->features |= BIT_ULL(NPC_LXMB); 1791 } 1792 1793 process_flow: 1794 if (from_vf && req->default_rule) { 1795 rvu_npc_free_entry_for_flow_install(rvu, req->hdr.pcifunc, 1796 allocated, req->entry); 1797 return NPC_FLOW_VF_PERM_DENIED; 1798 } 1799 1800 /* Each PF/VF info is maintained in struct rvu_pfvf. 1801 * rvu_pfvf for the target PF/VF needs to be retrieved 1802 * hence modify pcifunc accordingly. 1803 */ 1804 1805 if (!req->hdr.pcifunc) { 1806 /* AF installing for a PF/VF */ 1807 target = req->vf; 1808 } else if (!from_vf && req->vf && !from_rep_dev) { 1809 /* PF installing for its VF */ 1810 target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf; 1811 pf_set_vfs_mac = req->default_rule && 1812 (req->features & BIT_ULL(NPC_DMAC)); 1813 } else if (from_rep_dev && req->vf) { 1814 /* Representor device installing for a representee */ 1815 target = req->vf; 1816 } else { 1817 /* msg received from PF/VF */ 1818 target = req->hdr.pcifunc; 1819 } 1820 1821 /* ignore chan_mask in case pf func is not AF, revisit later */ 1822 if (!is_pffunc_af(req->hdr.pcifunc)) 1823 req->chan_mask = rvu_get_cpt_chan_mask(rvu); 1824 1825 err = npc_check_unsupported_flows(rvu, req->features, req->intf); 1826 if (err) { 1827 rvu_npc_free_entry_for_flow_install(rvu, req->hdr.pcifunc, 1828 allocated, req->entry); 1829 return NPC_FLOW_NOT_SUPPORTED; 1830 } 1831 1832 pfvf = rvu_get_pfvf(rvu, target); 1833 1834 if (from_rep_dev) 1835 req->channel = pfvf->rx_chan_base; 1836 /* PF installing for its VF */ 1837 if (req->hdr.pcifunc && !from_vf && req->vf && !from_rep_dev) 1838 set_bit(PF_SET_VF_CFG, &pfvf->flags); 1839 1840 /* update req destination mac addr */ 1841 if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) && 1842 is_zero_ether_addr(req->packet.dmac)) { 1843 ether_addr_copy(req->packet.dmac, pfvf->mac_addr); 1844 eth_broadcast_addr((u8 *)&req->mask.dmac); 1845 } 1846 1847 /* Proceed if NIXLF is attached or not for TX rules */ 1848 err = nix_get_nixlf(rvu, target, &nixlf, NULL); 1849 if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac) { 1850 rvu_npc_free_entry_for_flow_install(rvu, req->hdr.pcifunc, 1851 allocated, req->entry); 1852 return NPC_FLOW_NO_NIXLF; 1853 } 1854 1855 /* don't enable rule when nixlf not attached or initialized */ 1856 if (!(is_nixlf_attached(rvu, target) && 1857 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 1858 enable = false; 1859 1860 /* Packets reaching NPC in Tx path implies that a 1861 * NIXLF is properly setup and transmitting. 1862 * Hence rules can be enabled for Tx. 1863 */ 1864 if (is_npc_intf_tx(req->intf)) 1865 enable = true; 1866 1867 /* Do not allow requests from uninitialized VFs */ 1868 if (from_vf && !enable) { 1869 rvu_npc_free_entry_for_flow_install(rvu, req->hdr.pcifunc, 1870 allocated, req->entry); 1871 return NPC_FLOW_VF_NOT_INIT; 1872 } 1873 1874 /* PF sets VF mac & VF NIXLF is not attached, update the mac addr */ 1875 if (pf_set_vfs_mac && !enable) { 1876 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1877 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1878 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1879 rvu_npc_free_entry_for_flow_install(rvu, req->hdr.pcifunc, 1880 allocated, req->entry); 1881 return 0; 1882 } 1883 1884 mutex_lock(&rswitch->switch_lock); 1885 err = npc_install_flow(rvu, blkaddr, target, nixlf, pfvf, 1886 req, rsp, enable, pf_set_vfs_mac); 1887 if (err) 1888 rvu_npc_free_entry_for_flow_install(rvu, req->hdr.pcifunc, 1889 allocated, req->entry); 1890 1891 rsp->kw_type = kw_type; 1892 rsp->entry = req->entry; 1893 mutex_unlock(&rswitch->switch_lock); 1894 1895 return err; 1896 } 1897 1898 static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule, 1899 u16 pcifunc) 1900 { 1901 struct npc_mcam_ena_dis_entry_req dis_req = { 0 }; 1902 struct msg_rsp dis_rsp; 1903 1904 if (rule->default_rule) 1905 return 0; 1906 1907 if (rule->has_cntr) 1908 rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); 1909 1910 dis_req.hdr.pcifunc = pcifunc; 1911 dis_req.entry = rule->entry; 1912 1913 list_del(&rule->list); 1914 kfree(rule); 1915 1916 return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp); 1917 } 1918 1919 int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu, 1920 struct npc_delete_flow_req *req, 1921 struct npc_delete_flow_rsp *rsp) 1922 { 1923 struct npc_mcam *mcam = &rvu->hw->mcam; 1924 struct rvu_npc_mcam_rule *iter, *tmp; 1925 u16 pcifunc = req->hdr.pcifunc; 1926 struct list_head del_list; 1927 int blkaddr; 1928 1929 req->entry = npc_cn20k_vidx2idx(req->entry); 1930 req->start = npc_cn20k_vidx2idx(req->start); 1931 req->end = npc_cn20k_vidx2idx(req->end); 1932 1933 INIT_LIST_HEAD(&del_list); 1934 1935 mutex_lock(&mcam->lock); 1936 list_for_each_entry_safe(iter, tmp, &mcam->mcam_rules, list) { 1937 if (iter->owner == pcifunc) { 1938 /* All rules */ 1939 if (req->all) { 1940 list_move_tail(&iter->list, &del_list); 1941 /* Range of rules */ 1942 } else if (req->end && iter->entry >= req->start && 1943 iter->entry <= req->end) { 1944 list_move_tail(&iter->list, &del_list); 1945 /* single rule */ 1946 } else if (req->entry == iter->entry) { 1947 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1948 if (blkaddr) 1949 rsp->cntr_val = rvu_read64(rvu, blkaddr, 1950 NPC_AF_MATCH_STATX(iter->cntr)); 1951 list_move_tail(&iter->list, &del_list); 1952 break; 1953 } 1954 } 1955 } 1956 mutex_unlock(&mcam->lock); 1957 1958 list_for_each_entry_safe(iter, tmp, &del_list, list) { 1959 u16 entry = iter->entry; 1960 1961 /* clear the mcam entry target pcifunc */ 1962 mcam->entry2target_pffunc[entry] = 0x0; 1963 if (npc_delete_flow(rvu, iter, pcifunc)) 1964 dev_err(rvu->dev, "rule deletion failed for entry:%u", 1965 entry); 1966 } 1967 1968 return 0; 1969 } 1970 1971 static int npc_update_dmac_value(struct rvu *rvu, int npcblkaddr, 1972 struct rvu_npc_mcam_rule *rule, 1973 struct rvu_pfvf *pfvf) 1974 { 1975 struct npc_cn20k_mcam_write_entry_req cn20k_wreq = { 0 }; 1976 struct npc_mcam_write_entry_req write_req = { 0 }; 1977 struct mcam_entry_mdata mdata = { }; 1978 struct npc_mcam *mcam = &rvu->hw->mcam; 1979 struct cn20k_mcam_entry *cn20k_entry; 1980 struct mcam_entry *entry; 1981 u8 intf, enable, hw_prio; 1982 struct msg_rsp rsp; 1983 int err; 1984 1985 cn20k_entry = &cn20k_wreq.entry_data; 1986 entry = &write_req.entry_data; 1987 npc_populate_mcam_mdata(rvu, &mdata, cn20k_entry, entry); 1988 1989 ether_addr_copy(rule->packet.dmac, pfvf->mac_addr); 1990 1991 if (is_cn20k(rvu->pdev)) { 1992 if (npc_cn20k_read_mcam_entry(rvu, npcblkaddr, rule->entry, 1993 cn20k_entry, &intf, 1994 &enable, &hw_prio)) 1995 return -EINVAL; 1996 } else { 1997 npc_read_mcam_entry(rvu, mcam, npcblkaddr, rule->entry, 1998 entry, &intf, &enable); 1999 } 2000 2001 npc_update_entry(rvu, NPC_DMAC, &mdata, 2002 ether_addr_to_u64(pfvf->mac_addr), 0, 2003 0xffffffffffffull, 0, intf); 2004 2005 mutex_unlock(&mcam->lock); 2006 if (is_cn20k(rvu->pdev)) { 2007 cn20k_wreq.hdr.pcifunc = rule->owner; 2008 cn20k_wreq.entry = rule->entry; 2009 cn20k_wreq.intf = pfvf->nix_rx_intf; 2010 err = rvu_mbox_handler_npc_cn20k_mcam_write_entry(rvu, 2011 &cn20k_wreq, 2012 &rsp); 2013 } else { 2014 write_req.hdr.pcifunc = rule->owner; 2015 write_req.entry = rule->entry; 2016 write_req.intf = pfvf->nix_rx_intf; 2017 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, 2018 &rsp); 2019 } 2020 mutex_lock(&mcam->lock); 2021 2022 return err; 2023 } 2024 2025 void npc_mcam_enable_flows(struct rvu *rvu, u16 target) 2026 { 2027 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, target); 2028 struct rvu_npc_mcam_rule *def_ucast_rule; 2029 struct npc_mcam *mcam = &rvu->hw->mcam; 2030 struct rvu_npc_mcam_rule *rule; 2031 int blkaddr, bank, index; 2032 u64 def_action; 2033 2034 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2035 if (blkaddr < 0) 2036 return; 2037 2038 def_ucast_rule = pfvf->def_ucast_rule; 2039 2040 mutex_lock(&mcam->lock); 2041 list_for_each_entry(rule, &mcam->mcam_rules, list) { 2042 if (is_npc_intf_rx(rule->intf) && 2043 rule->rx_action.pf_func == target && !rule->enable) { 2044 if (rule->default_rule) { 2045 npc_enable_mcam_entry(rvu, mcam, blkaddr, 2046 rule->entry, true); 2047 rule->enable = true; 2048 continue; 2049 } 2050 2051 if (rule->vfvlan_cfg) { 2052 if (npc_update_dmac_value(rvu, blkaddr, rule, pfvf)) 2053 dev_err(rvu->dev, 2054 "Update dmac failed for %u, target=%#x\n", 2055 rule->entry, target); 2056 } 2057 2058 if (rule->rx_action.op == NIX_RX_ACTION_DEFAULT) { 2059 if (!def_ucast_rule) 2060 continue; 2061 /* Use default unicast entry action */ 2062 rule->rx_action = def_ucast_rule->rx_action; 2063 def_action = *(u64 *)&def_ucast_rule->rx_action; 2064 bank = npc_get_bank(mcam, rule->entry); 2065 rvu_write64(rvu, blkaddr, 2066 NPC_AF_MCAMEX_BANKX_ACTION 2067 (rule->entry, bank), def_action); 2068 } 2069 2070 npc_enable_mcam_entry(rvu, mcam, blkaddr, 2071 rule->entry, true); 2072 rule->enable = true; 2073 } 2074 } 2075 2076 /* Enable MCAM entries installed by PF with target as VF pcifunc */ 2077 for (index = 0; index < mcam->bmap_entries; index++) { 2078 if (mcam->entry2target_pffunc[index] == target) 2079 npc_enable_mcam_entry(rvu, mcam, blkaddr, 2080 index, true); 2081 } 2082 mutex_unlock(&mcam->lock); 2083 } 2084 2085 void npc_mcam_disable_flows(struct rvu *rvu, u16 target) 2086 { 2087 struct npc_mcam *mcam = &rvu->hw->mcam; 2088 int blkaddr, index; 2089 2090 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2091 if (blkaddr < 0) 2092 return; 2093 2094 mutex_lock(&mcam->lock); 2095 /* Disable MCAM entries installed by PF with target as VF pcifunc */ 2096 for (index = 0; index < mcam->bmap_entries; index++) { 2097 if (mcam->entry2target_pffunc[index] == target) 2098 npc_enable_mcam_entry(rvu, mcam, blkaddr, 2099 index, false); 2100 } 2101 mutex_unlock(&mcam->lock); 2102 } 2103 2104 /* single drop on non hit rule starting from 0th index. This an extension 2105 * to RPM mac filter to support more rules. 2106 */ 2107 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 2108 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 2109 u64 bcast_mcast_val, u64 bcast_mcast_mask) 2110 { 2111 struct npc_cn20k_mcam_write_entry_req cn20k_req = { 0 }; 2112 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 2113 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 2114 struct npc_mcam_write_entry_req req = { 0 }; 2115 struct npc_mcam *mcam = &rvu->hw->mcam; 2116 struct mcam_entry_mdata mdata = { }; 2117 struct rvu_npc_mcam_rule *rule; 2118 struct msg_rsp rsp; 2119 bool enabled; 2120 int blkaddr; 2121 int err; 2122 2123 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2124 if (blkaddr < 0) { 2125 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 2126 return -ENODEV; 2127 } 2128 2129 /* Bail out if no exact match support */ 2130 if (!rvu_npc_exact_has_match_table(rvu)) { 2131 dev_info(rvu->dev, "%s: No support for exact match feature\n", __func__); 2132 return -EINVAL; 2133 } 2134 2135 /* If 0th entry is already used, return err */ 2136 enabled = is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_idx); 2137 if (enabled) { 2138 dev_err(rvu->dev, "%s: failed to add single drop on non hit rule at %d th index\n", 2139 __func__, mcam_idx); 2140 return -EINVAL; 2141 } 2142 2143 /* Add this entry to mcam rules list */ 2144 rule = kzalloc_obj(*rule); 2145 if (!rule) 2146 return -ENOMEM; 2147 2148 /* Disable rule by default. Enable rule when first dmac filter is 2149 * installed 2150 */ 2151 rule->enable = false; 2152 rule->chan = chan_val; 2153 rule->chan_mask = chan_mask; 2154 rule->entry = mcam_idx; 2155 rvu_mcam_add_rule(mcam, rule); 2156 2157 /* Reserve slot 0 */ 2158 npc_mcam_rsrcs_reserve(rvu, blkaddr, mcam_idx); 2159 2160 if (!is_cn20k(rvu->pdev)) { 2161 /* Allocate counter for this single drop on non hit rule */ 2162 cntr_req.hdr.pcifunc = 0; /* AF request */ 2163 cntr_req.contig = true; 2164 cntr_req.count = 1; 2165 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, 2166 &cntr_rsp); 2167 if (err) { 2168 dev_err(rvu->dev, 2169 "%s: Err to allocate cntr for drop rule (err=%d)\n", 2170 __func__, err); 2171 return -EFAULT; 2172 } 2173 *counter_idx = cntr_rsp.cntr; 2174 } 2175 2176 npc_populate_mcam_mdata(rvu, &mdata, 2177 &cn20k_req.entry_data, 2178 &req.entry_data); 2179 2180 /* Fill in fields for this mcam entry */ 2181 npc_update_entry(rvu, NPC_EXACT_RESULT, &mdata, exact_val, 0, 2182 exact_mask, 0, NIX_INTF_RX); 2183 npc_update_entry(rvu, NPC_CHAN, &mdata, chan_val, 0, 2184 chan_mask, 0, NIX_INTF_RX); 2185 npc_update_entry(rvu, NPC_LXMB, &mdata, bcast_mcast_val, 0, 2186 bcast_mcast_mask, 0, NIX_INTF_RX); 2187 2188 if (is_cn20k(rvu->pdev)) { 2189 cn20k_req.intf = NIX_INTF_RX; 2190 cn20k_req.entry = mcam_idx; 2191 2192 err = rvu_mbox_handler_npc_cn20k_mcam_write_entry(rvu, 2193 &cn20k_req, 2194 &rsp); 2195 if (err) { 2196 dev_err(rvu->dev, 2197 "%s: Installation of single drop on non hit rule at %d failed\n", 2198 __func__, mcam_idx); 2199 return err; 2200 } 2201 2202 goto enable_entry; 2203 } 2204 2205 req.intf = NIX_INTF_RX; 2206 req.set_cntr = true; 2207 req.cntr = cntr_rsp.cntr; 2208 req.entry = mcam_idx; 2209 2210 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &req, &rsp); 2211 if (err) { 2212 dev_err(rvu->dev, 2213 "%s: Installation of single drop on non hit rule at %d failed\n", 2214 __func__, mcam_idx); 2215 return err; 2216 } 2217 2218 dev_err(rvu->dev, 2219 "%s: Installed single drop on non hit rule at %d, cntr=%d\n", 2220 __func__, mcam_idx, req.cntr); 2221 2222 enable_entry: 2223 /* disable entry at Bank 0, index 0 */ 2224 npc_enable_mcam_entry(rvu, mcam, blkaddr, mcam_idx, false); 2225 2226 return 0; 2227 } 2228 2229 int rvu_mbox_handler_npc_get_field_status(struct rvu *rvu, 2230 struct npc_get_field_status_req *req, 2231 struct npc_get_field_status_rsp *rsp) 2232 { 2233 int blkaddr; 2234 2235 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2236 if (blkaddr < 0) 2237 return NPC_MCAM_INVALID_REQ; 2238 2239 if (!is_npc_interface_valid(rvu, req->intf)) 2240 return NPC_FLOW_INTF_INVALID; 2241 2242 if (npc_check_field(rvu, blkaddr, req->field, req->intf)) 2243 rsp->enable = 1; 2244 2245 return 0; 2246 } 2247