1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/vga_switcheroo.h>
30 #include <linux/mmu_notifier.h>
31 #include <linux/dynamic_debug.h>
32
33 #include <drm/drm_aperture.h>
34 #include <drm/drm_drv.h>
35 #include <drm/drm_fbdev_ttm.h>
36 #include <drm/drm_gem_ttm_helper.h>
37 #include <drm/drm_ioctl.h>
38 #include <drm/drm_vblank.h>
39
40 #include <core/gpuobj.h>
41 #include <core/option.h>
42 #include <core/pci.h>
43 #include <core/tegra.h>
44
45 #include <nvif/driver.h>
46 #include <nvif/fifo.h>
47 #include <nvif/push006c.h>
48 #include <nvif/user.h>
49
50 #include <nvif/class.h>
51 #include <nvif/cl0002.h>
52
53 #include "nouveau_drv.h"
54 #include "nouveau_dma.h"
55 #include "nouveau_ttm.h"
56 #include "nouveau_gem.h"
57 #include "nouveau_vga.h"
58 #include "nouveau_led.h"
59 #include "nouveau_hwmon.h"
60 #include "nouveau_acpi.h"
61 #include "nouveau_bios.h"
62 #include "nouveau_ioctl.h"
63 #include "nouveau_abi16.h"
64 #include "nouveau_fence.h"
65 #include "nouveau_debugfs.h"
66 #include "nouveau_connector.h"
67 #include "nouveau_platform.h"
68 #include "nouveau_svm.h"
69 #include "nouveau_dmem.h"
70 #include "nouveau_exec.h"
71 #include "nouveau_uvmm.h"
72 #include "nouveau_sched.h"
73
74 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
75 "DRM_UT_CORE",
76 "DRM_UT_DRIVER",
77 "DRM_UT_KMS",
78 "DRM_UT_PRIME",
79 "DRM_UT_ATOMIC",
80 "DRM_UT_VBL",
81 "DRM_UT_STATE",
82 "DRM_UT_LEASE",
83 "DRM_UT_DP",
84 "DRM_UT_DRMRES");
85
86 MODULE_PARM_DESC(config, "option string to pass to driver core");
87 static char *nouveau_config;
88 module_param_named(config, nouveau_config, charp, 0400);
89
90 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
91 static char *nouveau_debug;
92 module_param_named(debug, nouveau_debug, charp, 0400);
93
94 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
95 static int nouveau_noaccel = 0;
96 module_param_named(noaccel, nouveau_noaccel, int, 0400);
97
98 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
99 "0 = disabled, 1 = enabled, 2 = headless)");
100 int nouveau_modeset = -1;
101 module_param_named(modeset, nouveau_modeset, int, 0400);
102
103 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
104 static int nouveau_atomic = 0;
105 module_param_named(atomic, nouveau_atomic, int, 0400);
106
107 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
108 static int nouveau_runtime_pm = -1;
109 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
110
111 static struct drm_driver driver_stub;
112 static struct drm_driver driver_pci;
113 static struct drm_driver driver_platform;
114
115 static u64
nouveau_pci_name(struct pci_dev * pdev)116 nouveau_pci_name(struct pci_dev *pdev)
117 {
118 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
119 name |= pdev->bus->number << 16;
120 name |= PCI_SLOT(pdev->devfn) << 8;
121 return name | PCI_FUNC(pdev->devfn);
122 }
123
124 static u64
nouveau_platform_name(struct platform_device * platformdev)125 nouveau_platform_name(struct platform_device *platformdev)
126 {
127 return platformdev->id;
128 }
129
130 static u64
nouveau_name(struct drm_device * dev)131 nouveau_name(struct drm_device *dev)
132 {
133 if (dev_is_pci(dev->dev))
134 return nouveau_pci_name(to_pci_dev(dev->dev));
135 else
136 return nouveau_platform_name(to_platform_device(dev->dev));
137 }
138
139 static inline bool
nouveau_cli_work_ready(struct dma_fence * fence)140 nouveau_cli_work_ready(struct dma_fence *fence)
141 {
142 bool ret = true;
143
144 spin_lock_irq(fence->lock);
145 if (!dma_fence_is_signaled_locked(fence))
146 ret = false;
147 spin_unlock_irq(fence->lock);
148
149 if (ret == true)
150 dma_fence_put(fence);
151 return ret;
152 }
153
154 static void
nouveau_cli_work(struct work_struct * w)155 nouveau_cli_work(struct work_struct *w)
156 {
157 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
158 struct nouveau_cli_work *work, *wtmp;
159 mutex_lock(&cli->lock);
160 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
161 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
162 list_del(&work->head);
163 work->func(work);
164 }
165 }
166 mutex_unlock(&cli->lock);
167 }
168
169 static void
nouveau_cli_work_fence(struct dma_fence * fence,struct dma_fence_cb * cb)170 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
171 {
172 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
173 schedule_work(&work->cli->work);
174 }
175
176 void
nouveau_cli_work_queue(struct nouveau_cli * cli,struct dma_fence * fence,struct nouveau_cli_work * work)177 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
178 struct nouveau_cli_work *work)
179 {
180 work->fence = dma_fence_get(fence);
181 work->cli = cli;
182 mutex_lock(&cli->lock);
183 list_add_tail(&work->head, &cli->worker);
184 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
185 nouveau_cli_work_fence(fence, &work->cb);
186 mutex_unlock(&cli->lock);
187 }
188
189 static void
nouveau_cli_fini(struct nouveau_cli * cli)190 nouveau_cli_fini(struct nouveau_cli *cli)
191 {
192 struct nouveau_uvmm *uvmm = nouveau_cli_uvmm_locked(cli);
193
194 /* All our channels are dead now, which means all the fences they
195 * own are signalled, and all callback functions have been called.
196 *
197 * So, after flushing the workqueue, there should be nothing left.
198 */
199 flush_work(&cli->work);
200 WARN_ON(!list_empty(&cli->worker));
201
202 if (cli->sched)
203 nouveau_sched_destroy(&cli->sched);
204 if (uvmm)
205 nouveau_uvmm_fini(uvmm);
206 nouveau_vmm_fini(&cli->svm);
207 nouveau_vmm_fini(&cli->vmm);
208 nvif_mmu_dtor(&cli->mmu);
209 cli->device.object.map.ptr = NULL;
210 nvif_device_dtor(&cli->device);
211 mutex_lock(&cli->drm->client_mutex);
212 nvif_client_dtor(&cli->base);
213 mutex_unlock(&cli->drm->client_mutex);
214 }
215
216 static int
nouveau_cli_init(struct nouveau_drm * drm,const char * sname,struct nouveau_cli * cli)217 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
218 struct nouveau_cli *cli)
219 {
220 static const struct nvif_mclass
221 mems[] = {
222 { NVIF_CLASS_MEM_GF100, -1 },
223 { NVIF_CLASS_MEM_NV50 , -1 },
224 { NVIF_CLASS_MEM_NV04 , -1 },
225 {}
226 };
227 static const struct nvif_mclass
228 vmms[] = {
229 { NVIF_CLASS_VMM_GP100, -1 },
230 { NVIF_CLASS_VMM_GM200, -1 },
231 { NVIF_CLASS_VMM_GF100, -1 },
232 { NVIF_CLASS_VMM_NV50 , -1 },
233 { NVIF_CLASS_VMM_NV04 , -1 },
234 {}
235 };
236 int ret;
237
238 snprintf(cli->name, sizeof(cli->name), "%s", sname);
239 cli->drm = drm;
240 mutex_init(&cli->mutex);
241
242 INIT_WORK(&cli->work, nouveau_cli_work);
243 INIT_LIST_HEAD(&cli->worker);
244 mutex_init(&cli->lock);
245
246 mutex_lock(&drm->client_mutex);
247 ret = nvif_client_ctor(&drm->_client, cli->name, &cli->base);
248 mutex_unlock(&drm->client_mutex);
249 if (ret) {
250 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
251 goto done;
252 }
253
254 ret = nvif_device_ctor(&cli->base, "drmDevice", &cli->device);
255 if (ret) {
256 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
257 goto done;
258 }
259
260 cli->device.object.map.ptr = drm->device.object.map.ptr;
261
262 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", drm->mmu.object.oclass,
263 &cli->mmu);
264 if (ret) {
265 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
266 goto done;
267 }
268
269 ret = nvif_mclass(&cli->mmu.object, vmms);
270 if (ret < 0) {
271 NV_PRINTK(err, cli, "No supported VMM class\n");
272 goto done;
273 }
274
275 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
276 if (ret) {
277 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
278 goto done;
279 }
280
281 ret = nvif_mclass(&cli->mmu.object, mems);
282 if (ret < 0) {
283 NV_PRINTK(err, cli, "No supported MEM class\n");
284 goto done;
285 }
286
287 cli->mem = &mems[ret];
288
289 /* Don't pass in the (shared) sched_wq in order to let
290 * nouveau_sched_create() create a dedicated one for VM_BIND jobs.
291 *
292 * This is required to ensure that for VM_BIND jobs free_job() work and
293 * run_job() work can always run concurrently and hence, free_job() work
294 * can never stall run_job() work. For EXEC jobs we don't have this
295 * requirement, since EXEC job's free_job() does not require to take any
296 * locks which indirectly or directly are held for allocations
297 * elsewhere.
298 */
299 ret = nouveau_sched_create(&cli->sched, drm, NULL, 1);
300 if (ret)
301 goto done;
302
303 return 0;
304 done:
305 if (ret)
306 nouveau_cli_fini(cli);
307 return ret;
308 }
309
310 static void
nouveau_accel_ce_fini(struct nouveau_drm * drm)311 nouveau_accel_ce_fini(struct nouveau_drm *drm)
312 {
313 nouveau_channel_idle(drm->cechan);
314 nvif_object_dtor(&drm->ttm.copy);
315 nouveau_channel_del(&drm->cechan);
316 }
317
318 static void
nouveau_accel_ce_init(struct nouveau_drm * drm)319 nouveau_accel_ce_init(struct nouveau_drm *drm)
320 {
321 struct nvif_device *device = &drm->client.device;
322 u64 runm;
323 int ret = 0;
324
325 /* Allocate channel that has access to a (preferably async) copy
326 * engine, to use for TTM buffer moves.
327 */
328 runm = nvif_fifo_runlist_ce(device);
329 if (!runm) {
330 NV_DEBUG(drm, "no ce runlist\n");
331 return;
332 }
333
334 ret = nouveau_channel_new(&drm->client, true, runm, NvDmaFB, NvDmaTT, &drm->cechan);
335 if (ret)
336 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
337 }
338
339 static void
nouveau_accel_gr_fini(struct nouveau_drm * drm)340 nouveau_accel_gr_fini(struct nouveau_drm *drm)
341 {
342 nouveau_channel_idle(drm->channel);
343 nvif_object_dtor(&drm->ntfy);
344 nvkm_gpuobj_del(&drm->notify);
345 nouveau_channel_del(&drm->channel);
346 }
347
348 static void
nouveau_accel_gr_init(struct nouveau_drm * drm)349 nouveau_accel_gr_init(struct nouveau_drm *drm)
350 {
351 struct nvif_device *device = &drm->client.device;
352 u64 runm;
353 int ret;
354
355 /* Allocate channel that has access to the graphics engine. */
356 runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
357 if (!runm) {
358 NV_DEBUG(drm, "no gr runlist\n");
359 return;
360 }
361
362 ret = nouveau_channel_new(&drm->client, false, runm, NvDmaFB, NvDmaTT, &drm->channel);
363 if (ret) {
364 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
365 nouveau_accel_gr_fini(drm);
366 return;
367 }
368
369 /* A SW class is used on pre-NV50 HW to assist with handling the
370 * synchronisation of page flips, as well as to implement fences
371 * on TNT/TNT2 HW that lacks any kind of support in host.
372 */
373 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
374 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
375 NVDRM_NVSW, nouveau_abi16_swclass(drm),
376 NULL, 0, &drm->channel->nvsw);
377
378 if (ret == 0 && device->info.chipset >= 0x11) {
379 ret = nvif_object_ctor(&drm->channel->user, "drmBlit",
380 0x005f, 0x009f,
381 NULL, 0, &drm->channel->blit);
382 }
383
384 if (ret == 0) {
385 struct nvif_push *push = &drm->channel->chan.push;
386
387 ret = PUSH_WAIT(push, 8);
388 if (ret == 0) {
389 if (device->info.chipset >= 0x11) {
390 PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
391 PUSH_NVSQ(push, NV09F, 0x0120, 0,
392 0x0124, 1,
393 0x0128, 2);
394 }
395 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
396 }
397 }
398
399 if (ret) {
400 NV_ERROR(drm, "failed to allocate sw or blit class, %d\n", ret);
401 nouveau_accel_gr_fini(drm);
402 return;
403 }
404 }
405
406 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
407 * even if notification is never requested, so, allocate a ctxdma on
408 * any GPU where it's possible we'll end up using M2MF for BO moves.
409 */
410 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
411 ret = nvkm_gpuobj_new(nvxx_device(drm), 32, 0, false, NULL, &drm->notify);
412 if (ret) {
413 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
414 nouveau_accel_gr_fini(drm);
415 return;
416 }
417
418 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
419 NvNotify0, NV_DMA_IN_MEMORY,
420 &(struct nv_dma_v0) {
421 .target = NV_DMA_V0_TARGET_VRAM,
422 .access = NV_DMA_V0_ACCESS_RDWR,
423 .start = drm->notify->addr,
424 .limit = drm->notify->addr + 31
425 }, sizeof(struct nv_dma_v0),
426 &drm->ntfy);
427 if (ret) {
428 nouveau_accel_gr_fini(drm);
429 return;
430 }
431 }
432 }
433
434 static void
nouveau_accel_fini(struct nouveau_drm * drm)435 nouveau_accel_fini(struct nouveau_drm *drm)
436 {
437 nouveau_accel_ce_fini(drm);
438 nouveau_accel_gr_fini(drm);
439 if (drm->fence)
440 nouveau_fence(drm)->dtor(drm);
441 nouveau_channels_fini(drm);
442 }
443
444 static void
nouveau_accel_init(struct nouveau_drm * drm)445 nouveau_accel_init(struct nouveau_drm *drm)
446 {
447 struct nvif_device *device = &drm->client.device;
448 struct nvif_sclass *sclass;
449 int ret, i, n;
450
451 if (nouveau_noaccel)
452 return;
453
454 /* Initialise global support for channels, and synchronisation. */
455 ret = nouveau_channels_init(drm);
456 if (ret)
457 return;
458
459 /*XXX: this is crap, but the fence/channel stuff is a little
460 * backwards in some places. this will be fixed.
461 */
462 ret = n = nvif_object_sclass_get(&device->object, &sclass);
463 if (ret < 0)
464 return;
465
466 for (ret = -ENOSYS, i = 0; i < n; i++) {
467 switch (sclass[i].oclass) {
468 case NV03_CHANNEL_DMA:
469 ret = nv04_fence_create(drm);
470 break;
471 case NV10_CHANNEL_DMA:
472 ret = nv10_fence_create(drm);
473 break;
474 case NV17_CHANNEL_DMA:
475 case NV40_CHANNEL_DMA:
476 ret = nv17_fence_create(drm);
477 break;
478 case NV50_CHANNEL_GPFIFO:
479 ret = nv50_fence_create(drm);
480 break;
481 case G82_CHANNEL_GPFIFO:
482 ret = nv84_fence_create(drm);
483 break;
484 case FERMI_CHANNEL_GPFIFO:
485 case KEPLER_CHANNEL_GPFIFO_A:
486 case KEPLER_CHANNEL_GPFIFO_B:
487 case MAXWELL_CHANNEL_GPFIFO_A:
488 case PASCAL_CHANNEL_GPFIFO_A:
489 case VOLTA_CHANNEL_GPFIFO_A:
490 case TURING_CHANNEL_GPFIFO_A:
491 case AMPERE_CHANNEL_GPFIFO_A:
492 case AMPERE_CHANNEL_GPFIFO_B:
493 ret = nvc0_fence_create(drm);
494 break;
495 default:
496 break;
497 }
498 }
499
500 nvif_object_sclass_put(&sclass);
501 if (ret) {
502 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
503 nouveau_accel_fini(drm);
504 return;
505 }
506
507 /* Volta requires access to a doorbell register for kickoff. */
508 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
509 ret = nvif_user_ctor(device, "drmUsermode");
510 if (ret)
511 return;
512 }
513
514 /* Allocate channels we need to support various functions. */
515 nouveau_accel_gr_init(drm);
516 nouveau_accel_ce_init(drm);
517
518 /* Initialise accelerated TTM buffer moves. */
519 nouveau_bo_move_init(drm);
520 }
521
522 static void __printf(2, 3)
nouveau_drm_errorf(struct nvif_object * object,const char * fmt,...)523 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
524 {
525 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
526 struct va_format vaf;
527 va_list va;
528
529 va_start(va, fmt);
530 vaf.fmt = fmt;
531 vaf.va = &va;
532 NV_ERROR(drm, "%pV", &vaf);
533 va_end(va);
534 }
535
536 static void __printf(2, 3)
nouveau_drm_debugf(struct nvif_object * object,const char * fmt,...)537 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
538 {
539 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
540 struct va_format vaf;
541 va_list va;
542
543 va_start(va, fmt);
544 vaf.fmt = fmt;
545 vaf.va = &va;
546 NV_DEBUG(drm, "%pV", &vaf);
547 va_end(va);
548 }
549
550 static const struct nvif_parent_func
551 nouveau_parent = {
552 .debugf = nouveau_drm_debugf,
553 .errorf = nouveau_drm_errorf,
554 };
555
556 static void
nouveau_drm_device_fini(struct nouveau_drm * drm)557 nouveau_drm_device_fini(struct nouveau_drm *drm)
558 {
559 struct drm_device *dev = drm->dev;
560 struct nouveau_cli *cli, *temp_cli;
561
562 if (nouveau_pmops_runtime()) {
563 pm_runtime_get_sync(dev->dev);
564 pm_runtime_forbid(dev->dev);
565 }
566
567 nouveau_led_fini(dev);
568 nouveau_dmem_fini(drm);
569 nouveau_svm_fini(drm);
570 nouveau_hwmon_fini(dev);
571 nouveau_debugfs_fini(drm);
572
573 if (dev->mode_config.num_crtc)
574 nouveau_display_fini(dev, false, false);
575 nouveau_display_destroy(dev);
576
577 nouveau_accel_fini(drm);
578 nouveau_bios_takedown(dev);
579
580 nouveau_ttm_fini(drm);
581 nouveau_vga_fini(drm);
582
583 /*
584 * There may be existing clients from as-yet unclosed files. For now,
585 * clean them up here rather than deferring until the file is closed,
586 * but this likely not correct if we want to support hot-unplugging
587 * properly.
588 */
589 mutex_lock(&drm->clients_lock);
590 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
591 list_del(&cli->head);
592 mutex_lock(&cli->mutex);
593 if (cli->abi16)
594 nouveau_abi16_fini(cli->abi16);
595 mutex_unlock(&cli->mutex);
596 nouveau_cli_fini(cli);
597 kfree(cli);
598 }
599 mutex_unlock(&drm->clients_lock);
600
601 nouveau_cli_fini(&drm->client);
602 destroy_workqueue(drm->sched_wq);
603 mutex_destroy(&drm->clients_lock);
604 }
605
606 static int
nouveau_drm_device_init(struct nouveau_drm * drm)607 nouveau_drm_device_init(struct nouveau_drm *drm)
608 {
609 struct drm_device *dev = drm->dev;
610 int ret;
611
612 drm->sched_wq = alloc_workqueue("nouveau_sched_wq_shared", 0,
613 WQ_MAX_ACTIVE);
614 if (!drm->sched_wq)
615 return -ENOMEM;
616
617 ret = nouveau_cli_init(drm, "DRM", &drm->client);
618 if (ret)
619 goto fail_wq;
620
621 INIT_LIST_HEAD(&drm->clients);
622 mutex_init(&drm->clients_lock);
623 spin_lock_init(&drm->tile.lock);
624
625 /* workaround an odd issue on nvc1 by disabling the device's
626 * nosnoop capability. hopefully won't cause issues until a
627 * better fix is found - assuming there is one...
628 */
629 if (drm->client.device.info.chipset == 0xc1)
630 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
631
632 nouveau_vga_init(drm);
633
634 ret = nouveau_ttm_init(drm);
635 if (ret)
636 goto fail_ttm;
637
638 ret = nouveau_bios_init(dev);
639 if (ret)
640 goto fail_bios;
641
642 nouveau_accel_init(drm);
643
644 ret = nouveau_display_create(dev);
645 if (ret)
646 goto fail_dispctor;
647
648 if (dev->mode_config.num_crtc) {
649 ret = nouveau_display_init(dev, false, false);
650 if (ret)
651 goto fail_dispinit;
652 }
653
654 nouveau_debugfs_init(drm);
655 nouveau_hwmon_init(dev);
656 nouveau_svm_init(drm);
657 nouveau_dmem_init(drm);
658 nouveau_led_init(dev);
659
660 if (nouveau_pmops_runtime()) {
661 pm_runtime_use_autosuspend(dev->dev);
662 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
663 pm_runtime_set_active(dev->dev);
664 pm_runtime_allow(dev->dev);
665 pm_runtime_mark_last_busy(dev->dev);
666 pm_runtime_put(dev->dev);
667 }
668
669 ret = drm_dev_register(drm->dev, 0);
670 if (ret) {
671 nouveau_drm_device_fini(drm);
672 return ret;
673 }
674
675 return 0;
676 fail_dispinit:
677 nouveau_display_destroy(dev);
678 fail_dispctor:
679 nouveau_accel_fini(drm);
680 nouveau_bios_takedown(dev);
681 fail_bios:
682 nouveau_ttm_fini(drm);
683 fail_ttm:
684 nouveau_vga_fini(drm);
685 nouveau_cli_fini(&drm->client);
686 fail_wq:
687 destroy_workqueue(drm->sched_wq);
688 return ret;
689 }
690
691 static void
nouveau_drm_device_del(struct nouveau_drm * drm)692 nouveau_drm_device_del(struct nouveau_drm *drm)
693 {
694 if (drm->dev)
695 drm_dev_put(drm->dev);
696
697 nvif_mmu_dtor(&drm->mmu);
698 nvif_device_dtor(&drm->device);
699 nvif_client_dtor(&drm->_client);
700 nvif_parent_dtor(&drm->parent);
701
702 mutex_destroy(&drm->client_mutex);
703 kfree(drm);
704 }
705
706 static struct nouveau_drm *
nouveau_drm_device_new(const struct drm_driver * drm_driver,struct device * parent,struct nvkm_device * device)707 nouveau_drm_device_new(const struct drm_driver *drm_driver, struct device *parent,
708 struct nvkm_device *device)
709 {
710 static const struct nvif_mclass
711 mmus[] = {
712 { NVIF_CLASS_MMU_GF100, -1 },
713 { NVIF_CLASS_MMU_NV50 , -1 },
714 { NVIF_CLASS_MMU_NV04 , -1 },
715 {}
716 };
717 struct nouveau_drm *drm;
718 int ret;
719
720 drm = kzalloc(sizeof(*drm), GFP_KERNEL);
721 if (!drm)
722 return ERR_PTR(-ENOMEM);
723
724 drm->nvkm = device;
725
726 drm->dev = drm_dev_alloc(drm_driver, parent);
727 if (IS_ERR(drm->dev)) {
728 ret = PTR_ERR(drm->dev);
729 goto done;
730 }
731
732 drm->dev->dev_private = drm;
733 dev_set_drvdata(parent, drm);
734
735 nvif_parent_ctor(&nouveau_parent, &drm->parent);
736 mutex_init(&drm->client_mutex);
737 drm->_client.object.parent = &drm->parent;
738
739 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, "drm",
740 nouveau_name(drm->dev), &drm->_client);
741 if (ret)
742 goto done;
743
744 ret = nvif_device_ctor(&drm->_client, "drmDevice", &drm->device);
745 if (ret) {
746 NV_ERROR(drm, "Device allocation failed: %d\n", ret);
747 goto done;
748 }
749
750 ret = nvif_device_map(&drm->device);
751 if (ret) {
752 NV_ERROR(drm, "Failed to map PRI: %d\n", ret);
753 goto done;
754 }
755
756 ret = nvif_mclass(&drm->device.object, mmus);
757 if (ret < 0) {
758 NV_ERROR(drm, "No supported MMU class\n");
759 goto done;
760 }
761
762 ret = nvif_mmu_ctor(&drm->device.object, "drmMmu", mmus[ret].oclass, &drm->mmu);
763 if (ret) {
764 NV_ERROR(drm, "MMU allocation failed: %d\n", ret);
765 goto done;
766 }
767
768 done:
769 if (ret) {
770 nouveau_drm_device_del(drm);
771 drm = NULL;
772 }
773
774 return ret ? ERR_PTR(ret) : drm;
775 }
776
777 /*
778 * On some Intel PCIe bridge controllers doing a
779 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
780 * Skipping the intermediate D3hot step seems to make it work again. This is
781 * probably caused by not meeting the expectation the involved AML code has
782 * when the GPU is put into D3hot state before invoking it.
783 *
784 * This leads to various manifestations of this issue:
785 * - AML code execution to power on the GPU hits an infinite loop (as the
786 * code waits on device memory to change).
787 * - kernel crashes, as all PCI reads return -1, which most code isn't able
788 * to handle well enough.
789 *
790 * In all cases dmesg will contain at least one line like this:
791 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
792 * followed by a lot of nouveau timeouts.
793 *
794 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
795 * documented PCI config space register 0x248 of the Intel PCIe bridge
796 * controller (0x1901) in order to change the state of the PCIe link between
797 * the PCIe port and the GPU. There are alternative code paths using other
798 * registers, which seem to work fine (executed pre Windows 8):
799 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
800 * - 0xb0 bit 0x10 (link disable)
801 * Changing the conditions inside the firmware by poking into the relevant
802 * addresses does resolve the issue, but it seemed to be ACPI private memory
803 * and not any device accessible memory at all, so there is no portable way of
804 * changing the conditions.
805 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
806 *
807 * The only systems where this behavior can be seen are hybrid graphics laptops
808 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
809 * this issue only occurs in combination with listed Intel PCIe bridge
810 * controllers and the mentioned GPUs or other devices as well.
811 *
812 * documentation on the PCIe bridge controller can be found in the
813 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
814 * Section "12 PCI Express* Controller (x16) Registers"
815 */
816
quirk_broken_nv_runpm(struct pci_dev * pdev)817 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
818 {
819 struct nouveau_drm *drm = pci_get_drvdata(pdev);
820 struct pci_dev *bridge = pci_upstream_bridge(pdev);
821
822 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
823 return;
824
825 switch (bridge->device) {
826 case 0x1901:
827 drm->old_pm_cap = pdev->pm_cap;
828 pdev->pm_cap = 0;
829 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
830 break;
831 }
832 }
833
nouveau_drm_probe(struct pci_dev * pdev,const struct pci_device_id * pent)834 static int nouveau_drm_probe(struct pci_dev *pdev,
835 const struct pci_device_id *pent)
836 {
837 struct nvkm_device *device;
838 struct nouveau_drm *drm;
839 int ret;
840
841 if (vga_switcheroo_client_probe_defer(pdev))
842 return -EPROBE_DEFER;
843
844 /* We need to check that the chipset is supported before booting
845 * fbdev off the hardware, as there's no way to put it back.
846 */
847 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, &device);
848 if (ret)
849 return ret;
850
851 /* Remove conflicting drivers (vesafb, efifb etc). */
852 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver_pci);
853 if (ret)
854 return ret;
855
856 pci_set_master(pdev);
857
858 if (nouveau_atomic)
859 driver_pci.driver_features |= DRIVER_ATOMIC;
860
861 drm = nouveau_drm_device_new(&driver_pci, &pdev->dev, device);
862 if (IS_ERR(drm)) {
863 ret = PTR_ERR(drm);
864 goto fail_nvkm;
865 }
866
867 ret = pci_enable_device(pdev);
868 if (ret)
869 goto fail_drm;
870
871 ret = nouveau_drm_device_init(drm);
872 if (ret)
873 goto fail_pci;
874
875 if (drm->client.device.info.ram_size <= 32 * 1024 * 1024)
876 drm_fbdev_ttm_setup(drm->dev, 8);
877 else
878 drm_fbdev_ttm_setup(drm->dev, 32);
879
880 quirk_broken_nv_runpm(pdev);
881 return 0;
882
883 fail_pci:
884 pci_disable_device(pdev);
885 fail_drm:
886 nouveau_drm_device_del(drm);
887 fail_nvkm:
888 nvkm_device_del(&device);
889 return ret;
890 }
891
892 void
nouveau_drm_device_remove(struct nouveau_drm * drm)893 nouveau_drm_device_remove(struct nouveau_drm *drm)
894 {
895 struct nvkm_device *device = drm->nvkm;
896
897 drm_dev_unplug(drm->dev);
898
899 nouveau_drm_device_fini(drm);
900 nouveau_drm_device_del(drm);
901 nvkm_device_del(&device);
902 }
903
904 static void
nouveau_drm_remove(struct pci_dev * pdev)905 nouveau_drm_remove(struct pci_dev *pdev)
906 {
907 struct nouveau_drm *drm = pci_get_drvdata(pdev);
908
909 /* revert our workaround */
910 if (drm->old_pm_cap)
911 pdev->pm_cap = drm->old_pm_cap;
912 nouveau_drm_device_remove(drm);
913 pci_disable_device(pdev);
914 }
915
916 static int
nouveau_do_suspend(struct nouveau_drm * drm,bool runtime)917 nouveau_do_suspend(struct nouveau_drm *drm, bool runtime)
918 {
919 struct drm_device *dev = drm->dev;
920 struct ttm_resource_manager *man;
921 int ret;
922
923 nouveau_svm_suspend(drm);
924 nouveau_dmem_suspend(drm);
925 nouveau_led_suspend(dev);
926
927 if (dev->mode_config.num_crtc) {
928 NV_DEBUG(drm, "suspending display...\n");
929 ret = nouveau_display_suspend(dev, runtime);
930 if (ret)
931 return ret;
932 }
933
934 NV_DEBUG(drm, "evicting buffers...\n");
935
936 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM);
937 ttm_resource_manager_evict_all(&drm->ttm.bdev, man);
938
939 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
940 if (drm->cechan) {
941 ret = nouveau_channel_idle(drm->cechan);
942 if (ret)
943 goto fail_display;
944 }
945
946 if (drm->channel) {
947 ret = nouveau_channel_idle(drm->channel);
948 if (ret)
949 goto fail_display;
950 }
951
952 NV_DEBUG(drm, "suspending fence...\n");
953 if (drm->fence && nouveau_fence(drm)->suspend) {
954 if (!nouveau_fence(drm)->suspend(drm)) {
955 ret = -ENOMEM;
956 goto fail_display;
957 }
958 }
959
960 NV_DEBUG(drm, "suspending object tree...\n");
961 ret = nvif_client_suspend(&drm->_client);
962 if (ret)
963 goto fail_client;
964
965 return 0;
966
967 fail_client:
968 if (drm->fence && nouveau_fence(drm)->resume)
969 nouveau_fence(drm)->resume(drm);
970
971 fail_display:
972 if (dev->mode_config.num_crtc) {
973 NV_DEBUG(drm, "resuming display...\n");
974 nouveau_display_resume(dev, runtime);
975 }
976 return ret;
977 }
978
979 static int
nouveau_do_resume(struct nouveau_drm * drm,bool runtime)980 nouveau_do_resume(struct nouveau_drm *drm, bool runtime)
981 {
982 struct drm_device *dev = drm->dev;
983 int ret = 0;
984
985 NV_DEBUG(drm, "resuming object tree...\n");
986 ret = nvif_client_resume(&drm->_client);
987 if (ret) {
988 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
989 return ret;
990 }
991
992 NV_DEBUG(drm, "resuming fence...\n");
993 if (drm->fence && nouveau_fence(drm)->resume)
994 nouveau_fence(drm)->resume(drm);
995
996 nouveau_run_vbios_init(dev);
997
998 if (dev->mode_config.num_crtc) {
999 NV_DEBUG(drm, "resuming display...\n");
1000 nouveau_display_resume(dev, runtime);
1001 }
1002
1003 nouveau_led_resume(dev);
1004 nouveau_dmem_resume(drm);
1005 nouveau_svm_resume(drm);
1006 return 0;
1007 }
1008
1009 int
nouveau_pmops_suspend(struct device * dev)1010 nouveau_pmops_suspend(struct device *dev)
1011 {
1012 struct pci_dev *pdev = to_pci_dev(dev);
1013 struct nouveau_drm *drm = pci_get_drvdata(pdev);
1014 int ret;
1015
1016 if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1017 drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1018 return 0;
1019
1020 ret = nouveau_do_suspend(drm, false);
1021 if (ret)
1022 return ret;
1023
1024 pci_save_state(pdev);
1025 pci_disable_device(pdev);
1026 pci_set_power_state(pdev, PCI_D3hot);
1027 udelay(200);
1028 return 0;
1029 }
1030
1031 int
nouveau_pmops_resume(struct device * dev)1032 nouveau_pmops_resume(struct device *dev)
1033 {
1034 struct pci_dev *pdev = to_pci_dev(dev);
1035 struct nouveau_drm *drm = pci_get_drvdata(pdev);
1036 int ret;
1037
1038 if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1039 drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1040 return 0;
1041
1042 pci_set_power_state(pdev, PCI_D0);
1043 pci_restore_state(pdev);
1044 ret = pci_enable_device(pdev);
1045 if (ret)
1046 return ret;
1047 pci_set_master(pdev);
1048
1049 ret = nouveau_do_resume(drm, false);
1050
1051 /* Monitors may have been connected / disconnected during suspend */
1052 nouveau_display_hpd_resume(drm);
1053
1054 return ret;
1055 }
1056
1057 static int
nouveau_pmops_freeze(struct device * dev)1058 nouveau_pmops_freeze(struct device *dev)
1059 {
1060 struct nouveau_drm *drm = dev_get_drvdata(dev);
1061
1062 return nouveau_do_suspend(drm, false);
1063 }
1064
1065 static int
nouveau_pmops_thaw(struct device * dev)1066 nouveau_pmops_thaw(struct device *dev)
1067 {
1068 struct nouveau_drm *drm = dev_get_drvdata(dev);
1069
1070 return nouveau_do_resume(drm, false);
1071 }
1072
1073 bool
nouveau_pmops_runtime(void)1074 nouveau_pmops_runtime(void)
1075 {
1076 if (nouveau_runtime_pm == -1)
1077 return nouveau_is_optimus() || nouveau_is_v1_dsm();
1078 return nouveau_runtime_pm == 1;
1079 }
1080
1081 static int
nouveau_pmops_runtime_suspend(struct device * dev)1082 nouveau_pmops_runtime_suspend(struct device *dev)
1083 {
1084 struct pci_dev *pdev = to_pci_dev(dev);
1085 struct nouveau_drm *drm = pci_get_drvdata(pdev);
1086 int ret;
1087
1088 if (!nouveau_pmops_runtime()) {
1089 pm_runtime_forbid(dev);
1090 return -EBUSY;
1091 }
1092
1093 nouveau_switcheroo_optimus_dsm();
1094 ret = nouveau_do_suspend(drm, true);
1095 pci_save_state(pdev);
1096 pci_disable_device(pdev);
1097 pci_ignore_hotplug(pdev);
1098 pci_set_power_state(pdev, PCI_D3cold);
1099 drm->dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1100 return ret;
1101 }
1102
1103 static int
nouveau_pmops_runtime_resume(struct device * dev)1104 nouveau_pmops_runtime_resume(struct device *dev)
1105 {
1106 struct pci_dev *pdev = to_pci_dev(dev);
1107 struct nouveau_drm *drm = pci_get_drvdata(pdev);
1108 struct nvif_device *device = &drm->client.device;
1109 int ret;
1110
1111 if (!nouveau_pmops_runtime()) {
1112 pm_runtime_forbid(dev);
1113 return -EBUSY;
1114 }
1115
1116 pci_set_power_state(pdev, PCI_D0);
1117 pci_restore_state(pdev);
1118 ret = pci_enable_device(pdev);
1119 if (ret)
1120 return ret;
1121 pci_set_master(pdev);
1122
1123 ret = nouveau_do_resume(drm, true);
1124 if (ret) {
1125 NV_ERROR(drm, "resume failed with: %d\n", ret);
1126 return ret;
1127 }
1128
1129 /* do magic */
1130 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1131 drm->dev->switch_power_state = DRM_SWITCH_POWER_ON;
1132
1133 /* Monitors may have been connected / disconnected during suspend */
1134 nouveau_display_hpd_resume(drm);
1135
1136 return ret;
1137 }
1138
1139 static int
nouveau_pmops_runtime_idle(struct device * dev)1140 nouveau_pmops_runtime_idle(struct device *dev)
1141 {
1142 if (!nouveau_pmops_runtime()) {
1143 pm_runtime_forbid(dev);
1144 return -EBUSY;
1145 }
1146
1147 pm_runtime_mark_last_busy(dev);
1148 pm_runtime_autosuspend(dev);
1149 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1150 return 1;
1151 }
1152
1153 static int
nouveau_drm_open(struct drm_device * dev,struct drm_file * fpriv)1154 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1155 {
1156 struct nouveau_drm *drm = nouveau_drm(dev);
1157 struct nouveau_cli *cli;
1158 char name[32], tmpname[TASK_COMM_LEN];
1159 int ret;
1160
1161 /* need to bring up power immediately if opening device */
1162 ret = pm_runtime_get_sync(dev->dev);
1163 if (ret < 0 && ret != -EACCES) {
1164 pm_runtime_put_autosuspend(dev->dev);
1165 return ret;
1166 }
1167
1168 get_task_comm(tmpname, current);
1169 rcu_read_lock();
1170 snprintf(name, sizeof(name), "%s[%d]",
1171 tmpname, pid_nr(rcu_dereference(fpriv->pid)));
1172 rcu_read_unlock();
1173
1174 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1175 ret = -ENOMEM;
1176 goto done;
1177 }
1178
1179 ret = nouveau_cli_init(drm, name, cli);
1180 if (ret)
1181 goto done;
1182
1183 fpriv->driver_priv = cli;
1184
1185 mutex_lock(&drm->clients_lock);
1186 list_add(&cli->head, &drm->clients);
1187 mutex_unlock(&drm->clients_lock);
1188
1189 done:
1190 if (ret && cli) {
1191 nouveau_cli_fini(cli);
1192 kfree(cli);
1193 }
1194
1195 pm_runtime_mark_last_busy(dev->dev);
1196 pm_runtime_put_autosuspend(dev->dev);
1197 return ret;
1198 }
1199
1200 static void
nouveau_drm_postclose(struct drm_device * dev,struct drm_file * fpriv)1201 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1202 {
1203 struct nouveau_cli *cli = nouveau_cli(fpriv);
1204 struct nouveau_drm *drm = nouveau_drm(dev);
1205 int dev_index;
1206
1207 /*
1208 * The device is gone, and as it currently stands all clients are
1209 * cleaned up in the removal codepath. In the future this may change
1210 * so that we can support hot-unplugging, but for now we immediately
1211 * return to avoid a double-free situation.
1212 */
1213 if (!drm_dev_enter(dev, &dev_index))
1214 return;
1215
1216 pm_runtime_get_sync(dev->dev);
1217
1218 mutex_lock(&cli->mutex);
1219 if (cli->abi16)
1220 nouveau_abi16_fini(cli->abi16);
1221 mutex_unlock(&cli->mutex);
1222
1223 mutex_lock(&drm->clients_lock);
1224 list_del(&cli->head);
1225 mutex_unlock(&drm->clients_lock);
1226
1227 nouveau_cli_fini(cli);
1228 kfree(cli);
1229 pm_runtime_mark_last_busy(dev->dev);
1230 pm_runtime_put_autosuspend(dev->dev);
1231 drm_dev_exit(dev_index);
1232 }
1233
1234 static const struct drm_ioctl_desc
1235 nouveau_ioctls[] = {
1236 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1237 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1238 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1239 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1240 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1241 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1242 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1243 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1244 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1245 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1246 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1247 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1248 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1249 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1250 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_INIT, nouveau_uvmm_ioctl_vm_init, DRM_RENDER_ALLOW),
1251 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_BIND, nouveau_uvmm_ioctl_vm_bind, DRM_RENDER_ALLOW),
1252 DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW),
1253 };
1254
1255 long
nouveau_drm_ioctl(struct file * file,unsigned int cmd,unsigned long arg)1256 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1257 {
1258 struct drm_file *filp = file->private_data;
1259 struct drm_device *dev = filp->minor->dev;
1260 long ret;
1261
1262 ret = pm_runtime_get_sync(dev->dev);
1263 if (ret < 0 && ret != -EACCES) {
1264 pm_runtime_put_autosuspend(dev->dev);
1265 return ret;
1266 }
1267
1268 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1269 case DRM_NOUVEAU_NVIF:
1270 ret = nouveau_abi16_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1271 break;
1272 default:
1273 ret = drm_ioctl(file, cmd, arg);
1274 break;
1275 }
1276
1277 pm_runtime_mark_last_busy(dev->dev);
1278 pm_runtime_put_autosuspend(dev->dev);
1279 return ret;
1280 }
1281
1282 static const struct file_operations
1283 nouveau_driver_fops = {
1284 .owner = THIS_MODULE,
1285 .open = drm_open,
1286 .release = drm_release,
1287 .unlocked_ioctl = nouveau_drm_ioctl,
1288 .mmap = drm_gem_mmap,
1289 .poll = drm_poll,
1290 .read = drm_read,
1291 #if defined(CONFIG_COMPAT)
1292 .compat_ioctl = nouveau_compat_ioctl,
1293 #endif
1294 .llseek = noop_llseek,
1295 .fop_flags = FOP_UNSIGNED_OFFSET,
1296 };
1297
1298 static struct drm_driver
1299 driver_stub = {
1300 .driver_features = DRIVER_GEM |
1301 DRIVER_SYNCOBJ | DRIVER_SYNCOBJ_TIMELINE |
1302 DRIVER_GEM_GPUVA |
1303 DRIVER_MODESET |
1304 DRIVER_RENDER,
1305 .open = nouveau_drm_open,
1306 .postclose = nouveau_drm_postclose,
1307
1308 #if defined(CONFIG_DEBUG_FS)
1309 .debugfs_init = nouveau_drm_debugfs_init,
1310 #endif
1311
1312 .ioctls = nouveau_ioctls,
1313 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1314 .fops = &nouveau_driver_fops,
1315
1316 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1317
1318 .dumb_create = nouveau_display_dumb_create,
1319 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1320
1321 .name = DRIVER_NAME,
1322 .desc = DRIVER_DESC,
1323 #ifdef GIT_REVISION
1324 .date = GIT_REVISION,
1325 #else
1326 .date = DRIVER_DATE,
1327 #endif
1328 .major = DRIVER_MAJOR,
1329 .minor = DRIVER_MINOR,
1330 .patchlevel = DRIVER_PATCHLEVEL,
1331 };
1332
1333 static struct pci_device_id
1334 nouveau_drm_pci_table[] = {
1335 {
1336 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1337 .class = PCI_BASE_CLASS_DISPLAY << 16,
1338 .class_mask = 0xff << 16,
1339 },
1340 {
1341 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1342 .class = PCI_BASE_CLASS_DISPLAY << 16,
1343 .class_mask = 0xff << 16,
1344 },
1345 {}
1346 };
1347
nouveau_display_options(void)1348 static void nouveau_display_options(void)
1349 {
1350 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1351
1352 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1353 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1354 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1355 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1356 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1357 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1358 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1359 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1360 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1361 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1362 }
1363
1364 static const struct dev_pm_ops nouveau_pm_ops = {
1365 .suspend = nouveau_pmops_suspend,
1366 .resume = nouveau_pmops_resume,
1367 .freeze = nouveau_pmops_freeze,
1368 .thaw = nouveau_pmops_thaw,
1369 .poweroff = nouveau_pmops_freeze,
1370 .restore = nouveau_pmops_resume,
1371 .runtime_suspend = nouveau_pmops_runtime_suspend,
1372 .runtime_resume = nouveau_pmops_runtime_resume,
1373 .runtime_idle = nouveau_pmops_runtime_idle,
1374 };
1375
1376 static struct pci_driver
1377 nouveau_drm_pci_driver = {
1378 .name = "nouveau",
1379 .id_table = nouveau_drm_pci_table,
1380 .probe = nouveau_drm_probe,
1381 .remove = nouveau_drm_remove,
1382 .driver.pm = &nouveau_pm_ops,
1383 };
1384
1385 struct drm_device *
nouveau_platform_device_create(const struct nvkm_device_tegra_func * func,struct platform_device * pdev,struct nvkm_device ** pdevice)1386 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1387 struct platform_device *pdev,
1388 struct nvkm_device **pdevice)
1389 {
1390 struct nouveau_drm *drm;
1391 int err;
1392
1393 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, pdevice);
1394 if (err)
1395 goto err_free;
1396
1397 drm = nouveau_drm_device_new(&driver_platform, &pdev->dev, *pdevice);
1398 if (IS_ERR(drm)) {
1399 err = PTR_ERR(drm);
1400 goto err_free;
1401 }
1402
1403 err = nouveau_drm_device_init(drm);
1404 if (err)
1405 goto err_put;
1406
1407 return drm->dev;
1408
1409 err_put:
1410 nouveau_drm_device_del(drm);
1411 err_free:
1412 nvkm_device_del(pdevice);
1413
1414 return ERR_PTR(err);
1415 }
1416
1417 static int __init
nouveau_drm_init(void)1418 nouveau_drm_init(void)
1419 {
1420 driver_pci = driver_stub;
1421 driver_platform = driver_stub;
1422
1423 nouveau_display_options();
1424
1425 if (nouveau_modeset == -1) {
1426 if (drm_firmware_drivers_only())
1427 nouveau_modeset = 0;
1428 }
1429
1430 if (!nouveau_modeset)
1431 return 0;
1432
1433 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1434 platform_driver_register(&nouveau_platform_driver);
1435 #endif
1436
1437 nouveau_register_dsm_handler();
1438 nouveau_backlight_ctor();
1439
1440 #ifdef CONFIG_PCI
1441 return pci_register_driver(&nouveau_drm_pci_driver);
1442 #else
1443 return 0;
1444 #endif
1445 }
1446
1447 static void __exit
nouveau_drm_exit(void)1448 nouveau_drm_exit(void)
1449 {
1450 if (!nouveau_modeset)
1451 return;
1452
1453 #ifdef CONFIG_PCI
1454 pci_unregister_driver(&nouveau_drm_pci_driver);
1455 #endif
1456 nouveau_backlight_dtor();
1457 nouveau_unregister_dsm_handler();
1458
1459 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1460 platform_driver_unregister(&nouveau_platform_driver);
1461 #endif
1462 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1463 mmu_notifier_synchronize();
1464 }
1465
1466 module_init(nouveau_drm_init);
1467 module_exit(nouveau_drm_exit);
1468
1469 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1470 MODULE_AUTHOR(DRIVER_AUTHOR);
1471 MODULE_DESCRIPTION(DRIVER_DESC);
1472 MODULE_LICENSE("GPL and additional rights");
1473