1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2026 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV 20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 21 */ 22 enum iwl_dbg_tlv_type { 23 IWL_DBG_TLV_TYPE_DEBUG_INFO = 24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 25 IWL_DBG_TLV_TYPE_BUF_ALLOC, 26 IWL_DBG_TLV_TYPE_HCMD, 27 IWL_DBG_TLV_TYPE_REGION, 28 IWL_DBG_TLV_TYPE_TRIGGER, 29 IWL_DBG_TLV_TYPE_CONF_SET, 30 IWL_DBG_TLV_TYPE_NUM, 31 }; 32 33 /** 34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 35 * @min_ver: min version supported 36 * @max_ver: max version supported 37 */ 38 struct iwl_dbg_tlv_ver_data { 39 int min_ver; 40 int max_ver; 41 }; 42 43 /** 44 * struct iwl_dbg_tlv_timer_node - timer node struct 45 * @list: list of &struct iwl_dbg_tlv_timer_node 46 * @timer: timer 47 * @fwrt: &struct iwl_fw_runtime 48 * @tlv: TLV attach to the timer node 49 */ 50 struct iwl_dbg_tlv_timer_node { 51 struct list_head list; 52 struct timer_list timer; 53 struct iwl_fw_runtime *fwrt; 54 struct iwl_ucode_tlv *tlv; 55 }; 56 57 static const struct iwl_dbg_tlv_ver_data 58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,}, 63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, 65 }; 66 67 /* add a new TLV node, returning it so it can be modified */ 68 static struct iwl_ucode_tlv *iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 69 struct list_head *list) 70 { 71 u32 len = le32_to_cpu(tlv->length); 72 struct iwl_dbg_tlv_node *node; 73 74 node = kzalloc_flex(*node, tlv.data, len); 75 if (!node) 76 return NULL; 77 78 memcpy(&node->tlv, tlv, sizeof(node->tlv)); 79 memcpy(node->tlv.data, tlv->data, len); 80 list_add_tail(&node->list, list); 81 82 return &node->tlv; 83 } 84 85 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 86 { 87 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 88 u32 type = le32_to_cpu(tlv->type); 89 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 90 u32 ver = le32_to_cpu(hdr->version); 91 92 if (ver < dbg_ver_table[tlv_idx].min_ver || 93 ver > dbg_ver_table[tlv_idx].max_ver) 94 return false; 95 96 return true; 97 } 98 99 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 100 const struct iwl_ucode_tlv *tlv) 101 { 102 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 103 104 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 105 return -EINVAL; 106 107 /* we use this as a string, ensure input was NUL terminated */ 108 if (strnlen(debug_info->debug_cfg_name, 109 sizeof(debug_info->debug_cfg_name)) == 110 sizeof(debug_info->debug_cfg_name)) 111 return -EINVAL; 112 113 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 114 debug_info->debug_cfg_name); 115 116 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list)) 117 return -ENOMEM; 118 return 0; 119 } 120 121 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 122 const struct iwl_ucode_tlv *tlv) 123 { 124 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 125 u32 buf_location; 126 u32 alloc_id; 127 128 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 129 return -EINVAL; 130 131 buf_location = le32_to_cpu(alloc->buf_location); 132 alloc_id = le32_to_cpu(alloc->alloc_id); 133 134 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 135 buf_location >= IWL_FW_INI_LOCATION_NUM) 136 goto err; 137 138 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 139 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 140 goto err; 141 142 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 143 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 144 goto err; 145 146 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 147 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 148 goto err; 149 150 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH && 151 alloc->req_size == 0) { 152 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n"); 153 return -EINVAL; 154 } 155 156 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 157 158 return 0; 159 err: 160 IWL_ERR(trans, 161 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 162 alloc_id, buf_location); 163 return -EINVAL; 164 } 165 166 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 167 const struct iwl_ucode_tlv *tlv) 168 { 169 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 170 u32 tp; 171 172 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 173 return -EINVAL; 174 175 tp = le32_to_cpu(hcmd->time_point); 176 177 /* Host commands can not be sent in early time point since the FW 178 * is not ready 179 */ 180 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 181 tp >= IWL_FW_INI_TIME_POINT_NUM || 182 tp == IWL_FW_INI_TIME_POINT_EARLY) { 183 IWL_ERR(trans, 184 "WRT: Invalid time point %u for host command TLV\n", 185 tp); 186 return -EINVAL; 187 } 188 189 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list)) 190 return -ENOMEM; 191 return 0; 192 } 193 194 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 195 const struct iwl_ucode_tlv *tlv) 196 { 197 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 198 struct iwl_ucode_tlv **active_reg; 199 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 200 u32 id; 201 u8 type; 202 203 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 204 return -EINVAL; 205 206 id = le32_to_cpu(reg->id); 207 208 /* 209 * The higher part of the ID from version 2 is debug policy. 210 * The id will be only lsb 16 bits, so mask it out. 211 */ 212 if (le32_to_cpu(reg->hdr.version) >= 2) 213 id &= IWL_FW_INI_REGION_ID_MASK; 214 215 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ 216 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", 217 IWL_FW_INI_MAX_NAME, reg->name); 218 219 if (id >= IWL_FW_INI_MAX_REGION_ID) { 220 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 221 return -EINVAL; 222 } 223 224 type = reg->type; 225 226 if (type <= IWL_FW_INI_REGION_INVALID || 227 type >= IWL_FW_INI_REGION_NUM) { 228 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 229 return -EINVAL; 230 } 231 232 if (type == IWL_FW_INI_REGION_DRAM_BUFFER) { 233 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 234 235 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 236 alloc_id >= ARRAY_SIZE(trans->dbg.fw_mon_ini)) { 237 IWL_ERR(trans, 238 "WRT: Invalid dram_alloc_id %u for region %u\n", 239 alloc_id, id); 240 return -EINVAL; 241 } 242 } 243 244 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) { 245 trans->dbg.imr_data.sram_addr = 246 le32_to_cpu(reg->internal_buffer.base_addr); 247 trans->dbg.imr_data.sram_size = 248 le32_to_cpu(reg->internal_buffer.size); 249 } 250 251 252 active_reg = &trans->dbg.active_regions[id]; 253 if (*active_reg) { 254 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 255 256 kfree(*active_reg); 257 } 258 259 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 260 if (!*active_reg) 261 return -ENOMEM; 262 263 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 264 265 return 0; 266 } 267 268 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 269 const struct iwl_ucode_tlv *tlv) 270 { 271 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 272 u32 tp, rf; 273 struct iwl_ucode_tlv *new_tlv; 274 275 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 276 return -EINVAL; 277 278 tp = le32_to_cpu(trig->time_point); 279 280 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 281 tp >= IWL_FW_INI_TIME_POINT_NUM) { 282 IWL_ERR(trans, 283 "WRT: Invalid time point %u for trigger TLV\n", 284 tp); 285 return -EINVAL; 286 } 287 288 rf = le32_to_cpu(trig->reset_fw); 289 290 IWL_DEBUG_FW(trans, 291 "WRT: time point %u for trigger TLV with reset_fw %u\n", 292 tp, rf); 293 trans->dbg.last_tp_resetfw = 0xFF; 294 295 new_tlv = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 296 if (!new_tlv) 297 return -ENOMEM; 298 299 if (!le32_to_cpu(trig->occurrences)) { 300 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new_tlv->data; 301 302 new_trig->occurrences = cpu_to_le32(-1); 303 } 304 305 return 0; 306 } 307 308 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, 309 const struct iwl_ucode_tlv *tlv) 310 { 311 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data; 312 u32 tp, type; 313 314 if (le32_to_cpu(tlv->length) < sizeof(*conf_set)) 315 return -EINVAL; 316 317 tp = le32_to_cpu(conf_set->time_point); 318 type = le32_to_cpu(conf_set->set_type); 319 320 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 321 tp >= IWL_FW_INI_TIME_POINT_NUM) { 322 IWL_DEBUG_FW(trans, 323 "WRT: Invalid time point %u for config set TLV\n", tp); 324 return -EINVAL; 325 } 326 327 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || 328 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { 329 IWL_DEBUG_FW(trans, 330 "WRT: Invalid config set type %u for config set TLV\n", type); 331 return -EINVAL; 332 } 333 334 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list)) 335 return -ENOMEM; 336 return 0; 337 } 338 339 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 340 const struct iwl_ucode_tlv *tlv) = { 341 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 342 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 343 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 344 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 345 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 346 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, 347 }; 348 349 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 350 bool ext) 351 { 352 enum iwl_ini_cfg_state *cfg_state = ext ? 353 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 354 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 355 u32 type; 356 u32 tlv_idx; 357 u32 domain; 358 int ret; 359 360 if (le32_to_cpu(tlv->length) < sizeof(*hdr)) 361 return; 362 363 type = le32_to_cpu(tlv->type); 364 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 365 domain = le32_to_cpu(hdr->domain); 366 367 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 368 !(domain & trans->dbg.domains_bitmap)) { 369 IWL_DEBUG_FW(trans, 370 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 371 domain, trans->dbg.domains_bitmap); 372 return; 373 } 374 375 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 376 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 377 goto out_err; 378 } 379 380 if (!iwl_dbg_tlv_ver_support(tlv)) { 381 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 382 le32_to_cpu(hdr->version)); 383 goto out_err; 384 } 385 386 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 387 if (ret) { 388 IWL_WARN(trans, 389 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 390 type, ret, ext); 391 goto out_err; 392 } 393 394 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 395 *cfg_state = IWL_INI_CFG_STATE_LOADED; 396 397 return; 398 399 out_err: 400 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 401 } 402 403 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 404 { 405 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 406 struct iwl_dbg_tlv_timer_node *node, *tmp; 407 408 list_for_each_entry_safe(node, tmp, timer_list, list) { 409 timer_shutdown_sync(&node->timer); 410 list_del(&node->list); 411 kfree(node); 412 } 413 } 414 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 415 416 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 417 enum iwl_fw_ini_allocation_id alloc_id) 418 { 419 struct iwl_fw_mon *fw_mon; 420 int i; 421 422 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 423 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 424 return; 425 426 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 427 428 for (i = 0; i < fw_mon->num_frags; i++) { 429 struct iwl_dram_data *frag = &fw_mon->frags[i]; 430 431 dma_free_coherent(trans->dev, frag->size, frag->block, 432 frag->physical); 433 434 frag->physical = 0; 435 frag->block = NULL; 436 frag->size = 0; 437 } 438 439 kfree(fw_mon->frags); 440 fw_mon->frags = NULL; 441 fw_mon->num_frags = 0; 442 } 443 444 void iwl_dbg_tlv_free(struct iwl_trans *trans) 445 { 446 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 447 int i; 448 449 iwl_dbg_tlv_del_timers(trans); 450 451 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 452 struct iwl_ucode_tlv **active_reg = 453 &trans->dbg.active_regions[i]; 454 455 kfree(*active_reg); 456 *active_reg = NULL; 457 } 458 459 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 460 &trans->dbg.debug_info_tlv_list, list) { 461 list_del(&tlv_node->list); 462 kfree(tlv_node); 463 } 464 465 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 466 struct iwl_dbg_tlv_time_point_data *tp = 467 &trans->dbg.time_point[i]; 468 469 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 470 list) { 471 list_del(&tlv_node->list); 472 kfree(tlv_node); 473 } 474 475 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 476 list) { 477 list_del(&tlv_node->list); 478 kfree(tlv_node); 479 } 480 481 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 482 &tp->active_trig_list, list) { 483 list_del(&tlv_node->list); 484 kfree(tlv_node); 485 } 486 487 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 488 &tp->config_list, list) { 489 list_del(&tlv_node->list); 490 kfree(tlv_node); 491 } 492 493 } 494 495 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 496 iwl_dbg_tlv_fragments_free(trans, i); 497 } 498 499 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 500 size_t len) 501 { 502 const struct iwl_ucode_tlv *tlv; 503 u32 tlv_len; 504 size_t aligned_tlv_len; 505 506 while (len >= sizeof(*tlv)) { 507 len -= sizeof(*tlv); 508 tlv = (const void *)data; 509 510 tlv_len = le32_to_cpu(tlv->length); 511 512 if (len < tlv_len) { 513 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 514 len, tlv_len); 515 return -EINVAL; 516 } 517 518 aligned_tlv_len = ALIGN(tlv_len, 4); 519 if (len < aligned_tlv_len) { 520 IWL_ERR(trans, "invalid aligned TLV len: %zd/%zu\n", 521 len, aligned_tlv_len); 522 return -EINVAL; 523 } 524 525 len -= aligned_tlv_len; 526 data += sizeof(*tlv) + aligned_tlv_len; 527 528 iwl_dbg_tlv_alloc(trans, tlv, true); 529 } 530 531 return 0; 532 } 533 534 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 535 { 536 const struct firmware *fw; 537 const char *yoyo_bin = "iwl-debug-yoyo.bin"; 538 int res; 539 540 if (!iwlwifi_mod_params.enable_ini || 541 trans->mac_cfg->device_family <= IWL_DEVICE_FAMILY_8000) 542 return; 543 544 res = firmware_request_nowarn(&fw, yoyo_bin, dev); 545 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); 546 547 if (res) 548 return; 549 550 trans->dbg.yoyo_bin_loaded = true; 551 552 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 553 554 release_firmware(fw); 555 } 556 557 void iwl_dbg_tlv_init(struct iwl_trans *trans) 558 { 559 int i; 560 561 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 562 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 563 564 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 565 struct iwl_dbg_tlv_time_point_data *tp = 566 &trans->dbg.time_point[i]; 567 568 INIT_LIST_HEAD(&tp->trig_list); 569 INIT_LIST_HEAD(&tp->hcmd_list); 570 INIT_LIST_HEAD(&tp->active_trig_list); 571 INIT_LIST_HEAD(&tp->config_list); 572 } 573 } 574 575 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 576 struct iwl_dram_data *frag, u32 pages) 577 { 578 void *block = NULL; 579 dma_addr_t physical; 580 581 if (!frag || frag->size || !pages) 582 return -EIO; 583 584 /* 585 * We try to allocate as many pages as we can, starting with 586 * the requested amount and going down until we can allocate 587 * something. Because of DIV_ROUND_UP(), pages will never go 588 * down to 0 and stop the loop, so stop when pages reaches 1, 589 * which is too small anyway. 590 */ 591 while (pages > 1) { 592 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 593 &physical, 594 GFP_KERNEL | __GFP_NOWARN); 595 if (block) 596 break; 597 598 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 599 pages * PAGE_SIZE); 600 601 pages = DIV_ROUND_UP(pages, 2); 602 } 603 604 if (!block) 605 return -ENOMEM; 606 607 frag->physical = physical; 608 frag->block = block; 609 frag->size = pages * PAGE_SIZE; 610 611 return pages; 612 } 613 614 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 615 enum iwl_fw_ini_allocation_id alloc_id) 616 { 617 struct iwl_fw_mon *fw_mon; 618 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 619 u32 num_frags, remain_pages, frag_pages; 620 int i; 621 622 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 623 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 624 return -EIO; 625 626 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 627 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 628 629 if (fw_mon->num_frags) { 630 for (i = 0; i < fw_mon->num_frags; i++) 631 memset(fw_mon->frags[i].block, 0, 632 fw_mon->frags[i].size); 633 return 0; 634 } 635 636 if (fw_mon_cfg->buf_location != 637 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 638 return 0; 639 640 if (!fw_mon_cfg->req_size) 641 return -EIO; 642 643 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 644 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 645 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 646 return -EIO; 647 num_frags = 1; 648 } else if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ && 649 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) { 650 return -EIO; 651 } 652 653 if (!num_frags) 654 return -EIO; 655 656 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 657 PAGE_SIZE); 658 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 659 num_frags = min_t(u32, num_frags, remain_pages); 660 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 661 662 fw_mon->frags = kzalloc_objs(*fw_mon->frags, num_frags); 663 if (!fw_mon->frags) 664 return -ENOMEM; 665 666 for (i = 0; i < num_frags; i++) { 667 int pages = min_t(u32, frag_pages, remain_pages); 668 669 IWL_DEBUG_FW(fwrt, 670 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 671 alloc_id, i, pages * PAGE_SIZE); 672 673 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 674 pages); 675 if (pages < 0) { 676 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 677 (remain_pages * PAGE_SIZE); 678 679 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 680 iwl_dbg_tlv_fragments_free(fwrt->trans, 681 alloc_id); 682 return pages; 683 } 684 break; 685 } 686 687 remain_pages -= pages; 688 fw_mon->num_frags++; 689 } 690 691 return 0; 692 } 693 694 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 695 enum iwl_fw_ini_allocation_id alloc_id) 696 { 697 struct iwl_fw_mon *fw_mon; 698 u32 remain_frags, num_commands; 699 int i, fw_mon_idx = 0; 700 701 if (!fw_has_capa(&fwrt->fw->ucode_capa, 702 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 703 return 0; 704 705 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 706 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 707 return -EIO; 708 709 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 710 IWL_FW_INI_LOCATION_DRAM_PATH) 711 return 0; 712 713 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 714 715 /* the first fragment of DBGC1 is given to the FW via register 716 * or context info 717 */ 718 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 719 fw_mon_idx++; 720 721 remain_frags = fw_mon->num_frags - fw_mon_idx; 722 if (!remain_frags) 723 return 0; 724 725 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 726 727 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 728 alloc_id); 729 730 for (i = 0; i < num_commands; i++) { 731 u32 num_frags = min_t(u32, remain_frags, 732 BUF_ALLOC_MAX_NUM_FRAGS); 733 struct iwl_buf_alloc_cmd data = { 734 .alloc_id = cpu_to_le32(alloc_id), 735 .num_frags = cpu_to_le32(num_frags), 736 .buf_location = 737 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 738 }; 739 struct iwl_host_cmd hcmd = { 740 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 741 .data[0] = &data, 742 .len[0] = sizeof(data), 743 .flags = CMD_SEND_IN_RFKILL, 744 }; 745 int ret, j; 746 747 for (j = 0; j < num_frags; j++) { 748 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 749 struct iwl_dram_data *fw_mon_frag = 750 &fw_mon->frags[fw_mon_idx++]; 751 752 frag->addr = cpu_to_le64(fw_mon_frag->physical); 753 frag->size = cpu_to_le32(fw_mon_frag->size); 754 } 755 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 756 if (ret) 757 return ret; 758 759 remain_frags -= num_frags; 760 } 761 762 return 0; 763 } 764 765 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 766 { 767 int ret, i; 768 769 if (fw_has_capa(&fwrt->fw->ucode_capa, 770 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 771 return; 772 773 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 774 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 775 if (ret) 776 IWL_WARN(fwrt, 777 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 778 i, ret); 779 } 780 } 781 782 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, 783 enum iwl_fw_ini_allocation_id alloc_id, 784 struct iwl_dram_info *dram_info) 785 { 786 struct iwl_fw_mon *fw_mon; 787 u32 remain_frags, num_frags; 788 int j, fw_mon_idx = 0; 789 struct iwl_buf_alloc_cmd *data; 790 791 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 792 IWL_FW_INI_LOCATION_DRAM_PATH) { 793 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n", 794 alloc_id); 795 return -1; 796 } 797 798 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 799 800 /* the first fragment of DBGC1 is given to the FW via register 801 * or context info 802 */ 803 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 804 fw_mon_idx++; 805 806 remain_frags = fw_mon->num_frags - fw_mon_idx; 807 if (!remain_frags) 808 return -1; 809 810 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 811 data = &dram_info->dram_frags[alloc_id - 1]; 812 data->alloc_id = cpu_to_le32(alloc_id); 813 data->num_frags = cpu_to_le32(num_frags); 814 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); 815 816 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", 817 cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); 818 819 for (j = 0; j < num_frags; j++) { 820 struct iwl_buf_alloc_frag *frag = &data->frags[j]; 821 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; 822 823 frag->addr = cpu_to_le64(fw_mon_frag->physical); 824 frag->size = cpu_to_le32(fw_mon_frag->size); 825 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); 826 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", 827 j, cpu_to_le64(fw_mon_frag->physical), 828 cpu_to_le32(fw_mon_frag->size)); 829 } 830 return 0; 831 } 832 833 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) 834 { 835 int ret, i; 836 bool dram_alloc = false; 837 struct iwl_dram_data *frags = 838 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; 839 struct iwl_dram_info *dram_info; 840 841 if (!frags || !frags->block) 842 return; 843 844 dram_info = frags->block; 845 846 if (!fw_has_capa(&fwrt->fw->ucode_capa, 847 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 848 return; 849 850 memset(dram_info, 0, sizeof(*dram_info)); 851 852 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; 853 i < IWL_FW_INI_ALLOCATION_NUM; i++) { 854 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location == 855 IWL_FW_INI_LOCATION_INVALID) 856 continue; 857 858 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); 859 if (!ret) 860 dram_alloc = true; 861 else 862 IWL_INFO(fwrt, 863 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", 864 i, ret); 865 } 866 867 if (dram_alloc) { 868 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); 869 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); 870 } 871 } 872 873 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 874 struct list_head *hcmd_list) 875 { 876 struct iwl_dbg_tlv_node *node; 877 878 list_for_each_entry(node, hcmd_list, list) { 879 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 880 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 881 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 882 struct iwl_host_cmd cmd = { 883 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 884 .len = { hcmd_len, }, 885 .data = { hcmd_data->data, }, 886 }; 887 888 iwl_trans_send_cmd(fwrt->trans, &cmd); 889 } 890 } 891 892 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, 893 struct list_head *conf_list) 894 { 895 struct iwl_dbg_tlv_node *node; 896 897 list_for_each_entry(node, conf_list, list) { 898 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; 899 u32 count, address, value; 900 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; 901 u32 type = le32_to_cpu(config_list->set_type); 902 u32 offset = le32_to_cpu(config_list->addr_offset); 903 904 switch (type) { 905 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { 906 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 907 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); 908 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); 909 continue; 910 } 911 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); 912 for (count = 0; count < len; count++) { 913 address = le32_to_cpu(config_list->addr_val[count].address); 914 value = le32_to_cpu(config_list->addr_val[count].value); 915 iwl_trans_write_prph_no_grab(fwrt->trans, address + offset, value); 916 } 917 iwl_trans_release_nic_access(fwrt->trans); 918 break; 919 } 920 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { 921 for (count = 0; count < len; count++) { 922 address = le32_to_cpu(config_list->addr_val[count].address); 923 value = le32_to_cpu(config_list->addr_val[count].value); 924 iwl_trans_write_mem32(fwrt->trans, address + offset, value); 925 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", 926 count, address, value); 927 } 928 break; 929 } 930 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { 931 for (count = 0; count < len; count++) { 932 address = le32_to_cpu(config_list->addr_val[count].address); 933 value = le32_to_cpu(config_list->addr_val[count].value); 934 iwl_trans_write32(fwrt->trans, address + offset, value); 935 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", 936 count, address, value); 937 } 938 break; 939 } 940 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { 941 struct iwl_dbgc1_info dram_info = {}; 942 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; 943 __le64 dram_base_addr; 944 __le32 dram_size; 945 u64 dram_addr; 946 u32 ret; 947 948 if (!frags) 949 break; 950 951 dram_base_addr = cpu_to_le64(frags->physical); 952 dram_size = cpu_to_le32(frags->size); 953 dram_addr = le64_to_cpu(dram_base_addr); 954 955 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", 956 dram_base_addr, dram_size); 957 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", 958 le32_to_cpu(config_list->addr_offset)); 959 for (count = 0; count < len; count++) { 960 address = le32_to_cpu(config_list->addr_val[count].address); 961 dram_info.dbgc1_add_lsb = 962 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); 963 dram_info.dbgc1_add_msb = 964 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); 965 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); 966 ret = iwl_trans_write_mem(fwrt->trans, 967 address + offset, &dram_info, 4); 968 if (ret) { 969 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); 970 break; 971 } 972 } 973 break; 974 } 975 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { 976 u32 debug_token_config = 977 le32_to_cpu(config_list->addr_val[0].value); 978 979 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", 980 debug_token_config); 981 fwrt->trans->dbg.ucode_preset = debug_token_config; 982 break; 983 } 984 default: 985 break; 986 } 987 } 988 } 989 990 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 991 { 992 struct iwl_dbg_tlv_timer_node *timer_node = 993 timer_container_of(timer_node, t, timer); 994 struct iwl_fwrt_dump_data dump_data = { 995 .trig = (void *)timer_node->tlv->data, 996 }; 997 int ret; 998 999 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); 1000 if (!ret || ret == -EBUSY) { 1001 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 1002 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 1003 1004 if (!occur) 1005 return; 1006 1007 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 1008 } 1009 } 1010 1011 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 1012 { 1013 struct iwl_dbg_tlv_node *node; 1014 struct list_head *trig_list = 1015 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 1016 1017 list_for_each_entry(node, trig_list, list) { 1018 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 1019 struct iwl_dbg_tlv_timer_node *timer_node; 1020 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 1021 u32 min_interval = 100; 1022 1023 if (!occur) 1024 continue; 1025 1026 /* make sure there is at least one dword of data for the 1027 * interval value 1028 */ 1029 if (le32_to_cpu(node->tlv.length) < 1030 sizeof(*trig) + sizeof(__le32)) { 1031 IWL_ERR(fwrt, 1032 "WRT: Invalid periodic trigger data was not given\n"); 1033 continue; 1034 } 1035 1036 if (le32_to_cpu(trig->data[0]) < min_interval) { 1037 IWL_WARN(fwrt, 1038 "WRT: Override min interval from %u to %u msec\n", 1039 le32_to_cpu(trig->data[0]), min_interval); 1040 trig->data[0] = cpu_to_le32(min_interval); 1041 } 1042 1043 collect_interval = le32_to_cpu(trig->data[0]); 1044 1045 timer_node = kzalloc_obj(*timer_node); 1046 if (!timer_node) { 1047 IWL_ERR(fwrt, 1048 "WRT: Failed to allocate periodic trigger\n"); 1049 continue; 1050 } 1051 1052 timer_node->fwrt = fwrt; 1053 timer_node->tlv = &node->tlv; 1054 timer_setup(&timer_node->timer, 1055 iwl_dbg_tlv_periodic_trig_handler, 0); 1056 1057 list_add_tail(&timer_node->list, 1058 &fwrt->trans->dbg.periodic_trig_list); 1059 1060 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 1061 1062 mod_timer(&timer_node->timer, 1063 jiffies + msecs_to_jiffies(collect_interval)); 1064 } 1065 } 1066 1067 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 1068 const struct iwl_ucode_tlv *old) 1069 { 1070 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 1071 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 1072 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 1073 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 1074 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 1075 int i, j; 1076 1077 for (i = 0; i < new_dwords_num; i++) { 1078 bool match = false; 1079 1080 for (j = 0; j < old_dwords_num; j++) { 1081 if (new_data[i] == old_data[j]) { 1082 match = true; 1083 break; 1084 } 1085 } 1086 if (!match) 1087 return false; 1088 } 1089 1090 return true; 1091 } 1092 1093 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 1094 struct iwl_ucode_tlv *trig_tlv, 1095 struct iwl_dbg_tlv_node *node) 1096 { 1097 struct iwl_ucode_tlv *node_tlv = &node->tlv; 1098 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 1099 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1100 u32 policy = le32_to_cpu(trig->apply_policy); 1101 u32 size = le32_to_cpu(trig_tlv->length); 1102 u32 trig_data_len = size - sizeof(*trig); 1103 u32 offset = 0; 1104 1105 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 1106 u32 data_len = le32_to_cpu(node_tlv->length) - 1107 sizeof(*node_trig); 1108 1109 IWL_DEBUG_FW(fwrt, 1110 "WRT: Appending trigger data (time point %u)\n", 1111 le32_to_cpu(trig->time_point)); 1112 1113 offset += data_len; 1114 size += data_len; 1115 } else { 1116 IWL_DEBUG_FW(fwrt, 1117 "WRT: Overriding trigger data (time point %u)\n", 1118 le32_to_cpu(trig->time_point)); 1119 } 1120 1121 if (size != le32_to_cpu(node_tlv->length)) { 1122 struct list_head *prev = node->list.prev; 1123 struct iwl_dbg_tlv_node *tmp; 1124 1125 list_del(&node->list); 1126 1127 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 1128 if (!tmp) { 1129 IWL_WARN(fwrt, 1130 "WRT: No memory to override trigger (time point %u)\n", 1131 le32_to_cpu(trig->time_point)); 1132 1133 list_add(&node->list, prev); 1134 1135 return -ENOMEM; 1136 } 1137 1138 list_add(&tmp->list, prev); 1139 node_tlv = &tmp->tlv; 1140 node_trig = (void *)node_tlv->data; 1141 } 1142 1143 memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len); 1144 node_tlv->length = cpu_to_le32(size); 1145 1146 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 1147 IWL_DEBUG_FW(fwrt, 1148 "WRT: Overriding trigger configuration (time point %u)\n", 1149 le32_to_cpu(trig->time_point)); 1150 1151 /* the first 11 dwords are configuration related */ 1152 memcpy(node_trig, trig, sizeof(__le32) * 11); 1153 } 1154 1155 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 1156 IWL_DEBUG_FW(fwrt, 1157 "WRT: Overriding trigger regions (time point %u)\n", 1158 le32_to_cpu(trig->time_point)); 1159 1160 node_trig->regions_mask = trig->regions_mask; 1161 } else { 1162 IWL_DEBUG_FW(fwrt, 1163 "WRT: Appending trigger regions (time point %u)\n", 1164 le32_to_cpu(trig->time_point)); 1165 1166 node_trig->regions_mask |= trig->regions_mask; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int 1173 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 1174 struct list_head *trig_list, 1175 struct iwl_ucode_tlv *trig_tlv) 1176 { 1177 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1178 struct iwl_dbg_tlv_node *node, *match = NULL; 1179 u32 policy = le32_to_cpu(trig->apply_policy); 1180 1181 list_for_each_entry(node, trig_list, list) { 1182 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 1183 break; 1184 1185 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 1186 is_trig_data_contained(trig_tlv, &node->tlv)) { 1187 match = node; 1188 break; 1189 } 1190 } 1191 1192 if (!match) { 1193 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 1194 le32_to_cpu(trig->time_point)); 1195 if (!iwl_dbg_tlv_add(trig_tlv, trig_list)) 1196 return -ENOMEM; 1197 return 0; 1198 } 1199 1200 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 1201 } 1202 1203 static void 1204 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 1205 struct iwl_dbg_tlv_time_point_data *tp) 1206 { 1207 struct iwl_dbg_tlv_node *node; 1208 struct list_head *trig_list = &tp->trig_list; 1209 struct list_head *active_trig_list = &tp->active_trig_list; 1210 1211 list_for_each_entry(node, trig_list, list) { 1212 struct iwl_ucode_tlv *tlv = &node->tlv; 1213 1214 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 1215 } 1216 } 1217 1218 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 1219 struct iwl_fwrt_dump_data *dump_data, 1220 union iwl_dbg_tlv_tp_data *tp_data, 1221 u32 trig_data) 1222 { 1223 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 1224 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 1225 1226 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 1227 pkt->hdr.group_id == wanted_hdr->group_id)) { 1228 struct iwl_rx_packet *fw_pkt = 1229 kmemdup(pkt, 1230 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 1231 GFP_ATOMIC); 1232 1233 if (!fw_pkt) 1234 return false; 1235 1236 dump_data->fw_pkt = fw_pkt; 1237 1238 return true; 1239 } 1240 1241 return false; 1242 } 1243 1244 static int 1245 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, 1246 struct list_head *active_trig_list, 1247 union iwl_dbg_tlv_tp_data *tp_data, 1248 bool (*data_check)(struct iwl_fw_runtime *fwrt, 1249 struct iwl_fwrt_dump_data *dump_data, 1250 union iwl_dbg_tlv_tp_data *tp_data, 1251 u32 trig_data)) 1252 { 1253 struct iwl_dbg_tlv_node *node; 1254 1255 list_for_each_entry(node, active_trig_list, list) { 1256 struct iwl_fwrt_dump_data dump_data = { 1257 .trig = (void *)node->tlv.data, 1258 }; 1259 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 1260 data); 1261 int ret, i; 1262 u32 tp = le32_to_cpu(dump_data.trig->time_point); 1263 1264 1265 if (!num_data) { 1266 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1267 if (ret) 1268 return ret; 1269 } 1270 1271 for (i = 0; i < num_data; i++) { 1272 if (!data_check || 1273 data_check(fwrt, &dump_data, tp_data, 1274 le32_to_cpu(dump_data.trig->data[i]))) { 1275 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1276 if (ret) 1277 return ret; 1278 1279 break; 1280 } 1281 } 1282 1283 fwrt->trans->dbg.restart_required = false; 1284 1285 if (fwrt->trans->mac_cfg->device_family == 1286 IWL_DEVICE_FAMILY_9000) { 1287 fwrt->trans->dbg.restart_required = true; 1288 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT && 1289 fwrt->trans->dbg.last_tp_resetfw == 1290 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1291 fwrt->trans->dbg.restart_required = false; 1292 fwrt->trans->dbg.last_tp_resetfw = 0xFF; 1293 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1294 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) { 1295 fwrt->trans->dbg.restart_required = true; 1296 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1297 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1298 fwrt->trans->dbg.restart_required = false; 1299 fwrt->trans->dbg.last_tp_resetfw = 1300 le32_to_cpu(dump_data.trig->reset_fw); 1301 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1302 IWL_FW_INI_RESET_FW_MODE_NOTHING) { 1303 /* nothing */ 1304 } else { 1305 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n", 1306 le32_to_cpu(dump_data.trig->reset_fw)); 1307 } 1308 } 1309 return 0; 1310 } 1311 1312 void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1313 { 1314 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1315 int ret, i; 1316 u32 failed_alloc = 0; 1317 1318 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) { 1319 IWL_DEBUG_FW(fwrt, 1320 "WRT: Generating active triggers list, domain 0x%x\n", 1321 fwrt->trans->dbg.domains_bitmap); 1322 1323 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1324 struct iwl_dbg_tlv_time_point_data *tp = 1325 &fwrt->trans->dbg.time_point[i]; 1326 1327 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1328 } 1329 } else if (*ini_dest != IWL_FW_INI_LOCATION_DRAM_PATH) { 1330 /* For DRAM, go through the loop below to clear all the buffers 1331 * properly on restart, otherwise garbage may be left there and 1332 * leak into new debug dumps. 1333 */ 1334 return; 1335 } 1336 1337 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1338 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1339 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1340 &fwrt->trans->dbg.fw_mon_cfg[i]; 1341 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1342 1343 if (dest == IWL_FW_INI_LOCATION_INVALID) { 1344 failed_alloc |= BIT(i); 1345 continue; 1346 } 1347 1348 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1349 *ini_dest = dest; 1350 1351 if (dest != *ini_dest) 1352 continue; 1353 1354 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1355 1356 if (ret) { 1357 IWL_WARN(fwrt, 1358 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1359 i, ret); 1360 failed_alloc |= BIT(i); 1361 } 1362 } 1363 1364 if (!failed_alloc) 1365 return; 1366 1367 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1368 struct iwl_fw_ini_region_tlv *reg; 1369 struct iwl_ucode_tlv **active_reg = 1370 &fwrt->trans->dbg.active_regions[i]; 1371 u32 reg_type; 1372 1373 if (!*active_reg) { 1374 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1375 continue; 1376 } 1377 1378 reg = (void *)(*active_reg)->data; 1379 reg_type = reg->type; 1380 1381 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1382 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1383 continue; 1384 1385 IWL_DEBUG_FW(fwrt, 1386 "WRT: removing allocation id %d from region id %d\n", 1387 le32_to_cpu(reg->dram_alloc_id), i); 1388 1389 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id)); 1390 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1391 1392 kfree(*active_reg); 1393 *active_reg = NULL; 1394 } 1395 } 1396 1397 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1398 enum iwl_fw_ini_time_point tp_id, 1399 union iwl_dbg_tlv_tp_data *tp_data, 1400 bool sync) 1401 { 1402 struct list_head *hcmd_list, *trig_list, *conf_list; 1403 1404 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1405 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1406 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1407 return; 1408 1409 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1410 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1411 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; 1412 1413 switch (tp_id) { 1414 case IWL_FW_INI_TIME_POINT_EARLY: 1415 iwl_dbg_tlv_init_cfg(fwrt); 1416 iwl_dbg_tlv_update_drams(fwrt); 1417 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1418 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1419 break; 1420 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1421 iwl_dbg_tlv_apply_buffers(fwrt); 1422 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1423 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1424 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1425 break; 1426 case IWL_FW_INI_TIME_POINT_PERIODIC: 1427 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1428 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1429 break; 1430 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1431 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1432 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1433 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1434 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, 1435 iwl_dbg_tlv_check_fw_pkt); 1436 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1437 break; 1438 default: 1439 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1440 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1441 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1442 break; 1443 } 1444 } 1445 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); 1446