1 /*- 2 * Copyright (c) 2012-2017, 2025 Chelsio Communications. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 27 #ifndef _T4FW_INTERFACE_H_ 28 #define _T4FW_INTERFACE_H_ 29 30 /****************************************************************************** 31 * R E T U R N V A L U E S 32 ********************************/ 33 34 enum fw_retval { 35 FW_SUCCESS = 0, /* completed successfully */ 36 FW_EPERM = 1, /* operation not permitted */ 37 FW_ENOENT = 2, /* no such file or directory */ 38 FW_EIO = 5, /* input/output error; hw bad */ 39 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 40 FW_EAGAIN = 11, /* try again */ 41 FW_ENOMEM = 12, /* out of memory */ 42 FW_EFAULT = 14, /* bad address; fw bad */ 43 FW_EBUSY = 16, /* resource busy */ 44 FW_EEXIST = 17, /* file exists */ 45 FW_ENODEV = 19, /* no such device */ 46 FW_EINVAL = 22, /* invalid argument */ 47 FW_ENOSPC = 28, /* no space left on device */ 48 FW_ENOSYS = 38, /* functionality not implemented */ 49 FW_ENODATA = 61, /* no data available */ 50 FW_EPROTO = 71, /* protocol error */ 51 FW_EADDRINUSE = 98, /* address already in use */ 52 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 53 FW_ENETDOWN = 100, /* network is down */ 54 FW_ENETUNREACH = 101, /* network is unreachable */ 55 FW_ENOBUFS = 105, /* no buffer space available */ 56 FW_ETIMEDOUT = 110, /* timeout */ 57 FW_EINPROGRESS = 115, /* fw internal */ 58 FW_SCSI_ABORT_REQUESTED = 128, /* */ 59 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 60 FW_SCSI_ABORTED = 130, /* */ 61 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 62 FW_ERR_LINK_DOWN = 132, /* */ 63 FW_RDEV_NOT_READY = 133, /* */ 64 FW_ERR_RDEV_LOST = 134, /* */ 65 FW_ERR_RDEV_LOGO = 135, /* */ 66 FW_FCOE_NO_XCHG = 136, /* */ 67 FW_SCSI_RSP_ERR = 137, /* */ 68 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 69 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 70 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 71 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 72 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 73 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 74 }; 75 76 /****************************************************************************** 77 * M E M O R Y T Y P E s 78 ******************************/ 79 80 enum fw_memtype { 81 FW_MEMTYPE_EDC0 = 0x0, 82 FW_MEMTYPE_EDC1 = 0x1, 83 FW_MEMTYPE_EXTMEM = 0x2, 84 FW_MEMTYPE_FLASH = 0x4, 85 FW_MEMTYPE_INTERNAL = 0x5, 86 FW_MEMTYPE_EXTMEM1 = 0x6, 87 FW_MEMTYPE_HMA = 0x7, 88 }; 89 90 /****************************************************************************** 91 * W O R K R E Q U E S T s 92 ********************************/ 93 94 enum fw_wr_opcodes { 95 FW_FRAG_WR = 0x1d, 96 FW_FILTER_WR = 0x02, 97 FW_ULPTX_WR = 0x04, 98 FW_TP_WR = 0x05, 99 FW_ETH_TX_PKT_WR = 0x08, 100 FW_ETH_TX_PKT2_WR = 0x44, 101 FW_ETH_TX_PKTS_WR = 0x09, 102 FW_ETH_TX_PKTS2_WR = 0x78, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_OFLD_TX_DATA_V2_WR = 0x0f, 109 FW_CMD_WR = 0x10, 110 FW_ETH_TX_PKT_VM_WR = 0x11, 111 FW_ETH_TX_PKTS_VM_WR = 0x12, 112 FW_RI_RES_WR = 0x0c, 113 FW_QP_RES_WR = FW_RI_RES_WR, 114 /* iwarp wr used from rdma kernel and user space */ 115 FW_V2_NVMET_TX_DATA_WR = 0x13, 116 FW_RI_RDMA_WRITE_WR = 0x14, 117 FW_RI_SEND_WR = 0x15, 118 FW_RI_RDMA_READ_WR = 0x16, 119 FW_RI_RECV_WR = 0x17, 120 FW_RI_BIND_MW_WR = 0x18, 121 FW_RI_FR_NSMR_WR = 0x19, 122 FW_RI_FR_NSMR_TPTE_WR = 0x20, 123 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 124 /* rocev2 wr used from rdma kernel and user space */ 125 FW_RI_V2_RDMA_WRITE_WR = 0x22, 126 FW_RI_V2_SEND_WR = 0x23, 127 FW_RI_V2_RDMA_READ_WR = 0x24, 128 FW_RI_V2_BIND_MW_WR = 0x25, 129 FW_RI_V2_FR_NSMR_WR = 0x26, 130 FW_RI_V2_ATOMIC_WR = 0x27, 131 FW_NVMET_V2_FR_NSMR_WR = 0x28, 132 FW_RI_V2_INV_LSTAG_WR = 0x1e, 133 FW_RI_INV_LSTAG_WR = 0x1a, 134 FW_RI_SEND_IMMEDIATE_WR = 0x15, 135 FW_RI_ATOMIC_WR = 0x16, 136 FW_RI_WR = 0x0d, 137 FW_CHNET_IFCONF_WR = 0x6b, 138 FW_RDEV_WR = 0x38, 139 FW_FOISCSI_NODE_WR = 0x60, 140 FW_FOISCSI_CTRL_WR = 0x6a, 141 FW_FOISCSI_CHAP_WR = 0x6c, 142 FW_FCOE_ELS_CT_WR = 0x30, 143 FW_SCSI_WRITE_WR = 0x31, 144 FW_SCSI_READ_WR = 0x32, 145 FW_SCSI_CMD_WR = 0x33, 146 FW_SCSI_ABRT_CLS_WR = 0x34, 147 FW_SCSI_TGT_ACC_WR = 0x35, 148 FW_SCSI_TGT_XMIT_WR = 0x36, 149 FW_SCSI_TGT_RSP_WR = 0x37, 150 FW_POFCOE_TCB_WR = 0x42, 151 FW_POFCOE_ULPTX_WR = 0x43, 152 FW_ISCSI_TX_DATA_WR = 0x45, 153 FW_PTP_TX_PKT_WR = 0x46, 154 FW_TLSTX_DATA_WR = 0x68, 155 FW_TLS_TUNNEL_OFLD_WR = 0x69, 156 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 157 FW_CRYPTO_UPDATE_SA_WR = 0x6e, 158 FW_COISCSI_TGT_WR = 0x70, 159 FW_COISCSI_TGT_CONN_WR = 0x71, 160 FW_COISCSI_TGT_XMIT_WR = 0x72, 161 FW_COISCSI_STATS_WR = 0x73, 162 FW_ISNS_WR = 0x75, 163 FW_ISNS_XMIT_WR = 0x76, 164 FW_FILTER2_WR = 0x77, 165 /* FW_LASTC2E_WR = 0x80 */ 166 FW_LASTC2E_WR = 0xB0 167 }; 168 169 /* 170 * Generic work request header flit0 171 */ 172 struct fw_wr_hdr { 173 __be32 hi; 174 __be32 lo; 175 }; 176 177 /* work request opcode (hi) 178 */ 179 #define S_FW_WR_OP 24 180 #define M_FW_WR_OP 0xff 181 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 182 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 183 184 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 185 */ 186 #define S_FW_WR_ATOMIC 23 187 #define M_FW_WR_ATOMIC 0x1 188 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 189 #define G_FW_WR_ATOMIC(x) \ 190 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 191 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 192 193 /* flush flag (hi) - firmware flushes flushable work request buffered 194 * in the flow context. 195 */ 196 #define S_FW_WR_FLUSH 22 197 #define M_FW_WR_FLUSH 0x1 198 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 199 #define G_FW_WR_FLUSH(x) \ 200 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 201 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 202 203 /* completion flag (hi) - firmware generates a cpl_fw6_ack 204 */ 205 #define S_FW_WR_COMPL 21 206 #define M_FW_WR_COMPL 0x1 207 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 208 #define G_FW_WR_COMPL(x) \ 209 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 210 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 211 212 213 /* work request immediate data lengh (hi) 214 */ 215 #define S_FW_WR_IMMDLEN 0 216 #define M_FW_WR_IMMDLEN 0xff 217 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 218 #define G_FW_WR_IMMDLEN(x) \ 219 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 220 221 /* egress queue status update to associated ingress queue entry (lo) 222 */ 223 #define S_FW_WR_EQUIQ 31 224 #define M_FW_WR_EQUIQ 0x1 225 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 226 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 227 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 228 229 /* egress queue status update to egress queue status entry (lo) 230 */ 231 #define S_FW_WR_EQUEQ 30 232 #define M_FW_WR_EQUEQ 0x1 233 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 234 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 235 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 236 237 /* flow context identifier (lo) 238 */ 239 #define S_FW_WR_FLOWID 8 240 #define M_FW_WR_FLOWID 0xfffff 241 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 242 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 243 244 /* length in units of 16-bytes (lo) 245 */ 246 #define S_FW_WR_LEN16 0 247 #define M_FW_WR_LEN16 0xff 248 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 249 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 250 251 struct fw_frag_wr { 252 __be32 op_to_fragoff16; 253 __be32 flowid_len16; 254 __be64 r4; 255 }; 256 257 #define S_FW_FRAG_WR_EOF 15 258 #define M_FW_FRAG_WR_EOF 0x1 259 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 260 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 261 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 262 263 #define S_FW_FRAG_WR_FRAGOFF16 8 264 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 265 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 266 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 267 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 268 269 /* valid filter configurations for compressed tuple 270 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 271 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 272 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 273 * OV - Outer VLAN/VNIC_ID, 274 */ 275 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 276 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 277 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 278 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 279 #define HW_TPL_FR_MT_E_PR_T 0x370 280 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 281 #define HW_TPL_FR_MT_E_T_P_FC 0X353 282 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 283 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 284 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 285 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 286 #define HW_TPL_FR_M_E_PR_FC 0X2E1 287 #define HW_TPL_FR_M_E_T_FC 0X2D1 288 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 289 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 290 #define HW_TPL_FR_M_T_IV_FC 0X299 291 #define HW_TPL_FR_M_T_OV_FC 0X295 292 #define HW_TPL_FR_E_PR_T_P 0X272 293 #define HW_TPL_FR_E_PR_T_FC 0X271 294 #define HW_TPL_FR_E_IV_FC 0X249 295 #define HW_TPL_FR_E_OV_FC 0X245 296 #define HW_TPL_FR_PR_T_IV_FC 0X239 297 #define HW_TPL_FR_PR_T_OV_FC 0X235 298 #define HW_TPL_FR_IV_OV_FC 0X20D 299 #define HW_TPL_MT_M_E_PR 0X1E0 300 #define HW_TPL_MT_M_E_T 0X1D0 301 #define HW_TPL_MT_E_PR_T_FC 0X171 302 #define HW_TPL_MT_E_IV 0X148 303 #define HW_TPL_MT_E_OV 0X144 304 #define HW_TPL_MT_PR_T_IV 0X138 305 #define HW_TPL_MT_PR_T_OV 0X134 306 #define HW_TPL_M_E_PR_P 0X0E2 307 #define HW_TPL_M_E_T_P 0X0D2 308 #define HW_TPL_E_PR_T_P_FC 0X073 309 #define HW_TPL_E_IV_P 0X04A 310 #define HW_TPL_E_OV_P 0X046 311 #define HW_TPL_PR_T_IV_P 0X03A 312 #define HW_TPL_PR_T_OV_P 0X036 313 314 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 315 enum fw_filter_wr_cookie { 316 FW_FILTER_WR_SUCCESS, 317 FW_FILTER_WR_FLT_ADDED, 318 FW_FILTER_WR_FLT_DELETED, 319 FW_FILTER_WR_SMT_TBL_FULL, 320 FW_FILTER_WR_EINVAL, 321 }; 322 323 enum fw_filter_wr_nat_mode { 324 FW_FILTER_WR_NATMODE_NONE = 0, 325 FW_FILTER_WR_NATMODE_DIP, 326 FW_FILTER_WR_NATMODE_DIPDP, 327 FW_FILTER_WR_NATMODE_DIPDPSIP, 328 FW_FILTER_WR_NATMODE_DIPDPSP, 329 FW_FILTER_WR_NATMODE_SIPSP, 330 FW_FILTER_WR_NATMODE_DIPSIPSP, 331 FW_FILTER_WR_NATMODE_FOURTUPLE, 332 }; 333 334 struct fw_filter_wr { 335 __be32 op_pkd; 336 __be32 len16_pkd; 337 __be64 r3; 338 __be32 tid_to_iq; 339 __be32 del_filter_to_l2tix; 340 __be16 ethtype; 341 __be16 ethtypem; 342 __u8 frag_to_ovlan_vldm; 343 __u8 smac_sel; 344 __be16 rx_chan_rx_rpl_iq; 345 __be32 maci_to_matchtypem; 346 __u8 ptcl; 347 __u8 ptclm; 348 __u8 ttyp; 349 __u8 ttypm; 350 __be16 ivlan; 351 __be16 ivlanm; 352 __be16 ovlan; 353 __be16 ovlanm; 354 __u8 lip[16]; 355 __u8 lipm[16]; 356 __u8 fip[16]; 357 __u8 fipm[16]; 358 __be16 lp; 359 __be16 lpm; 360 __be16 fp; 361 __be16 fpm; 362 __be16 r7; 363 __u8 sma[6]; 364 }; 365 366 struct fw_filter2_wr { 367 __be32 op_pkd; 368 __be32 len16_pkd; 369 __be64 r3; 370 __be32 tid_to_iq; 371 __be32 del_filter_to_l2tix; 372 __be16 ethtype; 373 __be16 ethtypem; 374 __u8 frag_to_ovlan_vldm; 375 __u8 smac_sel; 376 __be16 rx_chan_rx_rpl_iq; 377 __be32 maci_to_matchtypem; 378 __u8 ptcl; 379 __u8 ptclm; 380 __u8 ttyp; 381 __u8 ttypm; 382 __be16 ivlan; 383 __be16 ivlanm; 384 __be16 ovlan; 385 __be16 ovlanm; 386 __u8 lip[16]; 387 __u8 lipm[16]; 388 __u8 fip[16]; 389 __u8 fipm[16]; 390 __be16 lp; 391 __be16 lpm; 392 __be16 fp; 393 __be16 fpm; 394 __be16 r7; 395 __u8 sma[6]; 396 __be16 r8; 397 __u8 filter_type_swapmac; 398 __u8 natmode_to_ulp_type; 399 __be16 newlport; 400 __be16 newfport; 401 __u8 newlip[16]; 402 __u8 newfip[16]; 403 __be32 natseqcheck; 404 __be32 rocev2_qpn; 405 __be64 r10; 406 __be64 r11; 407 __be64 r12; 408 __be64 r13; 409 }; 410 411 #define S_FW_FILTER_WR_TID 12 412 #define M_FW_FILTER_WR_TID 0xfffff 413 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 414 #define G_FW_FILTER_WR_TID(x) \ 415 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 416 417 #define S_FW_FILTER_WR_RQTYPE 11 418 #define M_FW_FILTER_WR_RQTYPE 0x1 419 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 420 #define G_FW_FILTER_WR_RQTYPE(x) \ 421 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 422 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 423 424 #define S_FW_FILTER_WR_NOREPLY 10 425 #define M_FW_FILTER_WR_NOREPLY 0x1 426 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 427 #define G_FW_FILTER_WR_NOREPLY(x) \ 428 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 429 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 430 431 #define S_FW_FILTER_WR_IQ 0 432 #define M_FW_FILTER_WR_IQ 0x3ff 433 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 434 #define G_FW_FILTER_WR_IQ(x) \ 435 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 436 437 #define S_FW_FILTER_WR_DEL_FILTER 31 438 #define M_FW_FILTER_WR_DEL_FILTER 0x1 439 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 440 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 441 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 442 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 443 444 #define S_FW_FILTER2_WR_DROP_ENCAP 30 445 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 446 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 447 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 448 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 449 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 450 451 #define S_FW_FILTER2_WR_TX_LOOP 29 452 #define M_FW_FILTER2_WR_TX_LOOP 0x1 453 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 454 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 455 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 456 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 457 458 #define S_FW_FILTER_WR_RPTTID 25 459 #define M_FW_FILTER_WR_RPTTID 0x1 460 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 461 #define G_FW_FILTER_WR_RPTTID(x) \ 462 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 463 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 464 465 #define S_FW_FILTER_WR_DROP 24 466 #define M_FW_FILTER_WR_DROP 0x1 467 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 468 #define G_FW_FILTER_WR_DROP(x) \ 469 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 470 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 471 472 #define S_FW_FILTER_WR_DIRSTEER 23 473 #define M_FW_FILTER_WR_DIRSTEER 0x1 474 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 475 #define G_FW_FILTER_WR_DIRSTEER(x) \ 476 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 477 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 478 479 #define S_FW_FILTER_WR_MASKHASH 22 480 #define M_FW_FILTER_WR_MASKHASH 0x1 481 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 482 #define G_FW_FILTER_WR_MASKHASH(x) \ 483 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 484 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 485 486 #define S_FW_FILTER_WR_DIRSTEERHASH 21 487 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 488 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 489 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 490 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 491 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 492 493 #define S_FW_FILTER_WR_LPBK 20 494 #define M_FW_FILTER_WR_LPBK 0x1 495 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 496 #define G_FW_FILTER_WR_LPBK(x) \ 497 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 498 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 499 500 #define S_FW_FILTER_WR_DMAC 19 501 #define M_FW_FILTER_WR_DMAC 0x1 502 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 503 #define G_FW_FILTER_WR_DMAC(x) \ 504 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 505 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 506 507 #define S_FW_FILTER_WR_SMAC 18 508 #define M_FW_FILTER_WR_SMAC 0x1 509 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 510 #define G_FW_FILTER_WR_SMAC(x) \ 511 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 512 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 513 514 #define S_FW_FILTER_WR_INSVLAN 17 515 #define M_FW_FILTER_WR_INSVLAN 0x1 516 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 517 #define G_FW_FILTER_WR_INSVLAN(x) \ 518 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 519 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 520 521 #define S_FW_FILTER_WR_RMVLAN 16 522 #define M_FW_FILTER_WR_RMVLAN 0x1 523 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 524 #define G_FW_FILTER_WR_RMVLAN(x) \ 525 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 526 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 527 528 #define S_FW_FILTER_WR_HITCNTS 15 529 #define M_FW_FILTER_WR_HITCNTS 0x1 530 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 531 #define G_FW_FILTER_WR_HITCNTS(x) \ 532 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 533 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 534 535 #define S_FW_FILTER_WR_TXCHAN 13 536 #define M_FW_FILTER_WR_TXCHAN 0x3 537 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 538 #define G_FW_FILTER_WR_TXCHAN(x) \ 539 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 540 541 #define S_FW_FILTER_WR_PRIO 12 542 #define M_FW_FILTER_WR_PRIO 0x1 543 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 544 #define G_FW_FILTER_WR_PRIO(x) \ 545 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 546 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 547 548 #define S_FW_FILTER_WR_L2TIX 0 549 #define M_FW_FILTER_WR_L2TIX 0xfff 550 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 551 #define G_FW_FILTER_WR_L2TIX(x) \ 552 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 553 554 #define S_FW_FILTER_WR_FRAG 7 555 #define M_FW_FILTER_WR_FRAG 0x1 556 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 557 #define G_FW_FILTER_WR_FRAG(x) \ 558 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 559 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 560 561 #define S_FW_FILTER_WR_FRAGM 6 562 #define M_FW_FILTER_WR_FRAGM 0x1 563 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 564 #define G_FW_FILTER_WR_FRAGM(x) \ 565 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 566 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 567 568 #define S_FW_FILTER_WR_IVLAN_VLD 5 569 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 570 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 571 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 572 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 573 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 574 575 #define S_FW_FILTER_WR_OVLAN_VLD 4 576 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 577 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 578 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 579 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 580 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 581 582 #define S_FW_FILTER_WR_IVLAN_VLDM 3 583 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 584 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 585 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 586 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 587 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 588 589 #define S_FW_FILTER_WR_OVLAN_VLDM 2 590 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 591 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 592 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 593 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 594 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 595 596 #define S_FW_FILTER_WR_RX_CHAN 15 597 #define M_FW_FILTER_WR_RX_CHAN 0x1 598 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 599 #define G_FW_FILTER_WR_RX_CHAN(x) \ 600 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 601 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 602 603 #define S_FW_FILTER_WR_RX_RPL_IQ 0 604 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 605 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 606 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 607 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 608 609 #define S_FW_FILTER2_WR_FILTER_TYPE 1 610 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 611 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 612 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 613 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 614 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 615 616 #define S_FW_FILTER2_WR_SWAPMAC 0 617 #define M_FW_FILTER2_WR_SWAPMAC 0x1 618 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 619 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 620 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 621 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 622 623 #define S_FW_FILTER2_WR_NATMODE 5 624 #define M_FW_FILTER2_WR_NATMODE 0x7 625 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 626 #define G_FW_FILTER2_WR_NATMODE(x) \ 627 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 628 629 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 630 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 631 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 632 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 633 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 634 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 635 636 #define S_FW_FILTER2_WR_ULP_TYPE 0 637 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 638 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 639 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 640 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 641 642 #define S_FW_FILTER_WR_MACI 23 643 #define M_FW_FILTER_WR_MACI 0x1ff 644 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 645 #define G_FW_FILTER_WR_MACI(x) \ 646 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 647 648 #define S_FW_FILTER_WR_MACIM 14 649 #define M_FW_FILTER_WR_MACIM 0x1ff 650 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 651 #define G_FW_FILTER_WR_MACIM(x) \ 652 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 653 654 #define S_FW_FILTER_WR_FCOE 13 655 #define M_FW_FILTER_WR_FCOE 0x1 656 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 657 #define G_FW_FILTER_WR_FCOE(x) \ 658 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 659 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 660 661 #define S_FW_FILTER_WR_FCOEM 12 662 #define M_FW_FILTER_WR_FCOEM 0x1 663 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 664 #define G_FW_FILTER_WR_FCOEM(x) \ 665 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 666 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 667 668 #define S_FW_FILTER_WR_PORT 9 669 #define M_FW_FILTER_WR_PORT 0x7 670 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 671 #define G_FW_FILTER_WR_PORT(x) \ 672 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 673 674 #define S_FW_FILTER_WR_PORTM 6 675 #define M_FW_FILTER_WR_PORTM 0x7 676 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 677 #define G_FW_FILTER_WR_PORTM(x) \ 678 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 679 680 #define S_FW_FILTER_WR_MATCHTYPE 3 681 #define M_FW_FILTER_WR_MATCHTYPE 0x7 682 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 683 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 684 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 685 686 #define S_FW_FILTER_WR_MATCHTYPEM 0 687 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 688 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 689 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 690 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 691 692 #define S_FW_FILTER2_WR_ROCEV2 31 693 #define M_FW_FILTER2_WR_ROCEV2 0x1 694 #define V_FW_FILTER2_WR_ROCEV2(x) ((x) << S_FW_FILTER2_WR_ROCEV2) 695 #define G_FW_FILTER2_WR_ROCEV2(x) \ 696 (((x) >> S_FW_FILTER2_WR_ROCEV2) & M_FW_FILTER2_WR_ROCEV2) 697 #define F_FW_FILTER2_WR_ROCEV2 V_FW_FILTER2_WR_ROCEV2(1U) 698 699 #define S_FW_FILTER2_WR_QPN 0 700 #define M_FW_FILTER2_WR_QPN 0xffffff 701 #define V_FW_FILTER2_WR_QPN(x) ((x) << S_FW_FILTER2_WR_QPN) 702 #define G_FW_FILTER2_WR_QPN(x) \ 703 (((x) >> S_FW_FILTER2_WR_QPN) & M_FW_FILTER2_WR_QPN) 704 705 struct fw_ulptx_wr { 706 __be32 op_to_compl; 707 __be32 flowid_len16; 708 __u64 cookie; 709 }; 710 711 /* flag for packet type - control packet (0), data packet (1) 712 */ 713 #define S_FW_ULPTX_WR_DATA 28 714 #define M_FW_ULPTX_WR_DATA 0x1 715 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 716 #define G_FW_ULPTX_WR_DATA(x) \ 717 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 718 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 719 720 struct fw_tp_wr { 721 __be32 op_to_immdlen; 722 __be32 flowid_len16; 723 __u64 cookie; 724 }; 725 726 struct fw_eth_tx_pkt_wr { 727 __be32 op_immdlen; 728 __be32 equiq_to_len16; 729 __be64 r3; 730 }; 731 732 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 733 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 734 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 735 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 736 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 737 738 struct fw_eth_tx_pkt2_wr { 739 __be32 op_immdlen; 740 __be32 equiq_to_len16; 741 __be32 r3; 742 __be32 L4ChkDisable_to_IpHdrLen; 743 }; 744 745 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 746 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 747 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 748 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 749 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 750 751 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 752 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 753 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 754 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 755 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 756 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 757 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 758 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 759 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 760 761 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 762 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 763 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 764 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 765 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 766 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 767 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 768 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 769 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 770 771 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 772 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 773 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 774 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 775 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 776 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 777 778 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 779 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 780 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 781 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 782 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 783 784 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 785 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 786 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 787 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 788 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 789 790 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 791 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 792 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 793 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 794 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 795 796 struct fw_eth_tx_pkts_wr { 797 __be32 op_pkd; 798 __be32 equiq_to_len16; 799 __be32 r3; 800 __be16 plen; 801 __u8 npkt; 802 __u8 type; 803 }; 804 805 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 806 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 807 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 808 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 809 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 810 811 struct fw_eth_tx_pkt_ptp_wr { 812 __be32 op_immdlen; 813 __be32 equiq_to_len16; 814 __be64 r3; 815 }; 816 817 enum fw_eth_tx_eo_type { 818 FW_ETH_TX_EO_TYPE_UDPSEG, 819 FW_ETH_TX_EO_TYPE_TCPSEG, 820 FW_ETH_TX_EO_TYPE_NVGRESEG, 821 FW_ETH_TX_EO_TYPE_VXLANSEG, 822 FW_ETH_TX_EO_TYPE_GENEVESEG, 823 }; 824 825 struct fw_eth_tx_eo_wr { 826 __be32 op_immdlen; 827 __be32 equiq_to_len16; 828 __be64 r3; 829 union fw_eth_tx_eo { 830 struct fw_eth_tx_eo_udpseg { 831 __u8 type; 832 __u8 ethlen; 833 __be16 iplen; 834 __u8 udplen; 835 __u8 rtplen; 836 __be16 r4; 837 __be16 mss; 838 __be16 schedpktsize; 839 __be32 plen; 840 } udpseg; 841 struct fw_eth_tx_eo_tcpseg { 842 __u8 type; 843 __u8 ethlen; 844 __be16 iplen; 845 __u8 tcplen; 846 __u8 tsclk_tsoff; 847 __be16 r4; 848 __be16 mss; 849 __be16 r5; 850 __be32 plen; 851 } tcpseg; 852 struct fw_eth_tx_eo_nvgreseg { 853 __u8 type; 854 __u8 iphdroffout; 855 __be16 grehdroff; 856 __be16 iphdroffin; 857 __be16 tcphdroffin; 858 __be16 mss; 859 __be16 r4; 860 __be32 plen; 861 } nvgreseg; 862 struct fw_eth_tx_eo_vxlanseg { 863 __u8 type; 864 __u8 iphdroffout; 865 __be16 vxlanhdroff; 866 __be16 iphdroffin; 867 __be16 tcphdroffin; 868 __be16 mss; 869 __be16 r4; 870 __be32 plen; 871 872 } vxlanseg; 873 struct fw_eth_tx_eo_geneveseg { 874 __u8 type; 875 __u8 iphdroffout; 876 __be16 genevehdroff; 877 __be16 iphdroffin; 878 __be16 tcphdroffin; 879 __be16 mss; 880 __be16 r4; 881 __be32 plen; 882 } geneveseg; 883 } u; 884 }; 885 886 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 887 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 888 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 889 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 890 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 891 892 #define S_FW_ETH_TX_EO_WR_TSCLK 6 893 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 894 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 895 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 896 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 897 898 #define S_FW_ETH_TX_EO_WR_TSOFF 0 899 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 900 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 901 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 902 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 903 904 struct fw_eq_flush_wr { 905 __u8 opcode; 906 __u8 r1[3]; 907 __be32 equiq_to_len16; 908 __be64 r3; 909 }; 910 911 struct fw_ofld_connection_wr { 912 __be32 op_compl; 913 __be32 len16_pkd; 914 __u64 cookie; 915 __be64 r2; 916 __be64 r3; 917 struct fw_ofld_connection_le { 918 __be32 version_cpl; 919 __be32 filter; 920 __be32 r1; 921 __be16 lport; 922 __be16 pport; 923 union fw_ofld_connection_leip { 924 struct fw_ofld_connection_le_ipv4 { 925 __be32 pip; 926 __be32 lip; 927 __be64 r0; 928 __be64 r1; 929 __be64 r2; 930 } ipv4; 931 struct fw_ofld_connection_le_ipv6 { 932 __be64 pip_hi; 933 __be64 pip_lo; 934 __be64 lip_hi; 935 __be64 lip_lo; 936 } ipv6; 937 } u; 938 } le; 939 struct fw_ofld_connection_tcb { 940 __be32 t_state_to_astid; 941 __be16 cplrxdataack_cplpassacceptrpl; 942 __be16 rcv_adv; 943 __be32 rcv_nxt; 944 __be32 tx_max; 945 __be64 opt0; 946 __be32 opt2; 947 __be32 r1; 948 __be64 r2; 949 __be64 r3; 950 } tcb; 951 }; 952 953 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 954 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 955 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 956 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 957 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 958 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 959 M_FW_OFLD_CONNECTION_WR_VERSION) 960 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 961 962 #define S_FW_OFLD_CONNECTION_WR_CPL 30 963 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 964 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 965 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 966 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 967 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 968 969 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 970 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 971 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 972 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 973 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 974 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 975 M_FW_OFLD_CONNECTION_WR_T_STATE) 976 977 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 978 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 979 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 980 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 981 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 982 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 983 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 984 985 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 986 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 987 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 988 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 989 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 990 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 991 992 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 993 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 994 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 995 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 996 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 997 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 998 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 999 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 1000 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 1001 1002 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 1003 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 1004 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 1005 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 1006 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 1007 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 1008 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 1009 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 1010 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 1011 1012 enum fw_flowc_mnem_tcpstate { 1013 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 1014 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 1015 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 1016 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 1017 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 1018 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 1019 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 1020 * will resend FIN - equiv ESTAB 1021 */ 1022 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 1023 * will resend FIN but have 1024 * received FIN 1025 */ 1026 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 1027 * will resend FIN but have 1028 * received FIN 1029 */ 1030 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 1031 * waiting for FIN 1032 */ 1033 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 1034 }; 1035 1036 enum fw_flowc_mnem_eostate { 1037 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 1038 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1039 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1040 * outstanding payload 1041 */ 1042 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1043 * discarding outstanding payload 1044 */ 1045 }; 1046 1047 enum fw_flowc_mnem { 1048 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1049 FW_FLOWC_MNEM_CH = 1, 1050 FW_FLOWC_MNEM_PORT = 2, 1051 FW_FLOWC_MNEM_IQID = 3, 1052 FW_FLOWC_MNEM_SNDNXT = 4, 1053 FW_FLOWC_MNEM_RCVNXT = 5, 1054 FW_FLOWC_MNEM_SNDBUF = 6, 1055 FW_FLOWC_MNEM_MSS = 7, 1056 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1057 FW_FLOWC_MNEM_TCPSTATE = 9, 1058 FW_FLOWC_MNEM_EOSTATE = 10, 1059 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1060 FW_FLOWC_MNEM_DCBPRIO = 12, 1061 FW_FLOWC_MNEM_SND_SCALE = 13, 1062 FW_FLOWC_MNEM_RCV_SCALE = 14, 1063 FW_FLOWC_MNEM_ULP_MODE = 15, 1064 FW_FLOWC_MNEM_EQID = 16, 1065 FW_FLOWC_MNEM_CONG_ALG = 17, 1066 FW_FLOWC_MNEM_TXDATAPLEN_MIN = 18, 1067 FW_FLOWC_MNEM_MAX = 19, 1068 }; 1069 1070 struct fw_flowc_mnemval { 1071 __u8 mnemonic; 1072 __u8 r4[3]; 1073 __be32 val; 1074 }; 1075 1076 struct fw_flowc_wr { 1077 __be32 op_to_nparams; 1078 __be32 flowid_len16; 1079 #ifndef C99_NOT_SUPPORTED 1080 struct fw_flowc_mnemval mnemval[0]; 1081 #endif 1082 }; 1083 1084 #define S_FW_FLOWC_WR_NPARAMS 0 1085 #define M_FW_FLOWC_WR_NPARAMS 0xff 1086 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1087 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1088 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1089 1090 struct fw_ofld_tx_data_wr { 1091 __be32 op_to_immdlen; 1092 __be32 flowid_len16; 1093 __be32 plen; 1094 __be32 lsodisable_to_flags; 1095 }; 1096 1097 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1098 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1099 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1100 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1101 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1102 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1103 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1104 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1105 1106 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1107 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1108 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1109 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1110 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1111 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1112 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1113 1114 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1115 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1116 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1117 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1118 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1119 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1120 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1121 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1122 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1123 1124 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1125 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1126 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1127 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1128 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1129 1130 1131 /* Use fw_ofld_tx_data_wr structure */ 1132 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1133 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1134 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1135 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1136 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1137 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1138 1139 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1140 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1141 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1142 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1143 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1144 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1145 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1146 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1147 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1148 1149 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1150 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1151 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1152 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1153 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1154 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1155 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1156 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1157 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1158 1159 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1160 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1161 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1162 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1163 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1164 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1165 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1166 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1167 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1168 1169 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1170 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1171 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1172 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1173 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1174 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1175 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1176 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1177 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1178 1179 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1180 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1181 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1182 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1183 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1184 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1185 1186 struct fw_ofld_tx_data_v2_wr { 1187 __be32 op_to_immdlen; 1188 __be32 flowid_len16; 1189 __be32 r4; 1190 __be16 r5; 1191 __be16 wrid; 1192 __be32 r6; 1193 __be32 seqno; 1194 __be32 plen; 1195 __be32 lsodisable_to_flags; 1196 }; 1197 1198 #define S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE 31 1199 #define M_FW_OFLD_TX_DATA_V2_WR_LSODISABLE 0x1 1200 #define V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x) \ 1201 ((x) << S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) 1202 #define G_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x) \ 1203 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) & \ 1204 M_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) 1205 #define F_FW_OFLD_TX_DATA_V2_WR_LSODISABLE \ 1206 V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(1U) 1207 1208 #define S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD 30 1209 #define M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD 0x1 1210 #define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x) \ 1211 ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) 1212 #define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x) \ 1213 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) & \ 1214 M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) 1215 #define F_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD \ 1216 V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(1U) 1217 1218 #define S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE 29 1219 #define M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE 0x1 1220 #define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x) \ 1221 ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) 1222 #define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x) \ 1223 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) & \ 1224 M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) 1225 #define F_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE \ 1226 V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(1U) 1227 1228 #define S_FW_OFLD_TX_DATA_V2_WR_FLAGS 0 1229 #define M_FW_OFLD_TX_DATA_V2_WR_FLAGS 0xfffffff 1230 #define V_FW_OFLD_TX_DATA_V2_WR_FLAGS(x) \ 1231 ((x) << S_FW_OFLD_TX_DATA_V2_WR_FLAGS) 1232 #define G_FW_OFLD_TX_DATA_V2_WR_FLAGS(x) \ 1233 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_FLAGS) & M_FW_OFLD_TX_DATA_V2_WR_FLAGS) 1234 1235 struct fw_cmd_wr { 1236 __be32 op_dma; 1237 __be32 len16_pkd; 1238 __be64 cookie_daddr; 1239 }; 1240 1241 #define S_FW_CMD_WR_DMA 17 1242 #define M_FW_CMD_WR_DMA 0x1 1243 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1244 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1245 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1246 1247 struct fw_eth_tx_pkt_vm_wr { 1248 __be32 op_immdlen; 1249 __be32 equiq_to_len16; 1250 __be32 r3[2]; 1251 __u8 ethmacdst[6]; 1252 __u8 ethmacsrc[6]; 1253 __be16 ethtype; 1254 __be16 vlantci; 1255 }; 1256 1257 struct fw_eth_tx_pkts_vm_wr { 1258 __be32 op_pkd; 1259 __be32 equiq_to_len16; 1260 __be32 r3; 1261 __be16 plen; 1262 __u8 npkt; 1263 __u8 r4; 1264 __u8 ethmacdst[6]; 1265 __u8 ethmacsrc[6]; 1266 __be16 ethtype; 1267 __be16 vlantci; 1268 }; 1269 1270 /****************************************************************************** 1271 * R I W O R K R E Q U E S T s 1272 **************************************/ 1273 1274 enum fw_ri_wr_opcode { 1275 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1276 FW_RI_READ_REQ = 0x1, 1277 FW_RI_READ_RESP = 0x2, 1278 FW_RI_SEND = 0x3, 1279 FW_RI_SEND_WITH_INV = 0x4, 1280 FW_RI_SEND_WITH_SE = 0x5, 1281 FW_RI_SEND_WITH_SE_INV = 0x6, 1282 FW_RI_TERMINATE = 0x7, 1283 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1284 FW_RI_BIND_MW = 0x9, 1285 FW_RI_FAST_REGISTER = 0xa, 1286 FW_RI_LOCAL_INV = 0xb, 1287 FW_RI_QP_MODIFY = 0xc, 1288 FW_RI_BYPASS = 0xd, 1289 FW_RI_RECEIVE = 0xe, 1290 #if 0 1291 FW_RI_SEND_IMMEDIATE = 0x8, 1292 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1293 FW_RI_ATOMIC_REQUEST = 0xa, 1294 FW_RI_ATOMIC_RESPONSE = 0xb, 1295 1296 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1297 FW_RI_FAST_REGISTER = 0xd, 1298 FW_RI_LOCAL_INV = 0xe, 1299 #endif 1300 /* Chelsio specific */ 1301 FW_RI_SGE_EC_CR_RETURN = 0xf, 1302 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1303 FW_RI_SEND_IMMEDIATE = FW_RI_RDMA_INIT, 1304 1305 FW_RI_ROCEV2_SEND = 0x0, 1306 FW_RI_ROCEV2_WRITE = 0x0, 1307 FW_RI_ROCEV2_SEND_WITH_INV = 0x5, 1308 FW_RI_ROCEV2_SEND_IMMEDIATE = 0xa, 1309 }; 1310 1311 enum fw_ri_wr_flags { 1312 FW_RI_COMPLETION_FLAG = 0x01, 1313 FW_RI_NOTIFICATION_FLAG = 0x02, 1314 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1315 FW_RI_READ_FENCE_FLAG = 0x08, 1316 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1317 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1318 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40, 1319 //FW_RI_REPLAYED_WR_FLAG = 0x80, 1320 }; 1321 1322 enum fw_ri_mpa_attrs { 1323 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1324 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1325 FW_RI_MPA_CRC_ENABLE = 0x04, 1326 FW_RI_MPA_IETF_ENABLE = 0x08 1327 }; 1328 1329 enum fw_ri_qp_caps { 1330 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1331 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1332 FW_RI_QP_BIND_ENABLE = 0x04, 1333 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1334 FW_RI_QP_STAG0_ENABLE = 0x10, 1335 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1336 }; 1337 1338 enum fw_ri_addr_type { 1339 FW_RI_ZERO_BASED_TO = 0x00, 1340 FW_RI_VA_BASED_TO = 0x01 1341 }; 1342 1343 enum fw_ri_mem_perms { 1344 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1345 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1346 FW_RI_MEM_ACCESS_REM = 0x03, 1347 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1348 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1349 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1350 }; 1351 1352 enum fw_ri_stag_type { 1353 FW_RI_STAG_NSMR = 0x00, 1354 FW_RI_STAG_SMR = 0x01, 1355 FW_RI_STAG_MW = 0x02, 1356 FW_RI_STAG_MW_RELAXED = 0x03 1357 }; 1358 1359 enum fw_ri_data_op { 1360 FW_RI_DATA_IMMD = 0x81, 1361 FW_RI_DATA_DSGL = 0x82, 1362 FW_RI_DATA_ISGL = 0x83 1363 }; 1364 1365 enum fw_ri_sgl_depth { 1366 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1367 FW_RI_SGL_DEPTH_MAX_RQ = 4 1368 }; 1369 1370 enum fw_ri_cqe_err { 1371 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1372 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1373 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1374 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1375 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1376 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1377 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1378 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1379 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1380 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1381 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1382 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1383 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1384 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1385 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1386 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1387 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1388 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1389 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1390 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1391 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1392 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1393 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1394 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1395 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1396 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1397 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1398 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1399 1400 }; 1401 1402 struct fw_ri_dsge_pair { 1403 __be32 len[2]; 1404 __be64 addr[2]; 1405 }; 1406 1407 struct fw_ri_dsgl { 1408 __u8 op; 1409 __u8 r1; 1410 __be16 nsge; 1411 __be32 len0; 1412 __be64 addr0; 1413 #ifndef C99_NOT_SUPPORTED 1414 struct fw_ri_dsge_pair sge[0]; 1415 #endif 1416 }; 1417 1418 struct fw_ri_sge { 1419 __be32 stag; 1420 __be32 len; 1421 __be64 to; 1422 }; 1423 1424 struct fw_ri_isgl { 1425 __u8 op; 1426 __u8 r1; 1427 __be16 nsge; 1428 __be32 r2; 1429 #ifndef C99_NOT_SUPPORTED 1430 struct fw_ri_sge sge[0]; 1431 #endif 1432 }; 1433 1434 struct fw_ri_immd { 1435 __u8 op; 1436 __u8 r1; 1437 __be16 r2; 1438 __be32 immdlen; 1439 #ifndef C99_NOT_SUPPORTED 1440 __u8 data[0]; 1441 #endif 1442 }; 1443 1444 struct fw_ri_tpte { 1445 __be32 valid_to_pdid; 1446 __be32 locread_to_qpid; 1447 __be32 nosnoop_pbladdr; 1448 __be32 len_lo; 1449 __be32 va_hi; 1450 __be32 va_lo_fbo; 1451 __be32 dca_mwbcnt_pstag; 1452 __be32 len_hi; 1453 }; 1454 1455 #define S_FW_RI_TPTE_VALID 31 1456 #define M_FW_RI_TPTE_VALID 0x1 1457 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1458 #define G_FW_RI_TPTE_VALID(x) \ 1459 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1460 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1461 1462 #define S_FW_RI_TPTE_STAGKEY 23 1463 #define M_FW_RI_TPTE_STAGKEY 0xff 1464 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1465 #define G_FW_RI_TPTE_STAGKEY(x) \ 1466 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1467 1468 #define S_FW_RI_TPTE_STAGSTATE 22 1469 #define M_FW_RI_TPTE_STAGSTATE 0x1 1470 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1471 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1472 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1473 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1474 1475 #define S_FW_RI_TPTE_STAGTYPE 20 1476 #define M_FW_RI_TPTE_STAGTYPE 0x3 1477 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1478 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1479 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1480 1481 #define S_FW_RI_TPTE_PDID 0 1482 #define M_FW_RI_TPTE_PDID 0xfffff 1483 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1484 #define G_FW_RI_TPTE_PDID(x) \ 1485 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1486 1487 #define S_FW_RI_TPTE_PERM 28 1488 #define M_FW_RI_TPTE_PERM 0xf 1489 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1490 #define G_FW_RI_TPTE_PERM(x) \ 1491 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1492 1493 #define S_FW_RI_TPTE_REMINVDIS 27 1494 #define M_FW_RI_TPTE_REMINVDIS 0x1 1495 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1496 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1497 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1498 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1499 1500 #define S_FW_RI_TPTE_ADDRTYPE 26 1501 #define M_FW_RI_TPTE_ADDRTYPE 1 1502 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1503 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1504 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1505 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1506 1507 #define S_FW_RI_TPTE_MWBINDEN 25 1508 #define M_FW_RI_TPTE_MWBINDEN 0x1 1509 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1510 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1511 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1512 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1513 1514 #define S_FW_RI_TPTE_PS 20 1515 #define M_FW_RI_TPTE_PS 0x1f 1516 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1517 #define G_FW_RI_TPTE_PS(x) \ 1518 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1519 1520 #define S_FW_RI_TPTE_QPID 0 1521 #define M_FW_RI_TPTE_QPID 0xfffff 1522 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1523 #define G_FW_RI_TPTE_QPID(x) \ 1524 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1525 1526 #define S_FW_RI_TPTE_NOSNOOP 31 1527 #define M_FW_RI_TPTE_NOSNOOP 0x1 1528 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1529 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1530 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1531 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1532 1533 #define S_FW_RI_TPTE_PBLADDR 0 1534 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1535 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1536 #define G_FW_RI_TPTE_PBLADDR(x) \ 1537 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1538 1539 #define S_FW_RI_TPTE_DCA 24 1540 #define M_FW_RI_TPTE_DCA 0x1f 1541 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1542 #define G_FW_RI_TPTE_DCA(x) \ 1543 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1544 1545 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1546 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1547 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1548 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1549 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1550 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1551 1552 enum fw_ri_cqe_rxtx { 1553 FW_RI_CQE_RXTX_RX = 0x0, 1554 FW_RI_CQE_RXTX_TX = 0x1, 1555 }; 1556 1557 struct fw_ri_cqe { 1558 union fw_ri_rxtx { 1559 struct fw_ri_scqe { 1560 __be32 qpid_n_stat_rxtx_type; 1561 __be32 plen; 1562 __be32 stag; 1563 __be32 wrid; 1564 } scqe; 1565 struct fw_ri_rcqe { 1566 __be32 qpid_n_stat_rxtx_type; 1567 __be32 plen; 1568 __be32 stag; 1569 __be32 msn; 1570 } rcqe; 1571 struct fw_ri_rcqe_imm { 1572 __be32 qpid_n_stat_rxtx_type; 1573 __be32 plen; 1574 __be32 mo; 1575 __be32 msn; 1576 __u64 imm_data; 1577 } imm_data_rcqe; 1578 } u; 1579 }; 1580 1581 #define S_FW_RI_CQE_QPID 12 1582 #define M_FW_RI_CQE_QPID 0xfffff 1583 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1584 #define G_FW_RI_CQE_QPID(x) \ 1585 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1586 1587 #define S_FW_RI_CQE_NOTIFY 10 1588 #define M_FW_RI_CQE_NOTIFY 0x1 1589 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1590 #define G_FW_RI_CQE_NOTIFY(x) \ 1591 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1592 1593 #define S_FW_RI_CQE_STATUS 5 1594 #define M_FW_RI_CQE_STATUS 0x1f 1595 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1596 #define G_FW_RI_CQE_STATUS(x) \ 1597 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1598 1599 1600 #define S_FW_RI_CQE_RXTX 4 1601 #define M_FW_RI_CQE_RXTX 0x1 1602 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1603 #define G_FW_RI_CQE_RXTX(x) \ 1604 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1605 1606 #define S_FW_RI_CQE_TYPE 0 1607 #define M_FW_RI_CQE_TYPE 0xf 1608 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1609 #define G_FW_RI_CQE_TYPE(x) \ 1610 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1611 1612 enum fw_res_type { 1613 FW_RI_RES_TYPE_SQ, 1614 FW_RI_RES_TYPE_RQ, 1615 FW_RI_RES_TYPE_CQ, 1616 FW_RI_RES_TYPE_SRQ, 1617 FW_QP_RES_TYPE_SQ = FW_RI_RES_TYPE_SQ, 1618 FW_QP_RES_TYPE_CQ = FW_RI_RES_TYPE_CQ, 1619 }; 1620 1621 enum fw_res_op { 1622 FW_RI_RES_OP_WRITE, 1623 FW_RI_RES_OP_RESET, 1624 FW_QP_RES_OP_WRITE = FW_RI_RES_OP_WRITE, 1625 FW_QP_RES_OP_RESET = FW_RI_RES_OP_RESET, 1626 }; 1627 1628 enum fw_qp_transport_type { 1629 FW_QP_TRANSPORT_TYPE_IWARP, 1630 FW_QP_TRANSPORT_TYPE_ROCEV2_UD, 1631 FW_QP_TRANSPORT_TYPE_ROCEV2_RC, 1632 FW_QP_TRANSPORT_TYPE_ROCEV2_XRC_INI, 1633 FW_QP_TRANSPORT_TYPE_ROCEV2_XRC_TGT, 1634 FW_QP_TRANSPORT_TYPE_NVMET, 1635 FW_QP_TRANSPORT_TYPE_TOE, 1636 FW_QP_TRANSPORT_TYPE_ISCSI, 1637 }; 1638 1639 struct fw_qp_res { 1640 union fw_qp_restype { 1641 struct fw_qp_res_sqrq { 1642 __u8 restype; 1643 __u8 op; 1644 __be16 r3; 1645 __be32 eqid; 1646 __be32 r4[2]; 1647 __be32 fetchszm_to_iqid; 1648 __be32 dcaen_to_eqsize; 1649 __be64 eqaddr; 1650 } sqrq; 1651 struct fw_qp_res_cq { 1652 __u8 restype; 1653 __u8 op; 1654 __be16 r3; 1655 __be32 iqid; 1656 __be32 r4[2]; 1657 __be32 iqandst_to_iqandstindex; 1658 __be16 iqdroprss_to_iqesize; 1659 __be16 iqsize; 1660 __be64 iqaddr; 1661 __be32 iqns_iqro; 1662 __be32 r6_lo; 1663 __be64 r7; 1664 } cq; 1665 } u; 1666 }; 1667 1668 struct fw_qp_res_wr { 1669 __be32 op_to_nres; 1670 __be32 len16_pkd; 1671 __u64 cookie; 1672 #ifndef C99_NOT_SUPPORTED 1673 struct fw_qp_res res[0]; 1674 #endif 1675 }; 1676 1677 #define S_FW_QP_RES_WR_TRANSPORT_TYPE 16 1678 #define M_FW_QP_RES_WR_TRANSPORT_TYPE 0x7 1679 #define V_FW_QP_RES_WR_TRANSPORT_TYPE(x) \ 1680 ((x) << S_FW_QP_RES_WR_TRANSPORT_TYPE) 1681 #define G_FW_QP_RES_WR_TRANSPORT_TYPE(x) \ 1682 (((x) >> S_FW_QP_RES_WR_TRANSPORT_TYPE) & M_FW_QP_RES_WR_TRANSPORT_TYPE) 1683 1684 #define S_FW_QP_RES_WR_VFN 8 1685 #define M_FW_QP_RES_WR_VFN 0xff 1686 #define V_FW_QP_RES_WR_VFN(x) ((x) << S_FW_QP_RES_WR_VFN) 1687 #define G_FW_QP_RES_WR_VFN(x) \ 1688 (((x) >> S_FW_QP_RES_WR_VFN) & M_FW_QP_RES_WR_VFN) 1689 1690 #define S_FW_QP_RES_WR_NRES 0 1691 #define M_FW_QP_RES_WR_NRES 0xff 1692 #define V_FW_QP_RES_WR_NRES(x) ((x) << S_FW_QP_RES_WR_NRES) 1693 #define G_FW_QP_RES_WR_NRES(x) \ 1694 (((x) >> S_FW_QP_RES_WR_NRES) & M_FW_QP_RES_WR_NRES) 1695 1696 #define S_FW_QP_RES_WR_FETCHSZM 26 1697 #define M_FW_QP_RES_WR_FETCHSZM 0x1 1698 #define V_FW_QP_RES_WR_FETCHSZM(x) ((x) << S_FW_QP_RES_WR_FETCHSZM) 1699 #define G_FW_QP_RES_WR_FETCHSZM(x) \ 1700 (((x) >> S_FW_QP_RES_WR_FETCHSZM) & M_FW_QP_RES_WR_FETCHSZM) 1701 #define F_FW_QP_RES_WR_FETCHSZM V_FW_QP_RES_WR_FETCHSZM(1U) 1702 1703 #define S_FW_QP_RES_WR_STATUSPGNS 25 1704 #define M_FW_QP_RES_WR_STATUSPGNS 0x1 1705 #define V_FW_QP_RES_WR_STATUSPGNS(x) ((x) << S_FW_QP_RES_WR_STATUSPGNS) 1706 #define G_FW_QP_RES_WR_STATUSPGNS(x) \ 1707 (((x) >> S_FW_QP_RES_WR_STATUSPGNS) & M_FW_QP_RES_WR_STATUSPGNS) 1708 #define F_FW_QP_RES_WR_STATUSPGNS V_FW_QP_RES_WR_STATUSPGNS(1U) 1709 1710 #define S_FW_QP_RES_WR_STATUSPGRO 24 1711 #define M_FW_QP_RES_WR_STATUSPGRO 0x1 1712 #define V_FW_QP_RES_WR_STATUSPGRO(x) ((x) << S_FW_QP_RES_WR_STATUSPGRO) 1713 #define G_FW_QP_RES_WR_STATUSPGRO(x) \ 1714 (((x) >> S_FW_QP_RES_WR_STATUSPGRO) & M_FW_QP_RES_WR_STATUSPGRO) 1715 #define F_FW_QP_RES_WR_STATUSPGRO V_FW_QP_RES_WR_STATUSPGRO(1U) 1716 1717 #define S_FW_QP_RES_WR_FETCHNS 23 1718 #define M_FW_QP_RES_WR_FETCHNS 0x1 1719 #define V_FW_QP_RES_WR_FETCHNS(x) ((x) << S_FW_QP_RES_WR_FETCHNS) 1720 #define G_FW_QP_RES_WR_FETCHNS(x) \ 1721 (((x) >> S_FW_QP_RES_WR_FETCHNS) & M_FW_QP_RES_WR_FETCHNS) 1722 #define F_FW_QP_RES_WR_FETCHNS V_FW_QP_RES_WR_FETCHNS(1U) 1723 1724 #define S_FW_QP_RES_WR_FETCHRO 22 1725 #define M_FW_QP_RES_WR_FETCHRO 0x1 1726 #define V_FW_QP_RES_WR_FETCHRO(x) ((x) << S_FW_QP_RES_WR_FETCHRO) 1727 #define G_FW_QP_RES_WR_FETCHRO(x) \ 1728 (((x) >> S_FW_QP_RES_WR_FETCHRO) & M_FW_QP_RES_WR_FETCHRO) 1729 #define F_FW_QP_RES_WR_FETCHRO V_FW_QP_RES_WR_FETCHRO(1U) 1730 1731 #define S_FW_QP_RES_WR_HOSTFCMODE 20 1732 #define M_FW_QP_RES_WR_HOSTFCMODE 0x3 1733 #define V_FW_QP_RES_WR_HOSTFCMODE(x) ((x) << S_FW_QP_RES_WR_HOSTFCMODE) 1734 #define G_FW_QP_RES_WR_HOSTFCMODE(x) \ 1735 (((x) >> S_FW_QP_RES_WR_HOSTFCMODE) & M_FW_QP_RES_WR_HOSTFCMODE) 1736 1737 #define S_FW_QP_RES_WR_CPRIO 19 1738 #define M_FW_QP_RES_WR_CPRIO 0x1 1739 #define V_FW_QP_RES_WR_CPRIO(x) ((x) << S_FW_QP_RES_WR_CPRIO) 1740 #define G_FW_QP_RES_WR_CPRIO(x) \ 1741 (((x) >> S_FW_QP_RES_WR_CPRIO) & M_FW_QP_RES_WR_CPRIO) 1742 #define F_FW_QP_RES_WR_CPRIO V_FW_QP_RES_WR_CPRIO(1U) 1743 1744 #define S_FW_QP_RES_WR_ONCHIP 18 1745 #define M_FW_QP_RES_WR_ONCHIP 0x1 1746 #define V_FW_QP_RES_WR_ONCHIP(x) ((x) << S_FW_QP_RES_WR_ONCHIP) 1747 #define G_FW_QP_RES_WR_ONCHIP(x) \ 1748 (((x) >> S_FW_QP_RES_WR_ONCHIP) & M_FW_QP_RES_WR_ONCHIP) 1749 #define F_FW_QP_RES_WR_ONCHIP V_FW_QP_RES_WR_ONCHIP(1U) 1750 1751 #define S_FW_QP_RES_WR_PCIECHN 16 1752 #define M_FW_QP_RES_WR_PCIECHN 0x3 1753 #define V_FW_QP_RES_WR_PCIECHN(x) ((x) << S_FW_QP_RES_WR_PCIECHN) 1754 #define G_FW_QP_RES_WR_PCIECHN(x) \ 1755 (((x) >> S_FW_QP_RES_WR_PCIECHN) & M_FW_QP_RES_WR_PCIECHN) 1756 1757 #define S_FW_QP_RES_WR_IQID 0 1758 #define M_FW_QP_RES_WR_IQID 0xffff 1759 #define V_FW_QP_RES_WR_IQID(x) ((x) << S_FW_QP_RES_WR_IQID) 1760 #define G_FW_QP_RES_WR_IQID(x) \ 1761 (((x) >> S_FW_QP_RES_WR_IQID) & M_FW_QP_RES_WR_IQID) 1762 1763 #define S_FW_QP_RES_WR_DCAEN 31 1764 #define M_FW_QP_RES_WR_DCAEN 0x1 1765 #define V_FW_QP_RES_WR_DCAEN(x) ((x) << S_FW_QP_RES_WR_DCAEN) 1766 #define G_FW_QP_RES_WR_DCAEN(x) \ 1767 (((x) >> S_FW_QP_RES_WR_DCAEN) & M_FW_QP_RES_WR_DCAEN) 1768 #define F_FW_QP_RES_WR_DCAEN V_FW_QP_RES_WR_DCAEN(1U) 1769 1770 #define S_FW_QP_RES_WR_DCACPU 26 1771 #define M_FW_QP_RES_WR_DCACPU 0x1f 1772 #define V_FW_QP_RES_WR_DCACPU(x) ((x) << S_FW_QP_RES_WR_DCACPU) 1773 #define G_FW_QP_RES_WR_DCACPU(x) \ 1774 (((x) >> S_FW_QP_RES_WR_DCACPU) & M_FW_QP_RES_WR_DCACPU) 1775 1776 #define S_FW_QP_RES_WR_FBMIN 23 1777 #define M_FW_QP_RES_WR_FBMIN 0x7 1778 #define V_FW_QP_RES_WR_FBMIN(x) ((x) << S_FW_QP_RES_WR_FBMIN) 1779 #define G_FW_QP_RES_WR_FBMIN(x) \ 1780 (((x) >> S_FW_QP_RES_WR_FBMIN) & M_FW_QP_RES_WR_FBMIN) 1781 1782 #define S_FW_QP_RES_WR_FBMAX 20 1783 #define M_FW_QP_RES_WR_FBMAX 0x7 1784 #define V_FW_QP_RES_WR_FBMAX(x) ((x) << S_FW_QP_RES_WR_FBMAX) 1785 #define G_FW_QP_RES_WR_FBMAX(x) \ 1786 (((x) >> S_FW_QP_RES_WR_FBMAX) & M_FW_QP_RES_WR_FBMAX) 1787 1788 #define S_FW_QP_RES_WR_CIDXFTHRESHO 19 1789 #define M_FW_QP_RES_WR_CIDXFTHRESHO 0x1 1790 #define V_FW_QP_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_QP_RES_WR_CIDXFTHRESHO) 1791 #define G_FW_QP_RES_WR_CIDXFTHRESHO(x) \ 1792 (((x) >> S_FW_QP_RES_WR_CIDXFTHRESHO) & M_FW_QP_RES_WR_CIDXFTHRESHO) 1793 #define F_FW_QP_RES_WR_CIDXFTHRESHO V_FW_QP_RES_WR_CIDXFTHRESHO(1U) 1794 1795 #define S_FW_QP_RES_WR_CIDXFTHRESH 16 1796 #define M_FW_QP_RES_WR_CIDXFTHRESH 0x7 1797 #define V_FW_QP_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_QP_RES_WR_CIDXFTHRESH) 1798 #define G_FW_QP_RES_WR_CIDXFTHRESH(x) \ 1799 (((x) >> S_FW_QP_RES_WR_CIDXFTHRESH) & M_FW_QP_RES_WR_CIDXFTHRESH) 1800 1801 #define S_FW_QP_RES_WR_EQSIZE 0 1802 #define M_FW_QP_RES_WR_EQSIZE 0xffff 1803 #define V_FW_QP_RES_WR_EQSIZE(x) ((x) << S_FW_QP_RES_WR_EQSIZE) 1804 #define G_FW_QP_RES_WR_EQSIZE(x) \ 1805 (((x) >> S_FW_QP_RES_WR_EQSIZE) & M_FW_QP_RES_WR_EQSIZE) 1806 1807 #define S_FW_QP_RES_WR_IQANDST 15 1808 #define M_FW_QP_RES_WR_IQANDST 0x1 1809 #define V_FW_QP_RES_WR_IQANDST(x) ((x) << S_FW_QP_RES_WR_IQANDST) 1810 #define G_FW_QP_RES_WR_IQANDST(x) \ 1811 (((x) >> S_FW_QP_RES_WR_IQANDST) & M_FW_QP_RES_WR_IQANDST) 1812 #define F_FW_QP_RES_WR_IQANDST V_FW_QP_RES_WR_IQANDST(1U) 1813 1814 #define S_FW_QP_RES_WR_IQANUS 14 1815 #define M_FW_QP_RES_WR_IQANUS 0x1 1816 #define V_FW_QP_RES_WR_IQANUS(x) ((x) << S_FW_QP_RES_WR_IQANUS) 1817 #define G_FW_QP_RES_WR_IQANUS(x) \ 1818 (((x) >> S_FW_QP_RES_WR_IQANUS) & M_FW_QP_RES_WR_IQANUS) 1819 #define F_FW_QP_RES_WR_IQANUS V_FW_QP_RES_WR_IQANUS(1U) 1820 1821 #define S_FW_QP_RES_WR_IQANUD 12 1822 #define M_FW_QP_RES_WR_IQANUD 0x3 1823 #define V_FW_QP_RES_WR_IQANUD(x) ((x) << S_FW_QP_RES_WR_IQANUD) 1824 #define G_FW_QP_RES_WR_IQANUD(x) \ 1825 (((x) >> S_FW_QP_RES_WR_IQANUD) & M_FW_QP_RES_WR_IQANUD) 1826 1827 #define S_FW_QP_RES_WR_IQANDSTINDEX 0 1828 #define M_FW_QP_RES_WR_IQANDSTINDEX 0xfff 1829 #define V_FW_QP_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_QP_RES_WR_IQANDSTINDEX) 1830 #define G_FW_QP_RES_WR_IQANDSTINDEX(x) \ 1831 (((x) >> S_FW_QP_RES_WR_IQANDSTINDEX) & M_FW_QP_RES_WR_IQANDSTINDEX) 1832 1833 #define S_FW_QP_RES_WR_IQDROPRSS 15 1834 #define M_FW_QP_RES_WR_IQDROPRSS 0x1 1835 #define V_FW_QP_RES_WR_IQDROPRSS(x) ((x) << S_FW_QP_RES_WR_IQDROPRSS) 1836 #define G_FW_QP_RES_WR_IQDROPRSS(x) \ 1837 (((x) >> S_FW_QP_RES_WR_IQDROPRSS) & M_FW_QP_RES_WR_IQDROPRSS) 1838 #define F_FW_QP_RES_WR_IQDROPRSS V_FW_QP_RES_WR_IQDROPRSS(1U) 1839 1840 #define S_FW_QP_RES_WR_IQGTSMODE 14 1841 #define M_FW_QP_RES_WR_IQGTSMODE 0x1 1842 #define V_FW_QP_RES_WR_IQGTSMODE(x) ((x) << S_FW_QP_RES_WR_IQGTSMODE) 1843 #define G_FW_QP_RES_WR_IQGTSMODE(x) \ 1844 (((x) >> S_FW_QP_RES_WR_IQGTSMODE) & M_FW_QP_RES_WR_IQGTSMODE) 1845 #define F_FW_QP_RES_WR_IQGTSMODE V_FW_QP_RES_WR_IQGTSMODE(1U) 1846 1847 #define S_FW_QP_RES_WR_IQPCIECH 12 1848 #define M_FW_QP_RES_WR_IQPCIECH 0x3 1849 #define V_FW_QP_RES_WR_IQPCIECH(x) ((x) << S_FW_QP_RES_WR_IQPCIECH) 1850 #define G_FW_QP_RES_WR_IQPCIECH(x) \ 1851 (((x) >> S_FW_QP_RES_WR_IQPCIECH) & M_FW_QP_RES_WR_IQPCIECH) 1852 1853 #define S_FW_QP_RES_WR_IQDCAEN 11 1854 #define M_FW_QP_RES_WR_IQDCAEN 0x1 1855 #define V_FW_QP_RES_WR_IQDCAEN(x) ((x) << S_FW_QP_RES_WR_IQDCAEN) 1856 #define G_FW_QP_RES_WR_IQDCAEN(x) \ 1857 (((x) >> S_FW_QP_RES_WR_IQDCAEN) & M_FW_QP_RES_WR_IQDCAEN) 1858 #define F_FW_QP_RES_WR_IQDCAEN V_FW_QP_RES_WR_IQDCAEN(1U) 1859 1860 #define S_FW_QP_RES_WR_IQDCACPU 6 1861 #define M_FW_QP_RES_WR_IQDCACPU 0x1f 1862 #define V_FW_QP_RES_WR_IQDCACPU(x) ((x) << S_FW_QP_RES_WR_IQDCACPU) 1863 #define G_FW_QP_RES_WR_IQDCACPU(x) \ 1864 (((x) >> S_FW_QP_RES_WR_IQDCACPU) & M_FW_QP_RES_WR_IQDCACPU) 1865 1866 #define S_FW_QP_RES_WR_IQINTCNTTHRESH 4 1867 #define M_FW_QP_RES_WR_IQINTCNTTHRESH 0x3 1868 #define V_FW_QP_RES_WR_IQINTCNTTHRESH(x) \ 1869 ((x) << S_FW_QP_RES_WR_IQINTCNTTHRESH) 1870 #define G_FW_QP_RES_WR_IQINTCNTTHRESH(x) \ 1871 (((x) >> S_FW_QP_RES_WR_IQINTCNTTHRESH) & M_FW_QP_RES_WR_IQINTCNTTHRESH) 1872 1873 #define S_FW_QP_RES_WR_IQO 3 1874 #define M_FW_QP_RES_WR_IQO 0x1 1875 #define V_FW_QP_RES_WR_IQO(x) ((x) << S_FW_QP_RES_WR_IQO) 1876 #define G_FW_QP_RES_WR_IQO(x) \ 1877 (((x) >> S_FW_QP_RES_WR_IQO) & M_FW_QP_RES_WR_IQO) 1878 #define F_FW_QP_RES_WR_IQO V_FW_QP_RES_WR_IQO(1U) 1879 1880 #define S_FW_QP_RES_WR_IQCPRIO 2 1881 #define M_FW_QP_RES_WR_IQCPRIO 0x1 1882 #define V_FW_QP_RES_WR_IQCPRIO(x) ((x) << S_FW_QP_RES_WR_IQCPRIO) 1883 #define G_FW_QP_RES_WR_IQCPRIO(x) \ 1884 (((x) >> S_FW_QP_RES_WR_IQCPRIO) & M_FW_QP_RES_WR_IQCPRIO) 1885 #define F_FW_QP_RES_WR_IQCPRIO V_FW_QP_RES_WR_IQCPRIO(1U) 1886 1887 #define S_FW_QP_RES_WR_IQESIZE 0 1888 #define M_FW_QP_RES_WR_IQESIZE 0x3 1889 #define V_FW_QP_RES_WR_IQESIZE(x) ((x) << S_FW_QP_RES_WR_IQESIZE) 1890 #define G_FW_QP_RES_WR_IQESIZE(x) \ 1891 (((x) >> S_FW_QP_RES_WR_IQESIZE) & M_FW_QP_RES_WR_IQESIZE) 1892 1893 #define S_FW_QP_RES_WR_IQNS 31 1894 #define M_FW_QP_RES_WR_IQNS 0x1 1895 #define V_FW_QP_RES_WR_IQNS(x) ((x) << S_FW_QP_RES_WR_IQNS) 1896 #define G_FW_QP_RES_WR_IQNS(x) \ 1897 (((x) >> S_FW_QP_RES_WR_IQNS) & M_FW_QP_RES_WR_IQNS) 1898 #define F_FW_QP_RES_WR_IQNS V_FW_QP_RES_WR_IQNS(1U) 1899 1900 #define S_FW_QP_RES_WR_IQRO 30 1901 #define M_FW_QP_RES_WR_IQRO 0x1 1902 #define V_FW_QP_RES_WR_IQRO(x) ((x) << S_FW_QP_RES_WR_IQRO) 1903 #define G_FW_QP_RES_WR_IQRO(x) \ 1904 (((x) >> S_FW_QP_RES_WR_IQRO) & M_FW_QP_RES_WR_IQRO) 1905 #define F_FW_QP_RES_WR_IQRO V_FW_QP_RES_WR_IQRO(1U) 1906 1907 1908 struct fw_ri_res { 1909 union fw_ri_restype { 1910 struct fw_ri_res_sqrq { 1911 __u8 restype; 1912 __u8 op; 1913 __be16 r3; 1914 __be32 eqid; 1915 __be32 r4[2]; 1916 __be32 fetchszm_to_iqid; 1917 __be32 dcaen_to_eqsize; 1918 __be64 eqaddr; 1919 } sqrq; 1920 struct fw_ri_res_cq { 1921 __u8 restype; 1922 __u8 op; 1923 __be16 r3; 1924 __be32 iqid; 1925 __be32 r4[2]; 1926 __be32 iqandst_to_iqandstindex; 1927 __be16 iqdroprss_to_iqesize; 1928 __be16 iqsize; 1929 __be64 iqaddr; 1930 __be32 iqns_iqro; 1931 __be32 r6_lo; 1932 __be64 r7; 1933 } cq; 1934 struct fw_ri_res_srq { 1935 __u8 restype; 1936 __u8 op; 1937 __be16 r3; 1938 __be32 eqid; 1939 __be32 r4[2]; 1940 __be32 fetchszm_to_iqid; 1941 __be32 dcaen_to_eqsize; 1942 __be64 eqaddr; 1943 __be32 srqid; 1944 __be32 pdid; 1945 __be32 hwsrqsize; 1946 __be32 hwsrqaddr; 1947 } srq; 1948 } u; 1949 }; 1950 1951 struct fw_ri_res_wr { 1952 __be32 op_nres; 1953 __be32 len16_pkd; 1954 __u64 cookie; 1955 #ifndef C99_NOT_SUPPORTED 1956 struct fw_ri_res res[0]; 1957 #endif 1958 }; 1959 1960 #define S_FW_RI_RES_WR_TRANSPORT_TYPE 16 1961 #define M_FW_RI_RES_WR_TRANSPORT_TYPE 0x7 1962 #define V_FW_RI_RES_WR_TRANSPORT_TYPE(x) \ 1963 ((x) << S_FW_RI_RES_WR_TRANSPORT_TYPE) 1964 #define G_FW_RI_RES_WR_TRANSPORT_TYPE(x) \ 1965 (((x) >> S_FW_RI_RES_WR_TRANSPORT_TYPE) & M_FW_RI_RES_WR_TRANSPORT_TYPE) 1966 1967 #define S_FW_RI_RES_WR_VFN 8 1968 #define M_FW_RI_RES_WR_VFN 0xff 1969 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1970 #define G_FW_RI_RES_WR_VFN(x) \ 1971 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1972 1973 #define S_FW_RI_RES_WR_NRES 0 1974 #define M_FW_RI_RES_WR_NRES 0xff 1975 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1976 #define G_FW_RI_RES_WR_NRES(x) \ 1977 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1978 1979 #define S_FW_RI_RES_WR_FETCHSZM 26 1980 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1981 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1982 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1983 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1984 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1985 1986 #define S_FW_RI_RES_WR_STATUSPGNS 25 1987 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1988 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1989 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1990 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1991 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1992 1993 #define S_FW_RI_RES_WR_STATUSPGRO 24 1994 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1995 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1996 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1997 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1998 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1999 2000 #define S_FW_RI_RES_WR_FETCHNS 23 2001 #define M_FW_RI_RES_WR_FETCHNS 0x1 2002 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 2003 #define G_FW_RI_RES_WR_FETCHNS(x) \ 2004 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 2005 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 2006 2007 #define S_FW_RI_RES_WR_FETCHRO 22 2008 #define M_FW_RI_RES_WR_FETCHRO 0x1 2009 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 2010 #define G_FW_RI_RES_WR_FETCHRO(x) \ 2011 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 2012 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 2013 2014 #define S_FW_RI_RES_WR_HOSTFCMODE 20 2015 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 2016 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 2017 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 2018 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 2019 2020 #define S_FW_RI_RES_WR_CPRIO 19 2021 #define M_FW_RI_RES_WR_CPRIO 0x1 2022 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 2023 #define G_FW_RI_RES_WR_CPRIO(x) \ 2024 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 2025 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 2026 2027 #define S_FW_RI_RES_WR_ONCHIP 18 2028 #define M_FW_RI_RES_WR_ONCHIP 0x1 2029 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 2030 #define G_FW_RI_RES_WR_ONCHIP(x) \ 2031 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 2032 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 2033 2034 #define S_FW_RI_RES_WR_PCIECHN 16 2035 #define M_FW_RI_RES_WR_PCIECHN 0x3 2036 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 2037 #define G_FW_RI_RES_WR_PCIECHN(x) \ 2038 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 2039 2040 #define S_FW_RI_RES_WR_IQID 0 2041 #define M_FW_RI_RES_WR_IQID 0xffff 2042 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 2043 #define G_FW_RI_RES_WR_IQID(x) \ 2044 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 2045 2046 #define S_FW_RI_RES_WR_DCAEN 31 2047 #define M_FW_RI_RES_WR_DCAEN 0x1 2048 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 2049 #define G_FW_RI_RES_WR_DCAEN(x) \ 2050 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 2051 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 2052 2053 #define S_FW_RI_RES_WR_DCACPU 26 2054 #define M_FW_RI_RES_WR_DCACPU 0x1f 2055 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 2056 #define G_FW_RI_RES_WR_DCACPU(x) \ 2057 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 2058 2059 #define S_FW_RI_RES_WR_FBMIN 23 2060 #define M_FW_RI_RES_WR_FBMIN 0x7 2061 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 2062 #define G_FW_RI_RES_WR_FBMIN(x) \ 2063 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 2064 2065 #define S_FW_RI_RES_WR_FBMAX 20 2066 #define M_FW_RI_RES_WR_FBMAX 0x7 2067 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 2068 #define G_FW_RI_RES_WR_FBMAX(x) \ 2069 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 2070 2071 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 2072 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 2073 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 2074 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 2075 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 2076 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 2077 2078 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 2079 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 2080 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 2081 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 2082 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 2083 2084 #define S_FW_RI_RES_WR_EQSIZE 0 2085 #define M_FW_RI_RES_WR_EQSIZE 0xffff 2086 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 2087 #define G_FW_RI_RES_WR_EQSIZE(x) \ 2088 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 2089 2090 #define S_FW_RI_RES_WR_IQANDST 15 2091 #define M_FW_RI_RES_WR_IQANDST 0x1 2092 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 2093 #define G_FW_RI_RES_WR_IQANDST(x) \ 2094 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 2095 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 2096 2097 #define S_FW_RI_RES_WR_IQANUS 14 2098 #define M_FW_RI_RES_WR_IQANUS 0x1 2099 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 2100 #define G_FW_RI_RES_WR_IQANUS(x) \ 2101 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 2102 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 2103 2104 #define S_FW_RI_RES_WR_IQANUD 12 2105 #define M_FW_RI_RES_WR_IQANUD 0x3 2106 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 2107 #define G_FW_RI_RES_WR_IQANUD(x) \ 2108 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 2109 2110 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 2111 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 2112 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 2113 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 2114 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 2115 2116 #define S_FW_RI_RES_WR_IQDROPRSS 15 2117 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 2118 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 2119 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 2120 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 2121 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 2122 2123 #define S_FW_RI_RES_WR_IQGTSMODE 14 2124 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 2125 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 2126 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 2127 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 2128 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 2129 2130 #define S_FW_RI_RES_WR_IQPCIECH 12 2131 #define M_FW_RI_RES_WR_IQPCIECH 0x3 2132 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 2133 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 2134 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 2135 2136 #define S_FW_RI_RES_WR_IQDCAEN 11 2137 #define M_FW_RI_RES_WR_IQDCAEN 0x1 2138 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 2139 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 2140 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 2141 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 2142 2143 #define S_FW_RI_RES_WR_IQDCACPU 6 2144 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 2145 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 2146 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 2147 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 2148 2149 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 2150 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 2151 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 2152 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 2153 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 2154 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 2155 2156 #define S_FW_RI_RES_WR_IQO 3 2157 #define M_FW_RI_RES_WR_IQO 0x1 2158 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 2159 #define G_FW_RI_RES_WR_IQO(x) \ 2160 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 2161 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 2162 2163 #define S_FW_RI_RES_WR_IQCPRIO 2 2164 #define M_FW_RI_RES_WR_IQCPRIO 0x1 2165 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 2166 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 2167 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 2168 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 2169 2170 #define S_FW_RI_RES_WR_IQESIZE 0 2171 #define M_FW_RI_RES_WR_IQESIZE 0x3 2172 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 2173 #define G_FW_RI_RES_WR_IQESIZE(x) \ 2174 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 2175 2176 #define S_FW_RI_RES_WR_IQNS 31 2177 #define M_FW_RI_RES_WR_IQNS 0x1 2178 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 2179 #define G_FW_RI_RES_WR_IQNS(x) \ 2180 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 2181 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 2182 2183 #define S_FW_RI_RES_WR_IQRO 30 2184 #define M_FW_RI_RES_WR_IQRO 0x1 2185 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 2186 #define G_FW_RI_RES_WR_IQRO(x) \ 2187 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 2188 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 2189 2190 struct fw_ri_rdma_write_wr { 2191 __u8 opcode; 2192 __u8 flags; 2193 __u16 wrid; 2194 __u8 r1[3]; 2195 __u8 len16; 2196 __u64 immd_data; 2197 __be32 plen; 2198 __be32 stag_sink; 2199 __be64 to_sink; 2200 #ifndef C99_NOT_SUPPORTED 2201 union { 2202 struct fw_ri_immd immd_src[0]; 2203 struct fw_ri_isgl isgl_src[0]; 2204 } u; 2205 #endif 2206 }; 2207 2208 struct fw_ri_send_wr { 2209 __u8 opcode; 2210 __u8 flags; 2211 __u16 wrid; 2212 __u8 r1[3]; 2213 __u8 len16; 2214 __be32 sendop_pkd; 2215 __be32 stag_inv; 2216 __be32 plen; 2217 __be32 r3; 2218 __be64 r4; 2219 #ifndef C99_NOT_SUPPORTED 2220 union { 2221 struct fw_ri_immd immd_src[0]; 2222 struct fw_ri_isgl isgl_src[0]; 2223 } u; 2224 #endif 2225 }; 2226 2227 #define S_FW_RI_SEND_WR_SENDOP 0 2228 #define M_FW_RI_SEND_WR_SENDOP 0xf 2229 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 2230 #define G_FW_RI_SEND_WR_SENDOP(x) \ 2231 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 2232 2233 struct fw_ri_rdma_write_cmpl_wr { 2234 __u8 opcode; 2235 __u8 flags; 2236 __u16 wrid; 2237 __u8 r1[3]; 2238 __u8 len16; 2239 __u8 r2; 2240 __u8 flags_send; 2241 __u16 wrid_send; 2242 __be32 stag_inv; 2243 __be32 plen; 2244 __be32 stag_sink; 2245 __be64 to_sink; 2246 union fw_ri_cmpl { 2247 struct fw_ri_immd_cmpl { 2248 __u8 op; 2249 __u8 r1[6]; 2250 __u8 immdlen; 2251 __u8 data[16]; 2252 } immd_src; 2253 struct fw_ri_isgl isgl_src; 2254 } u_cmpl; 2255 __be64 r3; 2256 #ifndef C99_NOT_SUPPORTED 2257 union fw_ri_write { 2258 struct fw_ri_immd immd_src[0]; 2259 struct fw_ri_isgl isgl_src[0]; 2260 } u; 2261 #endif 2262 }; 2263 2264 struct fw_ri_rdma_read_wr { 2265 __u8 opcode; 2266 __u8 flags; 2267 __u16 wrid; 2268 __u8 r1[3]; 2269 __u8 len16; 2270 __be64 r2; 2271 __be32 stag_sink; 2272 __be32 to_sink_hi; 2273 __be32 to_sink_lo; 2274 __be32 plen; 2275 __be32 stag_src; 2276 __be32 to_src_hi; 2277 __be32 to_src_lo; 2278 __be32 r5; 2279 }; 2280 2281 struct fw_ri_recv_wr { 2282 __u8 opcode; 2283 __u8 r1; 2284 __u16 wrid; 2285 __u8 r2[3]; 2286 __u8 len16; 2287 struct fw_ri_isgl isgl; 2288 }; 2289 2290 struct fw_ri_bind_mw_wr { 2291 __u8 opcode; 2292 __u8 flags; 2293 __u16 wrid; 2294 __u8 r1[3]; 2295 __u8 len16; 2296 __u8 qpbinde_to_dcacpu; 2297 __u8 pgsz_shift; 2298 __u8 addr_type; 2299 __u8 mem_perms; 2300 __be32 stag_mr; 2301 __be32 stag_mw; 2302 __be32 r3; 2303 __be64 len_mw; 2304 __be64 va_fbo; 2305 __be64 r4; 2306 }; 2307 2308 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 2309 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 2310 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 2311 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 2312 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 2313 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 2314 2315 #define S_FW_RI_BIND_MW_WR_NS 5 2316 #define M_FW_RI_BIND_MW_WR_NS 0x1 2317 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 2318 #define G_FW_RI_BIND_MW_WR_NS(x) \ 2319 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 2320 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 2321 2322 #define S_FW_RI_BIND_MW_WR_DCACPU 0 2323 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 2324 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 2325 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 2326 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 2327 2328 struct fw_ri_fr_nsmr_wr { 2329 __u8 opcode; 2330 __u8 flags; 2331 __u16 wrid; 2332 __u8 r1[3]; 2333 __u8 len16; 2334 __u8 qpbinde_to_dcacpu; 2335 __u8 pgsz_shift; 2336 __u8 addr_type; 2337 __u8 mem_perms; 2338 __be32 stag; 2339 __be32 len_hi; 2340 __be32 len_lo; 2341 __be32 va_hi; 2342 __be32 va_lo_fbo; 2343 }; 2344 2345 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 2346 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 2347 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 2348 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 2349 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 2350 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 2351 2352 #define S_FW_RI_FR_NSMR_WR_NS 5 2353 #define M_FW_RI_FR_NSMR_WR_NS 0x1 2354 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 2355 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 2356 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 2357 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 2358 2359 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 2360 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 2361 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 2362 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 2363 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 2364 2365 struct fw_ri_fr_nsmr_tpte_wr { 2366 __u8 opcode; 2367 __u8 flags; 2368 __u16 wrid; 2369 __u8 r1[3]; 2370 __u8 len16; 2371 __be32 r2; 2372 __be32 stag; 2373 struct fw_ri_tpte tpte; 2374 __be64 pbl[2]; 2375 }; 2376 2377 struct fw_ri_inv_lstag_wr { 2378 __u8 opcode; 2379 __u8 flags; 2380 __u16 wrid; 2381 __u8 r1[3]; 2382 __u8 len16; 2383 __be32 r2; 2384 __be32 stag_inv; 2385 }; 2386 2387 struct fw_ri_send_immediate_wr { 2388 __u8 opcode; 2389 __u8 flags; 2390 __u16 wrid; 2391 __u8 r1[3]; 2392 __u8 len16; 2393 __be32 sendimmop_pkd; 2394 __be32 r3; 2395 __be32 plen; 2396 __be32 r4; 2397 __be64 r5; 2398 #ifndef C99_NOT_SUPPORTED 2399 struct fw_ri_immd immd_src[0]; 2400 #endif 2401 }; 2402 2403 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2404 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2405 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2406 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2407 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2408 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2409 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2410 2411 enum fw_ri_atomic_op { 2412 FW_RI_ATOMIC_OP_FETCHADD, 2413 FW_RI_ATOMIC_OP_SWAP, 2414 FW_RI_ATOMIC_OP_CMDSWAP, 2415 }; 2416 2417 struct fw_ri_atomic_wr { 2418 __u8 opcode; 2419 __u8 flags; 2420 __u16 wrid; 2421 __u8 r1[3]; 2422 __u8 len16; 2423 __be32 atomicop_pkd; 2424 __be64 r3; 2425 __be32 aopcode_pkd; 2426 __be32 reqid; 2427 __be32 stag; 2428 __be32 to_hi; 2429 __be32 to_lo; 2430 __be32 addswap_data_hi; 2431 __be32 addswap_data_lo; 2432 __be32 addswap_mask_hi; 2433 __be32 addswap_mask_lo; 2434 __be32 compare_data_hi; 2435 __be32 compare_data_lo; 2436 __be32 compare_mask_hi; 2437 __be32 compare_mask_lo; 2438 __be32 r5; 2439 }; 2440 2441 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2442 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2443 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2444 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2445 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2446 2447 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2448 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2449 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2450 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2451 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2452 2453 enum fw_ri_type { 2454 FW_RI_TYPE_INIT, 2455 FW_RI_TYPE_FINI, 2456 FW_RI_TYPE_TERMINATE 2457 }; 2458 2459 enum fw_ri_init_p2ptype { 2460 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2461 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2462 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2463 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2464 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2465 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2466 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2467 }; 2468 2469 enum fw_ri_init_rqeqid_srq { 2470 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2471 }; 2472 2473 enum fw_nvmet_ulpsubmode { 2474 FW_NVMET_ULPSUBMODE_HCRC = 0x1<<0, 2475 FW_NVMET_ULPSUBMODE_DCRC = 0x1<<1, 2476 FW_NVMET_ULPSUBMODE_ING_DIR = 0x1<<2, 2477 FW_NVMET_ULPSUBMODE_SRQ_ENABLE = 0x1<<3, 2478 FW_NVMET_ULPSUBMODE_PER_PDU_CMP = 0x1<<4, 2479 FW_NVMET_ULPSUBMODE_PI_ENABLE = 0x1<<5, 2480 FW_NVMET_ULPSUBMODE_USER_MODE = 0x1<<6, 2481 }; 2482 2483 struct fw_ri_wr { 2484 __be32 op_compl; /* op_to_transport_type */ 2485 __be32 flowid_len16; 2486 __u64 cookie; 2487 union fw_ri { 2488 struct fw_ri_init { 2489 __u8 type; 2490 __u8 mpareqbit_p2ptype; 2491 __u8 r4[2]; 2492 __u8 mpa_attrs; 2493 __u8 qp_caps; 2494 __be16 nrqe; 2495 __be32 pdid; 2496 __be32 qpid; 2497 __be32 sq_eqid; 2498 __be32 rq_eqid; 2499 __be32 scqid; 2500 __be32 rcqid; 2501 __be32 ord_max; 2502 __be32 ird_max; 2503 __be32 iss; 2504 __be32 irs; 2505 __be32 hwrqsize; 2506 __be32 hwrqaddr; 2507 __be64 r5; 2508 union fw_ri_init_p2p { 2509 struct fw_ri_rdma_write_wr write; 2510 struct fw_ri_rdma_read_wr read; 2511 struct fw_ri_send_wr send; 2512 } u; 2513 } init; 2514 struct fw_ri_rocev2_init { 2515 __u8 type; 2516 __u8 r3[3]; 2517 __u8 rocev2_flags; 2518 __u8 qp_caps; 2519 __be16 nrqe; 2520 __be32 pdid; 2521 __be32 qpid; 2522 __be32 sq_eqid; 2523 __be32 rq_eqid; 2524 __be32 scqid; 2525 __be32 rcqid; 2526 __be32 ord_max; 2527 __be32 ird_max; 2528 __be32 psn_pkd; 2529 __be32 epsn_pkd; 2530 __be32 hwrqsize; 2531 __be32 hwrqaddr; 2532 __be32 q_key; 2533 __u8 pkthdrsize; 2534 __u8 r; 2535 __be16 p_key; 2536 //struct cpl_tx_tnl_lso tnl_lso; 2537 __u8 tnl_lso[48]; /* cpl_tx_tnl_lso + cpl_tx_pkt_xt */ 2538 #ifndef C99_NOT_SUPPORTED 2539 struct fw_ri_immd pkthdr[0]; 2540 #endif 2541 } rocev2_init; 2542 struct fw_ri_nvmet_init { 2543 __u8 type; 2544 __u8 r3[3]; 2545 __u8 nvmt_flags; 2546 __u8 qp_caps; 2547 __be16 nrqe; 2548 __be32 pdid; 2549 __be32 qpid; 2550 __be32 sq_eqid; 2551 __be32 rq_eqid; 2552 __be32 scqid; 2553 __be32 rcqid; 2554 __be32 r4[4]; 2555 __be32 hwrqsize; 2556 __be32 hwrqaddr; 2557 __u8 ulpsubmode; 2558 __u8 nvmt_pda_cmp_imm_sz; 2559 __be16 r7; 2560 __be32 tpt_offset_t10_config; 2561 __be32 r8[2]; 2562 } nvmet_init; 2563 struct fw_ri_fini { 2564 __u8 type; 2565 __u8 r3[7]; 2566 __be64 r4; 2567 } fini; 2568 struct fw_ri_terminate { 2569 __u8 type; 2570 __u8 r3[3]; 2571 __be32 immdlen; 2572 __u8 termmsg[40]; 2573 } terminate; 2574 } u; 2575 }; 2576 2577 #define S_FW_RI_WR_TRANSPORT_TYPE 16 2578 #define M_FW_RI_WR_TRANSPORT_TYPE 0x7 2579 #define V_FW_RI_WR_TRANSPORT_TYPE(x) ((x) << S_FW_RI_WR_TRANSPORT_TYPE) 2580 #define G_FW_RI_WR_TRANSPORT_TYPE(x) \ 2581 (((x) >> S_FW_RI_WR_TRANSPORT_TYPE) & M_FW_RI_WR_TRANSPORT_TYPE) 2582 2583 #define S_FW_RI_WR_MPAREQBIT 7 2584 #define M_FW_RI_WR_MPAREQBIT 0x1 2585 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2586 #define G_FW_RI_WR_MPAREQBIT(x) \ 2587 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2588 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2589 2590 #define S_FW_RI_WR_0BRRBIT 6 2591 #define M_FW_RI_WR_0BRRBIT 0x1 2592 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2593 #define G_FW_RI_WR_0BRRBIT(x) \ 2594 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2595 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2596 2597 #define S_FW_RI_WR_P2PTYPE 0 2598 #define M_FW_RI_WR_P2PTYPE 0xf 2599 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2600 #define G_FW_RI_WR_P2PTYPE(x) \ 2601 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2602 2603 #define S_FW_RI_WR_PSN 0 2604 #define M_FW_RI_WR_PSN 0xffffff 2605 #define V_FW_RI_WR_PSN(x) ((x) << S_FW_RI_WR_PSN) 2606 #define G_FW_RI_WR_PSN(x) (((x) >> S_FW_RI_WR_PSN) & M_FW_RI_WR_PSN) 2607 2608 #define S_FW_RI_WR_EPSN 0 2609 #define M_FW_RI_WR_EPSN 0xffffff 2610 #define V_FW_RI_WR_EPSN(x) ((x) << S_FW_RI_WR_EPSN) 2611 #define G_FW_RI_WR_EPSN(x) (((x) >> S_FW_RI_WR_EPSN) & M_FW_RI_WR_EPSN) 2612 2613 #define S_FW_RI_WR_NVMT_PDA 3 2614 #define M_FW_RI_WR_NVMT_PDA 0x1f 2615 #define V_FW_RI_WR_NVMT_PDA(x) ((x) << S_FW_RI_WR_NVMT_PDA) 2616 #define G_FW_RI_WR_NVMT_PDA(x) \ 2617 (((x) >> S_FW_RI_WR_NVMT_PDA) & M_FW_RI_WR_NVMT_PDA) 2618 2619 #define S_FW_RI_WR_CMP_IMM_SZ 1 2620 #define M_FW_RI_WR_CMP_IMM_SZ 0x3 2621 #define V_FW_RI_WR_CMP_IMM_SZ(x) ((x) << S_FW_RI_WR_CMP_IMM_SZ) 2622 #define G_FW_RI_WR_CMP_IMM_SZ(x) \ 2623 (((x) >> S_FW_RI_WR_CMP_IMM_SZ) & M_FW_RI_WR_CMP_IMM_SZ) 2624 2625 #define S_FW_RI_WR_TPT_OFFSET 10 2626 #define M_FW_RI_WR_TPT_OFFSET 0x3fffff 2627 #define V_FW_RI_WR_TPT_OFFSET(x) ((x) << S_FW_RI_WR_TPT_OFFSET) 2628 #define G_FW_RI_WR_TPT_OFFSET(x) \ 2629 (((x) >> S_FW_RI_WR_TPT_OFFSET) & M_FW_RI_WR_TPT_OFFSET) 2630 2631 #define S_FW_RI_WR_T10_CONFIG 0 2632 #define M_FW_RI_WR_T10_CONFIG 0x3ff 2633 #define V_FW_RI_WR_T10_CONFIG(x) ((x) << S_FW_RI_WR_T10_CONFIG) 2634 #define G_FW_RI_WR_T10_CONFIG(x) \ 2635 (((x) >> S_FW_RI_WR_T10_CONFIG) & M_FW_RI_WR_T10_CONFIG) 2636 2637 2638 /****************************************************************************** 2639 * R o C E V 2 W O R K R E Q U E S T s 2640 **************************************/ 2641 enum fw_rocev2_wr_opcode { 2642 /* RC */ 2643 FW_ROCEV2_RC_SEND_FIRST = 0x00, 2644 FW_ROCEV2_RC_SEND_MIDDLE = 0x01, 2645 FW_ROCEV2_RC_SEND_LAST = 0x02, 2646 FW_ROCEV2_RC_SEND_LAST_WITH_IMMD = 0x03, 2647 FW_ROCEV2_RC_SEND_ONLY = 0x04, 2648 FW_ROCEV2_RC_SEND_ONLY_WITH_IMMD = 0x05, 2649 FW_ROCEV2_RC_RDMA_WRITE_FIRST = 0x06, 2650 FW_ROCEV2_RC_RDMA_WRITE_MIDDLE = 0x07, 2651 FW_ROCEV2_RC_RDMA_WRITE_LAST = 0x08, 2652 FW_ROCEV2_RC_RDMA_WRITE_LAST_WITH_IMMD = 0x09, 2653 FW_ROCEV2_RC_RDMA_WRITE_ONLY = 0x0a, 2654 FW_ROCEV2_RC_RDMA_WRITE_ONLY_WITH_IMMD = 0x0b, 2655 FW_ROCEV2_RC_RDMA_READ_REQ = 0x0c, 2656 FW_ROCEV2_RC_RDMA_READ_RESP_FIRST = 0x0d, 2657 FW_ROCEV2_RC_RDMA_READ_RESP_MIDDLE = 0x0e, 2658 FW_ROCEV2_RC_RDMA_READ_RESP_LAST = 0x0f, 2659 FW_ROCEV2_RC_RDMA_READ_RESP_ONLY = 0x10, 2660 FW_ROCEV2_RC_ACK = 0x11, 2661 FW_ROCEV2_RC_ATOMIC_ACK = 0x12, 2662 FW_ROCEV2_RC_CMP_SWAP = 0x13, 2663 FW_ROCEV2_RC_FETCH_ADD = 0x14, 2664 FW_ROCEV2_RC_SEND_LAST_WITH_INV = 0x16, 2665 FW_ROCEV2_RC_SEND_ONLY_WITH_INV = 0x17, 2666 2667 /* XRC */ 2668 FW_ROCEV2_XRC_SEND_FIRST = 0xa0, 2669 FW_ROCEV2_XRC_SEND_MIDDLE = 0xa1, 2670 FW_ROCEV2_XRC_SEND_LAST = 0xa2, 2671 FW_ROCEV2_XRC_SEND_LAST_WITH_IMMD = 0xa3, 2672 FW_ROCEV2_XRC_SEND_ONLY = 0xa4, 2673 FW_ROCEV2_XRC_SEND_ONLY_WITH_IMMD = 0xa5, 2674 FW_ROCEV2_XRC_RDMA_WRITE_FIRST = 0xa6, 2675 FW_ROCEV2_XRC_RDMA_WRITE_MIDDLE = 0xa7, 2676 FW_ROCEV2_XRC_RDMA_WRITE_LAST = 0xa8, 2677 FW_ROCEV2_XRC_RDMA_WRITE_LAST_WITH_IMMD = 0xa9, 2678 FW_ROCEV2_XRC_RDMA_WRITE_ONLY = 0xaa, 2679 FW_ROCEV2_XRC_RDMA_WRITE_ONLY_WITH_IMMD = 0xab, 2680 FW_ROCEV2_XRC_RDMA_READ_REQ = 0xac, 2681 FW_ROCEV2_XRC_RDMA_READ_RESP_FIRST = 0xad, 2682 FW_ROCEV2_XRC_RDMA_READ_RESP_MIDDLE = 0xae, 2683 FW_ROCEV2_XRC_RDMA_READ_RESP_LAST = 0xaf, 2684 FW_ROCEV2_XRC_RDMA_READ_RESP_ONLY = 0xb0, 2685 FW_ROCEV2_XRC_ACK = 0xb1, 2686 FW_ROCEV2_XRC_ATOMIC_ACK = 0xb2, 2687 FW_ROCEV2_XRC_CMP_SWAP = 0xb3, 2688 FW_ROCEV2_XRC_FETCH_ADD = 0xb4, 2689 FW_ROCEV2_XRC_SEND_LAST_WITH_INV = 0xb6, 2690 FW_ROCEV2_XRC_SEND_ONLY_WITH_INV = 0xb7, 2691 }; 2692 2693 #if 0 2694 enum fw_rocev2_cqe_err { 2695 /* TODO */ 2696 }; 2697 #endif 2698 2699 struct fw_ri_v2_rdma_write_wr { 2700 __u8 opcode; 2701 __u8 v2_flags; 2702 __u16 wrid; 2703 __u8 r1[3]; 2704 __u8 len16; 2705 __be32 r2; /* set to 0 */ 2706 __be32 psn_pkd; 2707 __be32 r4[2]; 2708 __be32 r5; 2709 __be32 immd_data; 2710 __be64 to_sink; 2711 __be32 stag_sink; 2712 __be32 plen; 2713 #ifndef C99_NOT_SUPPORTED 2714 union { 2715 struct fw_ri_immd immd_src[0]; 2716 struct fw_ri_isgl isgl_src[0]; 2717 } u; 2718 #endif 2719 }; 2720 2721 #define S_FW_RI_V2_RDMA_WRITE_WR_PSN 0 2722 #define M_FW_RI_V2_RDMA_WRITE_WR_PSN 0xffffff 2723 #define V_FW_RI_V2_RDMA_WRITE_WR_PSN(x) ((x) << S_FW_RI_V2_RDMA_WRITE_WR_PSN) 2724 #define G_FW_RI_V2_RDMA_WRITE_WR_PSN(x) \ 2725 (((x) >> S_FW_RI_V2_RDMA_WRITE_WR_PSN) & M_FW_RI_V2_RDMA_WRITE_WR_PSN) 2726 2727 struct fw_ri_v2_send_wr { 2728 __u8 opcode; 2729 __u8 v2_flags; 2730 __u16 wrid; 2731 __u8 r1[3]; 2732 __u8 len16; 2733 __be32 r2; /* set to 0 */ 2734 __be32 stag_inv; 2735 __be32 plen; 2736 __be32 sendop_psn; 2737 __u8 immdlen; 2738 __u8 r3[3]; 2739 __be32 r4; 2740 /* CPL_TX_TNL_LSO, CPL_TX_PKT_XT and Eth/IP/UDP/BTH 2741 * headers in UD QP case, align size to 16B */ 2742 #ifndef C99_NOT_SUPPORTED 2743 union { 2744 struct fw_ri_immd immd_src[0]; 2745 struct fw_ri_isgl isgl_src[0]; 2746 } u; 2747 #endif 2748 }; 2749 2750 #define S_FW_RI_V2_SEND_WR_SENDOP 24 2751 #define M_FW_RI_V2_SEND_WR_SENDOP 0xff 2752 #define V_FW_RI_V2_SEND_WR_SENDOP(x) ((x) << S_FW_RI_V2_SEND_WR_SENDOP) 2753 #define G_FW_RI_V2_SEND_WR_SENDOP(x) \ 2754 (((x) >> S_FW_RI_V2_SEND_WR_SENDOP) & M_FW_RI_V2_SEND_WR_SENDOP) 2755 2756 #define S_FW_RI_V2_SEND_WR_PSN 0 2757 #define M_FW_RI_V2_SEND_WR_PSN 0xffffff 2758 #define V_FW_RI_V2_SEND_WR_PSN(x) ((x) << S_FW_RI_V2_SEND_WR_PSN) 2759 #define G_FW_RI_V2_SEND_WR_PSN(x) \ 2760 (((x) >> S_FW_RI_V2_SEND_WR_PSN) & M_FW_RI_V2_SEND_WR_PSN) 2761 2762 struct fw_ri_v2_rdma_read_wr { 2763 __u8 opcode; 2764 __u8 v2_flags; 2765 __u16 wrid; 2766 __u8 r1[3]; 2767 __u8 len16; 2768 __be32 r2; /* set to 0 */ 2769 __be32 psn_pkd; 2770 __be64 to_src; 2771 __be32 stag_src; 2772 __be32 plen; 2773 struct fw_ri_isgl isgl_sink; /* RRQ, max 4 nsge in rocev2, 1 in iwarp */ 2774 }; 2775 2776 #define S_FW_RI_V2_RDMA_READ_WR_PSN 0 2777 #define M_FW_RI_V2_RDMA_READ_WR_PSN 0xffffff 2778 #define V_FW_RI_V2_RDMA_READ_WR_PSN(x) ((x) << S_FW_RI_V2_RDMA_READ_WR_PSN) 2779 #define G_FW_RI_V2_RDMA_READ_WR_PSN(x) \ 2780 (((x) >> S_FW_RI_V2_RDMA_READ_WR_PSN) & M_FW_RI_V2_RDMA_READ_WR_PSN) 2781 2782 struct fw_ri_v2_atomic_wr { 2783 __u8 opcode; 2784 __u8 v2_flags; 2785 __u16 wrid; 2786 __u8 r1[3]; 2787 __u8 len16; 2788 __be32 r2; /* set to 0 */ 2789 __be32 atomicop_psn; 2790 }; 2791 2792 #define S_FW_RI_V2_ATOMIC_WR_ATOMICOP 28 2793 #define M_FW_RI_V2_ATOMIC_WR_ATOMICOP 0xf 2794 #define V_FW_RI_V2_ATOMIC_WR_ATOMICOP(x) \ 2795 ((x) << S_FW_RI_V2_ATOMIC_WR_ATOMICOP) 2796 #define G_FW_RI_V2_ATOMIC_WR_ATOMICOP(x) \ 2797 (((x) >> S_FW_RI_V2_ATOMIC_WR_ATOMICOP) & M_FW_RI_V2_ATOMIC_WR_ATOMICOP) 2798 2799 #define S_FW_RI_V2_ATOMIC_WR_PSN 0 2800 #define M_FW_RI_V2_ATOMIC_WR_PSN 0xffffff 2801 #define V_FW_RI_V2_ATOMIC_WR_PSN(x) ((x) << S_FW_RI_V2_ATOMIC_WR_PSN) 2802 #define G_FW_RI_V2_ATOMIC_WR_PSN(x) \ 2803 (((x) >> S_FW_RI_V2_ATOMIC_WR_PSN) & M_FW_RI_V2_ATOMIC_WR_PSN) 2804 2805 struct fw_ri_v2_bind_mw_wr { 2806 __u8 opcode; 2807 __u8 flags; 2808 __u16 wrid; 2809 __u8 r1[3]; 2810 __u8 len16; 2811 __be32 r2; 2812 __be32 r5; 2813 __be32 r6[2]; 2814 __u8 qpbinde_to_dcacpu; 2815 __u8 pgsz_shift; 2816 __u8 addr_type; 2817 __u8 mem_perms; 2818 __be32 stag_mr; 2819 __be32 stag_mw; 2820 __be32 r3; 2821 __be64 len_mw; 2822 __be64 va_fbo; 2823 __be64 r4; 2824 }; 2825 2826 2827 #define S_FW_RI_V2_BIND_MW_WR_QPBINDE 6 2828 #define M_FW_RI_V2_BIND_MW_WR_QPBINDE 0x1 2829 #define V_FW_RI_V2_BIND_MW_WR_QPBINDE(x) \ 2830 ((x) << S_FW_RI_V2_BIND_MW_WR_QPBINDE) 2831 #define G_FW_RI_V2_BIND_MW_WR_QPBINDE(x) \ 2832 (((x) >> S_FW_RI_V2_BIND_MW_WR_QPBINDE) & M_FW_RI_V2_BIND_MW_WR_QPBINDE) 2833 #define F_FW_RI_V2_BIND_MW_WR_QPBINDE V_FW_RI_V2_BIND_MW_WR_QPBINDE(1U) 2834 2835 #define S_FW_RI_V2_BIND_MW_WR_NS 5 2836 #define M_FW_RI_V2_BIND_MW_WR_NS 0x1 2837 #define V_FW_RI_V2_BIND_MW_WR_NS(x) ((x) << S_FW_RI_V2_BIND_MW_WR_NS) 2838 #define G_FW_RI_V2_BIND_MW_WR_NS(x) \ 2839 (((x) >> S_FW_RI_V2_BIND_MW_WR_NS) & M_FW_RI_V2_BIND_MW_WR_NS) 2840 #define F_FW_RI_V2_BIND_MW_WR_NS V_FW_RI_V2_BIND_MW_WR_NS(1U) 2841 2842 #define S_FW_RI_V2_BIND_MW_WR_DCACPU 0 2843 #define M_FW_RI_V2_BIND_MW_WR_DCACPU 0x1f 2844 #define V_FW_RI_V2_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_V2_BIND_MW_WR_DCACPU) 2845 #define G_FW_RI_V2_BIND_MW_WR_DCACPU(x) \ 2846 (((x) >> S_FW_RI_V2_BIND_MW_WR_DCACPU) & M_FW_RI_V2_BIND_MW_WR_DCACPU) 2847 2848 struct fw_ri_v2_fr_nsmr_wr { 2849 __u8 opcode; 2850 __u8 v2_flags; 2851 __u16 wrid; 2852 __u8 r1[3]; 2853 __u8 len16; 2854 __be32 r2; 2855 __be32 r3; 2856 __be32 r4[2]; 2857 __u8 qpbinde_to_dcacpu; 2858 __u8 pgsz_shift; 2859 __u8 addr_type; 2860 __u8 mem_perms; 2861 __be32 stag; 2862 __be32 len_hi; 2863 __be32 len_lo; 2864 __be32 va_hi; 2865 __be32 va_lo_fbo; 2866 }; 2867 2868 #define S_FW_RI_V2_FR_NSMR_WR_QPBINDE 6 2869 #define M_FW_RI_V2_FR_NSMR_WR_QPBINDE 0x1 2870 #define V_FW_RI_V2_FR_NSMR_WR_QPBINDE(x) \ 2871 ((x) << S_FW_RI_V2_FR_NSMR_WR_QPBINDE) 2872 #define G_FW_RI_V2_FR_NSMR_WR_QPBINDE(x) \ 2873 (((x) >> S_FW_RI_V2_FR_NSMR_WR_QPBINDE) & M_FW_RI_V2_FR_NSMR_WR_QPBINDE) 2874 #define F_FW_RI_V2_FR_NSMR_WR_QPBINDE V_FW_RI_V2_FR_NSMR_WR_QPBINDE(1U) 2875 2876 #define S_FW_RI_V2_FR_NSMR_WR_NS 5 2877 #define M_FW_RI_V2_FR_NSMR_WR_NS 0x1 2878 #define V_FW_RI_V2_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_V2_FR_NSMR_WR_NS) 2879 #define G_FW_RI_V2_FR_NSMR_WR_NS(x) \ 2880 (((x) >> S_FW_RI_V2_FR_NSMR_WR_NS) & M_FW_RI_V2_FR_NSMR_WR_NS) 2881 #define F_FW_RI_V2_FR_NSMR_WR_NS V_FW_RI_V2_FR_NSMR_WR_NS(1U) 2882 2883 #define S_FW_RI_V2_FR_NSMR_WR_DCACPU 0 2884 #define M_FW_RI_V2_FR_NSMR_WR_DCACPU 0x1f 2885 #define V_FW_RI_V2_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_V2_FR_NSMR_WR_DCACPU) 2886 #define G_FW_RI_V2_FR_NSMR_WR_DCACPU(x) \ 2887 (((x) >> S_FW_RI_V2_FR_NSMR_WR_DCACPU) & M_FW_RI_V2_FR_NSMR_WR_DCACPU) 2888 2889 /****************************************************************************** 2890 * N V M E - T C P W O R K R E Q U E S T s 2891 *****************************************************************************/ 2892 2893 struct fw_nvmet_v2_fr_nsmr_wr { 2894 __be32 op_to_wrid; 2895 __be32 flowid_len16; 2896 __be32 r3; 2897 __be32 r4; 2898 __be32 mem_write_addr32; 2899 __u8 r5; 2900 __u8 imm_data_len32; 2901 union { 2902 __be16 dsgl_data_len32; 2903 __be16 reset_mem_len32; 2904 }; 2905 __be64 r6; 2906 }; 2907 2908 #define S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL 23 2909 #define M_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL 0x1 2910 #define V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x) \ 2911 ((x) << S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) 2912 #define G_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x) \ 2913 (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) & \ 2914 M_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) 2915 #define F_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL \ 2916 V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(1U) 2917 2918 #define S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM 22 2919 #define M_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM 0x1 2920 #define V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x) \ 2921 ((x) << S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) 2922 #define G_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x) \ 2923 (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) & \ 2924 M_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) 2925 #define F_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM \ 2926 V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(1U) 2927 2928 #define S_FW_NVMET_V2_FR_NSMR_WR_WRID 0 2929 #define M_FW_NVMET_V2_FR_NSMR_WR_WRID 0xffff 2930 #define V_FW_NVMET_V2_FR_NSMR_WR_WRID(x) \ 2931 ((x) << S_FW_NVMET_V2_FR_NSMR_WR_WRID) 2932 #define G_FW_NVMET_V2_FR_NSMR_WR_WRID(x) \ 2933 (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_WRID) & M_FW_NVMET_V2_FR_NSMR_WR_WRID) 2934 2935 struct fw_v2_nvmet_tx_data_wr { 2936 __be32 op_to_immdlen; 2937 __be32 flowid_len16; 2938 __be32 r4; 2939 __be16 r5; 2940 __be16 wrid; 2941 __be32 r6; 2942 __be32 seqno; 2943 __be32 plen; 2944 __be32 flags_hi_to_flags_lo; 2945 /* optional immdlen data (fw_tx_pi_hdr, iso cpl, nvmet header etc) */ 2946 #ifndef C99_NOT_SUPPORTED 2947 union { 2948 struct fw_ri_dsgl dsgl_src[0]; 2949 struct fw_ri_isgl isgl_src[0]; 2950 } u; 2951 #endif 2952 }; 2953 2954 #define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 10 2955 #define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 0x3fffff 2956 #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x) \ 2957 ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) 2958 #define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x) \ 2959 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) & \ 2960 M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) 2961 2962 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO 9 2963 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO 0x1 2964 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 2965 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) 2966 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 2967 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) & \ 2968 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) 2969 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO \ 2970 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(1U) 2971 2972 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI 8 2973 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI 0x1 2974 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x) \ 2975 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) 2976 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x) \ 2977 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) & \ 2978 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) 2979 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI \ 2980 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(1U) 2981 2982 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC 7 2983 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 2984 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 2985 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) 2986 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 2987 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 2988 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) 2989 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC \ 2990 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 2991 2992 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC 6 2993 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 2994 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 2995 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) 2996 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 2997 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 2998 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) 2999 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC \ 3000 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 3001 3002 #define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO 0 3003 #define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO 0x3f 3004 #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x) \ 3005 ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) 3006 #define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x) \ 3007 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) & \ 3008 M_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) 3009 3010 3011 /****************************************************************************** 3012 * F O i S C S I W O R K R E Q U E S T s 3013 *********************************************/ 3014 3015 #define FW_FOISCSI_NAME_MAX_LEN 224 3016 #define FW_FOISCSI_ALIAS_MAX_LEN 224 3017 #define FW_FOISCSI_KEY_MAX_LEN 64 3018 #define FW_FOISCSI_VAL_MAX_LEN 256 3019 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 3020 #define FW_FOISCSI_INIT_NODE_MAX 8 3021 3022 enum fw_chnet_ifconf_wr_subop { 3023 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 3024 3025 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 3026 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 3027 3028 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 3029 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 3030 3031 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 3032 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 3033 3034 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 3035 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 3036 3037 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 3038 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 3039 3040 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 3041 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 3042 3043 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 3044 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 3045 3046 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 3047 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 3048 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 3049 3050 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 3051 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 3052 3053 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4, 3054 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6, 3055 3056 FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR, 3057 3058 FW_CHNET_IFCONF_WR_SUBOP_MAX, 3059 }; 3060 3061 struct fw_chnet_ifconf_wr { 3062 __be32 op_compl; 3063 __be32 flowid_len16; 3064 __u64 cookie; 3065 __be32 if_flowid; 3066 __u8 idx; 3067 __u8 subop; 3068 __u8 retval; 3069 __u8 r2; 3070 union { 3071 __be64 r3; 3072 struct fw_chnet_ifconf_ping { 3073 __be16 ping_time; 3074 __u8 ping_rsptype; 3075 __u8 ping_param_rspcode_to_fin_bit; 3076 __u8 ping_pktsize; 3077 __u8 ping_ttl; 3078 __be16 ping_seq; 3079 } ping; 3080 struct fw_chnet_ifconf_mac { 3081 __u8 peer_mac[6]; 3082 __u8 smac_idx; 3083 } mac; 3084 } u; 3085 struct fw_chnet_ifconf_params { 3086 __be16 ping_pldsize; 3087 __be16 r0; 3088 __be16 vlanid; 3089 __be16 mtu; 3090 union fw_chnet_ifconf_addr_type { 3091 struct fw_chnet_ifconf_ipv4 { 3092 __be32 addr; 3093 __be32 mask; 3094 __be32 router; 3095 __be32 r0; 3096 __be64 r1; 3097 } ipv4; 3098 struct fw_chnet_ifconf_ipv6 { 3099 __u8 prefix_len; 3100 __u8 r0; 3101 __be16 r1; 3102 __be32 r2; 3103 __be64 addr_hi; 3104 __be64 addr_lo; 3105 __be64 router_hi; 3106 __be64 router_lo; 3107 } ipv6; 3108 } in_attr; 3109 } param; 3110 }; 3111 3112 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 3113 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 3114 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 3115 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 3116 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 3117 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 3118 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 3119 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 3120 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 3121 3122 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 3123 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 3124 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 3125 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 3126 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 3127 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 3128 3129 enum fw_foiscsi_node_type { 3130 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 3131 FW_FOISCSI_NODE_TYPE_TARGET, 3132 }; 3133 3134 enum fw_foiscsi_session_type { 3135 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 3136 FW_FOISCSI_SESSION_TYPE_NORMAL, 3137 }; 3138 3139 enum fw_foiscsi_auth_policy { 3140 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 3141 FW_FOISCSI_AUTH_POLICY_MUTUAL, 3142 }; 3143 3144 enum fw_foiscsi_auth_method { 3145 FW_FOISCSI_AUTH_METHOD_NONE = 0, 3146 FW_FOISCSI_AUTH_METHOD_CHAP, 3147 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 3148 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 3149 }; 3150 3151 enum fw_foiscsi_digest_type { 3152 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 3153 FW_FOISCSI_DIGEST_TYPE_CRC32, 3154 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 3155 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 3156 }; 3157 3158 enum fw_foiscsi_wr_subop { 3159 FW_FOISCSI_WR_SUBOP_ADD = 1, 3160 FW_FOISCSI_WR_SUBOP_DEL = 2, 3161 FW_FOISCSI_WR_SUBOP_MOD = 4, 3162 }; 3163 3164 enum fw_coiscsi_stats_wr_subop { 3165 FW_COISCSI_WR_SUBOP_TOT = 1, 3166 FW_COISCSI_WR_SUBOP_MAX = 2, 3167 FW_COISCSI_WR_SUBOP_CUR = 3, 3168 FW_COISCSI_WR_SUBOP_CLR = 4, 3169 }; 3170 3171 enum fw_foiscsi_ctrl_state { 3172 FW_FOISCSI_CTRL_STATE_FREE = 0, 3173 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 3174 FW_FOISCSI_CTRL_STATE_FAILED, 3175 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 3176 FW_FOISCSI_CTRL_STATE_REDIRECT, 3177 }; 3178 3179 struct fw_rdev_wr { 3180 __be32 op_to_immdlen; 3181 __be32 alloc_to_len16; 3182 __be64 cookie; 3183 __u8 protocol; 3184 __u8 event_cause; 3185 __u8 cur_state; 3186 __u8 prev_state; 3187 __be32 flags_to_assoc_flowid; 3188 union rdev_entry { 3189 struct fcoe_rdev_entry { 3190 __be32 flowid; 3191 __u8 protocol; 3192 __u8 event_cause; 3193 __u8 flags; 3194 __u8 rjt_reason; 3195 __u8 cur_login_st; 3196 __u8 prev_login_st; 3197 __be16 rcv_fr_sz; 3198 __u8 rd_xfer_rdy_to_rport_type; 3199 __u8 vft_to_qos; 3200 __u8 org_proc_assoc_to_acc_rsp_code; 3201 __u8 enh_disc_to_tgt; 3202 __u8 wwnn[8]; 3203 __u8 wwpn[8]; 3204 __be16 iqid; 3205 __u8 fc_oui[3]; 3206 __u8 r_id[3]; 3207 } fcoe_rdev; 3208 struct iscsi_rdev_entry { 3209 __be32 flowid; 3210 __u8 protocol; 3211 __u8 event_cause; 3212 __u8 flags; 3213 __u8 r3; 3214 __be16 iscsi_opts; 3215 __be16 tcp_opts; 3216 __be16 ip_opts; 3217 __be16 max_rcv_len; 3218 __be16 max_snd_len; 3219 __be16 first_brst_len; 3220 __be16 max_brst_len; 3221 __be16 r4; 3222 __be16 def_time2wait; 3223 __be16 def_time2ret; 3224 __be16 nop_out_intrvl; 3225 __be16 non_scsi_to; 3226 __be16 isid; 3227 __be16 tsid; 3228 __be16 port; 3229 __be16 tpgt; 3230 __u8 r5[6]; 3231 __be16 iqid; 3232 } iscsi_rdev; 3233 } u; 3234 }; 3235 3236 #define S_FW_RDEV_WR_IMMDLEN 0 3237 #define M_FW_RDEV_WR_IMMDLEN 0xff 3238 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 3239 #define G_FW_RDEV_WR_IMMDLEN(x) \ 3240 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 3241 3242 #define S_FW_RDEV_WR_ALLOC 31 3243 #define M_FW_RDEV_WR_ALLOC 0x1 3244 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 3245 #define G_FW_RDEV_WR_ALLOC(x) \ 3246 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 3247 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 3248 3249 #define S_FW_RDEV_WR_FREE 30 3250 #define M_FW_RDEV_WR_FREE 0x1 3251 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 3252 #define G_FW_RDEV_WR_FREE(x) \ 3253 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 3254 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 3255 3256 #define S_FW_RDEV_WR_MODIFY 29 3257 #define M_FW_RDEV_WR_MODIFY 0x1 3258 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 3259 #define G_FW_RDEV_WR_MODIFY(x) \ 3260 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 3261 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 3262 3263 #define S_FW_RDEV_WR_FLOWID 8 3264 #define M_FW_RDEV_WR_FLOWID 0xfffff 3265 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 3266 #define G_FW_RDEV_WR_FLOWID(x) \ 3267 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 3268 3269 #define S_FW_RDEV_WR_LEN16 0 3270 #define M_FW_RDEV_WR_LEN16 0xff 3271 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 3272 #define G_FW_RDEV_WR_LEN16(x) \ 3273 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 3274 3275 #define S_FW_RDEV_WR_FLAGS 24 3276 #define M_FW_RDEV_WR_FLAGS 0xff 3277 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 3278 #define G_FW_RDEV_WR_FLAGS(x) \ 3279 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 3280 3281 #define S_FW_RDEV_WR_GET_NEXT 20 3282 #define M_FW_RDEV_WR_GET_NEXT 0xf 3283 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 3284 #define G_FW_RDEV_WR_GET_NEXT(x) \ 3285 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 3286 3287 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 3288 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 3289 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 3290 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 3291 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 3292 3293 #define S_FW_RDEV_WR_RJT 7 3294 #define M_FW_RDEV_WR_RJT 0x1 3295 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 3296 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 3297 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 3298 3299 #define S_FW_RDEV_WR_REASON 0 3300 #define M_FW_RDEV_WR_REASON 0x7f 3301 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 3302 #define G_FW_RDEV_WR_REASON(x) \ 3303 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 3304 3305 #define S_FW_RDEV_WR_RD_XFER_RDY 7 3306 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 3307 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 3308 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 3309 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 3310 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 3311 3312 #define S_FW_RDEV_WR_WR_XFER_RDY 6 3313 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 3314 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 3315 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 3316 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 3317 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 3318 3319 #define S_FW_RDEV_WR_FC_SP 5 3320 #define M_FW_RDEV_WR_FC_SP 0x1 3321 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 3322 #define G_FW_RDEV_WR_FC_SP(x) \ 3323 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 3324 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 3325 3326 #define S_FW_RDEV_WR_RPORT_TYPE 0 3327 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 3328 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 3329 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 3330 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 3331 3332 #define S_FW_RDEV_WR_VFT 7 3333 #define M_FW_RDEV_WR_VFT 0x1 3334 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 3335 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 3336 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 3337 3338 #define S_FW_RDEV_WR_NPIV 6 3339 #define M_FW_RDEV_WR_NPIV 0x1 3340 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 3341 #define G_FW_RDEV_WR_NPIV(x) \ 3342 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 3343 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 3344 3345 #define S_FW_RDEV_WR_CLASS 4 3346 #define M_FW_RDEV_WR_CLASS 0x3 3347 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 3348 #define G_FW_RDEV_WR_CLASS(x) \ 3349 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 3350 3351 #define S_FW_RDEV_WR_SEQ_DEL 3 3352 #define M_FW_RDEV_WR_SEQ_DEL 0x1 3353 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 3354 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 3355 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 3356 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 3357 3358 #define S_FW_RDEV_WR_PRIO_PREEMP 2 3359 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 3360 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 3361 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 3362 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 3363 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 3364 3365 #define S_FW_RDEV_WR_PREF 1 3366 #define M_FW_RDEV_WR_PREF 0x1 3367 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 3368 #define G_FW_RDEV_WR_PREF(x) \ 3369 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 3370 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 3371 3372 #define S_FW_RDEV_WR_QOS 0 3373 #define M_FW_RDEV_WR_QOS 0x1 3374 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 3375 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 3376 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 3377 3378 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 3379 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 3380 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 3381 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 3382 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 3383 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 3384 3385 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 3386 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 3387 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 3388 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 3389 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 3390 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 3391 3392 #define S_FW_RDEV_WR_IMAGE_PAIR 5 3393 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 3394 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 3395 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 3396 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 3397 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 3398 3399 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 3400 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 3401 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 3402 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 3403 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 3404 3405 #define S_FW_RDEV_WR_ENH_DISC 7 3406 #define M_FW_RDEV_WR_ENH_DISC 0x1 3407 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 3408 #define G_FW_RDEV_WR_ENH_DISC(x) \ 3409 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 3410 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 3411 3412 #define S_FW_RDEV_WR_REC 6 3413 #define M_FW_RDEV_WR_REC 0x1 3414 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 3415 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 3416 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 3417 3418 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 3419 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 3420 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 3421 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 3422 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 3423 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 3424 3425 #define S_FW_RDEV_WR_RETRY 4 3426 #define M_FW_RDEV_WR_RETRY 0x1 3427 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 3428 #define G_FW_RDEV_WR_RETRY(x) \ 3429 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 3430 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 3431 3432 #define S_FW_RDEV_WR_CONF_CMPL 3 3433 #define M_FW_RDEV_WR_CONF_CMPL 0x1 3434 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 3435 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 3436 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 3437 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 3438 3439 #define S_FW_RDEV_WR_DATA_OVLY 2 3440 #define M_FW_RDEV_WR_DATA_OVLY 0x1 3441 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 3442 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 3443 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 3444 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 3445 3446 #define S_FW_RDEV_WR_INI 1 3447 #define M_FW_RDEV_WR_INI 0x1 3448 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 3449 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 3450 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 3451 3452 #define S_FW_RDEV_WR_TGT 0 3453 #define M_FW_RDEV_WR_TGT 0x1 3454 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 3455 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 3456 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 3457 3458 struct fw_foiscsi_node_wr { 3459 __be32 op_to_immdlen; 3460 __be32 no_sess_recv_to_len16; 3461 __u64 cookie; 3462 __u8 subop; 3463 __u8 status; 3464 __u8 alias_len; 3465 __u8 iqn_len; 3466 __be32 node_flowid; 3467 __be16 nodeid; 3468 __be16 login_retry; 3469 __be16 retry_timeout; 3470 __be16 r3; 3471 __u8 iqn[224]; 3472 __u8 alias[224]; 3473 __be32 isid_tval_to_isid_cval; 3474 }; 3475 3476 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 3477 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 3478 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 3479 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 3480 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 3481 3482 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 3483 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 3484 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 3485 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 3486 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 3487 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 3488 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 3489 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 3490 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 3491 3492 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 3493 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 3494 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 3495 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 3496 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 3497 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 3498 3499 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 3500 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 3501 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 3502 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 3503 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 3504 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 3505 3506 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 3507 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 3508 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 3509 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 3510 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 3511 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 3512 3513 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 3514 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 3515 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 3516 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 3517 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 3518 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 3519 3520 struct fw_foiscsi_ctrl_wr { 3521 __be32 op_to_no_fin; 3522 __be32 flowid_len16; 3523 __u64 cookie; 3524 __u8 subop; 3525 __u8 status; 3526 __u8 ctrl_state; 3527 __u8 io_state; 3528 __be32 node_id; 3529 __be32 ctrl_id; 3530 __be32 io_id; 3531 struct fw_foiscsi_sess_attr { 3532 __be32 sess_type_to_erl; 3533 __be16 max_conn; 3534 __be16 max_r2t; 3535 __be16 time2wait; 3536 __be16 time2retain; 3537 __be32 max_burst; 3538 __be32 first_burst; 3539 __be32 r1; 3540 } sess_attr; 3541 struct fw_foiscsi_conn_attr { 3542 __be32 hdigest_to_tcp_ws_en; 3543 __be32 max_rcv_dsl; 3544 __be32 ping_tmo; 3545 __be16 dst_port; 3546 __be16 src_port; 3547 union fw_foiscsi_conn_attr_addr { 3548 struct fw_foiscsi_conn_attr_ipv6 { 3549 __be64 dst_addr[2]; 3550 __be64 src_addr[2]; 3551 } ipv6_addr; 3552 struct fw_foiscsi_conn_attr_ipv4 { 3553 __be32 dst_addr; 3554 __be32 src_addr; 3555 } ipv4_addr; 3556 } u; 3557 } conn_attr; 3558 __u8 tgt_name_len; 3559 __u8 r3[7]; 3560 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 3561 }; 3562 3563 #define S_FW_FOISCSI_CTRL_WR_PORTID 1 3564 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7 3565 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID) 3566 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \ 3567 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID) 3568 3569 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 3570 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 3571 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 3572 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 3573 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 3574 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 3575 3576 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 3577 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 3578 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 3579 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 3580 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 3581 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 3582 3583 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 3584 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 3585 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 3586 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 3587 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 3588 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 3589 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 3590 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 3591 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 3592 3593 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 3594 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 3595 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 3596 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 3597 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 3598 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 3599 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 3600 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 3601 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 3602 3603 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 3604 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 3605 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 3606 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 3607 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 3608 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 3609 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 3610 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 3611 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 3612 3613 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 3614 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 3615 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 3616 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 3617 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 3618 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 3619 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 3620 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 3621 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 3622 3623 #define S_FW_FOISCSI_CTRL_WR_ERL 24 3624 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 3625 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 3626 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 3627 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 3628 3629 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 3630 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 3631 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 3632 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 3633 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 3634 3635 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 3636 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 3637 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 3638 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 3639 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 3640 3641 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 3642 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 3643 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 3644 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 3645 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 3646 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 3647 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 3648 3649 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 3650 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 3651 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 3652 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 3653 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 3654 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 3655 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 3656 3657 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 3658 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 3659 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 3660 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 3661 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 3662 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 3663 3664 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 3665 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 3666 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 3667 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 3668 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 3669 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 3670 3671 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 3672 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 3673 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 3674 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 3675 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 3676 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 3677 3678 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 3679 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 3680 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 3681 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 3682 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 3683 3684 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 3685 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 3686 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 3687 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 3688 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 3689 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 3690 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 3691 3692 struct fw_foiscsi_chap_wr { 3693 __be32 op_to_kv_flag; 3694 __be32 flowid_len16; 3695 __u64 cookie; 3696 __u8 status; 3697 union fw_foiscsi_len { 3698 struct fw_foiscsi_chap_lens { 3699 __u8 id_len; 3700 __u8 sec_len; 3701 } chapl; 3702 struct fw_foiscsi_vend_kv_lens { 3703 __u8 key_len; 3704 __u8 val_len; 3705 } vend_kvl; 3706 } lenu; 3707 __u8 node_type; 3708 __be16 node_id; 3709 __u8 r3[2]; 3710 union fw_foiscsi_chap_vend { 3711 struct fw_foiscsi_chap { 3712 __u8 chap_id[224]; 3713 __u8 chap_sec[128]; 3714 } chap; 3715 struct fw_foiscsi_vend_kv { 3716 __u8 vend_key[64]; 3717 __u8 vend_val[256]; 3718 } vend_kv; 3719 } u; 3720 }; 3721 3722 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 3723 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 3724 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 3725 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 3726 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 3727 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 3728 3729 /****************************************************************************** 3730 * C O i S C S I W O R K R E Q U E S T S 3731 ********************************************/ 3732 3733 enum fw_chnet_addr_type { 3734 FW_CHNET_ADDD_TYPE_NONE = 0, 3735 FW_CHNET_ADDR_TYPE_IPV4, 3736 FW_CHNET_ADDR_TYPE_IPV6, 3737 }; 3738 3739 enum fw_msg_wr_type { 3740 FW_MSG_WR_TYPE_RPL = 0, 3741 FW_MSG_WR_TYPE_ERR, 3742 FW_MSG_WR_TYPE_PLD, 3743 }; 3744 3745 struct fw_coiscsi_tgt_wr { 3746 __be32 op_compl; 3747 __be32 flowid_len16; 3748 __u64 cookie; 3749 __u8 subop; 3750 __u8 status; 3751 __be16 r4; 3752 __be32 flags; 3753 struct fw_coiscsi_tgt_conn_attr { 3754 __be32 in_tid; 3755 __be16 in_port; 3756 __u8 in_type; 3757 __u8 r6; 3758 union fw_coiscsi_tgt_conn_attr_addr { 3759 struct fw_coiscsi_tgt_conn_attr_in_addr { 3760 __be32 addr; 3761 __be32 r7; 3762 __be32 r8[2]; 3763 } in_addr; 3764 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 3765 __be64 addr[2]; 3766 } in_addr6; 3767 } u; 3768 } conn_attr; 3769 }; 3770 3771 #define S_FW_COISCSI_TGT_WR_PORTID 0 3772 #define M_FW_COISCSI_TGT_WR_PORTID 0x7 3773 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID) 3774 #define G_FW_COISCSI_TGT_WR_PORTID(x) \ 3775 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID) 3776 3777 struct fw_coiscsi_tgt_conn_wr { 3778 __be32 op_compl; 3779 __be32 flowid_len16; 3780 __u64 cookie; 3781 __u8 subop; 3782 __u8 status; 3783 __be16 iq_id; 3784 __be32 in_stid; 3785 __be32 io_id; 3786 __be32 flags_fin; 3787 union { 3788 struct fw_coiscsi_tgt_conn_tcp { 3789 __be16 in_sport; 3790 __be16 in_dport; 3791 __u8 wscale_wsen; 3792 __u8 r4[3]; 3793 union fw_coiscsi_tgt_conn_tcp_addr { 3794 struct fw_coiscsi_tgt_conn_tcp_in_addr { 3795 __be32 saddr; 3796 __be32 daddr; 3797 } in_addr; 3798 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 3799 __be64 saddr[2]; 3800 __be64 daddr[2]; 3801 } in_addr6; 3802 } u; 3803 } conn_tcp; 3804 struct fw_coiscsi_tgt_conn_stats { 3805 __be32 ddp_reqs; 3806 __be32 ddp_cmpls; 3807 __be16 ddp_aborts; 3808 __be16 ddp_bps; 3809 } stats; 3810 } u; 3811 struct fw_coiscsi_tgt_conn_iscsi { 3812 __be32 hdigest_to_ddp_pgsz; 3813 __be32 tgt_id; 3814 __be16 max_r2t; 3815 __be16 r5; 3816 __be32 max_burst; 3817 __be32 max_rdsl; 3818 __be32 max_tdsl; 3819 __be32 cur_sn; 3820 __be32 r6; 3821 } conn_iscsi; 3822 }; 3823 3824 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0 3825 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7 3826 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 3827 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID) 3828 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 3829 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \ 3830 M_FW_COISCSI_TGT_CONN_WR_PORTID) 3831 3832 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0 3833 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 3834 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 3835 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 3836 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 3837 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 3838 3839 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 3840 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 3841 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 3842 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 3843 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 3844 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 3845 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 3846 3847 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 3848 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 3849 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 3850 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 3851 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 3852 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 3853 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 3854 3855 struct fw_coiscsi_tgt_xmit_wr { 3856 __be32 op_to_immdlen; 3857 union { 3858 struct cmpl_stat { 3859 __be32 cmpl_status_pkd; 3860 } cs; 3861 struct flowid_len { 3862 __be32 flowid_len16; 3863 } fllen; 3864 } u; 3865 __u64 cookie; 3866 __be16 iq_id; 3867 __be16 r3; 3868 __be32 pz_off; 3869 __be32 t_xfer_len; 3870 union { 3871 __be32 tag; 3872 __be32 datasn; 3873 __be32 ddp_status; 3874 } cu; 3875 }; 3876 3877 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 3878 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 3879 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3880 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 3881 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3882 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 3883 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 3884 3885 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 3886 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 3887 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3888 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 3889 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3890 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 3891 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 3892 3893 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 3894 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 3895 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 3896 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 3897 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 3898 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 3899 3900 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 3901 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 3902 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3903 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 3904 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3905 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 3906 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 3907 3908 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 3909 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 3910 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3911 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 3912 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3913 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 3914 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 3915 3916 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 3917 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 3918 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3919 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3920 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3921 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 3922 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3923 3924 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 3925 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 3926 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3927 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3928 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3929 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 3930 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3931 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 3932 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 3933 3934 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 3935 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 3936 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3937 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3938 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3939 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 3940 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3941 3942 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 3943 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 3944 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3945 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3946 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3947 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 3948 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3949 3950 struct fw_coiscsi_stats_wr { 3951 __be32 op_compl; 3952 __be32 flowid_len16; 3953 __u64 cookie; 3954 __u8 subop; 3955 __u8 status; 3956 union fw_coiscsi_stats { 3957 struct fw_coiscsi_resource { 3958 __u8 num_ipv4_tgt; 3959 __u8 num_ipv6_tgt; 3960 __be16 num_l2t_entries; 3961 __be16 num_csocks; 3962 __be16 num_tasks; 3963 __be16 num_ppods_zone[11]; 3964 __be32 num_bufll64; 3965 __u8 r2[12]; 3966 } rsrc; 3967 } u; 3968 }; 3969 3970 #define S_FW_COISCSI_STATS_WR_PORTID 0 3971 #define M_FW_COISCSI_STATS_WR_PORTID 0x7 3972 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID) 3973 #define G_FW_COISCSI_STATS_WR_PORTID(x) \ 3974 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID) 3975 3976 struct fw_isns_wr { 3977 __be32 op_compl; 3978 __be32 flowid_len16; 3979 __u64 cookie; 3980 __u8 subop; 3981 __u8 status; 3982 __be16 iq_id; 3983 __be16 vlanid; 3984 __be16 r4; 3985 struct fw_tcp_conn_attr { 3986 __be32 in_tid; 3987 __be16 in_port; 3988 __u8 in_type; 3989 __u8 r6; 3990 union fw_tcp_conn_attr_addr { 3991 struct fw_tcp_conn_attr_in_addr { 3992 __be32 addr; 3993 __be32 r7; 3994 __be32 r8[2]; 3995 } in_addr; 3996 struct fw_tcp_conn_attr_in_addr6 { 3997 __be64 addr[2]; 3998 } in_addr6; 3999 } u; 4000 } conn_attr; 4001 }; 4002 4003 #define S_FW_ISNS_WR_PORTID 0 4004 #define M_FW_ISNS_WR_PORTID 0x7 4005 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID) 4006 #define G_FW_ISNS_WR_PORTID(x) \ 4007 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID) 4008 4009 struct fw_isns_xmit_wr { 4010 __be32 op_to_immdlen; 4011 __be32 flowid_len16; 4012 __u64 cookie; 4013 __be16 iq_id; 4014 __be16 r4; 4015 __be32 xfer_len; 4016 __be64 r5; 4017 }; 4018 4019 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 4020 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 4021 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 4022 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 4023 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 4024 4025 /****************************************************************************** 4026 * F O F C O E W O R K R E Q U E S T s 4027 *******************************************/ 4028 4029 struct fw_fcoe_els_ct_wr { 4030 __be32 op_immdlen; 4031 __be32 flowid_len16; 4032 __be64 cookie; 4033 __be16 iqid; 4034 __u8 tmo_val; 4035 __u8 els_ct_type; 4036 __u8 ctl_pri; 4037 __u8 cp_en_class; 4038 __be16 xfer_cnt; 4039 __u8 fl_to_sp; 4040 __u8 l_id[3]; 4041 __u8 r5; 4042 __u8 r_id[3]; 4043 __be64 rsp_dmaaddr; 4044 __be32 rsp_dmalen; 4045 __be32 r6; 4046 }; 4047 4048 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 4049 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 4050 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 4051 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 4052 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 4053 4054 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 4055 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 4056 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 4057 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 4058 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 4059 4060 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 4061 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 4062 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 4063 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 4064 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 4065 4066 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 4067 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 4068 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 4069 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 4070 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 4071 4072 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 4073 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 4074 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 4075 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 4076 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 4077 4078 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 4079 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 4080 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 4081 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 4082 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 4083 4084 #define S_FW_FCOE_ELS_CT_WR_FL 2 4085 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 4086 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 4087 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 4088 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 4089 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 4090 4091 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 4092 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 4093 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 4094 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 4095 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 4096 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 4097 4098 #define S_FW_FCOE_ELS_CT_WR_SP 0 4099 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 4100 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 4101 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 4102 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 4103 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 4104 4105 /****************************************************************************** 4106 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 4107 *****************************************************************************/ 4108 4109 struct fw_scsi_write_wr { 4110 __be32 op_immdlen; 4111 __be32 flowid_len16; 4112 __be64 cookie; 4113 __be16 iqid; 4114 __u8 tmo_val; 4115 __u8 use_xfer_cnt; 4116 union fw_scsi_write_priv { 4117 struct fcoe_write_priv { 4118 __u8 ctl_pri; 4119 __u8 cp_en_class; 4120 __u8 r3_lo[2]; 4121 } fcoe; 4122 struct iscsi_write_priv { 4123 __u8 r3[4]; 4124 } iscsi; 4125 } u; 4126 __be32 xfer_cnt; 4127 __be32 ini_xfer_cnt; 4128 __be64 rsp_dmaaddr; 4129 __be32 rsp_dmalen; 4130 __be32 r4; 4131 }; 4132 4133 #define S_FW_SCSI_WRITE_WR_OPCODE 24 4134 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 4135 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 4136 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 4137 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 4138 4139 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 4140 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 4141 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 4142 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 4143 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 4144 4145 #define S_FW_SCSI_WRITE_WR_FLOWID 8 4146 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 4147 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 4148 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 4149 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 4150 4151 #define S_FW_SCSI_WRITE_WR_LEN16 0 4152 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 4153 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 4154 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 4155 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 4156 4157 #define S_FW_SCSI_WRITE_WR_CP_EN 6 4158 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 4159 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 4160 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 4161 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 4162 4163 #define S_FW_SCSI_WRITE_WR_CLASS 4 4164 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 4165 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 4166 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 4167 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 4168 4169 struct fw_scsi_read_wr { 4170 __be32 op_immdlen; 4171 __be32 flowid_len16; 4172 __be64 cookie; 4173 __be16 iqid; 4174 __u8 tmo_val; 4175 __u8 use_xfer_cnt; 4176 union fw_scsi_read_priv { 4177 struct fcoe_read_priv { 4178 __u8 ctl_pri; 4179 __u8 cp_en_class; 4180 __u8 r3_lo[2]; 4181 } fcoe; 4182 struct iscsi_read_priv { 4183 __u8 r3[4]; 4184 } iscsi; 4185 } u; 4186 __be32 xfer_cnt; 4187 __be32 ini_xfer_cnt; 4188 __be64 rsp_dmaaddr; 4189 __be32 rsp_dmalen; 4190 __be32 r4; 4191 }; 4192 4193 #define S_FW_SCSI_READ_WR_OPCODE 24 4194 #define M_FW_SCSI_READ_WR_OPCODE 0xff 4195 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 4196 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 4197 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 4198 4199 #define S_FW_SCSI_READ_WR_IMMDLEN 0 4200 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 4201 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 4202 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 4203 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 4204 4205 #define S_FW_SCSI_READ_WR_FLOWID 8 4206 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 4207 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 4208 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 4209 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 4210 4211 #define S_FW_SCSI_READ_WR_LEN16 0 4212 #define M_FW_SCSI_READ_WR_LEN16 0xff 4213 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 4214 #define G_FW_SCSI_READ_WR_LEN16(x) \ 4215 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 4216 4217 #define S_FW_SCSI_READ_WR_CP_EN 6 4218 #define M_FW_SCSI_READ_WR_CP_EN 0x3 4219 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 4220 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 4221 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 4222 4223 #define S_FW_SCSI_READ_WR_CLASS 4 4224 #define M_FW_SCSI_READ_WR_CLASS 0x3 4225 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 4226 #define G_FW_SCSI_READ_WR_CLASS(x) \ 4227 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 4228 4229 struct fw_scsi_cmd_wr { 4230 __be32 op_immdlen; 4231 __be32 flowid_len16; 4232 __be64 cookie; 4233 __be16 iqid; 4234 __u8 tmo_val; 4235 __u8 r3; 4236 union fw_scsi_cmd_priv { 4237 struct fcoe_cmd_priv { 4238 __u8 ctl_pri; 4239 __u8 cp_en_class; 4240 __u8 r4_lo[2]; 4241 } fcoe; 4242 struct iscsi_cmd_priv { 4243 __u8 r4[4]; 4244 } iscsi; 4245 } u; 4246 __u8 r5[8]; 4247 __be64 rsp_dmaaddr; 4248 __be32 rsp_dmalen; 4249 __be32 r6; 4250 }; 4251 4252 #define S_FW_SCSI_CMD_WR_OPCODE 24 4253 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 4254 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 4255 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 4256 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 4257 4258 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 4259 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 4260 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 4261 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 4262 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 4263 4264 #define S_FW_SCSI_CMD_WR_FLOWID 8 4265 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 4266 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 4267 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 4268 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 4269 4270 #define S_FW_SCSI_CMD_WR_LEN16 0 4271 #define M_FW_SCSI_CMD_WR_LEN16 0xff 4272 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 4273 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 4274 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 4275 4276 #define S_FW_SCSI_CMD_WR_CP_EN 6 4277 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 4278 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 4279 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 4280 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 4281 4282 #define S_FW_SCSI_CMD_WR_CLASS 4 4283 #define M_FW_SCSI_CMD_WR_CLASS 0x3 4284 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 4285 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 4286 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 4287 4288 struct fw_scsi_abrt_cls_wr { 4289 __be32 op_immdlen; 4290 __be32 flowid_len16; 4291 __be64 cookie; 4292 __be16 iqid; 4293 __u8 tmo_val; 4294 __u8 sub_opcode_to_chk_all_io; 4295 __u8 r3[4]; 4296 __be64 t_cookie; 4297 }; 4298 4299 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 4300 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 4301 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 4302 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 4303 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 4304 4305 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 4306 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 4307 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 4308 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 4309 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 4310 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 4311 4312 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 4313 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 4314 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 4315 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 4316 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 4317 4318 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 4319 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 4320 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 4321 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 4322 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 4323 4324 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 4325 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 4326 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 4327 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 4328 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 4329 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 4330 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 4331 4332 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 4333 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 4334 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 4335 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 4336 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 4337 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 4338 4339 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 4340 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 4341 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 4342 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 4343 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 4344 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 4345 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 4346 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 4347 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 4348 4349 struct fw_scsi_tgt_acc_wr { 4350 __be32 op_immdlen; 4351 __be32 flowid_len16; 4352 __be64 cookie; 4353 __be16 iqid; 4354 __u8 r3; 4355 __u8 use_burst_len; 4356 union fw_scsi_tgt_acc_priv { 4357 struct fcoe_tgt_acc_priv { 4358 __u8 ctl_pri; 4359 __u8 cp_en_class; 4360 __u8 r4_lo[2]; 4361 } fcoe; 4362 struct iscsi_tgt_acc_priv { 4363 __u8 r4[4]; 4364 } iscsi; 4365 } u; 4366 __be32 burst_len; 4367 __be32 rel_off; 4368 __be64 r5; 4369 __be32 r6; 4370 __be32 tot_xfer_len; 4371 }; 4372 4373 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 4374 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 4375 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 4376 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 4377 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 4378 4379 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 4380 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 4381 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 4382 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 4383 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 4384 4385 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 4386 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 4387 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 4388 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 4389 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 4390 4391 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 4392 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 4393 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 4394 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 4395 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 4396 4397 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 4398 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 4399 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 4400 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 4401 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 4402 4403 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 4404 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 4405 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 4406 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 4407 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 4408 4409 struct fw_scsi_tgt_xmit_wr { 4410 __be32 op_immdlen; 4411 __be32 flowid_len16; 4412 __be64 cookie; 4413 __be16 iqid; 4414 __u8 auto_rsp; 4415 __u8 use_xfer_cnt; 4416 union fw_scsi_tgt_xmit_priv { 4417 struct fcoe_tgt_xmit_priv { 4418 __u8 ctl_pri; 4419 __u8 cp_en_class; 4420 __u8 r3_lo[2]; 4421 } fcoe; 4422 struct iscsi_tgt_xmit_priv { 4423 __u8 r3[4]; 4424 } iscsi; 4425 } u; 4426 __be32 xfer_cnt; 4427 __be32 r4; 4428 __be64 r5; 4429 __be32 r6; 4430 __be32 tot_xfer_len; 4431 }; 4432 4433 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 4434 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 4435 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 4436 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 4437 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 4438 4439 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 4440 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 4441 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 4442 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 4443 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 4444 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 4445 4446 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 4447 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 4448 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 4449 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 4450 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 4451 4452 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 4453 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 4454 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 4455 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 4456 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 4457 4458 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 4459 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 4460 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 4461 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 4462 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 4463 4464 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 4465 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 4466 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 4467 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 4468 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 4469 4470 struct fw_scsi_tgt_rsp_wr { 4471 __be32 op_immdlen; 4472 __be32 flowid_len16; 4473 __be64 cookie; 4474 __be16 iqid; 4475 __u8 r3[2]; 4476 union fw_scsi_tgt_rsp_priv { 4477 struct fcoe_tgt_rsp_priv { 4478 __u8 ctl_pri; 4479 __u8 cp_en_class; 4480 __u8 r4_lo[2]; 4481 } fcoe; 4482 struct iscsi_tgt_rsp_priv { 4483 __u8 r4[4]; 4484 } iscsi; 4485 } u; 4486 __u8 r5[8]; 4487 }; 4488 4489 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 4490 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 4491 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 4492 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 4493 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 4494 4495 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 4496 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 4497 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 4498 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 4499 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 4500 4501 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 4502 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 4503 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 4504 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 4505 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 4506 4507 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 4508 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 4509 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 4510 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 4511 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 4512 4513 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 4514 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 4515 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 4516 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 4517 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 4518 4519 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 4520 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 4521 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 4522 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 4523 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 4524 4525 struct fw_pofcoe_tcb_wr { 4526 __be32 op_compl; 4527 __be32 equiq_to_len16; 4528 __be32 r4; 4529 __be32 xfer_len; 4530 __be32 tid_to_port; 4531 __be16 x_id; 4532 __be16 vlan_id; 4533 __be64 cookie; 4534 __be32 s_id; 4535 __be32 d_id; 4536 __be32 tag; 4537 __be16 r6; 4538 __be16 iqid; 4539 }; 4540 4541 #define S_FW_POFCOE_TCB_WR_TID 12 4542 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 4543 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 4544 #define G_FW_POFCOE_TCB_WR_TID(x) \ 4545 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 4546 4547 #define S_FW_POFCOE_TCB_WR_ALLOC 4 4548 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 4549 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 4550 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 4551 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 4552 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 4553 4554 #define S_FW_POFCOE_TCB_WR_FREE 3 4555 #define M_FW_POFCOE_TCB_WR_FREE 0x1 4556 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 4557 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 4558 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 4559 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 4560 4561 #define S_FW_POFCOE_TCB_WR_PORT 0 4562 #define M_FW_POFCOE_TCB_WR_PORT 0x7 4563 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 4564 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 4565 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 4566 4567 struct fw_pofcoe_ulptx_wr { 4568 __be32 op_pkd; 4569 __be32 equiq_to_len16; 4570 __u64 cookie; 4571 }; 4572 4573 /******************************************************************* 4574 * T10 DIF related definition 4575 *******************************************************************/ 4576 struct fw_tx_pi_header { 4577 __be16 op_to_inline; 4578 __u8 pi_interval_tag_type; 4579 __u8 num_pi; 4580 __be32 pi_start4_pi_end4; 4581 __u8 tag_gen_enabled_pkd; 4582 __u8 num_pi_dsg; 4583 __be16 app_tag; 4584 __be32 ref_tag; 4585 }; 4586 4587 #define S_FW_TX_PI_HEADER_OP 8 4588 #define M_FW_TX_PI_HEADER_OP 0xff 4589 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 4590 #define G_FW_TX_PI_HEADER_OP(x) \ 4591 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 4592 4593 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 4594 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 4595 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 4596 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 4597 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 4598 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 4599 4600 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 4601 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 4602 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 4603 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 4604 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 4605 4606 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 4607 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 4608 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 4609 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 4610 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 4611 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 4612 4613 #define S_FW_TX_PI_HEADER_VALIDATE 1 4614 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 4615 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 4616 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 4617 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 4618 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 4619 4620 #define S_FW_TX_PI_HEADER_INLINE 0 4621 #define M_FW_TX_PI_HEADER_INLINE 0x1 4622 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 4623 #define G_FW_TX_PI_HEADER_INLINE(x) \ 4624 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 4625 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 4626 4627 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 4628 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 4629 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 4630 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 4631 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 4632 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 4633 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 4634 4635 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 4636 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 4637 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 4638 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 4639 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 4640 4641 #define S_FW_TX_PI_HEADER_PI_START4 22 4642 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 4643 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 4644 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 4645 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 4646 4647 #define S_FW_TX_PI_HEADER_PI_END4 0 4648 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 4649 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 4650 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 4651 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 4652 4653 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 4654 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 4655 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 4656 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 4657 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 4658 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 4659 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 4660 4661 enum fw_pi_error_type { 4662 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 4663 }; 4664 4665 struct fw_pi_error { 4666 __be32 err_type_pkd; 4667 __be32 flowid_len16; 4668 __be16 r2; 4669 __be16 app_tag; 4670 __be32 ref_tag; 4671 __be32 pisc[4]; 4672 }; 4673 4674 #define S_FW_PI_ERROR_ERR_TYPE 24 4675 #define M_FW_PI_ERROR_ERR_TYPE 0xff 4676 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 4677 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 4678 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 4679 4680 struct fw_tlstx_data_wr { 4681 __be32 op_to_immdlen; 4682 __be32 flowid_len16; 4683 __be32 plen; 4684 __be32 lsodisable_to_flags; 4685 __be32 r5; 4686 __be32 ctxloc_to_exp; 4687 __be16 mfs; 4688 __be16 adjustedplen_pkd; 4689 __be16 expinplenmax_pkd; 4690 __u8 pdusinplenmax_pkd; 4691 __u8 r10; 4692 }; 4693 4694 #define S_FW_TLSTX_DATA_WR_OPCODE 24 4695 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 4696 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 4697 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 4698 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 4699 4700 #define S_FW_TLSTX_DATA_WR_COMPL 21 4701 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 4702 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 4703 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 4704 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 4705 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 4706 4707 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 4708 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 4709 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 4710 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 4711 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 4712 4713 #define S_FW_TLSTX_DATA_WR_FLOWID 8 4714 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 4715 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 4716 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 4717 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 4718 4719 #define S_FW_TLSTX_DATA_WR_LEN16 0 4720 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 4721 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 4722 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 4723 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 4724 4725 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 4726 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 4727 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 4728 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 4729 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 4730 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 4731 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 4732 4733 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 4734 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 4735 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 4736 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 4737 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 4738 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 4739 4740 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 4741 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 4742 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 4743 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 4744 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 4745 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 4746 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 4747 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 4748 4749 #define S_FW_TLSTX_DATA_WR_FLAGS 0 4750 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 4751 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 4752 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 4753 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 4754 4755 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 4756 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 4757 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 4758 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 4759 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 4760 4761 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 4762 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 4763 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 4764 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 4765 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 4766 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 4767 4768 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 4769 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 4770 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 4771 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 4772 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 4773 4774 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 4775 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 4776 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 4777 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 4778 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 4779 4780 #define S_FW_TLSTX_DATA_WR_EXP 0 4781 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 4782 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 4783 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 4784 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 4785 4786 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 4787 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 4788 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 4789 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 4790 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 4791 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 4792 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 4793 4794 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 4795 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 4796 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 4797 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 4798 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 4799 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 4800 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 4801 4802 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 4803 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 4804 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 4805 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 4806 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 4807 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 4808 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 4809 4810 struct fw_crypto_lookaside_wr { 4811 __be32 op_to_cctx_size; 4812 __be32 len16_pkd; 4813 __be32 session_id; 4814 __be32 rx_chid_to_rx_q_id; 4815 __be32 key_addr; 4816 __be32 pld_size_hash_size; 4817 __be64 cookie; 4818 }; 4819 4820 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 4821 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 4822 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 4823 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 4824 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 4825 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 4826 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 4827 4828 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 4829 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 4830 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 4831 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 4832 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 4833 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 4834 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 4835 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 4836 4837 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 4838 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 4839 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4840 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4841 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4842 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 4843 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4844 4845 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 4846 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 4847 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4848 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4849 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4850 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 4851 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4852 4853 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 4854 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 4855 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4856 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4857 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4858 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4859 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4860 4861 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4862 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4863 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4864 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4865 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4866 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4867 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4868 4869 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4870 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4871 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4872 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4873 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4874 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4875 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4876 4877 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4878 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4879 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4880 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4881 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4882 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4883 4884 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4885 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4886 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4887 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4888 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4889 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4890 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4891 4892 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4893 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4894 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4895 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4896 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4897 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4898 4899 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4900 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4901 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4902 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4903 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4904 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4905 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4906 4907 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4908 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4909 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4910 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4911 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4912 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4913 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4914 4915 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4916 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4917 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4918 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4919 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4920 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4921 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4922 4923 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4924 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4925 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4926 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4927 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4928 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4929 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4930 4931 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4932 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4933 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4934 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4935 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4936 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4937 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4938 4939 struct fw_tls_tunnel_ofld_wr { 4940 __be32 op_compl; 4941 __be32 flowid_len16; 4942 __be32 plen; 4943 __be32 r4; 4944 }; 4945 4946 struct fw_crypto_update_sa_wr { 4947 __u8 opcode; 4948 __u8 saop_to_txrx; 4949 __u8 vfn; 4950 __u8 r1; 4951 __u8 r2[3]; 4952 __u8 len16; 4953 __be64 cookie; 4954 __be16 r3; 4955 __be16 ipsecidx; 4956 __be32 SPI; 4957 __be64 dip_hi; 4958 __be64 dip_lo; 4959 __be64 lip_hi; 4960 __be64 lip_lo; 4961 union fw_crypto_update_sa_sa { 4962 struct egress_sa { 4963 __be32 valid_SPI_hi; 4964 __be32 SPI_lo_eSeqNum_hi; 4965 __be32 eSeqNum_lo_Salt_hi; 4966 __be32 Salt_lo_to_keyID; 4967 } egress; 4968 struct ingress_sa { 4969 __be32 valid_to_iSeqNum_hi; 4970 __be32 iSeqNum_mi; 4971 __be32 iSeqNum_lo_Salt_hi; 4972 __be32 Salt_lo_to_IPVer; 4973 } ingress; 4974 } sa; 4975 union fw_crypto_update_sa_key { 4976 struct _aes128 { 4977 __u8 key128[16]; 4978 __u8 H128[16]; 4979 __u8 rsvd[16]; 4980 } aes128; 4981 struct _aes192 { 4982 __u8 key192[24]; 4983 __be64 r3; 4984 __u8 H192[16]; 4985 } aes192; 4986 struct _aes256 { 4987 __u8 key256[32]; 4988 __u8 H256[16]; 4989 } aes256; 4990 } key; 4991 }; 4992 4993 #define S_FW_CRYPTO_UPDATE_SA_WR_SAOP 2 4994 #define M_FW_CRYPTO_UPDATE_SA_WR_SAOP 0x1 4995 #define V_FW_CRYPTO_UPDATE_SA_WR_SAOP(x) \ 4996 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SAOP) 4997 #define G_FW_CRYPTO_UPDATE_SA_WR_SAOP(x) \ 4998 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SAOP) & M_FW_CRYPTO_UPDATE_SA_WR_SAOP) 4999 #define F_FW_CRYPTO_UPDATE_SA_WR_SAOP V_FW_CRYPTO_UPDATE_SA_WR_SAOP(1U) 5000 5001 #define S_FW_CRYPTO_UPDATE_SA_WR_MODE 1 5002 #define M_FW_CRYPTO_UPDATE_SA_WR_MODE 0x1 5003 #define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5004 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE) 5005 #define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5006 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE) 5007 #define F_FW_CRYPTO_UPDATE_SA_WR_MODE V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U) 5008 5009 #define S_FW_CRYPTO_UPDATE_SA_WR_TXRX 0 5010 #define M_FW_CRYPTO_UPDATE_SA_WR_TXRX 0x1 5011 #define V_FW_CRYPTO_UPDATE_SA_WR_TXRX(x) \ 5012 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_TXRX) 5013 #define G_FW_CRYPTO_UPDATE_SA_WR_TXRX(x) \ 5014 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_TXRX) & M_FW_CRYPTO_UPDATE_SA_WR_TXRX) 5015 #define F_FW_CRYPTO_UPDATE_SA_WR_TXRX V_FW_CRYPTO_UPDATE_SA_WR_TXRX(1U) 5016 5017 #define S_FW_CRYPTO_UPDATE_SA_WR_VALID 31 5018 #define M_FW_CRYPTO_UPDATE_SA_WR_VALID 0x1 5019 #define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5020 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID) 5021 #define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5022 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID) 5023 #define F_FW_CRYPTO_UPDATE_SA_WR_VALID V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U) 5024 5025 #define S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI 0 5026 #define M_FW_CRYPTO_UPDATE_SA_WR_SPI_HI 0x7fffffff 5027 #define V_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x) \ 5028 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) 5029 #define G_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x) \ 5030 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) & \ 5031 M_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) 5032 5033 #define S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO 31 5034 #define M_FW_CRYPTO_UPDATE_SA_WR_SPI_LO 0x1 5035 #define V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x) \ 5036 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) 5037 #define G_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x) \ 5038 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) & \ 5039 M_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) 5040 #define F_FW_CRYPTO_UPDATE_SA_WR_SPI_LO V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(1U) 5041 5042 #define S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI 0 5043 #define M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI 0x7fffffff 5044 #define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x) \ 5045 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) 5046 #define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x) \ 5047 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) & \ 5048 M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) 5049 5050 #define S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO 7 5051 #define M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO 0x1ffffff 5052 #define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x) \ 5053 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) 5054 #define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x) \ 5055 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) & \ 5056 M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) 5057 5058 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0 5059 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0x7f 5060 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5061 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5062 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5063 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \ 5064 M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5065 5066 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 7 5067 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 0x1ffffff 5068 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5069 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5070 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5071 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \ 5072 M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5073 5074 #define S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 5 5075 #define M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 0x3 5076 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5077 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5078 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5079 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \ 5080 M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5081 5082 #define S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE 4 5083 #define M_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE 0x1 5084 #define V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x) \ 5085 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) 5086 #define G_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x) \ 5087 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) & \ 5088 M_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) 5089 #define F_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE \ 5090 V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(1U) 5091 5092 #define S_FW_CRYPTO_UPDATE_SA_WR_KEYID 0 5093 #define M_FW_CRYPTO_UPDATE_SA_WR_KEYID 0xf 5094 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYID(x) \ 5095 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYID) 5096 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYID(x) \ 5097 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYID) & M_FW_CRYPTO_UPDATE_SA_WR_KEYID) 5098 5099 #define S_FW_CRYPTO_UPDATE_SA_WR_VALID 31 5100 #define M_FW_CRYPTO_UPDATE_SA_WR_VALID 0x1 5101 #define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5102 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID) 5103 #define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5104 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID) 5105 #define F_FW_CRYPTO_UPDATE_SA_WR_VALID V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U) 5106 5107 #define S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID 12 5108 #define M_FW_CRYPTO_UPDATE_SA_WR_EGKEYID 0xfff 5109 #define V_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x) \ 5110 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) 5111 #define G_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x) \ 5112 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) & \ 5113 M_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) 5114 5115 #define S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN 11 5116 #define M_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN 0x1 5117 #define V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x) \ 5118 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) 5119 #define G_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x) \ 5120 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) & \ 5121 M_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) 5122 #define F_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN \ 5123 V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(1U) 5124 5125 #define S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW 7 5126 #define M_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW 0xf 5127 #define V_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x) \ 5128 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) 5129 #define G_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x) \ 5130 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) & \ 5131 M_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) 5132 5133 #define S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI 0 5134 #define M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI 0x7f 5135 #define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x) \ 5136 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) 5137 #define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x) \ 5138 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) & \ 5139 M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) 5140 5141 #define S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO 7 5142 #define M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO 0x1ffffff 5143 #define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x) \ 5144 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) 5145 #define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x) \ 5146 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) & \ 5147 M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) 5148 5149 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0 5150 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0x7f 5151 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5152 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5153 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5154 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \ 5155 M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5156 5157 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 7 5158 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 0x1ffffff 5159 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5160 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5161 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5162 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \ 5163 M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5164 5165 #define S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 5 5166 #define M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 0x3 5167 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5168 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5169 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5170 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \ 5171 M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5172 5173 #define S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH 3 5174 #define M_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH 0x3 5175 #define V_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x) \ 5176 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) 5177 #define G_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x) \ 5178 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) & \ 5179 M_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) 5180 5181 #define S_FW_CRYPTO_UPDATE_SA_WR_ESNEN 2 5182 #define M_FW_CRYPTO_UPDATE_SA_WR_ESNEN 0x1 5183 #define V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x) \ 5184 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNEN) 5185 #define G_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x) \ 5186 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNEN) & M_FW_CRYPTO_UPDATE_SA_WR_ESNEN) 5187 #define F_FW_CRYPTO_UPDATE_SA_WR_ESNEN V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(1U) 5188 5189 #define S_FW_CRYPTO_UPDATE_SA_WR_MODE 1 5190 #define M_FW_CRYPTO_UPDATE_SA_WR_MODE 0x1 5191 #define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5192 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE) 5193 #define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5194 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE) 5195 #define F_FW_CRYPTO_UPDATE_SA_WR_MODE V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U) 5196 5197 #define S_FW_CRYPTO_UPDATE_SA_WR_IPVER 0 5198 #define M_FW_CRYPTO_UPDATE_SA_WR_IPVER 0x1 5199 #define V_FW_CRYPTO_UPDATE_SA_WR_IPVER(x) \ 5200 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_IPVER) 5201 #define G_FW_CRYPTO_UPDATE_SA_WR_IPVER(x) \ 5202 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_IPVER) & M_FW_CRYPTO_UPDATE_SA_WR_IPVER) 5203 #define F_FW_CRYPTO_UPDATE_SA_WR_IPVER V_FW_CRYPTO_UPDATE_SA_WR_IPVER(1U) 5204 5205 /****************************************************************************** 5206 * C O M M A N D s 5207 *********************/ 5208 5209 /* 5210 * The maximum length of time, in miliseconds, that we expect any firmware 5211 * command to take to execute and return a reply to the host. The RESET 5212 * and INITIALIZE commands can take a fair amount of time to execute but 5213 * most execute in far less time than this maximum. This constant is used 5214 * by host software to determine how long to wait for a firmware command 5215 * reply before declaring the firmware as dead/unreachable ... 5216 */ 5217 #define FW_CMD_MAX_TIMEOUT 10000 5218 5219 /* 5220 * If a host driver does a HELLO and discovers that there's already a MASTER 5221 * selected, we may have to wait for that MASTER to finish issuing RESET, 5222 * configuration and INITIALIZE commands. Also, there's a possibility that 5223 * our own HELLO may get lost if it happens right as the MASTER is issuign a 5224 * RESET command, so we need to be willing to make a few retries of our HELLO. 5225 */ 5226 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 5227 #define FW_CMD_HELLO_RETRIES 3 5228 5229 enum fw_cmd_opcodes { 5230 FW_LDST_CMD = 0x01, 5231 FW_RESET_CMD = 0x03, 5232 FW_HELLO_CMD = 0x04, 5233 FW_BYE_CMD = 0x05, 5234 FW_INITIALIZE_CMD = 0x06, 5235 FW_CAPS_CONFIG_CMD = 0x07, 5236 FW_PARAMS_CMD = 0x08, 5237 FW_PFVF_CMD = 0x09, 5238 FW_IQ_CMD = 0x10, 5239 FW_EQ_MNGT_CMD = 0x11, 5240 FW_EQ_ETH_CMD = 0x12, 5241 FW_EQ_CTRL_CMD = 0x13, 5242 FW_EQ_OFLD_CMD = 0x21, 5243 FW_VI_CMD = 0x14, 5244 FW_VI_MAC_CMD = 0x15, 5245 FW_VI_RXMODE_CMD = 0x16, 5246 FW_VI_ENABLE_CMD = 0x17, 5247 FW_VI_STATS_CMD = 0x1a, 5248 FW_ACL_MAC_CMD = 0x18, 5249 FW_ACL_VLAN_CMD = 0x19, 5250 FW_PORT_CMD = 0x1b, 5251 FW_PORT_STATS_CMD = 0x1c, 5252 FW_PORT_LB_STATS_CMD = 0x1d, 5253 FW_PORT_TRACE_CMD = 0x1e, 5254 FW_PORT_TRACE_MMAP_CMD = 0x1f, 5255 FW_RSS_IND_TBL_CMD = 0x20, 5256 FW_RSS_GLB_CONFIG_CMD = 0x22, 5257 FW_RSS_VI_CONFIG_CMD = 0x23, 5258 FW_SCHED_CMD = 0x24, 5259 FW_DEVLOG_CMD = 0x25, 5260 FW_WATCHDOG_CMD = 0x27, 5261 FW_CLIP_CMD = 0x28, 5262 FW_CLIP2_CMD = 0x29, 5263 FW_CHNET_IFACE_CMD = 0x26, 5264 FW_FCOE_RES_INFO_CMD = 0x31, 5265 FW_FCOE_LINK_CMD = 0x32, 5266 FW_FCOE_VNP_CMD = 0x33, 5267 FW_FCOE_SPARAMS_CMD = 0x35, 5268 FW_FCOE_STATS_CMD = 0x37, 5269 FW_FCOE_FCF_CMD = 0x38, 5270 FW_DCB_IEEE_CMD = 0x3a, 5271 FW_DIAG_CMD = 0x3d, 5272 FW_PTP_CMD = 0x3e, 5273 FW_HMA_CMD = 0x3f, 5274 FW_JBOF_WIN_REG_CMD = 0x40, 5275 FW_LASTC2E_CMD = 0x41, 5276 FW_ERROR_CMD = 0x80, 5277 FW_DEBUG_CMD = 0x81, 5278 }; 5279 5280 enum fw_cmd_cap { 5281 FW_CMD_CAP_PF = 0x01, 5282 FW_CMD_CAP_DMAQ = 0x02, 5283 FW_CMD_CAP_PORT = 0x04, 5284 FW_CMD_CAP_PORTPROMISC = 0x08, 5285 FW_CMD_CAP_PORTSTATS = 0x10, 5286 FW_CMD_CAP_VF = 0x80, 5287 }; 5288 5289 /* 5290 * Generic command header flit0 5291 */ 5292 struct fw_cmd_hdr { 5293 __be32 hi; 5294 __be32 lo; 5295 }; 5296 5297 #define S_FW_CMD_OP 24 5298 #define M_FW_CMD_OP 0xff 5299 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 5300 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 5301 5302 #define S_FW_CMD_REQUEST 23 5303 #define M_FW_CMD_REQUEST 0x1 5304 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 5305 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 5306 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 5307 5308 #define S_FW_CMD_READ 22 5309 #define M_FW_CMD_READ 0x1 5310 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 5311 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 5312 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 5313 5314 #define S_FW_CMD_WRITE 21 5315 #define M_FW_CMD_WRITE 0x1 5316 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 5317 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 5318 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 5319 5320 #define S_FW_CMD_EXEC 20 5321 #define M_FW_CMD_EXEC 0x1 5322 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 5323 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 5324 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 5325 5326 #define S_FW_CMD_RAMASK 20 5327 #define M_FW_CMD_RAMASK 0xf 5328 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 5329 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 5330 5331 #define S_FW_CMD_RETVAL 8 5332 #define M_FW_CMD_RETVAL 0xff 5333 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 5334 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 5335 5336 #define S_FW_CMD_LEN16 0 5337 #define M_FW_CMD_LEN16 0xff 5338 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 5339 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 5340 5341 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 5342 5343 /* 5344 * address spaces 5345 */ 5346 enum fw_ldst_addrspc { 5347 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 5348 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 5349 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 5350 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 5351 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 5352 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 5353 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 5354 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 5355 FW_LDST_ADDRSPC_MDIO = 0x0018, 5356 FW_LDST_ADDRSPC_MPS = 0x0020, 5357 FW_LDST_ADDRSPC_FUNC = 0x0028, 5358 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 5359 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 5360 FW_LDST_ADDRSPC_LE = 0x0030, 5361 FW_LDST_ADDRSPC_I2C = 0x0038, 5362 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 5363 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 5364 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 5365 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 5366 }; 5367 5368 /* 5369 * MDIO VSC8634 register access control field 5370 */ 5371 enum fw_ldst_mdio_vsc8634_aid { 5372 FW_LDST_MDIO_VS_STANDARD, 5373 FW_LDST_MDIO_VS_EXTENDED, 5374 FW_LDST_MDIO_VS_GPIO 5375 }; 5376 5377 enum fw_ldst_mps_fid { 5378 FW_LDST_MPS_ATRB, 5379 FW_LDST_MPS_RPLC 5380 }; 5381 5382 enum fw_ldst_func_access_ctl { 5383 FW_LDST_FUNC_ACC_CTL_VIID, 5384 FW_LDST_FUNC_ACC_CTL_FID 5385 }; 5386 5387 enum fw_ldst_func_mod_index { 5388 FW_LDST_FUNC_MPS 5389 }; 5390 5391 struct fw_ldst_cmd { 5392 __be32 op_to_addrspace; 5393 __be32 cycles_to_len16; 5394 union fw_ldst { 5395 struct fw_ldst_addrval { 5396 __be32 addr; 5397 __be32 val; 5398 } addrval; 5399 struct fw_ldst_idctxt { 5400 __be32 physid; 5401 __be32 msg_ctxtflush; 5402 __be32 ctxt_data7; 5403 __be32 ctxt_data6; 5404 __be32 ctxt_data5; 5405 __be32 ctxt_data4; 5406 __be32 ctxt_data3; 5407 __be32 ctxt_data2; 5408 __be32 ctxt_data1; 5409 __be32 ctxt_data0; 5410 } idctxt; 5411 struct fw_ldst_mdio { 5412 __be16 paddr_mmd; 5413 __be16 raddr; 5414 __be16 vctl; 5415 __be16 rval; 5416 } mdio; 5417 struct fw_ldst_cim_rq { 5418 __u8 req_first64[8]; 5419 __u8 req_second64[8]; 5420 __u8 resp_first64[8]; 5421 __u8 resp_second64[8]; 5422 __be32 r3[2]; 5423 } cim_rq; 5424 union fw_ldst_mps { 5425 struct fw_ldst_mps_rplc { 5426 __be16 fid_idx; 5427 __be16 rplcpf_pkd; 5428 __be32 rplc255_224; 5429 __be32 rplc223_192; 5430 __be32 rplc191_160; 5431 __be32 rplc159_128; 5432 __be32 rplc127_96; 5433 __be32 rplc95_64; 5434 __be32 rplc63_32; 5435 __be32 rplc31_0; 5436 } rplc; 5437 struct fw_ldst_mps_atrb { 5438 __be16 fid_mpsid; 5439 __be16 r2[3]; 5440 __be32 r3[2]; 5441 __be32 r4; 5442 __be32 atrb; 5443 __be16 vlan[16]; 5444 } atrb; 5445 } mps; 5446 struct fw_ldst_func { 5447 __u8 access_ctl; 5448 __u8 mod_index; 5449 __be16 ctl_id; 5450 __be32 offset; 5451 __be64 data0; 5452 __be64 data1; 5453 } func; 5454 struct fw_ldst_pcie { 5455 __u8 ctrl_to_fn; 5456 __u8 bnum; 5457 __u8 r; 5458 __u8 ext_r; 5459 __u8 select_naccess; 5460 __u8 pcie_fn; 5461 __be16 nset_pkd; 5462 __be32 data[12]; 5463 } pcie; 5464 struct fw_ldst_i2c_deprecated { 5465 __u8 pid_pkd; 5466 __u8 base; 5467 __u8 boffset; 5468 __u8 data; 5469 __be32 r9; 5470 } i2c_deprecated; 5471 struct fw_ldst_i2c { 5472 __u8 pid; 5473 __u8 did; 5474 __u8 boffset; 5475 __u8 blen; 5476 __be32 r9; 5477 __u8 data[48]; 5478 } i2c; 5479 struct fw_ldst_le { 5480 __be32 index; 5481 __be32 r9; 5482 __u8 val[33]; 5483 __u8 r11[7]; 5484 } le; 5485 } u; 5486 }; 5487 5488 #define S_FW_LDST_CMD_ADDRSPACE 0 5489 #define M_FW_LDST_CMD_ADDRSPACE 0xff 5490 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 5491 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 5492 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 5493 5494 #define S_FW_LDST_CMD_CYCLES 16 5495 #define M_FW_LDST_CMD_CYCLES 0xffff 5496 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 5497 #define G_FW_LDST_CMD_CYCLES(x) \ 5498 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 5499 5500 #define S_FW_LDST_CMD_MSG 31 5501 #define M_FW_LDST_CMD_MSG 0x1 5502 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 5503 #define G_FW_LDST_CMD_MSG(x) \ 5504 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 5505 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 5506 5507 #define S_FW_LDST_CMD_CTXTFLUSH 30 5508 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 5509 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 5510 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 5511 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 5512 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 5513 5514 #define S_FW_LDST_CMD_PADDR 8 5515 #define M_FW_LDST_CMD_PADDR 0x1f 5516 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 5517 #define G_FW_LDST_CMD_PADDR(x) \ 5518 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 5519 5520 #define S_FW_LDST_CMD_MMD 0 5521 #define M_FW_LDST_CMD_MMD 0x1f 5522 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 5523 #define G_FW_LDST_CMD_MMD(x) \ 5524 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 5525 5526 #define S_FW_LDST_CMD_FID 15 5527 #define M_FW_LDST_CMD_FID 0x1 5528 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 5529 #define G_FW_LDST_CMD_FID(x) \ 5530 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 5531 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 5532 5533 #define S_FW_LDST_CMD_IDX 0 5534 #define M_FW_LDST_CMD_IDX 0x7fff 5535 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 5536 #define G_FW_LDST_CMD_IDX(x) \ 5537 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 5538 5539 #define S_FW_LDST_CMD_RPLCPF 0 5540 #define M_FW_LDST_CMD_RPLCPF 0xff 5541 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 5542 #define G_FW_LDST_CMD_RPLCPF(x) \ 5543 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 5544 5545 #define S_FW_LDST_CMD_MPSID 0 5546 #define M_FW_LDST_CMD_MPSID 0x7fff 5547 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 5548 #define G_FW_LDST_CMD_MPSID(x) \ 5549 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 5550 5551 #define S_FW_LDST_CMD_CTRL 7 5552 #define M_FW_LDST_CMD_CTRL 0x1 5553 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 5554 #define G_FW_LDST_CMD_CTRL(x) \ 5555 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 5556 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 5557 5558 #define S_FW_LDST_CMD_LC 4 5559 #define M_FW_LDST_CMD_LC 0x1 5560 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 5561 #define G_FW_LDST_CMD_LC(x) \ 5562 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 5563 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 5564 5565 #define S_FW_LDST_CMD_AI 3 5566 #define M_FW_LDST_CMD_AI 0x1 5567 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 5568 #define G_FW_LDST_CMD_AI(x) \ 5569 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 5570 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 5571 5572 #define S_FW_LDST_CMD_FN 0 5573 #define M_FW_LDST_CMD_FN 0x7 5574 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 5575 #define G_FW_LDST_CMD_FN(x) \ 5576 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 5577 5578 #define S_FW_LDST_CMD_SELECT 4 5579 #define M_FW_LDST_CMD_SELECT 0xf 5580 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 5581 #define G_FW_LDST_CMD_SELECT(x) \ 5582 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 5583 5584 #define S_FW_LDST_CMD_NACCESS 0 5585 #define M_FW_LDST_CMD_NACCESS 0xf 5586 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 5587 #define G_FW_LDST_CMD_NACCESS(x) \ 5588 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 5589 5590 #define S_FW_LDST_CMD_NSET 14 5591 #define M_FW_LDST_CMD_NSET 0x3 5592 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 5593 #define G_FW_LDST_CMD_NSET(x) \ 5594 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 5595 5596 #define S_FW_LDST_CMD_PID 6 5597 #define M_FW_LDST_CMD_PID 0x3 5598 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 5599 #define G_FW_LDST_CMD_PID(x) \ 5600 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 5601 5602 struct fw_reset_cmd { 5603 __be32 op_to_write; 5604 __be32 retval_len16; 5605 __be32 val; 5606 __be32 halt_pkd; 5607 }; 5608 5609 #define S_FW_RESET_CMD_HALT 31 5610 #define M_FW_RESET_CMD_HALT 0x1 5611 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 5612 #define G_FW_RESET_CMD_HALT(x) \ 5613 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 5614 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 5615 5616 enum { 5617 FW_HELLO_CMD_STAGE_OS = 0, 5618 FW_HELLO_CMD_STAGE_PREOS0 = 1, 5619 FW_HELLO_CMD_STAGE_PREOS1 = 2, 5620 FW_HELLO_CMD_STAGE_POSTOS = 3, 5621 }; 5622 5623 struct fw_hello_cmd { 5624 __be32 op_to_write; 5625 __be32 retval_len16; 5626 __be32 err_to_clearinit; 5627 __be32 fwrev; 5628 }; 5629 5630 #define S_FW_HELLO_CMD_ERR 31 5631 #define M_FW_HELLO_CMD_ERR 0x1 5632 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 5633 #define G_FW_HELLO_CMD_ERR(x) \ 5634 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 5635 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 5636 5637 #define S_FW_HELLO_CMD_INIT 30 5638 #define M_FW_HELLO_CMD_INIT 0x1 5639 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 5640 #define G_FW_HELLO_CMD_INIT(x) \ 5641 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 5642 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 5643 5644 #define S_FW_HELLO_CMD_MASTERDIS 29 5645 #define M_FW_HELLO_CMD_MASTERDIS 0x1 5646 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 5647 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 5648 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 5649 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 5650 5651 #define S_FW_HELLO_CMD_MASTERFORCE 28 5652 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 5653 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 5654 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 5655 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 5656 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 5657 5658 #define S_FW_HELLO_CMD_MBMASTER 24 5659 #define M_FW_HELLO_CMD_MBMASTER 0xf 5660 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 5661 #define G_FW_HELLO_CMD_MBMASTER(x) \ 5662 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 5663 5664 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 5665 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 5666 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 5667 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 5668 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 5669 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 5670 5671 #define S_FW_HELLO_CMD_MBASYNCNOT 20 5672 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 5673 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 5674 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 5675 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 5676 5677 #define S_FW_HELLO_CMD_STAGE 17 5678 #define M_FW_HELLO_CMD_STAGE 0x7 5679 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 5680 #define G_FW_HELLO_CMD_STAGE(x) \ 5681 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 5682 5683 #define S_FW_HELLO_CMD_CLEARINIT 16 5684 #define M_FW_HELLO_CMD_CLEARINIT 0x1 5685 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 5686 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 5687 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 5688 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 5689 5690 struct fw_bye_cmd { 5691 __be32 op_to_write; 5692 __be32 retval_len16; 5693 __be64 r3; 5694 }; 5695 5696 struct fw_initialize_cmd { 5697 __be32 op_to_write; 5698 __be32 retval_len16; 5699 __be64 r3; 5700 }; 5701 5702 enum fw_caps_config_hm { 5703 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 5704 FW_CAPS_CONFIG_HM_PL = 0x00000002, 5705 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 5706 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 5707 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 5708 FW_CAPS_CONFIG_HM_TP = 0x00000020, 5709 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 5710 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 5711 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 5712 FW_CAPS_CONFIG_HM_MC = 0x00000200, 5713 FW_CAPS_CONFIG_HM_LE = 0x00000400, 5714 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 5715 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 5716 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 5717 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 5718 FW_CAPS_CONFIG_HM_MI = 0x00008000, 5719 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 5720 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 5721 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 5722 FW_CAPS_CONFIG_HM_MA = 0x00080000, 5723 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 5724 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 5725 FW_CAPS_CONFIG_HM_UART = 0x00400000, 5726 FW_CAPS_CONFIG_HM_SF = 0x00800000, 5727 }; 5728 5729 /* 5730 * The VF Register Map. 5731 * 5732 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 5733 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 5734 * the Slice to Module Map Table (see below) in the Physical Function Register 5735 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 5736 * and Offset registers in the PF Register Map. The MBDATA base address is 5737 * quite constrained as it determines the Mailbox Data addresses for both PFs 5738 * and VFs, and therefore must fit in both the VF and PF Register Maps without 5739 * overlapping other registers. 5740 */ 5741 #define FW_T4VF_SGE_BASE_ADDR 0x0000 5742 #define FW_T4VF_MPS_BASE_ADDR 0x0100 5743 #define FW_T4VF_PL_BASE_ADDR 0x0200 5744 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 5745 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 5746 #define FW_T4VF_CIM_BASE_ADDR 0x0300 5747 5748 #define FW_T4VF_REGMAP_START 0x0000 5749 #define FW_T4VF_REGMAP_SIZE 0x0400 5750 5751 enum fw_caps_config_nbm { 5752 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 5753 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 5754 }; 5755 5756 enum fw_caps_config_link { 5757 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 5758 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 5759 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 5760 }; 5761 5762 enum fw_caps_config_switch { 5763 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 5764 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 5765 }; 5766 5767 enum fw_caps_config_nic { 5768 FW_CAPS_CONFIG_NIC = 0x00000001, 5769 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 5770 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 5771 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 5772 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 5773 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 5774 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 5775 }; 5776 5777 enum fw_caps_config_toe { 5778 FW_CAPS_CONFIG_TOE = 0x00000001, 5779 FW_CAPS_CONFIG_TOE_SENDPATH = 0x00000002, 5780 }; 5781 5782 enum fw_caps_config_rdma { 5783 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 5784 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 5785 FW_CAPS_CONFIG_RDMA_ROCEV2 = 0x00000004, 5786 }; 5787 5788 enum fw_caps_config_nvme { 5789 FW_CAPS_CONFIG_NVME_TCP = 0x00000001, 5790 }; 5791 5792 enum fw_caps_config_iscsi { 5793 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 5794 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 5795 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 5796 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 5797 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 5798 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 5799 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 5800 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 5801 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 5802 }; 5803 5804 enum fw_caps_config_crypto { 5805 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 5806 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 5807 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, /* NIC over ipsecofld */ 5808 FW_CAPS_CONFIG_TLS_HW = 0x00000008, 5809 FW_CAPS_CONFIG_OFLD_OVER_IPSEC_INLINE = 0x00000010,/* ofld over ipsecofld */ 5810 }; 5811 5812 enum fw_caps_config_fcoe { 5813 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 5814 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 5815 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 5816 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 5817 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 5818 }; 5819 5820 enum fw_memtype_cf { 5821 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 5822 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 5823 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 5824 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 5825 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 5826 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 5827 }; 5828 5829 struct fw_caps_config_cmd { 5830 __be32 op_to_write; 5831 __be32 cfvalid_to_len16; 5832 __be32 r2; 5833 __be32 hwmbitmap; 5834 __be16 nbmcaps; 5835 __be16 linkcaps; 5836 __be16 switchcaps; 5837 __be16 nvmecaps; 5838 __be16 niccaps; 5839 __be16 toecaps; 5840 __be16 rdmacaps; 5841 __be16 cryptocaps; 5842 __be16 iscsicaps; 5843 __be16 fcoecaps; 5844 __be32 cfcsum; 5845 __be32 finiver; 5846 __be32 finicsum; 5847 }; 5848 5849 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 5850 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 5851 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 5852 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 5853 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 5854 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 5855 5856 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 5857 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 5858 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 5859 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 5860 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 5861 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 5862 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 5863 5864 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 5865 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 5866 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 5867 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 5868 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 5869 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 5870 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 5871 5872 /* 5873 * params command mnemonics 5874 */ 5875 enum fw_params_mnem { 5876 FW_PARAMS_MNEM_DEV = 1, /* device params */ 5877 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 5878 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 5879 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 5880 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 5881 FW_PARAMS_MNEM_LAST 5882 }; 5883 5884 /* 5885 * device parameters 5886 */ 5887 #define S_FW_PARAMS_PARAM_FILTER_MODE 16 5888 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 5889 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 5890 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 5891 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 5892 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 5893 M_FW_PARAMS_PARAM_FILTER_MODE) 5894 5895 #define S_FW_PARAMS_PARAM_FILTER_MASK 0 5896 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 5897 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 5898 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 5899 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 5900 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 5901 M_FW_PARAMS_PARAM_FILTER_MASK) 5902 5903 enum fw_params_param_dev { 5904 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 5905 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 5906 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 5907 * allocated by the device's 5908 * Lookup Engine 5909 */ 5910 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 5911 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 5912 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 5913 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 5914 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 5915 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 5916 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 5917 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 5918 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 5919 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 5920 FW_PARAMS_PARAM_DEV_CF = 0x0D, 5921 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 5922 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 5923 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 5924 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 5925 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 5926 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 5927 */ 5928 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 5929 */ 5930 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 5931 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 5932 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 5933 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 5934 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 5935 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 5936 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 5937 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 5938 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 5939 5940 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 5941 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 5942 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 5943 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 5944 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 5945 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 5946 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 5947 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 5948 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 5949 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 5950 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 5951 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 5952 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 5953 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 5954 FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C, 5955 FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D, 5956 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 5957 FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F, 5958 FW_PARAMS_PARAM_DEV_DEV_512SGL_MR = 0x30, 5959 FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31, 5960 FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32, 5961 FW_PARAMS_PARAM_DEV_TID_QID_SEL_MASK = 0x33, 5962 FW_PARAMS_PARAM_DEV_TX_TPCHMAP = 0x3A, 5963 }; 5964 5965 /* 5966 * dev bypass parameters; actions and modes 5967 */ 5968 enum fw_params_param_dev_bypass { 5969 5970 /* actions 5971 */ 5972 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 5973 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 5974 5975 /* modes 5976 */ 5977 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 5978 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 5979 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 5980 }; 5981 5982 enum fw_params_param_dev_phyfw { 5983 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 5984 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 5985 }; 5986 5987 enum fw_params_param_dev_diag { 5988 FW_PARAM_DEV_DIAG_TMP = 0x00, 5989 FW_PARAM_DEV_DIAG_VDD = 0x01, 5990 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 5991 FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03, 5992 }; 5993 5994 enum fw_params_param_dev_filter{ 5995 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 5996 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 5997 }; 5998 5999 enum fw_filter_vnic_mode { 6000 FW_VNIC_MODE_PF_VF = 0, 6001 FW_VNIC_MODE_OUTER_VLAN = 1, 6002 FW_VNIC_MODE_ENCAP_EN = 2, 6003 }; 6004 6005 enum fw_params_param_dev_ktls_hw { 6006 FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00, 6007 FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE = 0x01, 6008 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE = 0x00, 6009 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE = 0x01, 6010 }; 6011 6012 enum fw_params_param_dev_fwcache { 6013 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 6014 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 6015 }; 6016 6017 /* 6018 * physical and virtual function parameters 6019 */ 6020 enum fw_params_param_pfvf { 6021 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 6022 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 6023 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 6024 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 6025 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 6026 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 6027 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 6028 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 6029 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 6030 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 6031 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 6032 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 6033 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 6034 /* no separate STAG/PBL START/END for nvmet. 6035 * use same rdma stag/pbl memory range */ 6036 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 6037 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 6038 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 6039 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 6040 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 6041 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 6042 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 6043 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 6044 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 6045 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 6046 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 6047 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 6048 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 6049 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 6050 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 6051 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 6052 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 6053 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 6054 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 6055 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 6056 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 6057 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 6058 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 6059 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 6060 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 6061 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 6062 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 6063 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 6064 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 6065 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 6066 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 6067 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 6068 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 6069 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 6070 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 6071 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 6072 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 6073 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 6074 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 6075 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 6076 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 6077 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 6078 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 6079 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 6080 FW_PARAMS_PARAM_PFVF_RRQ_START = 0x41, 6081 FW_PARAMS_PARAM_PFVF_RRQ_END = 0x42, 6082 FW_PARAMS_PARAM_PFVF_PKTHDR_START = 0x43, 6083 FW_PARAMS_PARAM_PFVF_PKTHDR_END = 0x44, 6084 FW_PARAMS_PARAM_PFVF_NIPSEC_TUNNEL = 0x45, 6085 FW_PARAMS_PARAM_PFVF_NIPSEC_TRANSPORT = 0x46, 6086 FW_PARAMS_PARAM_PFVF_OFLD_NIPSEC_TUNNEL = 0x47, 6087 }; 6088 6089 /* 6090 * virtual link state as seen by the specified VF 6091 */ 6092 enum vf_link_states { 6093 VF_LINK_STATE_AUTO = 0x00, 6094 VF_LINK_STATE_ENABLE = 0x01, 6095 VF_LINK_STATE_DISABLE = 0x02, 6096 }; 6097 6098 /* 6099 * dma queue parameters 6100 */ 6101 enum fw_params_param_dmaq { 6102 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 6103 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 6104 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 6105 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 6106 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 6107 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 6108 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 6109 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 6110 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 6111 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 6112 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 6113 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 6114 }; 6115 6116 #define S_T7_DMAQ_CONM_CTXT_CNGTPMODE 0 6117 #define M_T7_DMAQ_CONM_CTXT_CNGTPMODE 0x3 6118 #define V_T7_DMAQ_CONM_CTXT_CNGTPMODE(x) ((x) << S_T7_DMAQ_CONM_CTXT_CNGTPMODE) 6119 #define G_T7_DMAQ_CONM_CTXT_CNGTPMODE(x) \ 6120 (((x) >> S_T7_DMAQ_CONM_CTXT_CNGTPMODE) & M_T7_DMAQ_CONM_CTXT_CNGTPMODE) 6121 6122 #define S_T7_DMAQ_CONM_CTXT_CH_VEC 2 6123 #define M_T7_DMAQ_CONM_CTXT_CH_VEC 0xf 6124 #define V_T7_DMAQ_CONM_CTXT_CH_VEC(x) ((x) << S_T7_DMAQ_CONM_CTXT_CH_VEC) 6125 #define G_T7_DMAQ_CONM_CTXT_CH_VEC(x) \ 6126 (((x) >> S_T7_DMAQ_CONM_CTXT_CH_VEC) & M_T7_DMAQ_CONM_CTXT_CH_VEC) 6127 6128 6129 /* 6130 * chnet parameters 6131 */ 6132 enum fw_params_param_chnet { 6133 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 6134 }; 6135 6136 enum fw_params_param_chnet_flags { 6137 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 6138 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 6139 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 6140 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8, 6141 }; 6142 6143 #define S_FW_PARAMS_MNEM 24 6144 #define M_FW_PARAMS_MNEM 0xff 6145 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 6146 #define G_FW_PARAMS_MNEM(x) \ 6147 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 6148 6149 #define S_FW_PARAMS_PARAM_X 16 6150 #define M_FW_PARAMS_PARAM_X 0xff 6151 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 6152 #define G_FW_PARAMS_PARAM_X(x) \ 6153 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 6154 6155 #define S_FW_PARAMS_PARAM_Y 8 6156 #define M_FW_PARAMS_PARAM_Y 0xff 6157 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 6158 #define G_FW_PARAMS_PARAM_Y(x) \ 6159 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 6160 6161 #define S_FW_PARAMS_PARAM_Z 0 6162 #define M_FW_PARAMS_PARAM_Z 0xff 6163 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 6164 #define G_FW_PARAMS_PARAM_Z(x) \ 6165 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 6166 6167 #define S_FW_PARAMS_PARAM_XYZ 0 6168 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 6169 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 6170 #define G_FW_PARAMS_PARAM_XYZ(x) \ 6171 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 6172 6173 #define S_FW_PARAMS_PARAM_YZ 0 6174 #define M_FW_PARAMS_PARAM_YZ 0xffff 6175 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 6176 #define G_FW_PARAMS_PARAM_YZ(x) \ 6177 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 6178 6179 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 6180 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 6181 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 6182 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 6183 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 6184 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 6185 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 6186 6187 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 6188 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 6189 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 6190 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 6191 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 6192 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 6193 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 6194 6195 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 6196 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 6197 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 6198 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 6199 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 6200 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 6201 6202 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 6203 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 6204 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 6205 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 6206 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 6207 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 6208 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 6209 6210 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 6211 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 6212 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 6213 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 6214 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 6215 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 6216 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 6217 6218 struct fw_params_cmd { 6219 __be32 op_to_vfn; 6220 __be32 retval_len16; 6221 struct fw_params_param { 6222 __be32 mnem; 6223 __be32 val; 6224 } param[7]; 6225 }; 6226 6227 #define S_FW_PARAMS_CMD_PFN 8 6228 #define M_FW_PARAMS_CMD_PFN 0x7 6229 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 6230 #define G_FW_PARAMS_CMD_PFN(x) \ 6231 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 6232 6233 #define S_FW_PARAMS_CMD_VFN 0 6234 #define M_FW_PARAMS_CMD_VFN 0xff 6235 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 6236 #define G_FW_PARAMS_CMD_VFN(x) \ 6237 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 6238 6239 struct fw_pfvf_cmd { 6240 __be32 op_to_vfn; 6241 __be32 retval_len16; 6242 __be32 niqflint_niq; 6243 __be32 type_to_neq; 6244 __be32 tc_to_nexactf; 6245 __be32 r_caps_to_nethctrl; 6246 __be16 nricq; 6247 __be16 nriqp; 6248 __be32 r4; 6249 }; 6250 6251 #define S_FW_PFVF_CMD_PFN 8 6252 #define M_FW_PFVF_CMD_PFN 0x7 6253 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 6254 #define G_FW_PFVF_CMD_PFN(x) \ 6255 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 6256 6257 #define S_FW_PFVF_CMD_VFN 0 6258 #define M_FW_PFVF_CMD_VFN 0xff 6259 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 6260 #define G_FW_PFVF_CMD_VFN(x) \ 6261 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 6262 6263 #define S_FW_PFVF_CMD_NIQFLINT 20 6264 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 6265 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 6266 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 6267 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 6268 6269 #define S_FW_PFVF_CMD_NIQ 0 6270 #define M_FW_PFVF_CMD_NIQ 0xfffff 6271 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 6272 #define G_FW_PFVF_CMD_NIQ(x) \ 6273 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 6274 6275 #define S_FW_PFVF_CMD_TYPE 31 6276 #define M_FW_PFVF_CMD_TYPE 0x1 6277 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 6278 #define G_FW_PFVF_CMD_TYPE(x) \ 6279 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 6280 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 6281 6282 #define S_FW_PFVF_CMD_CMASK 24 6283 #define M_FW_PFVF_CMD_CMASK 0xf 6284 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 6285 #define G_FW_PFVF_CMD_CMASK(x) \ 6286 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 6287 6288 #define S_FW_PFVF_CMD_PMASK 20 6289 #define M_FW_PFVF_CMD_PMASK 0xf 6290 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 6291 #define G_FW_PFVF_CMD_PMASK(x) \ 6292 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 6293 6294 #define S_FW_PFVF_CMD_NEQ 0 6295 #define M_FW_PFVF_CMD_NEQ 0xfffff 6296 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 6297 #define G_FW_PFVF_CMD_NEQ(x) \ 6298 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 6299 6300 #define S_FW_PFVF_CMD_TC 24 6301 #define M_FW_PFVF_CMD_TC 0xff 6302 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 6303 #define G_FW_PFVF_CMD_TC(x) \ 6304 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 6305 6306 #define S_FW_PFVF_CMD_NVI 16 6307 #define M_FW_PFVF_CMD_NVI 0xff 6308 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 6309 #define G_FW_PFVF_CMD_NVI(x) \ 6310 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 6311 6312 #define S_FW_PFVF_CMD_NEXACTF 0 6313 #define M_FW_PFVF_CMD_NEXACTF 0xffff 6314 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 6315 #define G_FW_PFVF_CMD_NEXACTF(x) \ 6316 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 6317 6318 #define S_FW_PFVF_CMD_R_CAPS 24 6319 #define M_FW_PFVF_CMD_R_CAPS 0xff 6320 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 6321 #define G_FW_PFVF_CMD_R_CAPS(x) \ 6322 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 6323 6324 #define S_FW_PFVF_CMD_WX_CAPS 16 6325 #define M_FW_PFVF_CMD_WX_CAPS 0xff 6326 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 6327 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 6328 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 6329 6330 #define S_FW_PFVF_CMD_NETHCTRL 0 6331 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 6332 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 6333 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 6334 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 6335 6336 /* 6337 * ingress queue type; the first 1K ingress queues can have associated 0, 6338 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 6339 * capabilities 6340 */ 6341 enum fw_iq_type { 6342 FW_IQ_TYPE_FL_INT_CAP, 6343 FW_IQ_TYPE_NO_FL_INT_CAP, 6344 FW_IQ_TYPE_VF_CQ, 6345 FW_IQ_TYPE_CQ, 6346 }; 6347 6348 enum fw_iq_iqtype { 6349 FW_IQ_IQTYPE_OTHER, 6350 FW_IQ_IQTYPE_NIC, 6351 FW_IQ_IQTYPE_OFLD, 6352 }; 6353 6354 struct fw_iq_cmd { 6355 __be32 op_to_vfn; 6356 __be32 alloc_to_len16; 6357 __be16 physiqid; 6358 __be16 iqid; 6359 __be16 fl0id; 6360 __be16 fl1id; 6361 __be32 type_to_iqandstindex; 6362 __be16 iqdroprss_to_iqesize; 6363 __be16 iqsize; 6364 __be64 iqaddr; 6365 __be32 iqns_to_fl0congen; 6366 __be16 fl0dcaen_to_fl0cidxfthresh; 6367 __be16 fl0size; 6368 __be64 fl0addr; 6369 __be32 fl1cngchmap_to_fl1congen; 6370 __be16 fl1dcaen_to_fl1cidxfthresh; 6371 __be16 fl1size; 6372 __be64 fl1addr; 6373 }; 6374 6375 #define S_FW_IQ_CMD_PFN 8 6376 #define M_FW_IQ_CMD_PFN 0x7 6377 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 6378 #define G_FW_IQ_CMD_PFN(x) \ 6379 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 6380 6381 #define S_FW_IQ_CMD_VFN 0 6382 #define M_FW_IQ_CMD_VFN 0xff 6383 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 6384 #define G_FW_IQ_CMD_VFN(x) \ 6385 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 6386 6387 #define S_FW_IQ_CMD_ALLOC 31 6388 #define M_FW_IQ_CMD_ALLOC 0x1 6389 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 6390 #define G_FW_IQ_CMD_ALLOC(x) \ 6391 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 6392 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 6393 6394 #define S_FW_IQ_CMD_FREE 30 6395 #define M_FW_IQ_CMD_FREE 0x1 6396 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 6397 #define G_FW_IQ_CMD_FREE(x) \ 6398 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 6399 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 6400 6401 #define S_FW_IQ_CMD_MODIFY 29 6402 #define M_FW_IQ_CMD_MODIFY 0x1 6403 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 6404 #define G_FW_IQ_CMD_MODIFY(x) \ 6405 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 6406 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 6407 6408 #define S_FW_IQ_CMD_IQSTART 28 6409 #define M_FW_IQ_CMD_IQSTART 0x1 6410 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 6411 #define G_FW_IQ_CMD_IQSTART(x) \ 6412 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 6413 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 6414 6415 #define S_FW_IQ_CMD_IQSTOP 27 6416 #define M_FW_IQ_CMD_IQSTOP 0x1 6417 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 6418 #define G_FW_IQ_CMD_IQSTOP(x) \ 6419 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 6420 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 6421 6422 #define S_FW_IQ_CMD_TYPE 29 6423 #define M_FW_IQ_CMD_TYPE 0x7 6424 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 6425 #define G_FW_IQ_CMD_TYPE(x) \ 6426 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 6427 6428 #define S_FW_IQ_CMD_IQASYNCH 28 6429 #define M_FW_IQ_CMD_IQASYNCH 0x1 6430 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 6431 #define G_FW_IQ_CMD_IQASYNCH(x) \ 6432 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 6433 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 6434 6435 #define S_FW_IQ_CMD_VIID 16 6436 #define M_FW_IQ_CMD_VIID 0xfff 6437 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 6438 #define G_FW_IQ_CMD_VIID(x) \ 6439 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 6440 6441 #define S_FW_IQ_CMD_IQANDST 15 6442 #define M_FW_IQ_CMD_IQANDST 0x1 6443 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 6444 #define G_FW_IQ_CMD_IQANDST(x) \ 6445 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 6446 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 6447 6448 #define S_FW_IQ_CMD_IQANUS 14 6449 #define M_FW_IQ_CMD_IQANUS 0x1 6450 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 6451 #define G_FW_IQ_CMD_IQANUS(x) \ 6452 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 6453 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 6454 6455 #define S_FW_IQ_CMD_IQANUD 12 6456 #define M_FW_IQ_CMD_IQANUD 0x3 6457 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 6458 #define G_FW_IQ_CMD_IQANUD(x) \ 6459 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 6460 6461 #define S_FW_IQ_CMD_IQANDSTINDEX 0 6462 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 6463 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 6464 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 6465 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 6466 6467 #define S_FW_IQ_CMD_IQDROPRSS 15 6468 #define M_FW_IQ_CMD_IQDROPRSS 0x1 6469 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 6470 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 6471 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 6472 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 6473 6474 #define S_FW_IQ_CMD_IQGTSMODE 14 6475 #define M_FW_IQ_CMD_IQGTSMODE 0x1 6476 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 6477 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 6478 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 6479 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 6480 6481 #define S_FW_IQ_CMD_IQPCIECH 12 6482 #define M_FW_IQ_CMD_IQPCIECH 0x3 6483 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 6484 #define G_FW_IQ_CMD_IQPCIECH(x) \ 6485 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 6486 6487 #define S_FW_IQ_CMD_IQDCAEN 11 6488 #define M_FW_IQ_CMD_IQDCAEN 0x1 6489 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 6490 #define G_FW_IQ_CMD_IQDCAEN(x) \ 6491 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 6492 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 6493 6494 #define S_FW_IQ_CMD_IQDCACPU 6 6495 #define M_FW_IQ_CMD_IQDCACPU 0x1f 6496 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 6497 #define G_FW_IQ_CMD_IQDCACPU(x) \ 6498 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 6499 6500 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 6501 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 6502 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 6503 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 6504 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 6505 6506 #define S_FW_IQ_CMD_IQO 3 6507 #define M_FW_IQ_CMD_IQO 0x1 6508 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 6509 #define G_FW_IQ_CMD_IQO(x) \ 6510 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 6511 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 6512 6513 #define S_FW_IQ_CMD_IQCPRIO 2 6514 #define M_FW_IQ_CMD_IQCPRIO 0x1 6515 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 6516 #define G_FW_IQ_CMD_IQCPRIO(x) \ 6517 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 6518 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 6519 6520 #define S_FW_IQ_CMD_IQESIZE 0 6521 #define M_FW_IQ_CMD_IQESIZE 0x3 6522 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 6523 #define G_FW_IQ_CMD_IQESIZE(x) \ 6524 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 6525 6526 #define S_FW_IQ_CMD_IQNS 31 6527 #define M_FW_IQ_CMD_IQNS 0x1 6528 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 6529 #define G_FW_IQ_CMD_IQNS(x) \ 6530 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 6531 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 6532 6533 #define S_FW_IQ_CMD_IQRO 30 6534 #define M_FW_IQ_CMD_IQRO 0x1 6535 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 6536 #define G_FW_IQ_CMD_IQRO(x) \ 6537 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 6538 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 6539 6540 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 6541 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 6542 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 6543 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 6544 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 6545 6546 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 6547 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 6548 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 6549 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 6550 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 6551 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 6552 6553 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 6554 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 6555 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 6556 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 6557 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 6558 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 6559 6560 #define S_FW_IQ_CMD_IQTYPE 24 6561 #define M_FW_IQ_CMD_IQTYPE 0x3 6562 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 6563 #define G_FW_IQ_CMD_IQTYPE(x) \ 6564 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 6565 6566 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 6567 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 6568 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 6569 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 6570 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 6571 6572 #define S_FW_IQ_CMD_FL0CONGDROP 16 6573 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 6574 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 6575 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 6576 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 6577 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 6578 6579 #define S_FW_IQ_CMD_FL0CACHELOCK 15 6580 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 6581 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 6582 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 6583 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 6584 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 6585 6586 #define S_FW_IQ_CMD_FL0DBP 14 6587 #define M_FW_IQ_CMD_FL0DBP 0x1 6588 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 6589 #define G_FW_IQ_CMD_FL0DBP(x) \ 6590 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 6591 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 6592 6593 #define S_FW_IQ_CMD_FL0DATANS 13 6594 #define M_FW_IQ_CMD_FL0DATANS 0x1 6595 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 6596 #define G_FW_IQ_CMD_FL0DATANS(x) \ 6597 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 6598 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 6599 6600 #define S_FW_IQ_CMD_FL0DATARO 12 6601 #define M_FW_IQ_CMD_FL0DATARO 0x1 6602 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 6603 #define G_FW_IQ_CMD_FL0DATARO(x) \ 6604 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 6605 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 6606 6607 #define S_FW_IQ_CMD_FL0CONGCIF 11 6608 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 6609 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 6610 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 6611 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 6612 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 6613 6614 #define S_FW_IQ_CMD_FL0ONCHIP 10 6615 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 6616 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 6617 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 6618 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 6619 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 6620 6621 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 6622 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 6623 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 6624 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 6625 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 6626 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 6627 6628 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 6629 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 6630 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 6631 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 6632 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 6633 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 6634 6635 #define S_FW_IQ_CMD_FL0FETCHNS 7 6636 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 6637 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 6638 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 6639 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 6640 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 6641 6642 #define S_FW_IQ_CMD_FL0FETCHRO 6 6643 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 6644 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 6645 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 6646 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 6647 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 6648 6649 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 6650 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 6651 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 6652 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 6653 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 6654 6655 #define S_FW_IQ_CMD_FL0CPRIO 3 6656 #define M_FW_IQ_CMD_FL0CPRIO 0x1 6657 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 6658 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 6659 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 6660 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 6661 6662 #define S_FW_IQ_CMD_FL0PADEN 2 6663 #define M_FW_IQ_CMD_FL0PADEN 0x1 6664 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 6665 #define G_FW_IQ_CMD_FL0PADEN(x) \ 6666 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 6667 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 6668 6669 #define S_FW_IQ_CMD_FL0PACKEN 1 6670 #define M_FW_IQ_CMD_FL0PACKEN 0x1 6671 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 6672 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 6673 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 6674 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 6675 6676 #define S_FW_IQ_CMD_FL0CONGEN 0 6677 #define M_FW_IQ_CMD_FL0CONGEN 0x1 6678 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 6679 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 6680 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 6681 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 6682 6683 #define S_FW_IQ_CMD_FL0DCAEN 15 6684 #define M_FW_IQ_CMD_FL0DCAEN 0x1 6685 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 6686 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 6687 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 6688 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 6689 6690 #define S_FW_IQ_CMD_FL0DCACPU 10 6691 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 6692 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 6693 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 6694 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 6695 6696 #define S_FW_IQ_CMD_FL0FBMIN 7 6697 #define M_FW_IQ_CMD_FL0FBMIN 0x7 6698 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 6699 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 6700 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 6701 6702 #define S_FW_IQ_CMD_FL0FBMAX 4 6703 #define M_FW_IQ_CMD_FL0FBMAX 0x7 6704 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 6705 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 6706 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 6707 6708 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 6709 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 6710 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 6711 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 6712 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 6713 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 6714 6715 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 6716 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 6717 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 6718 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 6719 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 6720 6721 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 6722 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 6723 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 6724 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 6725 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 6726 6727 #define S_FW_IQ_CMD_FL1CONGDROP 16 6728 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 6729 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 6730 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 6731 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 6732 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 6733 6734 #define S_FW_IQ_CMD_FL1CACHELOCK 15 6735 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 6736 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 6737 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 6738 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 6739 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 6740 6741 #define S_FW_IQ_CMD_FL1DBP 14 6742 #define M_FW_IQ_CMD_FL1DBP 0x1 6743 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 6744 #define G_FW_IQ_CMD_FL1DBP(x) \ 6745 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 6746 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 6747 6748 #define S_FW_IQ_CMD_FL1DATANS 13 6749 #define M_FW_IQ_CMD_FL1DATANS 0x1 6750 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 6751 #define G_FW_IQ_CMD_FL1DATANS(x) \ 6752 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 6753 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 6754 6755 #define S_FW_IQ_CMD_FL1DATARO 12 6756 #define M_FW_IQ_CMD_FL1DATARO 0x1 6757 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 6758 #define G_FW_IQ_CMD_FL1DATARO(x) \ 6759 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 6760 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 6761 6762 #define S_FW_IQ_CMD_FL1CONGCIF 11 6763 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 6764 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 6765 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 6766 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 6767 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 6768 6769 #define S_FW_IQ_CMD_FL1ONCHIP 10 6770 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 6771 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 6772 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 6773 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 6774 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 6775 6776 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 6777 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 6778 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 6779 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 6780 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 6781 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 6782 6783 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 6784 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 6785 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 6786 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 6787 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 6788 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 6789 6790 #define S_FW_IQ_CMD_FL1FETCHNS 7 6791 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 6792 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 6793 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 6794 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 6795 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 6796 6797 #define S_FW_IQ_CMD_FL1FETCHRO 6 6798 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 6799 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 6800 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 6801 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 6802 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 6803 6804 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 6805 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 6806 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 6807 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 6808 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 6809 6810 #define S_FW_IQ_CMD_FL1CPRIO 3 6811 #define M_FW_IQ_CMD_FL1CPRIO 0x1 6812 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 6813 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 6814 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 6815 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 6816 6817 #define S_FW_IQ_CMD_FL1PADEN 2 6818 #define M_FW_IQ_CMD_FL1PADEN 0x1 6819 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 6820 #define G_FW_IQ_CMD_FL1PADEN(x) \ 6821 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 6822 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 6823 6824 #define S_FW_IQ_CMD_FL1PACKEN 1 6825 #define M_FW_IQ_CMD_FL1PACKEN 0x1 6826 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 6827 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 6828 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 6829 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 6830 6831 #define S_FW_IQ_CMD_FL1CONGEN 0 6832 #define M_FW_IQ_CMD_FL1CONGEN 0x1 6833 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 6834 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 6835 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 6836 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 6837 6838 #define S_FW_IQ_CMD_FL1DCAEN 15 6839 #define M_FW_IQ_CMD_FL1DCAEN 0x1 6840 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 6841 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 6842 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 6843 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 6844 6845 #define S_FW_IQ_CMD_FL1DCACPU 10 6846 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 6847 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 6848 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 6849 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 6850 6851 #define S_FW_IQ_CMD_FL1FBMIN 7 6852 #define M_FW_IQ_CMD_FL1FBMIN 0x7 6853 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 6854 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 6855 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 6856 6857 #define S_FW_IQ_CMD_FL1FBMAX 4 6858 #define M_FW_IQ_CMD_FL1FBMAX 0x7 6859 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 6860 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 6861 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 6862 6863 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 6864 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 6865 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 6866 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 6867 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 6868 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 6869 6870 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 6871 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 6872 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 6873 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 6874 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 6875 6876 struct fw_eq_mngt_cmd { 6877 __be32 op_to_vfn; 6878 __be32 alloc_to_len16; 6879 __be32 cmpliqid_eqid; 6880 __be32 physeqid_pkd; 6881 __be32 fetchszm_to_iqid; 6882 __be32 dcaen_to_eqsize; 6883 __be64 eqaddr; 6884 }; 6885 6886 #define S_FW_EQ_MNGT_CMD_PFN 8 6887 #define M_FW_EQ_MNGT_CMD_PFN 0x7 6888 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 6889 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 6890 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 6891 6892 #define S_FW_EQ_MNGT_CMD_VFN 0 6893 #define M_FW_EQ_MNGT_CMD_VFN 0xff 6894 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 6895 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 6896 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 6897 6898 #define S_FW_EQ_MNGT_CMD_ALLOC 31 6899 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 6900 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 6901 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 6902 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 6903 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 6904 6905 #define S_FW_EQ_MNGT_CMD_FREE 30 6906 #define M_FW_EQ_MNGT_CMD_FREE 0x1 6907 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 6908 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 6909 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 6910 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 6911 6912 #define S_FW_EQ_MNGT_CMD_MODIFY 29 6913 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 6914 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 6915 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 6916 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 6917 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 6918 6919 #define S_FW_EQ_MNGT_CMD_EQSTART 28 6920 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 6921 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 6922 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 6923 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 6924 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 6925 6926 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 6927 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 6928 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 6929 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 6930 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 6931 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 6932 6933 #define S_FW_EQ_MNGT_CMD_COREGROUP 16 6934 #define M_FW_EQ_MNGT_CMD_COREGROUP 0x3f 6935 #define V_FW_EQ_MNGT_CMD_COREGROUP(x) ((x) << S_FW_EQ_MNGT_CMD_COREGROUP) 6936 #define G_FW_EQ_MNGT_CMD_COREGROUP(x) \ 6937 (((x) >> S_FW_EQ_MNGT_CMD_COREGROUP) & M_FW_EQ_MNGT_CMD_COREGROUP) 6938 6939 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 6940 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 6941 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 6942 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 6943 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 6944 6945 #define S_FW_EQ_MNGT_CMD_EQID 0 6946 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 6947 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 6948 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 6949 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 6950 6951 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 6952 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 6953 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 6954 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 6955 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 6956 6957 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 6958 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 6959 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 6960 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 6961 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 6962 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 6963 6964 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 6965 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 6966 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 6967 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 6968 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 6969 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 6970 6971 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 6972 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 6973 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 6974 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 6975 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 6976 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 6977 6978 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 6979 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 6980 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 6981 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 6982 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 6983 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 6984 6985 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 6986 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 6987 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 6988 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 6989 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 6990 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 6991 6992 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 6993 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 6994 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 6995 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 6996 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 6997 6998 #define S_FW_EQ_MNGT_CMD_CPRIO 19 6999 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 7000 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 7001 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 7002 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 7003 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 7004 7005 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 7006 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 7007 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 7008 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 7009 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 7010 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 7011 7012 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 7013 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 7014 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 7015 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 7016 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 7017 7018 #define S_FW_EQ_MNGT_CMD_IQID 0 7019 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 7020 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 7021 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 7022 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 7023 7024 #define S_FW_EQ_MNGT_CMD_DCAEN 31 7025 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 7026 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 7027 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 7028 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 7029 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 7030 7031 #define S_FW_EQ_MNGT_CMD_DCACPU 26 7032 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 7033 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 7034 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 7035 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 7036 7037 #define S_FW_EQ_MNGT_CMD_FBMIN 23 7038 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 7039 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 7040 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 7041 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 7042 7043 #define S_FW_EQ_MNGT_CMD_FBMAX 20 7044 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 7045 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 7046 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 7047 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 7048 7049 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 7050 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 7051 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 7052 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 7053 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 7054 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 7055 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 7056 7057 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 7058 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 7059 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 7060 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 7061 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 7062 7063 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 7064 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 7065 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 7066 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 7067 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 7068 7069 struct fw_eq_eth_cmd { 7070 __be32 op_to_vfn; 7071 __be32 alloc_to_len16; 7072 __be32 eqid_pkd; 7073 __be32 physeqid_pkd; 7074 __be32 fetchszm_to_iqid; 7075 __be32 dcaen_to_eqsize; 7076 __be64 eqaddr; 7077 __be32 autoequiqe_to_viid; 7078 __be32 timeren_timerix; 7079 __be64 r9; 7080 }; 7081 7082 #define S_FW_EQ_ETH_CMD_PFN 8 7083 #define M_FW_EQ_ETH_CMD_PFN 0x7 7084 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 7085 #define G_FW_EQ_ETH_CMD_PFN(x) \ 7086 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 7087 7088 #define S_FW_EQ_ETH_CMD_VFN 0 7089 #define M_FW_EQ_ETH_CMD_VFN 0xff 7090 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 7091 #define G_FW_EQ_ETH_CMD_VFN(x) \ 7092 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 7093 7094 #define S_FW_EQ_ETH_CMD_ALLOC 31 7095 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 7096 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 7097 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 7098 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 7099 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 7100 7101 #define S_FW_EQ_ETH_CMD_FREE 30 7102 #define M_FW_EQ_ETH_CMD_FREE 0x1 7103 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 7104 #define G_FW_EQ_ETH_CMD_FREE(x) \ 7105 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 7106 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 7107 7108 #define S_FW_EQ_ETH_CMD_MODIFY 29 7109 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 7110 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 7111 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 7112 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 7113 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 7114 7115 #define S_FW_EQ_ETH_CMD_EQSTART 28 7116 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 7117 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 7118 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 7119 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 7120 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 7121 7122 #define S_FW_EQ_ETH_CMD_EQSTOP 27 7123 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 7124 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 7125 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 7126 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 7127 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 7128 7129 #define S_FW_EQ_ETH_CMD_COREGROUP 16 7130 #define M_FW_EQ_ETH_CMD_COREGROUP 0x3f 7131 #define V_FW_EQ_ETH_CMD_COREGROUP(x) ((x) << S_FW_EQ_ETH_CMD_COREGROUP) 7132 #define G_FW_EQ_ETH_CMD_COREGROUP(x) \ 7133 (((x) >> S_FW_EQ_ETH_CMD_COREGROUP) & M_FW_EQ_ETH_CMD_COREGROUP) 7134 7135 #define S_FW_EQ_ETH_CMD_EQID 0 7136 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 7137 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 7138 #define G_FW_EQ_ETH_CMD_EQID(x) \ 7139 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 7140 7141 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 7142 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 7143 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 7144 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 7145 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 7146 7147 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 7148 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 7149 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 7150 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 7151 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 7152 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 7153 7154 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 7155 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 7156 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 7157 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 7158 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 7159 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 7160 7161 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 7162 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 7163 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 7164 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 7165 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 7166 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 7167 7168 #define S_FW_EQ_ETH_CMD_FETCHNS 23 7169 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 7170 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 7171 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 7172 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 7173 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 7174 7175 #define S_FW_EQ_ETH_CMD_FETCHRO 22 7176 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 7177 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 7178 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 7179 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 7180 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 7181 7182 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 7183 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 7184 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 7185 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 7186 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 7187 7188 #define S_FW_EQ_ETH_CMD_CPRIO 19 7189 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 7190 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 7191 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 7192 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 7193 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 7194 7195 #define S_FW_EQ_ETH_CMD_ONCHIP 18 7196 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 7197 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 7198 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 7199 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 7200 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 7201 7202 #define S_FW_EQ_ETH_CMD_PCIECHN 16 7203 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 7204 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 7205 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 7206 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 7207 7208 #define S_FW_EQ_ETH_CMD_IQID 0 7209 #define M_FW_EQ_ETH_CMD_IQID 0xffff 7210 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 7211 #define G_FW_EQ_ETH_CMD_IQID(x) \ 7212 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 7213 7214 #define S_FW_EQ_ETH_CMD_DCAEN 31 7215 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 7216 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 7217 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 7218 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 7219 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 7220 7221 #define S_FW_EQ_ETH_CMD_DCACPU 26 7222 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 7223 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 7224 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 7225 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 7226 7227 #define S_FW_EQ_ETH_CMD_FBMIN 23 7228 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 7229 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 7230 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 7231 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 7232 7233 #define S_FW_EQ_ETH_CMD_FBMAX 20 7234 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 7235 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 7236 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 7237 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 7238 7239 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 7240 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 7241 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 7242 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 7243 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 7244 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 7245 7246 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 7247 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 7248 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 7249 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 7250 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 7251 7252 #define S_FW_EQ_ETH_CMD_EQSIZE 0 7253 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 7254 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 7255 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 7256 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 7257 7258 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 7259 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 7260 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 7261 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 7262 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 7263 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 7264 7265 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 7266 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 7267 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 7268 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 7269 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 7270 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 7271 7272 #define S_FW_EQ_ETH_CMD_VIID 16 7273 #define M_FW_EQ_ETH_CMD_VIID 0xfff 7274 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 7275 #define G_FW_EQ_ETH_CMD_VIID(x) \ 7276 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 7277 7278 #define S_FW_EQ_ETH_CMD_TIMEREN 3 7279 #define M_FW_EQ_ETH_CMD_TIMEREN 0x1 7280 #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN) 7281 #define G_FW_EQ_ETH_CMD_TIMEREN(x) \ 7282 (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN) 7283 #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U) 7284 7285 #define S_FW_EQ_ETH_CMD_TIMERIX 0 7286 #define M_FW_EQ_ETH_CMD_TIMERIX 0x7 7287 #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX) 7288 #define G_FW_EQ_ETH_CMD_TIMERIX(x) \ 7289 (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX) 7290 7291 struct fw_eq_ctrl_cmd { 7292 __be32 op_to_vfn; 7293 __be32 alloc_to_len16; 7294 __be32 cmpliqid_eqid; 7295 __be32 physeqid_pkd; 7296 __be32 fetchszm_to_iqid; 7297 __be32 dcaen_to_eqsize; 7298 __be64 eqaddr; 7299 }; 7300 7301 #define S_FW_EQ_CTRL_CMD_PFN 8 7302 #define M_FW_EQ_CTRL_CMD_PFN 0x7 7303 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 7304 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 7305 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 7306 7307 #define S_FW_EQ_CTRL_CMD_VFN 0 7308 #define M_FW_EQ_CTRL_CMD_VFN 0xff 7309 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 7310 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 7311 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 7312 7313 #define S_FW_EQ_CTRL_CMD_ALLOC 31 7314 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 7315 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 7316 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 7317 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 7318 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 7319 7320 #define S_FW_EQ_CTRL_CMD_FREE 30 7321 #define M_FW_EQ_CTRL_CMD_FREE 0x1 7322 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 7323 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 7324 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 7325 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 7326 7327 #define S_FW_EQ_CTRL_CMD_MODIFY 29 7328 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 7329 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 7330 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 7331 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 7332 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 7333 7334 #define S_FW_EQ_CTRL_CMD_EQSTART 28 7335 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 7336 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 7337 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 7338 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 7339 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 7340 7341 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 7342 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 7343 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 7344 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 7345 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 7346 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 7347 7348 #define S_FW_EQ_CTRL_CMD_COREGROUP 16 7349 #define M_FW_EQ_CTRL_CMD_COREGROUP 0x3f 7350 #define V_FW_EQ_CTRL_CMD_COREGROUP(x) ((x) << S_FW_EQ_CTRL_CMD_COREGROUP) 7351 #define G_FW_EQ_CTRL_CMD_COREGROUP(x) \ 7352 (((x) >> S_FW_EQ_CTRL_CMD_COREGROUP) & M_FW_EQ_CTRL_CMD_COREGROUP) 7353 7354 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 7355 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 7356 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 7357 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 7358 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 7359 7360 #define S_FW_EQ_CTRL_CMD_EQID 0 7361 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 7362 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 7363 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 7364 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 7365 7366 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 7367 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 7368 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 7369 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 7370 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 7371 7372 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 7373 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 7374 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 7375 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 7376 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 7377 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 7378 7379 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 7380 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 7381 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 7382 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 7383 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 7384 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 7385 7386 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 7387 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 7388 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 7389 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 7390 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 7391 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 7392 7393 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 7394 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 7395 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 7396 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 7397 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 7398 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 7399 7400 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 7401 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 7402 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 7403 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 7404 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 7405 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 7406 7407 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 7408 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 7409 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 7410 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 7411 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 7412 7413 #define S_FW_EQ_CTRL_CMD_CPRIO 19 7414 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 7415 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 7416 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 7417 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 7418 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 7419 7420 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 7421 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 7422 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 7423 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 7424 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 7425 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 7426 7427 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 7428 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 7429 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 7430 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 7431 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 7432 7433 #define S_FW_EQ_CTRL_CMD_IQID 0 7434 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 7435 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 7436 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 7437 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 7438 7439 #define S_FW_EQ_CTRL_CMD_DCAEN 31 7440 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 7441 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 7442 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 7443 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 7444 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 7445 7446 #define S_FW_EQ_CTRL_CMD_DCACPU 26 7447 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 7448 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 7449 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 7450 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 7451 7452 #define S_FW_EQ_CTRL_CMD_FBMIN 23 7453 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 7454 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 7455 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 7456 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 7457 7458 #define S_FW_EQ_CTRL_CMD_FBMAX 20 7459 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 7460 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 7461 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 7462 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 7463 7464 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 7465 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 7466 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 7467 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 7468 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 7469 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 7470 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 7471 7472 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 7473 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 7474 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 7475 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 7476 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 7477 7478 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 7479 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 7480 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 7481 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 7482 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 7483 7484 struct fw_eq_ofld_cmd { 7485 __be32 op_to_vfn; 7486 __be32 alloc_to_len16; 7487 __be32 eqid_pkd; 7488 __be32 physeqid_pkd; 7489 __be32 fetchszm_to_iqid; 7490 __be32 dcaen_to_eqsize; 7491 __be64 eqaddr; 7492 }; 7493 7494 #define S_FW_EQ_OFLD_CMD_PFN 8 7495 #define M_FW_EQ_OFLD_CMD_PFN 0x7 7496 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 7497 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 7498 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 7499 7500 #define S_FW_EQ_OFLD_CMD_VFN 0 7501 #define M_FW_EQ_OFLD_CMD_VFN 0xff 7502 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 7503 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 7504 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 7505 7506 #define S_FW_EQ_OFLD_CMD_ALLOC 31 7507 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 7508 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 7509 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 7510 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 7511 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 7512 7513 #define S_FW_EQ_OFLD_CMD_FREE 30 7514 #define M_FW_EQ_OFLD_CMD_FREE 0x1 7515 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 7516 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 7517 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 7518 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 7519 7520 #define S_FW_EQ_OFLD_CMD_MODIFY 29 7521 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 7522 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 7523 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 7524 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 7525 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 7526 7527 #define S_FW_EQ_OFLD_CMD_EQSTART 28 7528 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 7529 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 7530 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 7531 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 7532 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 7533 7534 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 7535 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 7536 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 7537 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 7538 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 7539 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 7540 7541 #define S_FW_EQ_OFLD_CMD_COREGROUP 16 7542 #define M_FW_EQ_OFLD_CMD_COREGROUP 0x3f 7543 #define V_FW_EQ_OFLD_CMD_COREGROUP(x) ((x) << S_FW_EQ_OFLD_CMD_COREGROUP) 7544 #define G_FW_EQ_OFLD_CMD_COREGROUP(x) \ 7545 (((x) >> S_FW_EQ_OFLD_CMD_COREGROUP) & M_FW_EQ_OFLD_CMD_COREGROUP) 7546 7547 #define S_FW_EQ_OFLD_CMD_EQID 0 7548 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 7549 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 7550 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 7551 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 7552 7553 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 7554 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 7555 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 7556 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 7557 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 7558 7559 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 7560 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 7561 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 7562 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 7563 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 7564 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 7565 7566 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 7567 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 7568 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 7569 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 7570 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 7571 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 7572 7573 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 7574 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 7575 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 7576 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 7577 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 7578 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 7579 7580 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 7581 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 7582 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 7583 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 7584 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 7585 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 7586 7587 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 7588 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 7589 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 7590 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 7591 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 7592 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 7593 7594 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 7595 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 7596 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 7597 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 7598 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 7599 7600 #define S_FW_EQ_OFLD_CMD_CPRIO 19 7601 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 7602 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 7603 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 7604 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 7605 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 7606 7607 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 7608 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 7609 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 7610 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 7611 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 7612 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 7613 7614 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 7615 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 7616 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 7617 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 7618 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 7619 7620 #define S_FW_EQ_OFLD_CMD_IQID 0 7621 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 7622 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 7623 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 7624 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 7625 7626 #define S_FW_EQ_OFLD_CMD_DCAEN 31 7627 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 7628 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 7629 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 7630 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 7631 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 7632 7633 #define S_FW_EQ_OFLD_CMD_DCACPU 26 7634 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 7635 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 7636 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 7637 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 7638 7639 #define S_FW_EQ_OFLD_CMD_FBMIN 23 7640 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 7641 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 7642 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 7643 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 7644 7645 #define S_FW_EQ_OFLD_CMD_FBMAX 20 7646 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 7647 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 7648 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 7649 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 7650 7651 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 7652 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 7653 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 7654 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 7655 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 7656 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 7657 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 7658 7659 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 7660 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 7661 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 7662 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 7663 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 7664 7665 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 7666 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 7667 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 7668 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 7669 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 7670 7671 /* Following macros present here only to maintain backward 7672 * compatibiity. Driver must not use these anymore */ 7673 /* Macros for VIID parsing: 7674 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 7675 #define S_FW_VIID_PFN 8 7676 #define M_FW_VIID_PFN 0x7 7677 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 7678 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 7679 7680 #define S_FW_VIID_VIVLD 7 7681 #define M_FW_VIID_VIVLD 0x1 7682 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 7683 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 7684 7685 #define S_FW_VIID_VIN 0 7686 #define M_FW_VIID_VIN 0x7F 7687 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 7688 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 7689 7690 /* Macros for VIID parsing: 7691 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 7692 #define S_FW_256VIID_PFN 9 7693 #define M_FW_256VIID_PFN 0x7 7694 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 7695 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 7696 7697 #define S_FW_256VIID_VIVLD 8 7698 #define M_FW_256VIID_VIVLD 0x1 7699 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 7700 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 7701 7702 #define S_FW_256VIID_VIN 0 7703 #define M_FW_256VIID_VIN 0xFF 7704 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 7705 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 7706 7707 enum fw_vi_func { 7708 FW_VI_FUNC_ETH, 7709 FW_VI_FUNC_OFLD, 7710 FW_VI_FUNC_IWARP, 7711 FW_VI_FUNC_OPENISCSI, 7712 FW_VI_FUNC_OPENFCOE, 7713 FW_VI_FUNC_FOISCSI, 7714 FW_VI_FUNC_FOFCOE, 7715 FW_VI_FUNC_FW, 7716 }; 7717 7718 struct fw_vi_cmd { 7719 __be32 op_to_vfn; 7720 __be32 alloc_to_len16; 7721 __be16 type_to_viid; 7722 __u8 mac[6]; 7723 __u8 portid_pkd; 7724 __u8 nmac; 7725 __u8 nmac0[6]; 7726 __be16 norss_rsssize; 7727 __u8 nmac1[6]; 7728 __be16 idsiiq_pkd; 7729 __u8 nmac2[6]; 7730 __be16 idseiq_pkd; 7731 __u8 nmac3[6]; 7732 __be64 r9; 7733 __be64 r10; 7734 }; 7735 7736 #define S_FW_VI_CMD_PFN 8 7737 #define M_FW_VI_CMD_PFN 0x7 7738 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 7739 #define G_FW_VI_CMD_PFN(x) \ 7740 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 7741 7742 #define S_FW_VI_CMD_VFN 0 7743 #define M_FW_VI_CMD_VFN 0xff 7744 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 7745 #define G_FW_VI_CMD_VFN(x) \ 7746 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 7747 7748 #define S_FW_VI_CMD_ALLOC 31 7749 #define M_FW_VI_CMD_ALLOC 0x1 7750 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 7751 #define G_FW_VI_CMD_ALLOC(x) \ 7752 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 7753 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 7754 7755 #define S_FW_VI_CMD_FREE 30 7756 #define M_FW_VI_CMD_FREE 0x1 7757 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 7758 #define G_FW_VI_CMD_FREE(x) \ 7759 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 7760 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 7761 7762 #define S_FW_VI_CMD_VFVLD 24 7763 #define M_FW_VI_CMD_VFVLD 0x1 7764 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD) 7765 #define G_FW_VI_CMD_VFVLD(x) \ 7766 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 7767 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U) 7768 7769 #define S_FW_VI_CMD_VIN 16 7770 #define M_FW_VI_CMD_VIN 0xff 7771 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN) 7772 #define G_FW_VI_CMD_VIN(x) \ 7773 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 7774 7775 #define S_FW_VI_CMD_TYPE 15 7776 #define M_FW_VI_CMD_TYPE 0x1 7777 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 7778 #define G_FW_VI_CMD_TYPE(x) \ 7779 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 7780 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 7781 7782 #define S_FW_VI_CMD_FUNC 12 7783 #define M_FW_VI_CMD_FUNC 0x7 7784 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 7785 #define G_FW_VI_CMD_FUNC(x) \ 7786 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 7787 7788 #define S_FW_VI_CMD_VIID 0 7789 #define M_FW_VI_CMD_VIID 0xfff 7790 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 7791 #define G_FW_VI_CMD_VIID(x) \ 7792 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 7793 7794 #define S_FW_VI_CMD_PORTID 4 7795 #define M_FW_VI_CMD_PORTID 0xf 7796 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 7797 #define G_FW_VI_CMD_PORTID(x) \ 7798 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 7799 7800 #define S_FW_VI_CMD_NORSS 11 7801 #define M_FW_VI_CMD_NORSS 0x1 7802 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 7803 #define G_FW_VI_CMD_NORSS(x) \ 7804 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 7805 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 7806 7807 #define S_FW_VI_CMD_RSSSIZE 0 7808 #define M_FW_VI_CMD_RSSSIZE 0x7ff 7809 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 7810 #define G_FW_VI_CMD_RSSSIZE(x) \ 7811 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 7812 7813 #define S_FW_VI_CMD_IDSIIQ 0 7814 #define M_FW_VI_CMD_IDSIIQ 0x3ff 7815 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 7816 #define G_FW_VI_CMD_IDSIIQ(x) \ 7817 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 7818 7819 #define S_FW_VI_CMD_IDSEIQ 0 7820 #define M_FW_VI_CMD_IDSEIQ 0x3ff 7821 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 7822 #define G_FW_VI_CMD_IDSEIQ(x) \ 7823 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 7824 7825 /* Special VI_MAC command index ids */ 7826 #define FW_VI_MAC_ADD_MAC 0x3FF 7827 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 7828 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 7829 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 7830 7831 enum fw_vi_mac_smac { 7832 FW_VI_MAC_MPS_TCAM_ENTRY, 7833 FW_VI_MAC_MPS_TCAM_ONLY, 7834 FW_VI_MAC_SMT_ONLY, 7835 FW_VI_MAC_SMT_AND_MPSTCAM 7836 }; 7837 7838 enum fw_vi_mac_result { 7839 FW_VI_MAC_R_SUCCESS, 7840 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 7841 FW_VI_MAC_R_SMAC_FAIL, 7842 FW_VI_MAC_R_F_ACL_CHECK 7843 }; 7844 7845 enum fw_vi_mac_entry_types { 7846 FW_VI_MAC_TYPE_EXACTMAC, 7847 FW_VI_MAC_TYPE_HASHVEC, 7848 FW_VI_MAC_TYPE_RAW, 7849 FW_VI_MAC_TYPE_EXACTMAC_VNI, 7850 }; 7851 7852 struct fw_vi_mac_cmd { 7853 __be32 op_to_viid; 7854 __be32 freemacs_to_len16; 7855 union fw_vi_mac { 7856 struct fw_vi_mac_exact { 7857 __be16 valid_to_idx; 7858 __u8 macaddr[6]; 7859 } exact[7]; 7860 struct fw_vi_mac_hash { 7861 __be64 hashvec; 7862 } hash; 7863 struct fw_vi_mac_raw { 7864 __be32 raw_idx_pkd; 7865 __be32 data0_pkd; 7866 __be32 data1[2]; 7867 __be64 data0m_pkd; 7868 __be32 data1m[2]; 7869 } raw; 7870 struct fw_vi_mac_vni { 7871 __be16 valid_to_idx; 7872 __u8 macaddr[6]; 7873 __be16 r7; 7874 __u8 macaddr_mask[6]; 7875 __be32 lookup_type_to_vni; 7876 __be32 vni_mask_pkd; 7877 } exact_vni[2]; 7878 } u; 7879 }; 7880 7881 #define S_FW_VI_MAC_CMD_SMTID 12 7882 #define M_FW_VI_MAC_CMD_SMTID 0xff 7883 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID) 7884 #define G_FW_VI_MAC_CMD_SMTID(x) \ 7885 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID) 7886 7887 #define S_FW_VI_MAC_CMD_VIID 0 7888 #define M_FW_VI_MAC_CMD_VIID 0xfff 7889 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 7890 #define G_FW_VI_MAC_CMD_VIID(x) \ 7891 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 7892 7893 #define S_FW_VI_MAC_CMD_FREEMACS 31 7894 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 7895 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 7896 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 7897 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 7898 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 7899 7900 #define S_FW_VI_MAC_CMD_IS_SMAC 30 7901 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1 7902 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 7903 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 7904 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 7905 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 7906 7907 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 7908 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 7909 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 7910 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 7911 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 7912 7913 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 7914 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 7915 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 7916 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 7917 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 7918 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 7919 7920 #define S_FW_VI_MAC_CMD_VALID 15 7921 #define M_FW_VI_MAC_CMD_VALID 0x1 7922 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 7923 #define G_FW_VI_MAC_CMD_VALID(x) \ 7924 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 7925 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 7926 7927 #define S_FW_VI_MAC_CMD_PRIO 12 7928 #define M_FW_VI_MAC_CMD_PRIO 0x7 7929 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 7930 #define G_FW_VI_MAC_CMD_PRIO(x) \ 7931 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 7932 7933 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 7934 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 7935 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 7936 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 7937 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 7938 7939 #define S_FW_VI_MAC_CMD_IDX 0 7940 #define M_FW_VI_MAC_CMD_IDX 0x3ff 7941 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 7942 #define G_FW_VI_MAC_CMD_IDX(x) \ 7943 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 7944 7945 #define S_FW_VI_MAC_CMD_RAW_IDX 16 7946 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 7947 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 7948 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 7949 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 7950 7951 #define S_FW_VI_MAC_CMD_DATA0 0 7952 #define M_FW_VI_MAC_CMD_DATA0 0xffff 7953 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 7954 #define G_FW_VI_MAC_CMD_DATA0(x) \ 7955 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 7956 7957 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 7958 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 7959 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 7960 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 7961 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 7962 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 7963 7964 #define S_FW_VI_MAC_CMD_DIP_HIT 30 7965 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 7966 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 7967 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 7968 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 7969 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 7970 7971 #define S_FW_VI_MAC_CMD_VNI 0 7972 #define M_FW_VI_MAC_CMD_VNI 0xffffff 7973 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 7974 #define G_FW_VI_MAC_CMD_VNI(x) \ 7975 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 7976 7977 /* Extracting loopback port number passed from driver. 7978 * as a part of fw_vi_mac_vni For non loopback entries 7979 * ignore the field and update port number from flowc. 7980 * Fw will ignore if physical port number received. 7981 * expected range (4-7). 7982 */ 7983 7984 #define S_FW_VI_MAC_CMD_PORT 24 7985 #define M_FW_VI_MAC_CMD_PORT 0x7 7986 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 7987 #define G_FW_VI_MAC_CMD_PORT(x) \ 7988 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 7989 7990 #define S_FW_VI_MAC_CMD_VNI_MASK 0 7991 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 7992 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 7993 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 7994 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 7995 7996 /* T4 max MTU supported */ 7997 #define T4_MAX_MTU_SUPPORTED 9600 7998 #define FW_RXMODE_MTU_NO_CHG 65535 7999 8000 struct fw_vi_rxmode_cmd { 8001 __be32 op_to_viid; 8002 __be32 retval_len16; 8003 __be32 mtu_to_vlanexen; 8004 __be32 r4_lo; 8005 }; 8006 8007 #define S_FW_VI_RXMODE_CMD_VIID 0 8008 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 8009 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 8010 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 8011 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 8012 8013 #define S_FW_VI_RXMODE_CMD_MTU 16 8014 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 8015 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 8016 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 8017 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 8018 8019 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 8020 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 8021 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 8022 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 8023 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 8024 8025 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 8026 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 8027 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 8028 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 8029 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 8030 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 8031 8032 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 8033 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 8034 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 8035 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 8036 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 8037 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 8038 8039 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 8040 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 8041 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 8042 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 8043 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 8044 8045 struct fw_vi_enable_cmd { 8046 __be32 op_to_viid; 8047 __be32 ien_to_len16; 8048 __be16 blinkdur; 8049 __be16 r3; 8050 __be32 r4; 8051 }; 8052 8053 #define S_FW_VI_ENABLE_CMD_VIID 0 8054 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 8055 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 8056 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 8057 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 8058 8059 #define S_FW_VI_ENABLE_CMD_IEN 31 8060 #define M_FW_VI_ENABLE_CMD_IEN 0x1 8061 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 8062 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 8063 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 8064 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 8065 8066 #define S_FW_VI_ENABLE_CMD_EEN 30 8067 #define M_FW_VI_ENABLE_CMD_EEN 0x1 8068 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 8069 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 8070 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 8071 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 8072 8073 #define S_FW_VI_ENABLE_CMD_LED 29 8074 #define M_FW_VI_ENABLE_CMD_LED 0x1 8075 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 8076 #define G_FW_VI_ENABLE_CMD_LED(x) \ 8077 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 8078 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 8079 8080 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 8081 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 8082 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 8083 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 8084 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 8085 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 8086 8087 /* VI VF stats offset definitions */ 8088 #define VI_VF_NUM_STATS 16 8089 enum fw_vi_stats_vf_index { 8090 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 8091 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 8092 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 8093 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 8094 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 8095 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 8096 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 8097 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 8098 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 8099 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 8100 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 8101 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 8102 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 8103 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 8104 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 8105 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 8106 }; 8107 8108 /* VI PF stats offset definitions */ 8109 #define VI_PF_NUM_STATS 17 8110 enum fw_vi_stats_pf_index { 8111 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 8112 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 8113 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 8114 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 8115 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 8116 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 8117 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 8118 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 8119 FW_VI_PF_STAT_RX_BYTES_IX, 8120 FW_VI_PF_STAT_RX_FRAMES_IX, 8121 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 8122 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 8123 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 8124 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 8125 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 8126 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 8127 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 8128 }; 8129 8130 struct fw_vi_stats_cmd { 8131 __be32 op_to_viid; 8132 __be32 retval_len16; 8133 union fw_vi_stats { 8134 struct fw_vi_stats_ctl { 8135 __be16 nstats_ix; 8136 __be16 r6; 8137 __be32 r7; 8138 __be64 stat0; 8139 __be64 stat1; 8140 __be64 stat2; 8141 __be64 stat3; 8142 __be64 stat4; 8143 __be64 stat5; 8144 } ctl; 8145 struct fw_vi_stats_pf { 8146 __be64 tx_bcast_bytes; 8147 __be64 tx_bcast_frames; 8148 __be64 tx_mcast_bytes; 8149 __be64 tx_mcast_frames; 8150 __be64 tx_ucast_bytes; 8151 __be64 tx_ucast_frames; 8152 __be64 tx_offload_bytes; 8153 __be64 tx_offload_frames; 8154 __be64 rx_pf_bytes; 8155 __be64 rx_pf_frames; 8156 __be64 rx_bcast_bytes; 8157 __be64 rx_bcast_frames; 8158 __be64 rx_mcast_bytes; 8159 __be64 rx_mcast_frames; 8160 __be64 rx_ucast_bytes; 8161 __be64 rx_ucast_frames; 8162 __be64 rx_err_frames; 8163 } pf; 8164 struct fw_vi_stats_vf { 8165 __be64 tx_bcast_bytes; 8166 __be64 tx_bcast_frames; 8167 __be64 tx_mcast_bytes; 8168 __be64 tx_mcast_frames; 8169 __be64 tx_ucast_bytes; 8170 __be64 tx_ucast_frames; 8171 __be64 tx_drop_frames; 8172 __be64 tx_offload_bytes; 8173 __be64 tx_offload_frames; 8174 __be64 rx_bcast_bytes; 8175 __be64 rx_bcast_frames; 8176 __be64 rx_mcast_bytes; 8177 __be64 rx_mcast_frames; 8178 __be64 rx_ucast_bytes; 8179 __be64 rx_ucast_frames; 8180 __be64 rx_err_frames; 8181 } vf; 8182 } u; 8183 }; 8184 8185 #define S_FW_VI_STATS_CMD_VIID 0 8186 #define M_FW_VI_STATS_CMD_VIID 0xfff 8187 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 8188 #define G_FW_VI_STATS_CMD_VIID(x) \ 8189 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 8190 8191 #define S_FW_VI_STATS_CMD_NSTATS 12 8192 #define M_FW_VI_STATS_CMD_NSTATS 0x7 8193 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 8194 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 8195 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 8196 8197 #define S_FW_VI_STATS_CMD_IX 0 8198 #define M_FW_VI_STATS_CMD_IX 0x1f 8199 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 8200 #define G_FW_VI_STATS_CMD_IX(x) \ 8201 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 8202 8203 struct fw_acl_mac_cmd { 8204 __be32 op_to_vfn; 8205 __be32 en_to_len16; 8206 __u8 nmac; 8207 __u8 r3[7]; 8208 __be16 r4; 8209 __u8 macaddr0[6]; 8210 __be16 r5; 8211 __u8 macaddr1[6]; 8212 __be16 r6; 8213 __u8 macaddr2[6]; 8214 __be16 r7; 8215 __u8 macaddr3[6]; 8216 }; 8217 8218 #define S_FW_ACL_MAC_CMD_PFN 8 8219 #define M_FW_ACL_MAC_CMD_PFN 0x7 8220 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 8221 #define G_FW_ACL_MAC_CMD_PFN(x) \ 8222 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 8223 8224 #define S_FW_ACL_MAC_CMD_VFN 0 8225 #define M_FW_ACL_MAC_CMD_VFN 0xff 8226 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 8227 #define G_FW_ACL_MAC_CMD_VFN(x) \ 8228 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 8229 8230 #define S_FW_ACL_MAC_CMD_EN 31 8231 #define M_FW_ACL_MAC_CMD_EN 0x1 8232 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 8233 #define G_FW_ACL_MAC_CMD_EN(x) \ 8234 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 8235 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 8236 8237 struct fw_acl_vlan_cmd { 8238 __be32 op_to_vfn; 8239 __be32 en_to_len16; 8240 __u8 nvlan; 8241 __u8 dropnovlan_fm; 8242 __u8 r3_lo[6]; 8243 __be16 vlanid[16]; 8244 }; 8245 8246 #define S_FW_ACL_VLAN_CMD_PFN 8 8247 #define M_FW_ACL_VLAN_CMD_PFN 0x7 8248 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 8249 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 8250 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 8251 8252 #define S_FW_ACL_VLAN_CMD_VFN 0 8253 #define M_FW_ACL_VLAN_CMD_VFN 0xff 8254 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 8255 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 8256 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 8257 8258 #define S_FW_ACL_VLAN_CMD_EN 31 8259 #define M_FW_ACL_VLAN_CMD_EN 0x1 8260 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 8261 #define G_FW_ACL_VLAN_CMD_EN(x) \ 8262 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 8263 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 8264 8265 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 8266 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 8267 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 8268 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 8269 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 8270 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 8271 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 8272 8273 #define S_FW_ACL_VLAN_CMD_PMASK 16 8274 #define M_FW_ACL_VLAN_CMD_PMASK 0xf 8275 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 8276 #define G_FW_ACL_VLAN_CMD_PMASK(x) \ 8277 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 8278 8279 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 8280 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 8281 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 8282 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 8283 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 8284 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 8285 8286 #define S_FW_ACL_VLAN_CMD_FM 6 8287 #define M_FW_ACL_VLAN_CMD_FM 0x1 8288 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 8289 #define G_FW_ACL_VLAN_CMD_FM(x) \ 8290 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 8291 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 8292 8293 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 8294 enum fw_port_cap { 8295 FW_PORT_CAP_SPEED_100M = 0x0001, 8296 FW_PORT_CAP_SPEED_1G = 0x0002, 8297 FW_PORT_CAP_SPEED_25G = 0x0004, 8298 FW_PORT_CAP_SPEED_10G = 0x0008, 8299 FW_PORT_CAP_SPEED_40G = 0x0010, 8300 FW_PORT_CAP_SPEED_100G = 0x0020, 8301 FW_PORT_CAP_FC_RX = 0x0040, 8302 FW_PORT_CAP_FC_TX = 0x0080, 8303 FW_PORT_CAP_ANEG = 0x0100, 8304 FW_PORT_CAP_MDIAUTO = 0x0200, 8305 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 8306 FW_PORT_CAP_FEC_RS = 0x0800, 8307 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 8308 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 8309 FW_PORT_CAP_802_3_PAUSE = 0x4000, 8310 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 8311 }; 8312 8313 #define S_FW_PORT_CAP_SPEED 0 8314 #define M_FW_PORT_CAP_SPEED 0x3f 8315 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 8316 #define G_FW_PORT_CAP_SPEED(x) \ 8317 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 8318 8319 #define S_FW_PORT_CAP_FC 6 8320 #define M_FW_PORT_CAP_FC 0x3 8321 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 8322 #define G_FW_PORT_CAP_FC(x) \ 8323 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 8324 8325 #define S_FW_PORT_CAP_ANEG 8 8326 #define M_FW_PORT_CAP_ANEG 0x1 8327 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 8328 #define G_FW_PORT_CAP_ANEG(x) \ 8329 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 8330 8331 #define S_FW_PORT_CAP_FEC 11 8332 #define M_FW_PORT_CAP_FEC 0x3 8333 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 8334 #define G_FW_PORT_CAP_FEC(x) \ 8335 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 8336 8337 #define S_FW_PORT_CAP_FORCE_PAUSE 13 8338 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 8339 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 8340 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 8341 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 8342 8343 #define S_FW_PORT_CAP_802_3 14 8344 #define M_FW_PORT_CAP_802_3 0x3 8345 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 8346 #define G_FW_PORT_CAP_802_3(x) \ 8347 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 8348 8349 enum fw_port_mdi { 8350 FW_PORT_CAP_MDI_UNCHANGED, 8351 FW_PORT_CAP_MDI_AUTO, 8352 FW_PORT_CAP_MDI_F_STRAIGHT, 8353 FW_PORT_CAP_MDI_F_CROSSOVER 8354 }; 8355 8356 #define S_FW_PORT_CAP_MDI 9 8357 #define M_FW_PORT_CAP_MDI 3 8358 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 8359 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 8360 8361 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 8362 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 8363 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 8364 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 8365 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 8366 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 8367 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 8368 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 8369 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 8370 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 8371 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 8372 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 8373 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 8374 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 8375 #define FW_PORT_CAP32_FC_RX 0x00010000UL 8376 #define FW_PORT_CAP32_FC_TX 0x00020000UL 8377 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 8378 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 8379 #define FW_PORT_CAP32_ANEG 0x00100000UL 8380 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 8381 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 8382 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 8383 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 8384 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL 8385 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 8386 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 8387 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 8388 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL 8389 #define FW_PORT_CAP32_RESERVED2 0xc0000000UL 8390 8391 #define S_FW_PORT_CAP32_SPEED 0 8392 #define M_FW_PORT_CAP32_SPEED 0xfff 8393 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 8394 #define G_FW_PORT_CAP32_SPEED(x) \ 8395 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 8396 8397 #define S_FW_PORT_CAP32_FC 16 8398 #define M_FW_PORT_CAP32_FC 0x3 8399 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 8400 #define G_FW_PORT_CAP32_FC(x) \ 8401 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 8402 8403 #define S_FW_PORT_CAP32_802_3 18 8404 #define M_FW_PORT_CAP32_802_3 0x3 8405 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 8406 #define G_FW_PORT_CAP32_802_3(x) \ 8407 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 8408 8409 #define S_FW_PORT_CAP32_ANEG 20 8410 #define M_FW_PORT_CAP32_ANEG 0x1 8411 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 8412 #define G_FW_PORT_CAP32_ANEG(x) \ 8413 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 8414 8415 #define S_FW_PORT_CAP32_FORCE_PAUSE 28 8416 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 8417 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 8418 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 8419 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 8420 8421 enum fw_port_mdi32 { 8422 FW_PORT_CAP32_MDI_UNCHANGED, 8423 FW_PORT_CAP32_MDI_AUTO, 8424 FW_PORT_CAP32_MDI_F_STRAIGHT, 8425 FW_PORT_CAP32_MDI_F_CROSSOVER 8426 }; 8427 8428 #define S_FW_PORT_CAP32_MDI 21 8429 #define M_FW_PORT_CAP32_MDI 3 8430 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 8431 #define G_FW_PORT_CAP32_MDI(x) \ 8432 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 8433 8434 #define S_FW_PORT_CAP32_FEC 23 8435 #define M_FW_PORT_CAP32_FEC 0x1f 8436 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 8437 #define G_FW_PORT_CAP32_FEC(x) \ 8438 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 8439 8440 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 8441 #define CAP32_SPEED(__cap32) \ 8442 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 8443 8444 #define CAP32_FEC(__cap32) \ 8445 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 8446 8447 #define CAP32_FC(__cap32) \ 8448 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 8449 8450 static inline bool 8451 fec_supported(uint32_t caps) 8452 { 8453 8454 return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G | 8455 FW_PORT_CAP32_SPEED_100G | FW_PORT_CAP32_SPEED_200G | 8456 FW_PORT_CAP32_SPEED_400G)) != 0); 8457 } 8458 8459 enum fw_port_action { 8460 FW_PORT_ACTION_L1_CFG = 0x0001, 8461 FW_PORT_ACTION_L2_CFG = 0x0002, 8462 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 8463 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 8464 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 8465 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 8466 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 8467 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 8468 FW_PORT_ACTION_L1_CFG32 = 0x0009, 8469 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 8470 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 8471 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 8472 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 8473 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 8474 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 8475 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 8476 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 8477 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 8478 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 8479 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 8480 FW_PORT_ACTION_PHY_RESET = 0x0040, 8481 FW_PORT_ACTION_PMA_RESET = 0x0041, 8482 FW_PORT_ACTION_PCS_RESET = 0x0042, 8483 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 8484 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 8485 FW_PORT_ACTION_AN_RESET = 0x0045, 8486 }; 8487 8488 enum fw_port_l2cfg_ctlbf { 8489 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 8490 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 8491 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 8492 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 8493 FW_PORT_L2_CTLBF_IVLAN = 0x10, 8494 FW_PORT_L2_CTLBF_TXIPG = 0x20, 8495 FW_PORT_L2_CTLBF_MTU = 0x40, 8496 FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80, 8497 }; 8498 8499 enum fw_dcb_app_tlv_sf { 8500 FW_DCB_APP_SF_ETHERTYPE, 8501 FW_DCB_APP_SF_SOCKET_TCP, 8502 FW_DCB_APP_SF_SOCKET_UDP, 8503 FW_DCB_APP_SF_SOCKET_ALL, 8504 }; 8505 8506 enum fw_port_dcb_versions { 8507 FW_PORT_DCB_VER_UNKNOWN, 8508 FW_PORT_DCB_VER_CEE1D0, 8509 FW_PORT_DCB_VER_CEE1D01, 8510 FW_PORT_DCB_VER_IEEE, 8511 FW_PORT_DCB_VER_AUTO=7 8512 }; 8513 8514 enum fw_port_dcb_cfg { 8515 FW_PORT_DCB_CFG_PG = 0x01, 8516 FW_PORT_DCB_CFG_PFC = 0x02, 8517 FW_PORT_DCB_CFG_APPL = 0x04 8518 }; 8519 8520 enum fw_port_dcb_cfg_rc { 8521 FW_PORT_DCB_CFG_SUCCESS = 0x0, 8522 FW_PORT_DCB_CFG_ERROR = 0x1 8523 }; 8524 8525 enum fw_port_dcb_type { 8526 FW_PORT_DCB_TYPE_PGID = 0x00, 8527 FW_PORT_DCB_TYPE_PGRATE = 0x01, 8528 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 8529 FW_PORT_DCB_TYPE_PFC = 0x03, 8530 FW_PORT_DCB_TYPE_APP_ID = 0x04, 8531 FW_PORT_DCB_TYPE_CONTROL = 0x05, 8532 }; 8533 8534 enum fw_port_dcb_feature_state { 8535 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 8536 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 8537 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 8538 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 8539 }; 8540 8541 enum fw_port_diag_ops { 8542 FW_PORT_DIAGS_TEMP = 0x00, 8543 FW_PORT_DIAGS_TX_POWER = 0x01, 8544 FW_PORT_DIAGS_RX_POWER = 0x02, 8545 FW_PORT_DIAGS_TX_DIS = 0x03, 8546 }; 8547 8548 struct fw_port_cmd { 8549 __be32 op_to_portid; 8550 __be32 action_to_len16; 8551 union fw_port { 8552 struct fw_port_l1cfg { 8553 __be32 rcap; 8554 __be32 r; 8555 } l1cfg; 8556 struct fw_port_l2cfg { 8557 __u8 ctlbf; 8558 __u8 ovlan3_to_ivlan0; 8559 __be16 ivlantype; 8560 __be16 txipg_force_pinfo; 8561 __be16 mtu; 8562 __be16 ovlan0mask; 8563 __be16 ovlan0type; 8564 __be16 ovlan1mask; 8565 __be16 ovlan1type; 8566 __be16 ovlan2mask; 8567 __be16 ovlan2type; 8568 __be16 ovlan3mask; 8569 __be16 ovlan3type; 8570 } l2cfg; 8571 struct fw_port_info { 8572 __be32 lstatus_to_modtype; 8573 __be16 pcap; 8574 __be16 acap; 8575 __be16 mtu; 8576 __u8 cbllen; 8577 __u8 auxlinfo; 8578 __u8 dcbxdis_pkd; 8579 __u8 r8_lo; 8580 __be16 lpacap; 8581 __be64 r9; 8582 } info; 8583 struct fw_port_diags { 8584 __u8 diagop; 8585 __u8 r[3]; 8586 __be32 diagval; 8587 } diags; 8588 union fw_port_dcb { 8589 struct fw_port_dcb_pgid { 8590 __u8 type; 8591 __u8 apply_pkd; 8592 __u8 r10_lo[2]; 8593 __be32 pgid; 8594 __be64 r11; 8595 } pgid; 8596 struct fw_port_dcb_pgrate { 8597 __u8 type; 8598 __u8 apply_pkd; 8599 __u8 r10_lo[5]; 8600 __u8 num_tcs_supported; 8601 __u8 pgrate[8]; 8602 __u8 tsa[8]; 8603 } pgrate; 8604 struct fw_port_dcb_priorate { 8605 __u8 type; 8606 __u8 apply_pkd; 8607 __u8 r10_lo[6]; 8608 __u8 strict_priorate[8]; 8609 } priorate; 8610 struct fw_port_dcb_pfc { 8611 __u8 type; 8612 __u8 pfcen; 8613 __u8 apply_pkd; 8614 __u8 r10_lo[4]; 8615 __u8 max_pfc_tcs; 8616 __be64 r11; 8617 } pfc; 8618 struct fw_port_app_priority { 8619 __u8 type; 8620 __u8 apply_pkd; 8621 __u8 r10_lo; 8622 __u8 idx; 8623 __u8 user_prio_map; 8624 __u8 sel_field; 8625 __be16 protocolid; 8626 __be64 r12; 8627 } app_priority; 8628 struct fw_port_dcb_control { 8629 __u8 type; 8630 __u8 all_syncd_pkd; 8631 __be16 dcb_version_to_app_state; 8632 __be32 r11; 8633 __be64 r12; 8634 } control; 8635 } dcb; 8636 struct fw_port_l1cfg32 { 8637 __be32 rcap32; 8638 __be32 r; 8639 } l1cfg32; 8640 struct fw_port_info32 { 8641 __be32 lstatus32_to_cbllen32; 8642 __be32 auxlinfo32_mtu32; 8643 __be32 linkattr32; 8644 __be32 pcaps32; 8645 __be32 acaps32; 8646 __be32 lpacaps32; 8647 } info32; 8648 } u; 8649 }; 8650 8651 #define S_FW_PORT_CMD_READ 22 8652 #define M_FW_PORT_CMD_READ 0x1 8653 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 8654 #define G_FW_PORT_CMD_READ(x) \ 8655 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 8656 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 8657 8658 #define S_FW_PORT_CMD_PORTID 0 8659 #define M_FW_PORT_CMD_PORTID 0xf 8660 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 8661 #define G_FW_PORT_CMD_PORTID(x) \ 8662 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 8663 8664 #define S_FW_PORT_CMD_ACTION 16 8665 #define M_FW_PORT_CMD_ACTION 0xffff 8666 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 8667 #define G_FW_PORT_CMD_ACTION(x) \ 8668 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 8669 8670 #define S_FW_PORT_CMD_OVLAN3 7 8671 #define M_FW_PORT_CMD_OVLAN3 0x1 8672 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 8673 #define G_FW_PORT_CMD_OVLAN3(x) \ 8674 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 8675 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 8676 8677 #define S_FW_PORT_CMD_OVLAN2 6 8678 #define M_FW_PORT_CMD_OVLAN2 0x1 8679 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 8680 #define G_FW_PORT_CMD_OVLAN2(x) \ 8681 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 8682 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 8683 8684 #define S_FW_PORT_CMD_OVLAN1 5 8685 #define M_FW_PORT_CMD_OVLAN1 0x1 8686 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 8687 #define G_FW_PORT_CMD_OVLAN1(x) \ 8688 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 8689 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 8690 8691 #define S_FW_PORT_CMD_OVLAN0 4 8692 #define M_FW_PORT_CMD_OVLAN0 0x1 8693 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 8694 #define G_FW_PORT_CMD_OVLAN0(x) \ 8695 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 8696 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 8697 8698 #define S_FW_PORT_CMD_IVLAN0 3 8699 #define M_FW_PORT_CMD_IVLAN0 0x1 8700 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 8701 #define G_FW_PORT_CMD_IVLAN0(x) \ 8702 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 8703 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 8704 8705 #define S_FW_PORT_CMD_OVLAN_FILT 2 8706 #define M_FW_PORT_CMD_OVLAN_FILT 0x1 8707 #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT) 8708 #define G_FW_PORT_CMD_OVLAN_FILT(x) \ 8709 (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT) 8710 #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U) 8711 8712 #define S_FW_PORT_CMD_TXIPG 3 8713 #define M_FW_PORT_CMD_TXIPG 0x1fff 8714 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 8715 #define G_FW_PORT_CMD_TXIPG(x) \ 8716 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 8717 8718 #define S_FW_PORT_CMD_FORCE_PINFO 0 8719 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 8720 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 8721 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 8722 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 8723 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 8724 8725 #define S_FW_PORT_CMD_LSTATUS 31 8726 #define M_FW_PORT_CMD_LSTATUS 0x1 8727 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 8728 #define G_FW_PORT_CMD_LSTATUS(x) \ 8729 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 8730 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 8731 8732 #define S_FW_PORT_CMD_LSPEED 24 8733 #define M_FW_PORT_CMD_LSPEED 0x3f 8734 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 8735 #define G_FW_PORT_CMD_LSPEED(x) \ 8736 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 8737 8738 #define S_FW_PORT_CMD_TXPAUSE 23 8739 #define M_FW_PORT_CMD_TXPAUSE 0x1 8740 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 8741 #define G_FW_PORT_CMD_TXPAUSE(x) \ 8742 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 8743 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 8744 8745 #define S_FW_PORT_CMD_RXPAUSE 22 8746 #define M_FW_PORT_CMD_RXPAUSE 0x1 8747 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 8748 #define G_FW_PORT_CMD_RXPAUSE(x) \ 8749 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 8750 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 8751 8752 #define S_FW_PORT_CMD_MDIOCAP 21 8753 #define M_FW_PORT_CMD_MDIOCAP 0x1 8754 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 8755 #define G_FW_PORT_CMD_MDIOCAP(x) \ 8756 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 8757 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 8758 8759 #define S_FW_PORT_CMD_MDIOADDR 16 8760 #define M_FW_PORT_CMD_MDIOADDR 0x1f 8761 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 8762 #define G_FW_PORT_CMD_MDIOADDR(x) \ 8763 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 8764 8765 #define S_FW_PORT_CMD_LPTXPAUSE 15 8766 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 8767 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 8768 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 8769 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 8770 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 8771 8772 #define S_FW_PORT_CMD_LPRXPAUSE 14 8773 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 8774 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 8775 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 8776 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 8777 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 8778 8779 #define S_FW_PORT_CMD_PTYPE 8 8780 #define M_FW_PORT_CMD_PTYPE 0x1f 8781 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 8782 #define G_FW_PORT_CMD_PTYPE(x) \ 8783 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 8784 8785 #define S_FW_PORT_CMD_LINKDNRC 5 8786 #define M_FW_PORT_CMD_LINKDNRC 0x7 8787 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 8788 #define G_FW_PORT_CMD_LINKDNRC(x) \ 8789 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 8790 8791 #define S_FW_PORT_CMD_MODTYPE 0 8792 #define M_FW_PORT_CMD_MODTYPE 0x1f 8793 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 8794 #define G_FW_PORT_CMD_MODTYPE(x) \ 8795 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 8796 8797 #define S_FW_PORT_AUXLINFO_KX4 2 8798 #define M_FW_PORT_AUXLINFO_KX4 0x1 8799 #define V_FW_PORT_AUXLINFO_KX4(x) \ 8800 ((x) << S_FW_PORT_AUXLINFO_KX4) 8801 #define G_FW_PORT_AUXLINFO_KX4(x) \ 8802 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 8803 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 8804 8805 #define S_FW_PORT_AUXLINFO_KR 1 8806 #define M_FW_PORT_AUXLINFO_KR 0x1 8807 #define V_FW_PORT_AUXLINFO_KR(x) \ 8808 ((x) << S_FW_PORT_AUXLINFO_KR) 8809 #define G_FW_PORT_AUXLINFO_KR(x) \ 8810 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 8811 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 8812 8813 #define S_FW_PORT_CMD_DCBXDIS 7 8814 #define M_FW_PORT_CMD_DCBXDIS 0x1 8815 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 8816 #define G_FW_PORT_CMD_DCBXDIS(x) \ 8817 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 8818 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 8819 8820 #define S_FW_PORT_CMD_APPLY 7 8821 #define M_FW_PORT_CMD_APPLY 0x1 8822 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 8823 #define G_FW_PORT_CMD_APPLY(x) \ 8824 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 8825 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 8826 8827 #define S_FW_PORT_CMD_ALL_SYNCD 7 8828 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 8829 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 8830 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 8831 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 8832 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 8833 8834 #define S_FW_PORT_CMD_DCB_VERSION 12 8835 #define M_FW_PORT_CMD_DCB_VERSION 0x7 8836 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 8837 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 8838 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 8839 8840 #define S_FW_PORT_CMD_PFC_STATE 8 8841 #define M_FW_PORT_CMD_PFC_STATE 0xf 8842 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 8843 #define G_FW_PORT_CMD_PFC_STATE(x) \ 8844 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 8845 8846 #define S_FW_PORT_CMD_ETS_STATE 4 8847 #define M_FW_PORT_CMD_ETS_STATE 0xf 8848 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 8849 #define G_FW_PORT_CMD_ETS_STATE(x) \ 8850 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 8851 8852 #define S_FW_PORT_CMD_APP_STATE 0 8853 #define M_FW_PORT_CMD_APP_STATE 0xf 8854 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 8855 #define G_FW_PORT_CMD_APP_STATE(x) \ 8856 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 8857 8858 #define S_FW_PORT_CMD_LSTATUS32 31 8859 #define M_FW_PORT_CMD_LSTATUS32 0x1 8860 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 8861 #define G_FW_PORT_CMD_LSTATUS32(x) \ 8862 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 8863 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 8864 8865 #define S_FW_PORT_CMD_LINKDNRC32 28 8866 #define M_FW_PORT_CMD_LINKDNRC32 0x7 8867 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 8868 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 8869 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 8870 8871 #define S_FW_PORT_CMD_DCBXDIS32 27 8872 #define M_FW_PORT_CMD_DCBXDIS32 0x1 8873 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 8874 #define G_FW_PORT_CMD_DCBXDIS32(x) \ 8875 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 8876 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 8877 8878 #define S_FW_PORT_CMD_MDIOCAP32 26 8879 #define M_FW_PORT_CMD_MDIOCAP32 0x1 8880 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 8881 #define G_FW_PORT_CMD_MDIOCAP32(x) \ 8882 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 8883 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 8884 8885 #define S_FW_PORT_CMD_MDIOADDR32 21 8886 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 8887 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 8888 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 8889 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 8890 8891 #define S_FW_PORT_CMD_PORTTYPE32 13 8892 #define M_FW_PORT_CMD_PORTTYPE32 0xff 8893 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 8894 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 8895 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 8896 8897 #define S_FW_PORT_CMD_MODTYPE32 8 8898 #define M_FW_PORT_CMD_MODTYPE32 0x1f 8899 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 8900 #define G_FW_PORT_CMD_MODTYPE32(x) \ 8901 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 8902 8903 #define S_FW_PORT_CMD_CBLLEN32 0 8904 #define M_FW_PORT_CMD_CBLLEN32 0xff 8905 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 8906 #define G_FW_PORT_CMD_CBLLEN32(x) \ 8907 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 8908 8909 #define S_FW_PORT_CMD_AUXLINFO32 24 8910 #define M_FW_PORT_CMD_AUXLINFO32 0xff 8911 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 8912 #define G_FW_PORT_CMD_AUXLINFO32(x) \ 8913 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 8914 8915 #define S_FW_PORT_AUXLINFO32_KX4 2 8916 #define M_FW_PORT_AUXLINFO32_KX4 0x1 8917 #define V_FW_PORT_AUXLINFO32_KX4(x) \ 8918 ((x) << S_FW_PORT_AUXLINFO32_KX4) 8919 #define G_FW_PORT_AUXLINFO32_KX4(x) \ 8920 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 8921 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 8922 8923 #define S_FW_PORT_AUXLINFO32_KR 1 8924 #define M_FW_PORT_AUXLINFO32_KR 0x1 8925 #define V_FW_PORT_AUXLINFO32_KR(x) \ 8926 ((x) << S_FW_PORT_AUXLINFO32_KR) 8927 #define G_FW_PORT_AUXLINFO32_KR(x) \ 8928 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 8929 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 8930 8931 #define S_FW_PORT_CMD_MTU32 0 8932 #define M_FW_PORT_CMD_MTU32 0xffff 8933 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 8934 #define G_FW_PORT_CMD_MTU32(x) \ 8935 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 8936 8937 /* 8938 * These are configured into the VPD and hence tools that generate 8939 * VPD may use this enumeration. 8940 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 8941 * 8942 * REMEMBER: 8943 * Update the Common Code t4_hw.c:t4_get_port_type_description() 8944 * with any new Firmware Port Technology Types! 8945 */ 8946 enum fw_port_type { 8947 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 8948 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 8949 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 8950 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 8951 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 8952 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 8953 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 8954 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 8955 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 8956 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 8957 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 8958 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 8959 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 8960 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 8961 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 8962 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 8963 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 8964 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 8965 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 8966 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 8967 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 8968 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 8969 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 8970 FW_PORT_TYPE_SFP56 = 26, 8971 FW_PORT_TYPE_QSFP56 = 27, 8972 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 8973 }; 8974 8975 static inline bool 8976 is_bt(enum fw_port_type port_type) 8977 { 8978 return (port_type == FW_PORT_TYPE_BT_SGMII || 8979 port_type == FW_PORT_TYPE_BT_XFI || 8980 port_type == FW_PORT_TYPE_BT_XAUI); 8981 } 8982 8983 /* These are read from module's EEPROM and determined once the 8984 module is inserted. */ 8985 enum fw_port_module_type { 8986 FW_PORT_MOD_TYPE_NA = 0x0, 8987 FW_PORT_MOD_TYPE_LR = 0x1, 8988 FW_PORT_MOD_TYPE_SR = 0x2, 8989 FW_PORT_MOD_TYPE_ER = 0x3, 8990 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 8991 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 8992 FW_PORT_MOD_TYPE_LRM = 0x6, 8993 FW_PORT_MOD_TYPE_LR_SIMPLEX = 0x7, 8994 FW_PORT_MOD_TYPE_DR = 0x8, 8995 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 8996 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 8997 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 8998 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 8999 }; 9000 9001 /* used by FW and tools may use this to generate VPD */ 9002 enum fw_port_mod_sub_type { 9003 FW_PORT_MOD_SUB_TYPE_NA, 9004 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 9005 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 9006 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 9007 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 9008 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 9009 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 9010 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 9011 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 9012 9013 /* 9014 * The following will never been in the VPD. They are TWINAX cable 9015 * lengths decoded from SFP+ module i2c PROMs. These should almost 9016 * certainly go somewhere else ... 9017 */ 9018 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 9019 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 9020 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 9021 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 9022 }; 9023 9024 /* link down reason codes (3b) */ 9025 enum fw_port_link_dn_rc { 9026 FW_PORT_LINK_DN_RC_NONE, 9027 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 9028 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 9029 FW_PORT_LINK_DN_RESERVED3, 9030 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 9031 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 9032 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 9033 FW_PORT_LINK_DN_RESERVED7 9034 }; 9035 enum fw_port_stats_tx_index { 9036 FW_STAT_TX_PORT_BYTES_IX = 0, 9037 FW_STAT_TX_PORT_FRAMES_IX, 9038 FW_STAT_TX_PORT_BCAST_IX, 9039 FW_STAT_TX_PORT_MCAST_IX, 9040 FW_STAT_TX_PORT_UCAST_IX, 9041 FW_STAT_TX_PORT_ERROR_IX, 9042 FW_STAT_TX_PORT_64B_IX, 9043 FW_STAT_TX_PORT_65B_127B_IX, 9044 FW_STAT_TX_PORT_128B_255B_IX, 9045 FW_STAT_TX_PORT_256B_511B_IX, 9046 FW_STAT_TX_PORT_512B_1023B_IX, 9047 FW_STAT_TX_PORT_1024B_1518B_IX, 9048 FW_STAT_TX_PORT_1519B_MAX_IX, 9049 FW_STAT_TX_PORT_DROP_IX, 9050 FW_STAT_TX_PORT_PAUSE_IX, 9051 FW_STAT_TX_PORT_PPP0_IX, 9052 FW_STAT_TX_PORT_PPP1_IX, 9053 FW_STAT_TX_PORT_PPP2_IX, 9054 FW_STAT_TX_PORT_PPP3_IX, 9055 FW_STAT_TX_PORT_PPP4_IX, 9056 FW_STAT_TX_PORT_PPP5_IX, 9057 FW_STAT_TX_PORT_PPP6_IX, 9058 FW_STAT_TX_PORT_PPP7_IX, 9059 FW_NUM_PORT_TX_STATS 9060 }; 9061 9062 enum fw_port_stat_rx_index { 9063 FW_STAT_RX_PORT_BYTES_IX = 0, 9064 FW_STAT_RX_PORT_FRAMES_IX, 9065 FW_STAT_RX_PORT_BCAST_IX, 9066 FW_STAT_RX_PORT_MCAST_IX, 9067 FW_STAT_RX_PORT_UCAST_IX, 9068 FW_STAT_RX_PORT_MTU_ERROR_IX, 9069 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 9070 FW_STAT_RX_PORT_CRC_ERROR_IX, 9071 FW_STAT_RX_PORT_LEN_ERROR_IX, 9072 FW_STAT_RX_PORT_SYM_ERROR_IX, 9073 FW_STAT_RX_PORT_64B_IX, 9074 FW_STAT_RX_PORT_65B_127B_IX, 9075 FW_STAT_RX_PORT_128B_255B_IX, 9076 FW_STAT_RX_PORT_256B_511B_IX, 9077 FW_STAT_RX_PORT_512B_1023B_IX, 9078 FW_STAT_RX_PORT_1024B_1518B_IX, 9079 FW_STAT_RX_PORT_1519B_MAX_IX, 9080 FW_STAT_RX_PORT_PAUSE_IX, 9081 FW_STAT_RX_PORT_PPP0_IX, 9082 FW_STAT_RX_PORT_PPP1_IX, 9083 FW_STAT_RX_PORT_PPP2_IX, 9084 FW_STAT_RX_PORT_PPP3_IX, 9085 FW_STAT_RX_PORT_PPP4_IX, 9086 FW_STAT_RX_PORT_PPP5_IX, 9087 FW_STAT_RX_PORT_PPP6_IX, 9088 FW_STAT_RX_PORT_PPP7_IX, 9089 FW_STAT_RX_PORT_LESS_64B_IX, 9090 FW_STAT_RX_PORT_MAC_ERROR_IX, 9091 FW_NUM_PORT_RX_STATS 9092 }; 9093 /* port stats */ 9094 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 9095 FW_NUM_PORT_RX_STATS) 9096 9097 9098 struct fw_port_stats_cmd { 9099 __be32 op_to_portid; 9100 __be32 retval_len16; 9101 union fw_port_stats { 9102 struct fw_port_stats_ctl { 9103 __u8 nstats_bg_bm; 9104 __u8 tx_ix; 9105 __be16 r6; 9106 __be32 r7; 9107 __be64 stat0; 9108 __be64 stat1; 9109 __be64 stat2; 9110 __be64 stat3; 9111 __be64 stat4; 9112 __be64 stat5; 9113 } ctl; 9114 struct fw_port_stats_all { 9115 __be64 tx_bytes; 9116 __be64 tx_frames; 9117 __be64 tx_bcast; 9118 __be64 tx_mcast; 9119 __be64 tx_ucast; 9120 __be64 tx_error; 9121 __be64 tx_64b; 9122 __be64 tx_65b_127b; 9123 __be64 tx_128b_255b; 9124 __be64 tx_256b_511b; 9125 __be64 tx_512b_1023b; 9126 __be64 tx_1024b_1518b; 9127 __be64 tx_1519b_max; 9128 __be64 tx_drop; 9129 __be64 tx_pause; 9130 __be64 tx_ppp0; 9131 __be64 tx_ppp1; 9132 __be64 tx_ppp2; 9133 __be64 tx_ppp3; 9134 __be64 tx_ppp4; 9135 __be64 tx_ppp5; 9136 __be64 tx_ppp6; 9137 __be64 tx_ppp7; 9138 __be64 rx_bytes; 9139 __be64 rx_frames; 9140 __be64 rx_bcast; 9141 __be64 rx_mcast; 9142 __be64 rx_ucast; 9143 __be64 rx_mtu_error; 9144 __be64 rx_mtu_crc_error; 9145 __be64 rx_crc_error; 9146 __be64 rx_len_error; 9147 __be64 rx_sym_error; 9148 __be64 rx_64b; 9149 __be64 rx_65b_127b; 9150 __be64 rx_128b_255b; 9151 __be64 rx_256b_511b; 9152 __be64 rx_512b_1023b; 9153 __be64 rx_1024b_1518b; 9154 __be64 rx_1519b_max; 9155 __be64 rx_pause; 9156 __be64 rx_ppp0; 9157 __be64 rx_ppp1; 9158 __be64 rx_ppp2; 9159 __be64 rx_ppp3; 9160 __be64 rx_ppp4; 9161 __be64 rx_ppp5; 9162 __be64 rx_ppp6; 9163 __be64 rx_ppp7; 9164 __be64 rx_less_64b; 9165 __be64 rx_bg_drop; 9166 __be64 rx_bg_trunc; 9167 } all; 9168 } u; 9169 }; 9170 9171 #define S_FW_PORT_STATS_CMD_NSTATS 4 9172 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 9173 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 9174 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 9175 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 9176 9177 #define S_FW_PORT_STATS_CMD_BG_BM 0 9178 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 9179 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 9180 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 9181 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 9182 9183 #define S_FW_PORT_STATS_CMD_TX 7 9184 #define M_FW_PORT_STATS_CMD_TX 0x1 9185 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 9186 #define G_FW_PORT_STATS_CMD_TX(x) \ 9187 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 9188 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 9189 9190 #define S_FW_PORT_STATS_CMD_IX 0 9191 #define M_FW_PORT_STATS_CMD_IX 0x3f 9192 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 9193 #define G_FW_PORT_STATS_CMD_IX(x) \ 9194 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 9195 9196 /* port loopback stats */ 9197 #define FW_NUM_LB_STATS 14 9198 enum fw_port_lb_stats_index { 9199 FW_STAT_LB_PORT_BYTES_IX, 9200 FW_STAT_LB_PORT_FRAMES_IX, 9201 FW_STAT_LB_PORT_BCAST_IX, 9202 FW_STAT_LB_PORT_MCAST_IX, 9203 FW_STAT_LB_PORT_UCAST_IX, 9204 FW_STAT_LB_PORT_ERROR_IX, 9205 FW_STAT_LB_PORT_64B_IX, 9206 FW_STAT_LB_PORT_65B_127B_IX, 9207 FW_STAT_LB_PORT_128B_255B_IX, 9208 FW_STAT_LB_PORT_256B_511B_IX, 9209 FW_STAT_LB_PORT_512B_1023B_IX, 9210 FW_STAT_LB_PORT_1024B_1518B_IX, 9211 FW_STAT_LB_PORT_1519B_MAX_IX, 9212 FW_STAT_LB_PORT_DROP_FRAMES_IX 9213 }; 9214 9215 struct fw_port_lb_stats_cmd { 9216 __be32 op_to_lbport; 9217 __be32 retval_len16; 9218 union fw_port_lb_stats { 9219 struct fw_port_lb_stats_ctl { 9220 __u8 nstats_bg_bm; 9221 __u8 ix_pkd; 9222 __be16 r6; 9223 __be32 r7; 9224 __be64 stat0; 9225 __be64 stat1; 9226 __be64 stat2; 9227 __be64 stat3; 9228 __be64 stat4; 9229 __be64 stat5; 9230 } ctl; 9231 struct fw_port_lb_stats_all { 9232 __be64 tx_bytes; 9233 __be64 tx_frames; 9234 __be64 tx_bcast; 9235 __be64 tx_mcast; 9236 __be64 tx_ucast; 9237 __be64 tx_error; 9238 __be64 tx_64b; 9239 __be64 tx_65b_127b; 9240 __be64 tx_128b_255b; 9241 __be64 tx_256b_511b; 9242 __be64 tx_512b_1023b; 9243 __be64 tx_1024b_1518b; 9244 __be64 tx_1519b_max; 9245 __be64 rx_lb_drop; 9246 __be64 rx_lb_trunc; 9247 } all; 9248 } u; 9249 }; 9250 9251 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 9252 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 9253 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 9254 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 9255 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 9256 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 9257 9258 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 9259 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 9260 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 9261 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 9262 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 9263 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 9264 9265 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 9266 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 9267 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 9268 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 9269 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 9270 9271 #define S_FW_PORT_LB_STATS_CMD_IX 0 9272 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 9273 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 9274 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 9275 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 9276 9277 /* Trace related defines */ 9278 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 9279 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 9280 9281 struct fw_port_trace_cmd { 9282 __be32 op_to_portid; 9283 __be32 retval_len16; 9284 __be16 traceen_to_pciech; 9285 __be16 qnum; 9286 __be32 r5; 9287 }; 9288 9289 #define S_FW_PORT_TRACE_CMD_PORTID 0 9290 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 9291 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 9292 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 9293 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 9294 9295 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 9296 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 9297 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 9298 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 9299 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 9300 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 9301 9302 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 9303 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 9304 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 9305 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 9306 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 9307 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 9308 9309 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 9310 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 9311 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 9312 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 9313 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 9314 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 9315 9316 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 9317 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 9318 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 9319 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 9320 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 9321 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 9322 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 9323 9324 #define S_FW_PORT_TRACE_CMD_PCIECH 6 9325 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 9326 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 9327 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 9328 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 9329 9330 struct fw_port_trace_mmap_cmd { 9331 __be32 op_to_portid; 9332 __be32 retval_len16; 9333 __be32 fid_to_skipoffset; 9334 __be32 minpktsize_capturemax; 9335 __u8 map[224]; 9336 }; 9337 9338 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 9339 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 9340 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 9341 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 9342 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 9343 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 9344 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 9345 9346 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 9347 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 9348 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 9349 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 9350 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 9351 9352 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 9353 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 9354 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 9355 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 9356 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 9357 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 9358 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 9359 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 9360 9361 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 9362 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 9363 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 9364 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 9365 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 9366 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 9367 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 9368 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 9369 9370 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 9371 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 9372 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 9373 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 9374 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 9375 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 9376 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 9377 9378 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 9379 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 9380 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 9381 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 9382 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 9383 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 9384 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 9385 9386 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 9387 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 9388 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 9389 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 9390 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 9391 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 9392 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 9393 9394 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 9395 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 9396 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 9397 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 9398 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 9399 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 9400 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 9401 9402 enum fw_ptp_subop { 9403 9404 /* none */ 9405 FW_PTP_SC_INIT_TIMER = 0x00, 9406 FW_PTP_SC_TX_TYPE = 0x01, 9407 9408 /* init */ 9409 FW_PTP_SC_RXTIME_STAMP = 0x08, 9410 FW_PTP_SC_RDRX_TYPE = 0x09, 9411 9412 /* ts */ 9413 FW_PTP_SC_ADJ_FREQ = 0x10, 9414 FW_PTP_SC_ADJ_TIME = 0x11, 9415 FW_PTP_SC_ADJ_FTIME = 0x12, 9416 FW_PTP_SC_WALL_CLOCK = 0x13, 9417 FW_PTP_SC_GET_TIME = 0x14, 9418 FW_PTP_SC_SET_TIME = 0x15, 9419 }; 9420 9421 struct fw_ptp_cmd { 9422 __be32 op_to_portid; 9423 __be32 retval_len16; 9424 union fw_ptp { 9425 struct fw_ptp_sc { 9426 __u8 sc; 9427 __u8 r3[7]; 9428 } scmd; 9429 struct fw_ptp_init { 9430 __u8 sc; 9431 __u8 txchan; 9432 __be16 absid; 9433 __be16 mode; 9434 __be16 ptp_rx_ctrl_pkd; 9435 } init; 9436 struct fw_ptp_ts { 9437 __u8 sc; 9438 __u8 sign; 9439 __be16 r3; 9440 __be32 ppb; 9441 __be64 tm; 9442 } ts; 9443 } u; 9444 __be64 r3; 9445 }; 9446 9447 #define S_FW_PTP_CMD_PORTID 0 9448 #define M_FW_PTP_CMD_PORTID 0xf 9449 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 9450 #define G_FW_PTP_CMD_PORTID(x) \ 9451 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 9452 9453 #define S_FW_PTP_CMD_PTP_RX_CTRL 15 9454 #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1 9455 #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL) 9456 #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \ 9457 (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL) 9458 #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U) 9459 9460 9461 struct fw_rss_ind_tbl_cmd { 9462 __be32 op_to_viid; 9463 __be32 retval_len16; 9464 __be16 niqid; 9465 __be16 startidx; 9466 __be32 r3; 9467 __be32 iq0_to_iq2; 9468 __be32 iq3_to_iq5; 9469 __be32 iq6_to_iq8; 9470 __be32 iq9_to_iq11; 9471 __be32 iq12_to_iq14; 9472 __be32 iq15_to_iq17; 9473 __be32 iq18_to_iq20; 9474 __be32 iq21_to_iq23; 9475 __be32 iq24_to_iq26; 9476 __be32 iq27_to_iq29; 9477 __be32 iq30_iq31; 9478 __be32 r15_lo; 9479 }; 9480 9481 #define S_FW_RSS_IND_TBL_CMD_VIID 0 9482 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 9483 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 9484 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 9485 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 9486 9487 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 9488 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 9489 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 9490 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 9491 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 9492 9493 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 9494 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 9495 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 9496 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 9497 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 9498 9499 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 9500 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 9501 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 9502 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 9503 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 9504 9505 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 9506 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 9507 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 9508 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 9509 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 9510 9511 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 9512 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 9513 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 9514 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 9515 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 9516 9517 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 9518 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 9519 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 9520 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 9521 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 9522 9523 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 9524 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 9525 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 9526 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 9527 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 9528 9529 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 9530 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 9531 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 9532 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 9533 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 9534 9535 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 9536 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 9537 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 9538 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 9539 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 9540 9541 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 9542 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 9543 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 9544 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 9545 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 9546 9547 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 9548 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 9549 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 9550 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 9551 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 9552 9553 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 9554 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 9555 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 9556 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 9557 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 9558 9559 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 9560 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 9561 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 9562 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 9563 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 9564 9565 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 9566 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 9567 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 9568 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 9569 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 9570 9571 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 9572 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 9573 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 9574 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 9575 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 9576 9577 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 9578 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 9579 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 9580 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 9581 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 9582 9583 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 9584 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 9585 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 9586 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 9587 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 9588 9589 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 9590 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 9591 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 9592 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 9593 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 9594 9595 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 9596 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 9597 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 9598 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 9599 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 9600 9601 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 9602 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 9603 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 9604 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 9605 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 9606 9607 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 9608 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 9609 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 9610 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 9611 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 9612 9613 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 9614 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 9615 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 9616 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 9617 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 9618 9619 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 9620 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 9621 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 9622 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 9623 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 9624 9625 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 9626 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 9627 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 9628 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 9629 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 9630 9631 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 9632 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 9633 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 9634 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 9635 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 9636 9637 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 9638 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 9639 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 9640 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 9641 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 9642 9643 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 9644 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 9645 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 9646 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 9647 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 9648 9649 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 9650 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 9651 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 9652 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 9653 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 9654 9655 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 9656 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 9657 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 9658 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 9659 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 9660 9661 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 9662 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 9663 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 9664 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 9665 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 9666 9667 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 9668 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 9669 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 9670 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 9671 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 9672 9673 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 9674 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 9675 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 9676 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 9677 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 9678 9679 struct fw_rss_glb_config_cmd { 9680 __be32 op_to_write; 9681 __be32 retval_len16; 9682 union fw_rss_glb_config { 9683 struct fw_rss_glb_config_manual { 9684 __be32 mode_pkd; 9685 __be32 r3; 9686 __be64 r4; 9687 __be64 r5; 9688 } manual; 9689 struct fw_rss_glb_config_basicvirtual { 9690 __be32 mode_keymode; 9691 __be32 synmapen_to_hashtoeplitz; 9692 __be64 r8; 9693 __be64 r9; 9694 } basicvirtual; 9695 } u; 9696 }; 9697 9698 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 9699 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 9700 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 9701 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 9702 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 9703 9704 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 9705 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 9706 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 9707 9708 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 9709 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 9710 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 9711 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 9712 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 9713 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 9714 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 9715 9716 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 9717 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 9718 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 9719 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 9720 9721 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 9722 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 9723 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 9724 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 9725 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 9726 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 9727 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 9728 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 9729 9730 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 9731 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 9732 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 9733 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 9734 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 9735 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 9736 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 9737 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 9738 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 9739 9740 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 9741 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 9742 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 9743 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 9744 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 9745 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 9746 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 9747 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 9748 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 9749 9750 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 9751 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 9752 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 9753 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 9754 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 9755 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 9756 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 9757 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 9758 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 9759 9760 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 9761 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 9762 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 9763 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 9764 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 9765 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 9766 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 9767 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 9768 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 9769 9770 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 9771 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 9772 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 9773 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 9774 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 9775 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 9776 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 9777 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 9778 9779 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 9780 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 9781 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 9782 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 9783 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 9784 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 9785 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 9786 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 9787 9788 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 9789 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 9790 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 9791 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 9792 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 9793 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 9794 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 9795 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 9796 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 9797 9798 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 9799 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 9800 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 9801 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 9802 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 9803 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 9804 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 9805 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 9806 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 9807 9808 struct fw_rss_vi_config_cmd { 9809 __be32 op_to_viid; 9810 __be32 retval_len16; 9811 union fw_rss_vi_config { 9812 struct fw_rss_vi_config_manual { 9813 __be64 r3; 9814 __be64 r4; 9815 __be64 r5; 9816 } manual; 9817 struct fw_rss_vi_config_basicvirtual { 9818 __be32 r6; 9819 __be32 defaultq_to_udpen; 9820 __be32 secretkeyidx_pkd; 9821 __be32 secretkeyxor; 9822 __be64 r10; 9823 } basicvirtual; 9824 } u; 9825 }; 9826 9827 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 9828 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 9829 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 9830 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 9831 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 9832 9833 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 9834 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 9835 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 9836 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 9837 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 9838 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 9839 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 9840 9841 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 9842 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 9843 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 9844 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 9845 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 9846 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 9847 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 9848 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 9849 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 9850 9851 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 9852 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 9853 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 9854 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 9855 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 9856 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 9857 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 9858 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 9859 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 9860 9861 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 9862 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 9863 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 9864 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 9865 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 9866 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 9867 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 9868 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 9869 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 9870 9871 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 9872 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 9873 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 9874 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 9875 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 9876 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 9877 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 9878 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 9879 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 9880 9881 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 9882 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 9883 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 9884 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 9885 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 9886 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 9887 9888 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 9889 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 9890 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 9891 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 9892 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 9893 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 9894 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 9895 9896 enum fw_sched_sc { 9897 FW_SCHED_SC_CONFIG = 0, 9898 FW_SCHED_SC_PARAMS = 1, 9899 }; 9900 9901 enum fw_sched_type { 9902 FW_SCHED_TYPE_PKTSCHED = 0, 9903 FW_SCHED_TYPE_STREAMSCHED = 1, 9904 }; 9905 9906 enum fw_sched_params_level { 9907 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 9908 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 9909 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 9910 }; 9911 9912 enum fw_sched_params_mode { 9913 FW_SCHED_PARAMS_MODE_CLASS = 0, 9914 FW_SCHED_PARAMS_MODE_FLOW = 1, 9915 }; 9916 9917 enum fw_sched_params_unit { 9918 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 9919 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 9920 }; 9921 9922 enum fw_sched_params_rate { 9923 FW_SCHED_PARAMS_RATE_REL = 0, 9924 FW_SCHED_PARAMS_RATE_ABS = 1, 9925 }; 9926 9927 struct fw_sched_cmd { 9928 __be32 op_to_write; 9929 __be32 retval_len16; 9930 union fw_sched { 9931 struct fw_sched_config { 9932 __u8 sc; 9933 __u8 type; 9934 __u8 minmaxen; 9935 __u8 r3[5]; 9936 __u8 nclasses[4]; 9937 __be32 r4; 9938 } config; 9939 struct fw_sched_params { 9940 __u8 sc; 9941 __u8 type; 9942 __u8 level; 9943 __u8 mode; 9944 __u8 unit; 9945 __u8 rate; 9946 __u8 ch; 9947 __u8 cl; 9948 __be32 min; 9949 __be32 max; 9950 __be16 weight; 9951 __be16 pktsize; 9952 __be16 burstsize; 9953 __be16 r4; 9954 } params; 9955 } u; 9956 }; 9957 9958 /* 9959 * length of the formatting string 9960 */ 9961 #define FW_DEVLOG_FMT_LEN 192 9962 9963 /* 9964 * maximum number of the formatting string parameters 9965 */ 9966 #define FW_DEVLOG_FMT_PARAMS_NUM 8 9967 9968 /* 9969 * priority levels 9970 */ 9971 enum fw_devlog_level { 9972 FW_DEVLOG_LEVEL_EMERG = 0x0, 9973 FW_DEVLOG_LEVEL_CRIT = 0x1, 9974 FW_DEVLOG_LEVEL_ERR = 0x2, 9975 FW_DEVLOG_LEVEL_NOTICE = 0x3, 9976 FW_DEVLOG_LEVEL_INFO = 0x4, 9977 FW_DEVLOG_LEVEL_DEBUG = 0x5, 9978 FW_DEVLOG_LEVEL_MAX = 0x5, 9979 }; 9980 9981 /* 9982 * facilities that may send a log message 9983 */ 9984 enum fw_devlog_facility { 9985 FW_DEVLOG_FACILITY_CORE = 0x00, 9986 FW_DEVLOG_FACILITY_CF = 0x01, 9987 FW_DEVLOG_FACILITY_SCHED = 0x02, 9988 FW_DEVLOG_FACILITY_TIMER = 0x04, 9989 FW_DEVLOG_FACILITY_RES = 0x06, 9990 FW_DEVLOG_FACILITY_HW = 0x08, 9991 FW_DEVLOG_FACILITY_FLR = 0x10, 9992 FW_DEVLOG_FACILITY_DMAQ = 0x12, 9993 FW_DEVLOG_FACILITY_PHY = 0x14, 9994 FW_DEVLOG_FACILITY_MAC = 0x16, 9995 FW_DEVLOG_FACILITY_PORT = 0x18, 9996 FW_DEVLOG_FACILITY_VI = 0x1A, 9997 FW_DEVLOG_FACILITY_FILTER = 0x1C, 9998 FW_DEVLOG_FACILITY_ACL = 0x1E, 9999 FW_DEVLOG_FACILITY_TM = 0x20, 10000 FW_DEVLOG_FACILITY_QFC = 0x22, 10001 FW_DEVLOG_FACILITY_DCB = 0x24, 10002 FW_DEVLOG_FACILITY_ETH = 0x26, 10003 FW_DEVLOG_FACILITY_OFLD = 0x28, 10004 FW_DEVLOG_FACILITY_RI = 0x2A, 10005 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 10006 FW_DEVLOG_FACILITY_FCOE = 0x2E, 10007 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 10008 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 10009 FW_DEVLOG_FACILITY_CHNET = 0x34, 10010 FW_DEVLOG_FACILITY_COISCSI = 0x36, 10011 FW_DEVLOG_FACILITY_MAX = 0x38, 10012 }; 10013 10014 /* 10015 * log message format 10016 */ 10017 struct fw_devlog_e { 10018 __be64 timestamp; 10019 __be32 seqno; 10020 __be16 reserved1; 10021 __u8 level; 10022 __u8 facility; 10023 __u8 fmt[FW_DEVLOG_FMT_LEN]; 10024 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 10025 __be32 reserved3[4]; 10026 }; 10027 10028 struct fw_devlog_cmd { 10029 __be32 op_to_write; 10030 __be32 retval_len16; 10031 __u8 level; 10032 __u8 r2[7]; 10033 __be32 memtype_devlog_memaddr16_devlog; 10034 __be32 memsize_devlog; 10035 __u8 num_devlog; 10036 __u8 r3[3]; 10037 __be32 r4; 10038 }; 10039 10040 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 10041 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 10042 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 10043 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 10044 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 10045 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 10046 10047 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 10048 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 10049 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 10050 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 10051 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 10052 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 10053 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 10054 10055 enum fw_watchdog_actions { 10056 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 10057 FW_WATCHDOG_ACTION_FLR = 1, 10058 FW_WATCHDOG_ACTION_BYPASS = 2, 10059 FW_WATCHDOG_ACTION_TMPCHK = 3, 10060 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 10061 10062 FW_WATCHDOG_ACTION_MAX = 5, 10063 }; 10064 10065 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 10066 10067 struct fw_watchdog_cmd { 10068 __be32 op_to_vfn; 10069 __be32 retval_len16; 10070 __be32 timeout; 10071 __be32 action; 10072 }; 10073 10074 #define S_FW_WATCHDOG_CMD_PFN 8 10075 #define M_FW_WATCHDOG_CMD_PFN 0x7 10076 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 10077 #define G_FW_WATCHDOG_CMD_PFN(x) \ 10078 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 10079 10080 #define S_FW_WATCHDOG_CMD_VFN 0 10081 #define M_FW_WATCHDOG_CMD_VFN 0xff 10082 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 10083 #define G_FW_WATCHDOG_CMD_VFN(x) \ 10084 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 10085 10086 struct fw_clip_cmd { 10087 __be32 op_to_write; 10088 __be32 alloc_to_len16; 10089 __be64 ip_hi; 10090 __be64 ip_lo; 10091 __be32 r4[2]; 10092 }; 10093 10094 #define S_FW_CLIP_CMD_ALLOC 31 10095 #define M_FW_CLIP_CMD_ALLOC 0x1 10096 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 10097 #define G_FW_CLIP_CMD_ALLOC(x) \ 10098 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 10099 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 10100 10101 #define S_FW_CLIP_CMD_FREE 30 10102 #define M_FW_CLIP_CMD_FREE 0x1 10103 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 10104 #define G_FW_CLIP_CMD_FREE(x) \ 10105 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 10106 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 10107 10108 #define S_FW_CLIP_CMD_INDEX 16 10109 #define M_FW_CLIP_CMD_INDEX 0x1fff 10110 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 10111 #define G_FW_CLIP_CMD_INDEX(x) \ 10112 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 10113 10114 struct fw_clip2_cmd { 10115 __be32 op_to_write; 10116 __be32 alloc_to_len16; 10117 __be64 ip_hi; 10118 __be64 ip_lo; 10119 __be64 ipm_hi; 10120 __be64 ipm_lo; 10121 __be32 r4[2]; 10122 }; 10123 10124 /****************************************************************************** 10125 * F O i S C S I C O M M A N D s 10126 **************************************/ 10127 10128 #define FW_CHNET_IFACE_ADDR_MAX 3 10129 10130 enum fw_chnet_iface_cmd_subop { 10131 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 10132 10133 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 10134 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 10135 10136 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 10137 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 10138 10139 FW_CHNET_IFACE_CMD_SUBOP_MAX, 10140 }; 10141 10142 struct fw_chnet_iface_cmd { 10143 __be32 op_to_portid; 10144 __be32 retval_len16; 10145 __u8 subop; 10146 __u8 r2[2]; 10147 __u8 flags; 10148 __be32 ifid_ifstate; 10149 __be16 mtu; 10150 __be16 vlanid; 10151 __be32 r3; 10152 __be16 r4; 10153 __u8 mac[6]; 10154 }; 10155 10156 #define S_FW_CHNET_IFACE_CMD_PORTID 0 10157 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 10158 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 10159 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 10160 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 10161 10162 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16 10163 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff 10164 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 10165 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID) 10166 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 10167 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID) 10168 10169 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0 10170 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1 10171 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 10172 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F) 10173 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 10174 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \ 10175 M_FW_CHNET_IFACE_CMD_RSS_IQID_F) 10176 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U) 10177 10178 #define S_FW_CHNET_IFACE_CMD_IFID 8 10179 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 10180 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 10181 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 10182 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 10183 10184 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 10185 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 10186 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 10187 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 10188 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 10189 10190 struct fw_fcoe_res_info_cmd { 10191 __be32 op_to_read; 10192 __be32 retval_len16; 10193 __be16 e_d_tov; 10194 __be16 r_a_tov_seq; 10195 __be16 r_a_tov_els; 10196 __be16 r_r_tov; 10197 __be32 max_xchgs; 10198 __be32 max_ssns; 10199 __be32 used_xchgs; 10200 __be32 used_ssns; 10201 __be32 max_fcfs; 10202 __be32 max_vnps; 10203 __be32 used_fcfs; 10204 __be32 used_vnps; 10205 }; 10206 10207 struct fw_fcoe_link_cmd { 10208 __be32 op_to_portid; 10209 __be32 retval_len16; 10210 __be32 sub_opcode_fcfi; 10211 __u8 r3; 10212 __u8 lstatus; 10213 __be16 flags; 10214 __u8 r4; 10215 __u8 set_vlan; 10216 __be16 vlan_id; 10217 __be32 vnpi_pkd; 10218 __be16 r6; 10219 __u8 phy_mac[6]; 10220 __u8 vnport_wwnn[8]; 10221 __u8 vnport_wwpn[8]; 10222 }; 10223 10224 #define S_FW_FCOE_LINK_CMD_PORTID 0 10225 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 10226 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 10227 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 10228 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 10229 10230 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 10231 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 10232 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 10233 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 10234 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 10235 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 10236 10237 #define S_FW_FCOE_LINK_CMD_FCFI 0 10238 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 10239 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 10240 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 10241 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 10242 10243 #define S_FW_FCOE_LINK_CMD_VNPI 0 10244 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 10245 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 10246 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 10247 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 10248 10249 struct fw_fcoe_vnp_cmd { 10250 __be32 op_to_fcfi; 10251 __be32 alloc_to_len16; 10252 __be32 gen_wwn_to_vnpi; 10253 __be32 vf_id; 10254 __be16 iqid; 10255 __u8 vnport_mac[6]; 10256 __u8 vnport_wwnn[8]; 10257 __u8 vnport_wwpn[8]; 10258 __u8 cmn_srv_parms[16]; 10259 __u8 clsp_word_0_1[8]; 10260 }; 10261 10262 #define S_FW_FCOE_VNP_CMD_FCFI 0 10263 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 10264 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 10265 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 10266 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 10267 10268 #define S_FW_FCOE_VNP_CMD_ALLOC 31 10269 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 10270 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 10271 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 10272 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 10273 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 10274 10275 #define S_FW_FCOE_VNP_CMD_FREE 30 10276 #define M_FW_FCOE_VNP_CMD_FREE 0x1 10277 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 10278 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 10279 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 10280 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 10281 10282 #define S_FW_FCOE_VNP_CMD_MODIFY 29 10283 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 10284 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 10285 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 10286 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 10287 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 10288 10289 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 10290 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 10291 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 10292 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 10293 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 10294 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 10295 10296 #define S_FW_FCOE_VNP_CMD_PERSIST 21 10297 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 10298 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 10299 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 10300 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 10301 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 10302 10303 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 10304 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 10305 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 10306 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 10307 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 10308 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 10309 10310 #define S_FW_FCOE_VNP_CMD_VNPI 0 10311 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 10312 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 10313 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 10314 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 10315 10316 struct fw_fcoe_sparams_cmd { 10317 __be32 op_to_portid; 10318 __be32 retval_len16; 10319 __u8 r3[7]; 10320 __u8 cos; 10321 __u8 lport_wwnn[8]; 10322 __u8 lport_wwpn[8]; 10323 __u8 cmn_srv_parms[16]; 10324 __u8 cls_srv_parms[16]; 10325 }; 10326 10327 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 10328 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 10329 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 10330 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 10331 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 10332 10333 struct fw_fcoe_stats_cmd { 10334 __be32 op_to_flowid; 10335 __be32 free_to_len16; 10336 union fw_fcoe_stats { 10337 struct fw_fcoe_stats_ctl { 10338 __u8 nstats_port; 10339 __u8 port_valid_ix; 10340 __be16 r6; 10341 __be32 r7; 10342 __be64 stat0; 10343 __be64 stat1; 10344 __be64 stat2; 10345 __be64 stat3; 10346 __be64 stat4; 10347 __be64 stat5; 10348 } ctl; 10349 struct fw_fcoe_port_stats { 10350 __be64 tx_bcast_bytes; 10351 __be64 tx_bcast_frames; 10352 __be64 tx_mcast_bytes; 10353 __be64 tx_mcast_frames; 10354 __be64 tx_ucast_bytes; 10355 __be64 tx_ucast_frames; 10356 __be64 tx_drop_frames; 10357 __be64 tx_offload_bytes; 10358 __be64 tx_offload_frames; 10359 __be64 rx_bcast_bytes; 10360 __be64 rx_bcast_frames; 10361 __be64 rx_mcast_bytes; 10362 __be64 rx_mcast_frames; 10363 __be64 rx_ucast_bytes; 10364 __be64 rx_ucast_frames; 10365 __be64 rx_err_frames; 10366 } port_stats; 10367 struct fw_fcoe_fcf_stats { 10368 __be32 fip_tx_bytes; 10369 __be32 fip_tx_fr; 10370 __be64 fcf_ka; 10371 __be64 mcast_adv_rcvd; 10372 __be16 ucast_adv_rcvd; 10373 __be16 sol_sent; 10374 __be16 vlan_req; 10375 __be16 vlan_rpl; 10376 __be16 clr_vlink; 10377 __be16 link_down; 10378 __be16 link_up; 10379 __be16 logo; 10380 __be16 flogi_req; 10381 __be16 flogi_rpl; 10382 __be16 fdisc_req; 10383 __be16 fdisc_rpl; 10384 __be16 fka_prd_chg; 10385 __be16 fc_map_chg; 10386 __be16 vfid_chg; 10387 __u8 no_fka_req; 10388 __u8 no_vnp; 10389 } fcf_stats; 10390 struct fw_fcoe_pcb_stats { 10391 __be64 tx_bytes; 10392 __be64 tx_frames; 10393 __be64 rx_bytes; 10394 __be64 rx_frames; 10395 __be32 vnp_ka; 10396 __be32 unsol_els_rcvd; 10397 __be64 unsol_cmd_rcvd; 10398 __be16 implicit_logo; 10399 __be16 flogi_inv_sparm; 10400 __be16 fdisc_inv_sparm; 10401 __be16 flogi_rjt; 10402 __be16 fdisc_rjt; 10403 __be16 no_ssn; 10404 __be16 mac_flt_fail; 10405 __be16 inv_fr_rcvd; 10406 } pcb_stats; 10407 struct fw_fcoe_scb_stats { 10408 __be64 tx_bytes; 10409 __be64 tx_frames; 10410 __be64 rx_bytes; 10411 __be64 rx_frames; 10412 __be32 host_abrt_req; 10413 __be32 adap_auto_abrt; 10414 __be32 adap_abrt_rsp; 10415 __be32 host_ios_req; 10416 __be16 ssn_offl_ios; 10417 __be16 ssn_not_rdy_ios; 10418 __u8 rx_data_ddp_err; 10419 __u8 ddp_flt_set_err; 10420 __be16 rx_data_fr_err; 10421 __u8 bad_st_abrt_req; 10422 __u8 no_io_abrt_req; 10423 __u8 abort_tmo; 10424 __u8 abort_tmo_2; 10425 __be32 abort_req; 10426 __u8 no_ppod_res_tmo; 10427 __u8 bp_tmo; 10428 __u8 adap_auto_cls; 10429 __u8 no_io_cls_req; 10430 __be32 host_cls_req; 10431 __be64 unsol_cmd_rcvd; 10432 __be32 plogi_req_rcvd; 10433 __be32 prli_req_rcvd; 10434 __be16 logo_req_rcvd; 10435 __be16 prlo_req_rcvd; 10436 __be16 plogi_rjt_rcvd; 10437 __be16 prli_rjt_rcvd; 10438 __be32 adisc_req_rcvd; 10439 __be32 rscn_rcvd; 10440 __be32 rrq_req_rcvd; 10441 __be32 unsol_els_rcvd; 10442 __u8 adisc_rjt_rcvd; 10443 __u8 scr_rjt; 10444 __u8 ct_rjt; 10445 __u8 inval_bls_rcvd; 10446 __be32 ba_rjt_rcvd; 10447 } scb_stats; 10448 } u; 10449 }; 10450 10451 #define S_FW_FCOE_STATS_CMD_FLOWID 0 10452 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 10453 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 10454 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 10455 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 10456 10457 #define S_FW_FCOE_STATS_CMD_FREE 30 10458 #define M_FW_FCOE_STATS_CMD_FREE 0x1 10459 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 10460 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 10461 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 10462 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 10463 10464 #define S_FW_FCOE_STATS_CMD_NSTATS 4 10465 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 10466 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 10467 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 10468 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 10469 10470 #define S_FW_FCOE_STATS_CMD_PORT 0 10471 #define M_FW_FCOE_STATS_CMD_PORT 0x3 10472 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 10473 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 10474 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 10475 10476 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 10477 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 10478 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 10479 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 10480 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 10481 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 10482 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 10483 10484 #define S_FW_FCOE_STATS_CMD_IX 0 10485 #define M_FW_FCOE_STATS_CMD_IX 0x3f 10486 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 10487 #define G_FW_FCOE_STATS_CMD_IX(x) \ 10488 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 10489 10490 struct fw_fcoe_fcf_cmd { 10491 __be32 op_to_fcfi; 10492 __be32 retval_len16; 10493 __be16 priority_pkd; 10494 __u8 mac[6]; 10495 __u8 name_id[8]; 10496 __u8 fabric[8]; 10497 __be16 vf_id; 10498 __be16 max_fcoe_size; 10499 __u8 vlan_id; 10500 __u8 fc_map[3]; 10501 __be32 fka_adv; 10502 __be32 r6; 10503 __u8 r7_hi; 10504 __u8 fpma_to_portid; 10505 __u8 spma_mac[6]; 10506 __be64 r8; 10507 }; 10508 10509 #define S_FW_FCOE_FCF_CMD_FCFI 0 10510 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 10511 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 10512 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 10513 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 10514 10515 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 10516 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 10517 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 10518 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 10519 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 10520 10521 #define S_FW_FCOE_FCF_CMD_FPMA 6 10522 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 10523 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 10524 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 10525 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 10526 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 10527 10528 #define S_FW_FCOE_FCF_CMD_SPMA 5 10529 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 10530 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 10531 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 10532 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 10533 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 10534 10535 #define S_FW_FCOE_FCF_CMD_LOGIN 4 10536 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 10537 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 10538 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 10539 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 10540 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 10541 10542 #define S_FW_FCOE_FCF_CMD_PORTID 0 10543 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 10544 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 10545 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 10546 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 10547 10548 /****************************************************************************** 10549 * E R R O R a n d D E B U G C O M M A N D s 10550 ******************************************************/ 10551 10552 enum fw_error_type { 10553 FW_ERROR_TYPE_EXCEPTION = 0x0, 10554 FW_ERROR_TYPE_HWMODULE = 0x1, 10555 FW_ERROR_TYPE_WR = 0x2, 10556 FW_ERROR_TYPE_ACL = 0x3, 10557 }; 10558 10559 enum fw_dcb_ieee_locations { 10560 FW_IEEE_LOC_LOCAL, 10561 FW_IEEE_LOC_PEER, 10562 FW_IEEE_LOC_OPERATIONAL, 10563 }; 10564 10565 struct fw_dcb_ieee_cmd { 10566 __be32 op_to_location; 10567 __be32 changed_to_len16; 10568 union fw_dcbx_stats { 10569 struct fw_dcbx_pfc_stats_ieee { 10570 __be32 pfc_mbc_pkd; 10571 __be32 pfc_willing_to_pfc_en; 10572 } dcbx_pfc_stats; 10573 struct fw_dcbx_ets_stats_ieee { 10574 __be32 cbs_to_ets_max_tc; 10575 __be32 pg_table; 10576 __u8 pg_percent[8]; 10577 __u8 tsa[8]; 10578 } dcbx_ets_stats; 10579 struct fw_dcbx_app_stats_ieee { 10580 __be32 num_apps_pkd; 10581 __be32 r6; 10582 __be32 app[4]; 10583 } dcbx_app_stats; 10584 struct fw_dcbx_control { 10585 __be32 multi_peer_invalidated; 10586 __u8 version; 10587 __u8 r6[3]; 10588 } dcbx_control; 10589 } u; 10590 }; 10591 10592 #define S_FW_DCB_IEEE_CMD_PORT 8 10593 #define M_FW_DCB_IEEE_CMD_PORT 0x7 10594 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 10595 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 10596 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 10597 10598 #define S_FW_DCB_IEEE_CMD_FEATURE 2 10599 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 10600 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 10601 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 10602 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 10603 10604 #define S_FW_DCB_IEEE_CMD_LOCATION 0 10605 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 10606 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 10607 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 10608 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 10609 10610 #define S_FW_DCB_IEEE_CMD_CHANGED 20 10611 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 10612 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 10613 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 10614 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 10615 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 10616 10617 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 10618 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 10619 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 10620 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 10621 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 10622 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 10623 10624 #define S_FW_DCB_IEEE_CMD_APPLY 18 10625 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 10626 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 10627 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 10628 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 10629 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 10630 10631 #define S_FW_DCB_IEEE_CMD_DISABLED 17 10632 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 10633 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 10634 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 10635 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 10636 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 10637 10638 #define S_FW_DCB_IEEE_CMD_MORE 16 10639 #define M_FW_DCB_IEEE_CMD_MORE 0x1 10640 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 10641 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 10642 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 10643 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 10644 10645 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 10646 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 10647 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 10648 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 10649 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 10650 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 10651 10652 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 10653 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 10654 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 10655 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 10656 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 10657 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 10658 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 10659 10660 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 10661 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 10662 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 10663 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 10664 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 10665 10666 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 10667 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 10668 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 10669 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 10670 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 10671 10672 #define S_FW_DCB_IEEE_CMD_CBS 16 10673 #define M_FW_DCB_IEEE_CMD_CBS 0x1 10674 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 10675 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 10676 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 10677 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 10678 10679 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 10680 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 10681 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 10682 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 10683 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 10684 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 10685 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 10686 10687 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 10688 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 10689 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 10690 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 10691 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 10692 10693 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 10694 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 10695 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 10696 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 10697 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 10698 10699 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 10700 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 10701 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 10702 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 10703 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 10704 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 10705 10706 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 10707 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 10708 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 10709 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 10710 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 10711 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 10712 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 10713 10714 /* Hand-written */ 10715 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 10716 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 10717 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 10718 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 10719 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 10720 10721 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 10722 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 10723 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 10724 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 10725 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 10726 10727 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 10728 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 10729 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 10730 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 10731 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 10732 10733 10734 struct fw_error_cmd { 10735 __be32 op_to_type; 10736 __be32 len16_pkd; 10737 union fw_error { 10738 struct fw_error_exception { 10739 __be32 info[6]; 10740 } exception; 10741 struct fw_error_hwmodule { 10742 __be32 regaddr; 10743 __be32 regval; 10744 } hwmodule; 10745 struct fw_error_wr { 10746 __be16 cidx; 10747 __be16 pfn_vfn; 10748 __be32 eqid; 10749 __u8 wrhdr[16]; 10750 } wr; 10751 struct fw_error_acl { 10752 __be16 cidx; 10753 __be16 pfn_vfn; 10754 __be32 eqid; 10755 __be16 mv_pkd; 10756 __u8 val[6]; 10757 __be64 r4; 10758 } acl; 10759 } u; 10760 }; 10761 10762 #define S_FW_ERROR_CMD_FATAL 4 10763 #define M_FW_ERROR_CMD_FATAL 0x1 10764 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 10765 #define G_FW_ERROR_CMD_FATAL(x) \ 10766 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 10767 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 10768 10769 #define S_FW_ERROR_CMD_TYPE 0 10770 #define M_FW_ERROR_CMD_TYPE 0xf 10771 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 10772 #define G_FW_ERROR_CMD_TYPE(x) \ 10773 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 10774 10775 #define S_FW_ERROR_CMD_PFN 8 10776 #define M_FW_ERROR_CMD_PFN 0x7 10777 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 10778 #define G_FW_ERROR_CMD_PFN(x) \ 10779 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 10780 10781 #define S_FW_ERROR_CMD_VFN 0 10782 #define M_FW_ERROR_CMD_VFN 0xff 10783 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 10784 #define G_FW_ERROR_CMD_VFN(x) \ 10785 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 10786 10787 #define S_FW_ERROR_CMD_PFN 8 10788 #define M_FW_ERROR_CMD_PFN 0x7 10789 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 10790 #define G_FW_ERROR_CMD_PFN(x) \ 10791 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 10792 10793 #define S_FW_ERROR_CMD_VFN 0 10794 #define M_FW_ERROR_CMD_VFN 0xff 10795 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 10796 #define G_FW_ERROR_CMD_VFN(x) \ 10797 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 10798 10799 #define S_FW_ERROR_CMD_MV 15 10800 #define M_FW_ERROR_CMD_MV 0x1 10801 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 10802 #define G_FW_ERROR_CMD_MV(x) \ 10803 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 10804 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 10805 10806 struct fw_debug_cmd { 10807 __be32 op_type; 10808 __be32 len16_pkd; 10809 union fw_debug { 10810 struct fw_debug_assert { 10811 __be32 fcid; 10812 __be32 line; 10813 __be32 x; 10814 __be32 y; 10815 __u8 filename_0_7[8]; 10816 __u8 filename_8_15[8]; 10817 __be64 r3; 10818 } assert; 10819 struct fw_debug_prt { 10820 __be16 dprtstridx; 10821 __be16 r3[3]; 10822 __be32 dprtstrparam0; 10823 __be32 dprtstrparam1; 10824 __be32 dprtstrparam2; 10825 __be32 dprtstrparam3; 10826 } prt; 10827 } u; 10828 }; 10829 10830 #define S_FW_DEBUG_CMD_TYPE 0 10831 #define M_FW_DEBUG_CMD_TYPE 0xff 10832 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 10833 #define G_FW_DEBUG_CMD_TYPE(x) \ 10834 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 10835 10836 enum fw_diag_cmd_type { 10837 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 10838 FW_DIAG_CMD_TYPE_MEM_TEST_DIAG, 10839 }; 10840 10841 enum fw_diag_cmd_ofldiag_op { 10842 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 10843 FW_DIAG_CMD_OFLDIAG_TEST_START, 10844 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 10845 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 10846 }; 10847 10848 enum fw_diag_cmd_ofldiag_status { 10849 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 10850 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 10851 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 10852 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 10853 }; 10854 10855 enum fw_diag_cmd_memdiag_op { 10856 FW_DIAG_CMD_MEMDIAG_TEST_START=1, 10857 FW_DIAG_CMD_MEMDIAG_TEST_STOP, 10858 FW_DIAG_CMD_MEMDIAG_TEST_STATUS, 10859 FW_DIAG_CMD_MEMDIAG_TEST_INIT, 10860 }; 10861 10862 10863 enum fw_diag_cmd_memdiag_status { 10864 FW_DIAG_CMD_MEMDIAG_STATUS_NONE, 10865 FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING, 10866 FW_DIAG_CMD_MEMDIAG_STATUS_FAILED, 10867 FW_DIAG_CMD_MEMDIAG_STATUS_PASSED 10868 }; 10869 10870 10871 struct fw_diag_cmd { 10872 __be32 op_type; 10873 __be32 len16_pkd; 10874 union fw_diag_test { 10875 struct fw_diag_test_ofldiag { 10876 __u8 test_op; 10877 __u8 r3; 10878 __be16 test_status; 10879 __be32 duration; 10880 } ofldiag; 10881 struct fw_diag_test_memtest_diag { 10882 __u8 test_op; 10883 __u8 test_status; 10884 __be16 size; /* in KB */ 10885 __be32 duration; /* in seconds */ 10886 } memdiag; 10887 } u; 10888 }; 10889 10890 #define S_FW_DIAG_CMD_OPCODE 24 10891 #define M_FW_DIAG_CMD_OPCODE 0xff 10892 #define V_FW_DIAG_CMD_OPCODE(x) ((x) << S_FW_DIAG_CMD_OPCODE) 10893 #define G_FW_DIAG_CMD_OPCODE(x) \ 10894 (((x) >> S_FW_DIAG_CMD_OPCODE) & M_FW_DIAG_CMD_OPCODE) 10895 10896 #define S_FW_DIAG_CMD_TYPE 0 10897 #define M_FW_DIAG_CMD_TYPE 0xff 10898 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 10899 #define G_FW_DIAG_CMD_TYPE(x) \ 10900 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 10901 10902 #define S_FW_DIAG_CMD_LEN16 0 10903 #define M_FW_DIAG_CMD_LEN16 0xff 10904 #define V_FW_DIAG_CMD_LEN16(x) ((x) << S_FW_DIAG_CMD_LEN16) 10905 #define G_FW_DIAG_CMD_LEN16(x) \ 10906 (((x) >> S_FW_DIAG_CMD_LEN16) & M_FW_DIAG_CMD_LEN16) 10907 10908 struct fw_hma_cmd { 10909 __be32 op_pkd; 10910 __be32 retval_len16; 10911 __be32 mode_to_pcie_params; 10912 __be32 naddr_size; 10913 __be32 addr_size_pkd; 10914 __be32 r6; 10915 __be64 phy_address[5]; 10916 }; 10917 10918 #define S_FW_HMA_CMD_MODE 31 10919 #define M_FW_HMA_CMD_MODE 0x1 10920 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 10921 #define G_FW_HMA_CMD_MODE(x) \ 10922 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 10923 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 10924 10925 #define S_FW_HMA_CMD_SOC 30 10926 #define M_FW_HMA_CMD_SOC 0x1 10927 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 10928 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 10929 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 10930 10931 #define S_FW_HMA_CMD_EOC 29 10932 #define M_FW_HMA_CMD_EOC 0x1 10933 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 10934 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 10935 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 10936 10937 #define S_FW_HMA_CMD_PCIE_PARAMS 0 10938 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 10939 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 10940 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 10941 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 10942 10943 #define S_FW_HMA_CMD_NADDR 12 10944 #define M_FW_HMA_CMD_NADDR 0x3f 10945 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 10946 #define G_FW_HMA_CMD_NADDR(x) \ 10947 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 10948 10949 #define S_FW_HMA_CMD_SIZE 0 10950 #define M_FW_HMA_CMD_SIZE 0xfff 10951 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 10952 #define G_FW_HMA_CMD_SIZE(x) \ 10953 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 10954 10955 #define S_FW_HMA_CMD_ADDR_SIZE 11 10956 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 10957 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 10958 #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 10959 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 10960 10961 struct fw_jbof_win_reg_cmd { 10962 __be32 op_pkd; 10963 __be32 alloc_to_len16; 10964 __be32 window_num_pcie_params; 10965 __be32 window_size; 10966 __be64 bus_addr; 10967 __be64 phy_address; 10968 }; 10969 10970 #define S_FW_JBOF_WIN_REG_CMD_ALLOC 31 10971 #define M_FW_JBOF_WIN_REG_CMD_ALLOC 0x1 10972 #define V_FW_JBOF_WIN_REG_CMD_ALLOC(x) ((x) << S_FW_JBOF_WIN_REG_CMD_ALLOC) 10973 #define G_FW_JBOF_WIN_REG_CMD_ALLOC(x) \ 10974 (((x) >> S_FW_JBOF_WIN_REG_CMD_ALLOC) & M_FW_JBOF_WIN_REG_CMD_ALLOC) 10975 #define F_FW_JBOF_WIN_REG_CMD_ALLOC V_FW_JBOF_WIN_REG_CMD_ALLOC(1U) 10976 10977 #define S_FW_JBOF_WIN_REG_CMD_FREE 30 10978 #define M_FW_JBOF_WIN_REG_CMD_FREE 0x1 10979 #define V_FW_JBOF_WIN_REG_CMD_FREE(x) ((x) << S_FW_JBOF_WIN_REG_CMD_FREE) 10980 #define G_FW_JBOF_WIN_REG_CMD_FREE(x) \ 10981 (((x) >> S_FW_JBOF_WIN_REG_CMD_FREE) & M_FW_JBOF_WIN_REG_CMD_FREE) 10982 #define F_FW_JBOF_WIN_REG_CMD_FREE V_FW_JBOF_WIN_REG_CMD_FREE(1U) 10983 10984 #define S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM 7 10985 #define M_FW_JBOF_WIN_REG_CMD_WINDOW_NUM 0xf 10986 #define V_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x) \ 10987 ((x) << S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) 10988 #define G_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x) \ 10989 (((x) >> S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) & \ 10990 M_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) 10991 10992 #define S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS 0 10993 #define M_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS 0x7f 10994 #define V_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x) \ 10995 ((x) << S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) 10996 #define G_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x) \ 10997 (((x) >> S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) & \ 10998 M_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) 10999 11000 /****************************************************************************** 11001 * P C I E F W R E G I S T E R 11002 **************************************/ 11003 11004 enum pcie_fw_eval { 11005 PCIE_FW_EVAL_CRASH = 0, 11006 PCIE_FW_EVAL_PREP = 1, 11007 PCIE_FW_EVAL_CONF = 2, 11008 PCIE_FW_EVAL_INIT = 3, 11009 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 11010 PCIE_FW_EVAL_OVERHEAT = 5, 11011 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 11012 }; 11013 11014 /** 11015 * Register definitions for the PCIE_FW register which the firmware uses 11016 * to retain status across RESETs. This register should be considered 11017 * as a READ-ONLY register for Host Software and only to be used to 11018 * track firmware initialization/error state, etc. 11019 */ 11020 #define S_PCIE_FW_ERR 31 11021 #define M_PCIE_FW_ERR 0x1 11022 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 11023 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 11024 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 11025 11026 #define S_PCIE_FW_INIT 30 11027 #define M_PCIE_FW_INIT 0x1 11028 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 11029 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 11030 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 11031 11032 #define S_PCIE_FW_HALT 29 11033 #define M_PCIE_FW_HALT 0x1 11034 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 11035 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 11036 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 11037 11038 #define S_PCIE_FW_EVAL 24 11039 #define M_PCIE_FW_EVAL 0x7 11040 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 11041 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 11042 11043 #define S_PCIE_FW_STAGE 21 11044 #define M_PCIE_FW_STAGE 0x7 11045 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 11046 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 11047 11048 #define S_PCIE_FW_ASYNCNOT_VLD 20 11049 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 11050 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 11051 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 11052 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 11053 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 11054 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 11055 11056 #define S_PCIE_FW_ASYNCNOTINT 19 11057 #define M_PCIE_FW_ASYNCNOTINT 0x1 11058 #define V_PCIE_FW_ASYNCNOTINT(x) \ 11059 ((x) << S_PCIE_FW_ASYNCNOTINT) 11060 #define G_PCIE_FW_ASYNCNOTINT(x) \ 11061 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 11062 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 11063 11064 #define S_PCIE_FW_ASYNCNOT 16 11065 #define M_PCIE_FW_ASYNCNOT 0x7 11066 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 11067 #define G_PCIE_FW_ASYNCNOT(x) \ 11068 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 11069 11070 #define S_PCIE_FW_MASTER_VLD 15 11071 #define M_PCIE_FW_MASTER_VLD 0x1 11072 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 11073 #define G_PCIE_FW_MASTER_VLD(x) \ 11074 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 11075 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 11076 11077 #define S_PCIE_FW_MASTER 12 11078 #define M_PCIE_FW_MASTER 0x7 11079 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 11080 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 11081 11082 #define S_PCIE_FW_RESET_VLD 11 11083 #define M_PCIE_FW_RESET_VLD 0x1 11084 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 11085 #define G_PCIE_FW_RESET_VLD(x) \ 11086 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 11087 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 11088 11089 #define S_PCIE_FW_RESET 8 11090 #define M_PCIE_FW_RESET 0x7 11091 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 11092 #define G_PCIE_FW_RESET(x) \ 11093 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 11094 11095 #define S_PCIE_FW_REGISTERED 0 11096 #define M_PCIE_FW_REGISTERED 0xff 11097 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 11098 #define G_PCIE_FW_REGISTERED(x) \ 11099 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 11100 11101 11102 /****************************************************************************** 11103 * P C I E F W P F 0 R E G I S T E R 11104 **********************************************/ 11105 11106 /* 11107 * this register is available as 32-bit of persistent storage (across 11108 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 11109 * will not write it) 11110 */ 11111 11112 11113 /****************************************************************************** 11114 * P C I E F W P F 7 R E G I S T E R 11115 **********************************************/ 11116 11117 /* 11118 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 11119 * access the "devlog" which needing to contact firmware. The encoding is 11120 * mostly the same as that returned by the DEVLOG command except for the size 11121 * which is encoded as the number of entries in multiples-1 of 128 here rather 11122 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 11123 * and 15 means 2048. This of course in turn constrains the allowed values 11124 * for the devlog size ... 11125 */ 11126 #define PCIE_FW_PF_DEVLOG 7 11127 11128 #define S_PCIE_FW_PF_DEVLOG_COUNT_MSB 31 11129 #define M_PCIE_FW_PF_DEVLOG_COUNT_MSB 0x1 11130 #define V_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \ 11131 ((x) << S_PCIE_FW_PF_DEVLOG_COUNT_MSB) 11132 #define G_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \ 11133 (((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_MSB) & M_PCIE_FW_PF_DEVLOG_COUNT_MSB) 11134 11135 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 11136 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0x7 11137 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 11138 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 11139 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 11140 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 11141 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 11142 11143 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 11144 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 11145 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 11146 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 11147 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 11148 11149 #define S_PCIE_FW_PF_DEVLOG_COUNT_LSB 3 11150 #define M_PCIE_FW_PF_DEVLOG_COUNT_LSB 0x1 11151 #define V_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \ 11152 ((x) << S_PCIE_FW_PF_DEVLOG_COUNT_LSB) 11153 #define G_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \ 11154 (((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_LSB) & M_PCIE_FW_PF_DEVLOG_COUNT_LSB) 11155 11156 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 11157 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0x7 11158 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 11159 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 11160 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 11161 11162 11163 /****************************************************************************** 11164 * B I N A R Y H E A D E R F O R M A T 11165 **********************************************/ 11166 11167 /* 11168 * firmware binary header format 11169 */ 11170 struct fw_hdr { 11171 __u8 ver; 11172 __u8 chip; /* terminator chip family */ 11173 __be16 len512; /* bin length in units of 512-bytes */ 11174 __be32 fw_ver; /* firmware version */ 11175 __be32 tp_microcode_ver; /* tcp processor microcode version */ 11176 __u8 intfver_nic; 11177 __u8 intfver_vnic; 11178 __u8 intfver_ofld; 11179 __u8 intfver_ri; 11180 __u8 intfver_iscsipdu; 11181 __u8 intfver_iscsi; 11182 __u8 intfver_fcoepdu; 11183 __u8 intfver_fcoe; 11184 __u32 reserved2; 11185 __u32 reserved3; 11186 __be32 magic; /* runtime or bootstrap fw */ 11187 __be32 flags; 11188 __be32 reserved6[4]; 11189 __u8 reserved7[3]; 11190 __u8 dsign_len; 11191 __u8 dsign[72]; /* fw binary digital signature */ 11192 }; 11193 11194 enum fw_hdr_chip { 11195 FW_HDR_CHIP_T4, 11196 FW_HDR_CHIP_T5, 11197 FW_HDR_CHIP_T6, 11198 FW_HDR_CHIP_T7 11199 }; 11200 11201 #define S_FW_HDR_FW_VER_MAJOR 24 11202 #define M_FW_HDR_FW_VER_MAJOR 0xff 11203 #define V_FW_HDR_FW_VER_MAJOR(x) \ 11204 ((x) << S_FW_HDR_FW_VER_MAJOR) 11205 #define G_FW_HDR_FW_VER_MAJOR(x) \ 11206 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 11207 11208 #define S_FW_HDR_FW_VER_MINOR 16 11209 #define M_FW_HDR_FW_VER_MINOR 0xff 11210 #define V_FW_HDR_FW_VER_MINOR(x) \ 11211 ((x) << S_FW_HDR_FW_VER_MINOR) 11212 #define G_FW_HDR_FW_VER_MINOR(x) \ 11213 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 11214 11215 #define S_FW_HDR_FW_VER_MICRO 8 11216 #define M_FW_HDR_FW_VER_MICRO 0xff 11217 #define V_FW_HDR_FW_VER_MICRO(x) \ 11218 ((x) << S_FW_HDR_FW_VER_MICRO) 11219 #define G_FW_HDR_FW_VER_MICRO(x) \ 11220 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 11221 11222 #define S_FW_HDR_FW_VER_BUILD 0 11223 #define M_FW_HDR_FW_VER_BUILD 0xff 11224 #define V_FW_HDR_FW_VER_BUILD(x) \ 11225 ((x) << S_FW_HDR_FW_VER_BUILD) 11226 #define G_FW_HDR_FW_VER_BUILD(x) \ 11227 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 11228 11229 enum { 11230 T4FW_VERSION_MAJOR = 1, 11231 T4FW_VERSION_MINOR = 27, 11232 T4FW_VERSION_MICRO = 5, 11233 T4FW_VERSION_BUILD = 0, 11234 11235 T5FW_VERSION_MAJOR = 1, 11236 T5FW_VERSION_MINOR = 27, 11237 T5FW_VERSION_MICRO = 5, 11238 T5FW_VERSION_BUILD = 0, 11239 11240 T6FW_VERSION_MAJOR = 1, 11241 T6FW_VERSION_MINOR = 27, 11242 T6FW_VERSION_MICRO = 5, 11243 T6FW_VERSION_BUILD = 0, 11244 11245 T7FW_VERSION_MAJOR = 2, 11246 T7FW_VERSION_MINOR = 0, 11247 T7FW_VERSION_MICRO = 0, 11248 T7FW_VERSION_BUILD = 0, 11249 }; 11250 11251 enum { 11252 /* T4 11253 */ 11254 T4FW_HDR_INTFVER_NIC = 0x00, 11255 T4FW_HDR_INTFVER_VNIC = 0x00, 11256 T4FW_HDR_INTFVER_OFLD = 0x00, 11257 T4FW_HDR_INTFVER_RI = 0x00, 11258 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 11259 T4FW_HDR_INTFVER_ISCSI = 0x00, 11260 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 11261 T4FW_HDR_INTFVER_FCOE = 0x00, 11262 11263 /* T5 11264 */ 11265 T5FW_HDR_INTFVER_NIC = 0x00, 11266 T5FW_HDR_INTFVER_VNIC = 0x00, 11267 T5FW_HDR_INTFVER_OFLD = 0x00, 11268 T5FW_HDR_INTFVER_RI = 0x00, 11269 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 11270 T5FW_HDR_INTFVER_ISCSI = 0x00, 11271 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 11272 T5FW_HDR_INTFVER_FCOE = 0x00, 11273 11274 /* T6 11275 */ 11276 T6FW_HDR_INTFVER_NIC = 0x00, 11277 T6FW_HDR_INTFVER_VNIC = 0x00, 11278 T6FW_HDR_INTFVER_OFLD = 0x00, 11279 T6FW_HDR_INTFVER_RI = 0x00, 11280 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 11281 T6FW_HDR_INTFVER_ISCSI = 0x00, 11282 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 11283 T6FW_HDR_INTFVER_FCOE = 0x00, 11284 11285 /* T7 11286 */ 11287 T7FW_HDR_INTFVER_NIC = 0x00, 11288 T7FW_HDR_INTFVER_VNIC = 0x00, 11289 T7FW_HDR_INTFVER_OFLD = 0x00, 11290 T7FW_HDR_INTFVER_RI = 0x00, 11291 T7FW_HDR_INTFVER_ISCSIPDU= 0x00, 11292 T7FW_HDR_INTFVER_ISCSI = 0x00, 11293 T7FW_HDR_INTFVER_FCOEPDU= 0x00, 11294 T7FW_HDR_INTFVER_FCOE = 0x00, 11295 }; 11296 11297 #define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \ 11298 V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \ 11299 V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD)) 11300 11301 enum { 11302 FW_HDR_MAGIC_RUNTIME = 0x00000000, 11303 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 11304 }; 11305 11306 enum fw_hdr_flags { 11307 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 11308 FW_HDR_FLAGS_SIGNED_FW = 0x00000002, 11309 }; 11310 11311 /* 11312 * External PHY firmware binary header format 11313 */ 11314 struct fw_ephy_hdr { 11315 __u8 ver; 11316 __u8 reserved; 11317 __be16 len512; /* bin length in units of 512-bytes */ 11318 __be32 magic; 11319 11320 __be16 vendor_id; 11321 __be16 device_id; 11322 __be32 version; 11323 11324 __be32 reserved1[4]; 11325 }; 11326 11327 enum { 11328 FW_EPHY_HDR_MAGIC = 0x65706879, 11329 }; 11330 11331 struct fw_ifconf_dhcp_info { 11332 __be32 addr; 11333 __be32 mask; 11334 __be16 vlanid; 11335 __be16 mtu; 11336 __be32 gw; 11337 __u8 op; 11338 __u8 len; 11339 __u8 data[270]; 11340 }; 11341 11342 struct fw_ifconf_ping_info { 11343 __be16 ping_pldsize; 11344 }; 11345 11346 #endif /* _T4FW_INTERFACE_H_ */ 11347