1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28
29 #include <drm/display/drm_dp.h>
30 #include <drm/drm_connector.h>
31
32 struct drm_device;
33 struct drm_dp_aux;
34 struct drm_panel;
35
36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 int lane_count);
38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 int lane_count);
40 bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]);
41 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
42 int lane);
43 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
44 int lane);
45 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
46 int lane);
47
48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 enum drm_dp_phy dp_phy, bool uhbr);
50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
51 enum drm_dp_phy dp_phy, bool uhbr);
52
53 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
55 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
56 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
58 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
59 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
60
61 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
62 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
63 int lane_count);
64 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
65 int lane_count);
66 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
68 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
69
70 u8 drm_dp_link_rate_to_bw_code(int link_rate);
71 int drm_dp_bw_code_to_link_rate(u8 link_bw);
72
73 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
74
75 /**
76 * struct drm_dp_vsc_sdp - drm DP VSC SDP
77 *
78 * This structure represents a DP VSC SDP of drm
79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
80 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
81 *
82 * @sdp_type: secondary-data packet type
83 * @revision: revision number
84 * @length: number of valid data bytes
85 * @pixelformat: pixel encoding format
86 * @colorimetry: colorimetry format
87 * @bpc: bit per color
88 * @dynamic_range: dynamic range information
89 * @content_type: CTA-861-G defines content types and expected processing by a sink device
90 */
91 struct drm_dp_vsc_sdp {
92 unsigned char sdp_type;
93 unsigned char revision;
94 unsigned char length;
95 enum dp_pixelformat pixelformat;
96 enum dp_colorimetry colorimetry;
97 int bpc;
98 enum dp_dynamic_range dynamic_range;
99 enum dp_content_type content_type;
100 };
101
102 /**
103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
104 *
105 * This structure represents a DP AS SDP of drm
106 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and
107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
108 *
109 * @sdp_type: Secondary-data packet type
110 * @revision: Revision Number
111 * @length: Number of valid data bytes
112 * @vtotal: Minimum Vertical Vtotal
113 * @target_rr: Target Refresh
114 * @duration_incr_ms: Successive frame duration increase
115 * @duration_decr_ms: Successive frame duration decrease
116 * @target_rr_divider: Target refresh rate divider
117 * @mode: Adaptive Sync Operation Mode
118 */
119 struct drm_dp_as_sdp {
120 unsigned char sdp_type;
121 unsigned char revision;
122 unsigned char length;
123 int vtotal;
124 int target_rr;
125 int duration_incr_ms;
126 int duration_decr_ms;
127 bool target_rr_divider;
128 enum operation_mode mode;
129 };
130
131 void drm_dp_as_sdp_log(struct drm_printer *p,
132 const struct drm_dp_as_sdp *as_sdp);
133 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
134
135 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
136 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
137
138 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
139
140 static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])141 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
142 {
143 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
144 }
145
146 static inline u8
drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])147 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
148 {
149 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
150 }
151
152 static inline bool
drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])153 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
154 {
155 return dpcd[DP_DPCD_REV] >= 0x11 &&
156 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
157 }
158
159 static inline bool
drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])160 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
161 {
162 return dpcd[DP_DPCD_REV] >= 0x13 &&
163 (dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED);
164 }
165
166 static inline bool
drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])167 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
168 {
169 return dpcd[DP_DPCD_REV] >= 0x11 &&
170 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
171 }
172
173 static inline bool
drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])174 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
175 {
176 return dpcd[DP_DPCD_REV] >= 0x12 &&
177 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
178 }
179
180 static inline bool
drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])181 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
182 {
183 return dpcd[DP_DPCD_REV] >= 0x11 ||
184 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
185 }
186
187 static inline bool
drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])188 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
189 {
190 return dpcd[DP_DPCD_REV] >= 0x14 &&
191 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
192 }
193
194 static inline u8
drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])195 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
196 {
197 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
198 DP_TRAINING_PATTERN_MASK;
199 }
200
201 static inline bool
drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])202 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
203 {
204 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
205 }
206
207 /* DP/eDP DSC support */
208 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
209 u32 drm_dp_dsc_slice_count_to_mask(int slice_count);
210 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
211 bool is_edp);
212 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
213 bool is_edp);
214 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
215 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
216 u8 dsc_bpc[3]);
217 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
218 int peak_pixel_rate, bool is_rgb_yuv444);
219 int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
220 bool is_rgb_yuv444);
221 int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
222
223 static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])224 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
225 {
226 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
227 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
228 }
229
230 static inline u16
drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])231 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
232 {
233 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
234 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
235 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
236 }
237
238 static inline u32
drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])239 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
240 {
241 /* Max Slicewidth = Number of Pixels * 320 */
242 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
243 DP_DSC_SLICE_WIDTH_MULTIPLIER;
244 }
245
246 /**
247 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
248 * @dsc_dpcd : DSC-capability DPCDs of the sink
249 * @output_format: output_format which is to be checked
250 *
251 * Returns true if the sink supports DSC with the given output_format, false otherwise.
252 */
253 static inline bool
drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],u8 output_format)254 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
255 {
256 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
257 }
258
259 /* Forward Error Correction Support on DP 1.4 */
260 static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)261 drm_dp_sink_supports_fec(const u8 fec_capable)
262 {
263 return fec_capable & DP_FEC_CAPABLE;
264 }
265
266 static inline bool
drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])267 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
268 {
269 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
270 }
271
272 static inline bool
drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])273 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
274 {
275 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
276 }
277
278 static inline bool
drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])279 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
280 {
281 return dpcd[DP_EDP_CONFIGURATION_CAP] &
282 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
283 }
284
285 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
286 static inline bool
drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])287 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
288 {
289 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
290 DP_MSA_TIMING_PAR_IGNORED;
291 }
292
293 /**
294 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
295 * @edp_dpcd: The DPCD to check
296 *
297 * Note that currently this function will return %false for panels which support various DPCD
298 * backlight features but which require the brightness be set through PWM, and don't support setting
299 * the brightness level via the DPCD.
300 *
301 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
302 * otherwise
303 */
304 static inline bool
drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])305 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
306 {
307 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
308 }
309
310 /**
311 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
312 * @link_rate: link rate in 10kbits/s units
313 *
314 * Determine if the provided link rate is an UHBR rate.
315 *
316 * Returns: %True if @link_rate is an UHBR rate.
317 */
drm_dp_is_uhbr_rate(int link_rate)318 static inline bool drm_dp_is_uhbr_rate(int link_rate)
319 {
320 return link_rate >= 1000000;
321 }
322
323 /*
324 * DisplayPort AUX channel
325 */
326
327 /**
328 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
329 * @address: address of the (first) register to access
330 * @request: contains the type of transaction (see DP_AUX_* macros)
331 * @reply: upon completion, contains the reply type of the transaction
332 * @buffer: pointer to a transmission or reception buffer
333 * @size: size of @buffer
334 */
335 struct drm_dp_aux_msg {
336 unsigned int address;
337 u8 request;
338 u8 reply;
339 void *buffer;
340 size_t size;
341 };
342
343 struct cec_adapter;
344 struct drm_connector;
345 struct drm_edid;
346
347 /**
348 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
349 * @lock: mutex protecting this struct
350 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
351 * @connector: the connector this CEC adapter is associated with
352 * @unregister_work: unregister the CEC adapter
353 */
354 struct drm_dp_aux_cec {
355 struct mutex lock;
356 struct cec_adapter *adap;
357 struct drm_connector *connector;
358 struct delayed_work unregister_work;
359 };
360
361 /**
362 * struct drm_dp_aux - DisplayPort AUX channel
363 *
364 * An AUX channel can also be used to transport I2C messages to a sink. A
365 * typical application of that is to access an EDID that's present in the sink
366 * device. The @transfer() function can also be used to execute such
367 * transactions. The drm_dp_aux_register() function registers an I2C adapter
368 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
369 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
370 * transfers by default; if a partial response is received, the adapter will
371 * drop down to the size given by the partial response for this transaction
372 * only.
373 */
374 struct drm_dp_aux {
375 /**
376 * @name: user-visible name of this AUX channel and the
377 * I2C-over-AUX adapter.
378 *
379 * It's also used to specify the name of the I2C adapter. If set
380 * to %NULL, dev_name() of @dev will be used.
381 */
382 const char *name;
383
384 /**
385 * @ddc: I2C adapter that can be used for I2C-over-AUX
386 * communication
387 */
388 struct i2c_adapter ddc;
389
390 /**
391 * @dev: pointer to struct device that is the parent for this
392 * AUX channel.
393 */
394 struct device *dev;
395
396 /**
397 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
398 * Beware, this may be %NULL before drm_dp_aux_register() has been
399 * called.
400 *
401 * It should be set to the &drm_device that will be using this AUX
402 * channel as early as possible. For many graphics drivers this should
403 * happen before drm_dp_aux_init(), however it's perfectly fine to set
404 * this field later so long as it's assigned before calling
405 * drm_dp_aux_register().
406 */
407 struct drm_device *drm_dev;
408
409 /**
410 * @crtc: backpointer to the crtc that is currently using this
411 * AUX channel
412 */
413 struct drm_crtc *crtc;
414
415 /**
416 * @hw_mutex: internal mutex used for locking transfers.
417 *
418 * Note that if the underlying hardware is shared among multiple
419 * channels, the driver needs to do additional locking to
420 * prevent concurrent access.
421 */
422 struct mutex hw_mutex;
423
424 /**
425 * @crc_work: worker that captures CRCs for each frame
426 */
427 struct work_struct crc_work;
428
429 /**
430 * @crc_count: counter of captured frame CRCs
431 */
432 u8 crc_count;
433
434 /**
435 * @transfer: transfers a message representing a single AUX
436 * transaction.
437 *
438 * This is a hardware-specific implementation of how
439 * transactions are executed that the drivers must provide.
440 *
441 * A pointer to a &drm_dp_aux_msg structure describing the
442 * transaction is passed into this function. Upon success, the
443 * implementation should return the number of payload bytes that
444 * were transferred, or a negative error-code on failure.
445 *
446 * Helpers will propagate these errors, with the exception of
447 * the %-EBUSY error, which causes a transaction to be retried.
448 * On a short, helpers will return %-EPROTO to make it simpler
449 * to check for failure.
450 *
451 * The @transfer() function must only modify the reply field of
452 * the &drm_dp_aux_msg structure. The retry logic and i2c
453 * helpers assume this is the case.
454 *
455 * Also note that this callback can be called no matter the
456 * state @dev is in and also no matter what state the panel is
457 * in. It's expected:
458 *
459 * - If the @dev providing the AUX bus is currently unpowered then
460 * it will power itself up for the transfer.
461 *
462 * - If we're on eDP (using a drm_panel) and the panel is not in a
463 * state where it can respond (it's not powered or it's in a
464 * low power state) then this function may return an error, but
465 * not crash. It's up to the caller of this code to make sure that
466 * the panel is powered on if getting an error back is not OK. If a
467 * drm_panel driver is initiating a DP AUX transfer it may power
468 * itself up however it wants. All other code should ensure that
469 * the pre_enable() bridge chain (which eventually calls the
470 * drm_panel prepare function) has powered the panel.
471 */
472 ssize_t (*transfer)(struct drm_dp_aux *aux,
473 struct drm_dp_aux_msg *msg);
474
475 /**
476 * @wait_hpd_asserted: wait for HPD to be asserted
477 *
478 * This is mainly useful for eDP panels drivers to wait for an eDP
479 * panel to finish powering on. It is optional for DP AUX controllers
480 * to implement this function. It is required for DP AUX endpoints
481 * (panel drivers) to call this function after powering up but before
482 * doing AUX transfers unless the DP AUX endpoint driver knows that
483 * we're not using the AUX controller's HPD. One example of the panel
484 * driver not needing to call this is if HPD is hooked up to a GPIO
485 * that the panel driver can read directly.
486 *
487 * If a DP AUX controller does not implement this function then it
488 * may still support eDP panels that use the AUX controller's built-in
489 * HPD signal by implementing a long wait for HPD in the transfer()
490 * callback, though this is deprecated.
491 *
492 * This function will efficiently wait for the HPD signal to be
493 * asserted. The `wait_us` parameter that is passed in says that we
494 * know that the HPD signal is expected to be asserted within `wait_us`
495 * microseconds. This function could wait for longer than `wait_us` if
496 * the logic in the DP controller has a long debouncing time. The
497 * important thing is that if this function returns success that the
498 * DP controller is ready to send AUX transactions.
499 *
500 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
501 * expired and HPD wasn't asserted. This function should not print
502 * timeout errors to the log.
503 *
504 * The semantics of this function are designed to match the
505 * readx_poll_timeout() function. That means a `wait_us` of 0 means
506 * to wait forever. Like readx_poll_timeout(), this function may sleep.
507 *
508 * NOTE: this function specifically reports the state of the HPD pin
509 * that's associated with the DP AUX channel. This is different from
510 * the HPD concept in much of the rest of DRM which is more about
511 * physical presence of a display. For eDP, for instance, a display is
512 * assumed always present even if the HPD pin is deasserted.
513 */
514 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
515
516 /**
517 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
518 */
519 unsigned i2c_nack_count;
520 /**
521 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
522 */
523 unsigned i2c_defer_count;
524 /**
525 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
526 */
527 struct drm_dp_aux_cec cec;
528 /**
529 * @is_remote: Is this AUX CH actually using sideband messaging.
530 */
531 bool is_remote;
532
533 /**
534 * @powered_down: If true then the remote endpoint is powered down.
535 */
536 bool powered_down;
537
538 /**
539 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA)
540 */
541 bool no_zero_sized;
542
543 /**
544 * @dpcd_probe_disabled: If probing before a DPCD access is disabled.
545 */
546 bool dpcd_probe_disabled;
547 };
548
549 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
550 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered);
551 void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable);
552 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
553 void *buffer, size_t size);
554 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
555 void *buffer, size_t size);
556
557 /**
558 * drm_dp_dpcd_readb() - read a single byte from the DPCD
559 * @aux: DisplayPort AUX channel
560 * @offset: address of the register to read
561 * @valuep: location where the value of the register will be stored
562 *
563 * Returns the number of bytes transferred (1) on success, or a negative
564 * error code on failure. In most of the cases you should be using
565 * drm_dp_dpcd_read_byte() instead.
566 */
drm_dp_dpcd_readb(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)567 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
568 unsigned int offset, u8 *valuep)
569 {
570 return drm_dp_dpcd_read(aux, offset, valuep, 1);
571 }
572
573 /**
574 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD
575 * @aux: DisplayPort AUX channel (SST or MST)
576 * @offset: address of the (first) register to read
577 * @buffer: buffer to store the register values
578 * @size: number of bytes in @buffer
579 *
580 * Returns zero (0) on success, or a negative error
581 * code on failure. -EIO is returned if the request was NAKed by the sink or
582 * if the retry count was exceeded. If not all bytes were transferred, this
583 * function returns -EPROTO. Errors from the underlying AUX channel transfer
584 * function, with the exception of -EBUSY (which causes the transaction to
585 * be retried), are propagated to the caller.
586 */
drm_dp_dpcd_read_data(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)587 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux,
588 unsigned int offset,
589 void *buffer, size_t size)
590 {
591 int ret;
592 size_t i;
593 u8 *buf = buffer;
594
595 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
596 if (ret >= 0) {
597 if (ret < size)
598 return -EPROTO;
599 return 0;
600 }
601
602 /*
603 * Workaround for USB-C hubs/adapters with buggy firmware that fail
604 * multi-byte AUX reads but work with single-byte reads.
605 * Known affected devices:
606 * - Lenovo USB-C to VGA adapter (VIA VL817, idVendor=17ef, idProduct=7217)
607 * - Dell DA310 USB-C hub (idVendor=413c, idProduct=c010)
608 * Attempt byte-by-byte reading as a fallback.
609 */
610 for (i = 0; i < size; i++) {
611 ret = drm_dp_dpcd_readb(aux, offset + i, &buf[i]);
612 if (ret < 0)
613 return ret;
614 }
615
616 return 0;
617 }
618
619 /**
620 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD
621 * @aux: DisplayPort AUX channel (SST or MST)
622 * @offset: address of the (first) register to write
623 * @buffer: buffer containing the values to write
624 * @size: number of bytes in @buffer
625 *
626 * Returns zero (0) on success, or a negative error
627 * code on failure. -EIO is returned if the request was NAKed by the sink or
628 * if the retry count was exceeded. If not all bytes were transferred, this
629 * function returns -EPROTO. Errors from the underlying AUX channel transfer
630 * function, with the exception of -EBUSY (which causes the transaction to
631 * be retried), are propagated to the caller.
632 */
drm_dp_dpcd_write_data(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)633 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux,
634 unsigned int offset,
635 void *buffer, size_t size)
636 {
637 int ret;
638
639 ret = drm_dp_dpcd_write(aux, offset, buffer, size);
640 if (ret < 0)
641 return ret;
642 if (ret < size)
643 return -EPROTO;
644
645 return 0;
646 }
647
648 /**
649 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
650 * @aux: DisplayPort AUX channel
651 * @offset: address of the register to write
652 * @value: value to write to the register
653 *
654 * Returns the number of bytes transferred (1) on success, or a negative
655 * error code on failure. In most of the cases you should be using
656 * drm_dp_dpcd_write_byte() instead.
657 */
drm_dp_dpcd_writeb(struct drm_dp_aux * aux,unsigned int offset,u8 value)658 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
659 unsigned int offset, u8 value)
660 {
661 return drm_dp_dpcd_write(aux, offset, &value, 1);
662 }
663
664 /**
665 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD
666 * @aux: DisplayPort AUX channel
667 * @offset: address of the register to read
668 * @valuep: location where the value of the register will be stored
669 *
670 * Returns zero (0) on success, or a negative error code on failure.
671 */
drm_dp_dpcd_read_byte(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)672 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux,
673 unsigned int offset, u8 *valuep)
674 {
675 return drm_dp_dpcd_read_data(aux, offset, valuep, 1);
676 }
677
678 /**
679 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD
680 * @aux: DisplayPort AUX channel
681 * @offset: address of the register to write
682 * @value: value to write to the register
683 *
684 * Returns zero (0) on success, or a negative error code on failure.
685 */
drm_dp_dpcd_write_byte(struct drm_dp_aux * aux,unsigned int offset,u8 value)686 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux,
687 unsigned int offset, u8 value)
688 {
689 return drm_dp_dpcd_write_data(aux, offset, &value, 1);
690 }
691
692 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
693 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
694
695 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
696 u8 status[DP_LINK_STATUS_SIZE]);
697
698 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
699 enum drm_dp_phy dp_phy,
700 u8 link_status[DP_LINK_STATUS_SIZE]);
701 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision);
702 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision);
703
704 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
705 int vcpid, u8 start_time_slot, u8 time_slot_count);
706 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux);
707 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms);
708
709 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
710 u8 real_edid_checksum);
711
712 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
713 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
714 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
715 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
716 const u8 port_cap[4], u8 type);
717 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
718 const u8 port_cap[4],
719 const struct drm_edid *drm_edid);
720 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
721 const u8 port_cap[4]);
722 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
723 const u8 port_cap[4],
724 const struct drm_edid *drm_edid);
725 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
726 const u8 port_cap[4],
727 const struct drm_edid *drm_edid);
728 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
729 const u8 port_cap[4],
730 const struct drm_edid *drm_edid);
731 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
732 const u8 port_cap[4]);
733 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
734 const u8 port_cap[4]);
735 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
736 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
737 const u8 port_cap[4]);
738 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
739 void drm_dp_downstream_debug(struct seq_file *m,
740 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
741 const u8 port_cap[4],
742 const struct drm_edid *drm_edid,
743 struct drm_dp_aux *aux);
744 enum drm_mode_subconnector
745 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
746 const u8 port_cap[4]);
747 void drm_dp_set_subconnector_property(struct drm_connector *connector,
748 enum drm_connector_status status,
749 const u8 *dpcd,
750 const u8 port_cap[4]);
751
752 struct drm_dp_desc;
753 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
754 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
755 const struct drm_dp_desc *desc);
756 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
757
758 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
759 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
760 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
761 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
762 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
763 enum drm_dp_phy dp_phy,
764 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
765 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
766 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
767 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable);
768 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count);
769 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
770 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
771 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
772 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode);
773
774 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
775 void drm_dp_aux_init(struct drm_dp_aux *aux);
776 int drm_dp_aux_register(struct drm_dp_aux *aux);
777 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
778
779 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
780 int drm_dp_stop_crc(struct drm_dp_aux *aux);
781
782 struct drm_dp_dpcd_ident {
783 u8 oui[3];
784 u8 device_id[6];
785 u8 hw_rev;
786 u8 sw_major_rev;
787 u8 sw_minor_rev;
788 } __packed;
789
790 /**
791 * struct drm_dp_desc - DP branch/sink device descriptor
792 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
793 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
794 */
795 struct drm_dp_desc {
796 struct drm_dp_dpcd_ident ident;
797 u32 quirks;
798 };
799
800 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
801 bool is_branch);
802
803 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
804
805 /**
806 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
807 *
808 * Display Port sink and branch devices in the wild have a variety of bugs, try
809 * to collect them here. The quirks are shared, but it's up to the drivers to
810 * implement workarounds for them.
811 */
812 enum drm_dp_quirk {
813 /**
814 * @DP_DPCD_QUIRK_CONSTANT_N:
815 *
816 * The device requires main link attributes Mvid and Nvid to be limited
817 * to 16 bits. So will give a constant value (0x8000) for compatability.
818 */
819 DP_DPCD_QUIRK_CONSTANT_N,
820 /**
821 * @DP_DPCD_QUIRK_NO_PSR:
822 *
823 * The device does not support PSR even if reports that it supports or
824 * driver still need to implement proper handling for such device.
825 */
826 DP_DPCD_QUIRK_NO_PSR,
827 /**
828 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
829 *
830 * The device does not set SINK_COUNT to a non-zero value.
831 * The driver should ignore SINK_COUNT during detection. Note that
832 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
833 */
834 DP_DPCD_QUIRK_NO_SINK_COUNT,
835 /**
836 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
837 *
838 * The device supports MST DSC despite not supporting Virtual DPCD.
839 * The DSC caps can be read from the physical aux instead.
840 */
841 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
842 /**
843 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
844 *
845 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
846 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
847 */
848 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
849 /**
850 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
851 *
852 * The device applies HBLANK expansion for some modes, but this
853 * requires enabling DSC.
854 */
855 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
856 /**
857 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT:
858 *
859 * The device doesn't support DSC decompression at the maximum DSC
860 * pixel throughput and compressed bpp it indicates via its DPCD DSC
861 * capabilities. The compressed bpp must be limited above a device
862 * specific DSC pixel throughput.
863 */
864 DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT,
865 };
866
867 /**
868 * drm_dp_has_quirk() - does the DP device have a specific quirk
869 * @desc: Device descriptor filled by drm_dp_read_desc()
870 * @quirk: Quirk to query for
871 *
872 * Return true if DP device identified by @desc has @quirk.
873 */
874 static inline bool
drm_dp_has_quirk(const struct drm_dp_desc * desc,enum drm_dp_quirk quirk)875 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
876 {
877 return desc->quirks & BIT(quirk);
878 }
879
880 /**
881 * struct drm_edp_backlight_info - Probed eDP backlight info struct
882 * @pwmgen_bit_count: The pwmgen bit count
883 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
884 * @max: The maximum backlight level that may be set
885 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
886 * @aux_enable: Does the panel support the AUX enable cap?
887 * @aux_set: Does the panel support setting the brightness through AUX?
888 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values?
889 *
890 * This structure contains various data about an eDP backlight, which can be populated by using
891 * drm_edp_backlight_init().
892 */
893 struct drm_edp_backlight_info {
894 u8 pwmgen_bit_count;
895 u8 pwm_freq_pre_divider;
896 u32 max;
897
898 bool lsb_reg_used : 1;
899 bool aux_enable : 1;
900 bool aux_set : 1;
901 bool luminance_set : 1;
902 };
903
904 int
905 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
906 u32 max_luminance,
907 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
908 u32 *current_level, u8 *current_mode, bool need_luminance);
909 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
910 u32 level);
911 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
912 u32 level);
913 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
914
915 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
916 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
917
918 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
919
920 #else
921
drm_panel_dp_aux_backlight(struct drm_panel * panel,struct drm_dp_aux * aux)922 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
923 struct drm_dp_aux *aux)
924 {
925 return 0;
926 }
927
928 #endif
929
930 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC
931 void drm_dp_cec_irq(struct drm_dp_aux *aux);
932 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
933 struct drm_connector *connector);
934 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
935 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
936 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
937 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
938 #else
drm_dp_cec_irq(struct drm_dp_aux * aux)939 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
940 {
941 }
942
943 static inline void
drm_dp_cec_register_connector(struct drm_dp_aux * aux,struct drm_connector * connector)944 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
945 struct drm_connector *connector)
946 {
947 }
948
drm_dp_cec_unregister_connector(struct drm_dp_aux * aux)949 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
950 {
951 }
952
drm_dp_cec_attach(struct drm_dp_aux * aux,u16 source_physical_address)953 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
954 u16 source_physical_address)
955 {
956 }
957
drm_dp_cec_set_edid(struct drm_dp_aux * aux,const struct edid * edid)958 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
959 const struct edid *edid)
960 {
961 }
962
drm_dp_cec_unset_edid(struct drm_dp_aux * aux)963 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
964 {
965 }
966
967 #endif
968
969 /**
970 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
971 * @link_rate: Requested Link rate from DPCD 0x219
972 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
973 * @phy_pattern: DP Phy test pattern from DPCD 0x248
974 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
975 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
976 * @enhanced_frame_cap: flag for enhanced frame capability.
977 */
978 struct drm_dp_phy_test_params {
979 int link_rate;
980 u8 num_lanes;
981 u8 phy_pattern;
982 u8 hbr2_reset[2];
983 u8 custom80[10];
984 bool enhanced_frame_cap;
985 };
986
987 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
988 struct drm_dp_phy_test_params *data);
989 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
990 struct drm_dp_phy_test_params *data, u8 dp_rev);
991 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
992 const u8 port_cap[4]);
993 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
994 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
995 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
996 u8 frl_mode);
997 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
998 u8 frl_type);
999 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
1000 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
1001
1002 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
1003 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
1004 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
1005 struct drm_connector *connector);
1006 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1007 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1008 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1009 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1010 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
1011 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
1012 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
1013 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1014 const u8 port_cap[4], u8 color_spc);
1015 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
1016
1017 #define DRM_DP_BW_OVERHEAD_MST BIT(0)
1018 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
1019 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
1020 #define DRM_DP_BW_OVERHEAD_FEC BIT(3)
1021 #define DRM_DP_BW_OVERHEAD_DSC BIT(4)
1022
1023 int drm_dp_bw_overhead(int lane_count, int hactive,
1024 int dsc_slice_count,
1025 int bpp_x16, unsigned long flags);
1026 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
1027 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
1028
1029 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
1030 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
1031 int bpp_x16, int symbol_size, bool is_mst);
1032
1033 #endif /* _DRM_DP_HELPER_H_ */
1034