1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "cpuid.h" 26 #include "kvm_cache_regs.h" 27 28 /* 29 * Helpers to convert to/from physical addresses for pages whose address is 30 * consumed directly by hardware. Even though it's a physical address, SVM 31 * often restricts the address to the natural width, hence 'unsigned long' 32 * instead of 'hpa_t'. 33 */ 34 static inline unsigned long __sme_page_pa(struct page *page) 35 { 36 return __sme_set(page_to_pfn(page) << PAGE_SHIFT); 37 } 38 39 static inline struct page *__sme_pa_to_page(unsigned long pa) 40 { 41 return pfn_to_page(__sme_clr(pa) >> PAGE_SHIFT); 42 } 43 44 #define IOPM_SIZE PAGE_SIZE * 3 45 #define MSRPM_SIZE PAGE_SIZE * 2 46 47 extern bool npt_enabled; 48 extern int nrips; 49 extern int vgif; 50 extern bool intercept_smi; 51 extern bool vnmi; 52 extern int lbrv; 53 54 extern int tsc_aux_uret_slot __ro_after_init; 55 56 extern struct kvm_x86_ops svm_x86_ops __initdata; 57 58 /* 59 * Clean bits in VMCB. 60 * VMCB_ALL_CLEAN_MASK might also need to 61 * be updated if this enum is modified. 62 */ 63 enum { 64 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 65 pause filter count */ 66 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 67 VMCB_ASID, /* ASID */ 68 VMCB_INTR, /* int_ctl, int_vector */ 69 VMCB_NPT, /* npt_en, nCR3, gPAT */ 70 VMCB_CR, /* CR0, CR3, CR4, EFER */ 71 VMCB_DR, /* DR6, DR7 */ 72 VMCB_DT, /* GDT, IDT */ 73 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 74 VMCB_CR2, /* CR2 only */ 75 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 76 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 77 * AVIC PHYSICAL_TABLE pointer, 78 * AVIC LOGICAL_TABLE pointer 79 */ 80 VMCB_CET, /* S_CET, SSP, ISST_ADDR */ 81 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 82 }; 83 84 #define VMCB_ALL_CLEAN_MASK ( \ 85 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 86 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 87 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 88 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 89 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | (1U << VMCB_CET) | \ 90 (1U << VMCB_SW)) 91 92 /* TPR and CR2 are always written before VMRUN */ 93 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 94 95 #ifdef CONFIG_KVM_AMD_SEV 96 struct kvm_sev_info { 97 bool active; /* SEV enabled guest */ 98 bool es_active; /* SEV-ES enabled guest */ 99 bool need_init; /* waiting for SEV_INIT2 */ 100 unsigned int asid; /* ASID used for this guest */ 101 unsigned int handle; /* SEV firmware handle */ 102 int fd; /* SEV device fd */ 103 unsigned long policy; 104 unsigned long pages_locked; /* Number of pages locked */ 105 struct list_head regions_list; /* List of registered regions */ 106 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 107 u64 vmsa_features; 108 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */ 109 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 110 struct list_head mirror_vms; /* List of VMs mirroring */ 111 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 112 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 113 atomic_t migration_in_progress; 114 void *snp_context; /* SNP guest context page */ 115 void *guest_req_buf; /* Bounce buffer for SNP Guest Request input */ 116 void *guest_resp_buf; /* Bounce buffer for SNP Guest Request output */ 117 struct mutex guest_req_mutex; /* Must acquire before using bounce buffers */ 118 cpumask_var_t have_run_cpus; /* CPUs that have done VMRUN for this VM. */ 119 bool snp_certs_enabled; /* SNP certificate-fetching support. */ 120 }; 121 #endif 122 123 struct kvm_svm { 124 struct kvm kvm; 125 126 /* Struct members for AVIC */ 127 u32 avic_vm_id; 128 u32 *avic_logical_id_table; 129 u64 *avic_physical_id_table; 130 struct hlist_node hnode; 131 132 #ifdef CONFIG_KVM_AMD_SEV 133 struct kvm_sev_info sev_info; 134 #endif 135 }; 136 137 struct kvm_vcpu; 138 139 struct kvm_vmcb_info { 140 struct vmcb *ptr; 141 unsigned long pa; 142 int cpu; 143 uint64_t asid_generation; 144 }; 145 146 struct vmcb_save_area_cached { 147 struct vmcb_seg es; 148 struct vmcb_seg cs; 149 struct vmcb_seg ss; 150 struct vmcb_seg ds; 151 struct vmcb_seg gdtr; 152 struct vmcb_seg idtr; 153 u8 cpl; 154 u64 efer; 155 u64 cr4; 156 u64 cr3; 157 u64 cr0; 158 u64 dr7; 159 u64 dr6; 160 u64 rflags; 161 u64 rip; 162 u64 rsp; 163 u64 s_cet; 164 u64 ssp; 165 u64 isst_addr; 166 u64 rax; 167 u64 cr2; 168 u64 dbgctl; 169 u64 br_from; 170 u64 br_to; 171 u64 last_excp_from; 172 u64 last_excp_to; 173 }; 174 175 struct vmcb_ctrl_area_cached { 176 u32 intercepts[MAX_INTERCEPT]; 177 u16 pause_filter_thresh; 178 u16 pause_filter_count; 179 u64 iopm_base_pa; 180 u64 msrpm_base_pa; 181 u64 tsc_offset; 182 u32 asid; 183 u8 tlb_ctl; 184 u8 erap_ctl; 185 u32 int_ctl; 186 u32 int_vector; 187 u32 int_state; 188 u64 exit_code; 189 u64 exit_info_1; 190 u64 exit_info_2; 191 u32 exit_int_info; 192 u32 exit_int_info_err; 193 u64 misc_ctl; 194 u32 event_inj; 195 u32 event_inj_err; 196 u64 next_rip; 197 u64 nested_cr3; 198 u64 misc_ctl2; 199 u32 clean; 200 union { 201 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV) 202 struct hv_vmcb_enlightenments hv_enlightenments; 203 #endif 204 u8 reserved_sw[32]; 205 }; 206 }; 207 208 struct svm_nested_state { 209 struct kvm_vmcb_info vmcb02; 210 u64 hsave_msr; 211 u64 vm_cr_msr; 212 u64 vmcb12_gpa; 213 u64 last_vmcb12_gpa; 214 u64 last_bus_lock_rip; 215 216 /* 217 * The MSR permissions map used for vmcb02, which is the merge result 218 * of vmcb01 and vmcb12 219 */ 220 void *msrpm; 221 222 /* cache for control fields of the guest */ 223 struct vmcb_ctrl_area_cached ctl; 224 225 /* 226 * Note: this struct is not kept up-to-date while L2 runs; it is only 227 * valid within nested_svm_vmrun. 228 */ 229 struct vmcb_save_area_cached save; 230 231 bool initialized; 232 233 /* 234 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 235 * changes in MSR bitmap for L1 or switching to a different L2. Note, 236 * this flag can only be used reliably in conjunction with a paravirt L1 237 * which informs L0 whether any changes to MSR bitmap for L2 were done 238 * on its side. 239 */ 240 bool force_msr_bitmap_recalc; 241 }; 242 243 struct vcpu_sev_es_state { 244 /* SEV-ES support */ 245 struct sev_es_save_area *vmsa; 246 struct ghcb *ghcb; 247 u8 valid_bitmap[16]; 248 struct kvm_host_map ghcb_map; 249 bool received_first_sipi; 250 unsigned int ap_reset_hold_type; 251 252 /* SEV-ES scratch area support */ 253 u64 sw_scratch; 254 void *ghcb_sa; 255 u32 ghcb_sa_len; 256 bool ghcb_sa_sync; 257 bool ghcb_sa_free; 258 259 /* SNP Page-State-Change buffer entries currently being processed */ 260 struct { 261 u16 cur_idx; 262 u16 end_idx; 263 u16 batch_size; 264 bool is_2m; 265 } psc; 266 267 u64 ghcb_registered_gpa; 268 269 struct mutex snp_vmsa_mutex; /* Used to handle concurrent updates of VMSA. */ 270 gpa_t snp_vmsa_gpa; 271 bool snp_ap_waiting_for_reset; 272 bool snp_has_guest_vmsa; 273 }; 274 275 struct vcpu_svm { 276 struct kvm_vcpu vcpu; 277 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 278 struct vmcb *vmcb; 279 struct kvm_vmcb_info vmcb01; 280 struct kvm_vmcb_info *current_vmcb; 281 u32 asid; 282 u32 sysenter_esp_hi; 283 u32 sysenter_eip_hi; 284 uint64_t tsc_aux; 285 286 u64 msr_decfg; 287 288 u64 next_rip; 289 290 u64 spec_ctrl; 291 292 u64 tsc_ratio_msr; 293 /* 294 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 295 * translated into the appropriate L2_CFG bits on the host to 296 * perform speculative control. 297 */ 298 u64 virt_spec_ctrl; 299 300 void *msrpm; 301 302 ulong nmi_iret_rip; 303 304 struct svm_nested_state nested; 305 306 /* NMI mask value, used when vNMI is not enabled */ 307 bool nmi_masked; 308 309 /* 310 * True when NMIs are still masked but guest IRET was just intercepted 311 * and KVM is waiting for RIP to change, which will signal that the 312 * intercepted IRET was retired and thus NMI can be unmasked. 313 */ 314 bool awaiting_iret_completion; 315 316 /* 317 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 318 * soon as the IRET completes (e.g. NMI is pending injection). KVM 319 * temporarily steals RFLAGS.TF to single-step the guest in this case 320 * in order to regain control as soon as the NMI-blocking condition 321 * goes away. 322 */ 323 bool nmi_singlestep; 324 u64 nmi_singlestep_guest_rflags; 325 326 bool nmi_l1_to_l2; 327 328 unsigned long soft_int_csbase; 329 unsigned long soft_int_old_rip; 330 unsigned long soft_int_next_rip; 331 bool soft_int_injected; 332 333 u32 ldr_reg; 334 u32 dfr_reg; 335 336 /* This is essentially a shadow of the vCPU's actual entry in the 337 * Physical ID table that is programmed into the VMCB, i.e. that is 338 * seen by the CPU. If IPI virtualization is disabled, IsRunning is 339 * only ever set in the shadow, i.e. is never propagated to the "real" 340 * table, so that hardware never sees IsRunning=1. 341 */ 342 u64 avic_physical_id_entry; 343 344 /* 345 * Per-vCPU list of irqfds that are eligible to post IRQs directly to 346 * the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass). The list 347 * is used to reconfigure IRTEs when the vCPU is loaded/put (to set the 348 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass), 349 * and if the irqfd becomes ineligible for posting (to put the IRTE 350 * back into remapped mode). 351 */ 352 struct list_head ir_list; 353 raw_spinlock_t ir_list_lock; 354 355 struct vcpu_sev_es_state sev_es; 356 357 bool guest_state_loaded; 358 359 bool avic_irq_window; 360 bool x2avic_msrs_intercepted; 361 bool lbr_msrs_intercepted; 362 363 /* Guest GIF value, used when vGIF is not enabled */ 364 bool guest_gif; 365 }; 366 367 struct svm_cpu_data { 368 u64 asid_generation; 369 u32 max_asid; 370 u32 next_asid; 371 u32 min_asid; 372 373 bool bp_spec_reduce_set; 374 375 struct vmcb *save_area; 376 unsigned long save_area_pa; 377 378 /* index = sev_asid, value = vmcb pointer */ 379 struct vmcb **sev_vmcbs; 380 }; 381 382 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 383 384 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 385 { 386 return container_of(kvm, struct kvm_svm, kvm); 387 } 388 389 #ifdef CONFIG_KVM_AMD_SEV 390 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm) 391 { 392 return &to_kvm_svm(kvm)->sev_info; 393 } 394 395 static __always_inline bool ____sev_guest(struct kvm *kvm) 396 { 397 return to_kvm_sev_info(kvm)->active; 398 } 399 static __always_inline bool ____sev_es_guest(struct kvm *kvm) 400 { 401 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 402 403 return sev->es_active && !WARN_ON_ONCE(!sev->active); 404 } 405 406 static __always_inline bool ____sev_snp_guest(struct kvm *kvm) 407 { 408 struct kvm_sev_info *sev = to_kvm_sev_info(kvm); 409 410 return (sev->vmsa_features & SVM_SEV_FEAT_SNP_ACTIVE) && 411 !WARN_ON_ONCE(!____sev_es_guest(kvm)); 412 } 413 414 static __always_inline bool is_sev_guest(struct kvm_vcpu *vcpu) 415 { 416 return ____sev_guest(vcpu->kvm); 417 } 418 static __always_inline bool is_sev_es_guest(struct kvm_vcpu *vcpu) 419 { 420 return ____sev_es_guest(vcpu->kvm); 421 } 422 423 static __always_inline bool is_sev_snp_guest(struct kvm_vcpu *vcpu) 424 { 425 return ____sev_snp_guest(vcpu->kvm); 426 } 427 #else 428 static __always_inline bool is_sev_guest(struct kvm_vcpu *vcpu) 429 { 430 return false; 431 } 432 static __always_inline bool is_sev_es_guest(struct kvm_vcpu *vcpu) 433 { 434 return false; 435 } 436 437 static __always_inline bool is_sev_snp_guest(struct kvm_vcpu *vcpu) 438 { 439 return false; 440 } 441 #endif 442 443 static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val) 444 { 445 return svm->sev_es.ghcb_registered_gpa == val; 446 } 447 448 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 449 { 450 vmcb->control.clean = 0; 451 } 452 453 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 454 { 455 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 456 & ~VMCB_ALWAYS_DIRTY_MASK; 457 } 458 459 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 460 { 461 vmcb->control.clean &= ~(1 << bit); 462 } 463 464 static inline bool vmcb12_is_dirty(struct vmcb_ctrl_area_cached *control, int bit) 465 { 466 return !test_bit(bit, (unsigned long *)&control->clean); 467 } 468 469 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 470 { 471 return container_of(vcpu, struct vcpu_svm, vcpu); 472 } 473 474 static inline bool svm_is_vmrun_failure(u64 exit_code) 475 { 476 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 477 return (u32)exit_code == (u32)SVM_EXIT_ERR; 478 479 return exit_code == SVM_EXIT_ERR; 480 } 481 482 /* 483 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 484 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 485 * 486 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 487 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 488 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 489 */ 490 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 491 492 static inline void __vmcb_set_intercept(unsigned long *intercepts, u32 bit) 493 { 494 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 495 __set_bit(bit, intercepts); 496 } 497 498 static inline void __vmcb_clr_intercept(unsigned long *intercepts, u32 bit) 499 { 500 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 501 __clear_bit(bit, intercepts); 502 } 503 504 static inline bool __vmcb_is_intercept(unsigned long *intercepts, u32 bit) 505 { 506 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 507 return test_bit(bit, intercepts); 508 } 509 510 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 511 { 512 __vmcb_set_intercept((unsigned long *)&control->intercepts, bit); 513 } 514 515 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 516 { 517 __vmcb_clr_intercept((unsigned long *)&control->intercepts, bit); 518 } 519 520 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 521 { 522 return __vmcb_is_intercept((unsigned long *)&control->intercepts, bit); 523 } 524 525 static inline void vmcb12_clr_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 526 { 527 __vmcb_clr_intercept((unsigned long *)&control->intercepts, bit); 528 } 529 530 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 531 { 532 return __vmcb_is_intercept((unsigned long *)&control->intercepts, bit); 533 } 534 535 void nested_vmcb02_recalc_intercepts(struct vcpu_svm *svm); 536 537 static inline void svm_mark_intercepts_dirty(struct vcpu_svm *svm) 538 { 539 vmcb_mark_dirty(svm->vmcb01.ptr, VMCB_INTERCEPTS); 540 541 /* 542 * If L2 is active, recalculate the intercepts for vmcb02 to account 543 * for the changes made to vmcb01. All intercept configuration is done 544 * for vmcb01 and then propagated to vmcb02 to combine KVM's intercepts 545 * with L1's intercepts (from the vmcb12 snapshot). 546 */ 547 if (is_guest_mode(&svm->vcpu)) 548 nested_vmcb02_recalc_intercepts(svm); 549 } 550 551 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 552 { 553 struct vmcb *vmcb = svm->vmcb01.ptr; 554 555 WARN_ON_ONCE(bit >= 32); 556 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 557 558 svm_mark_intercepts_dirty(svm); 559 } 560 561 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 562 { 563 struct vmcb *vmcb = svm->vmcb01.ptr; 564 565 WARN_ON_ONCE(bit >= 32); 566 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 567 568 svm_mark_intercepts_dirty(svm); 569 } 570 571 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 572 { 573 struct vmcb *vmcb = svm->vmcb01.ptr; 574 575 vmcb_set_intercept(&vmcb->control, bit); 576 577 svm_mark_intercepts_dirty(svm); 578 } 579 580 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 581 { 582 struct vmcb *vmcb = svm->vmcb01.ptr; 583 584 vmcb_clr_intercept(&vmcb->control, bit); 585 586 svm_mark_intercepts_dirty(svm); 587 } 588 589 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 590 { 591 return vmcb_is_intercept(&svm->vmcb->control, bit); 592 } 593 594 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 595 { 596 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VGIF) && 597 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 598 } 599 600 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 601 { 602 if (!vgif) 603 return NULL; 604 605 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 606 return svm->nested.vmcb02.ptr; 607 else 608 return svm->vmcb01.ptr; 609 } 610 611 static inline void enable_gif(struct vcpu_svm *svm) 612 { 613 struct vmcb *vmcb = get_vgif_vmcb(svm); 614 615 if (vmcb) 616 vmcb->control.int_ctl |= V_GIF_MASK; 617 else 618 svm->guest_gif = true; 619 } 620 621 static inline void disable_gif(struct vcpu_svm *svm) 622 { 623 struct vmcb *vmcb = get_vgif_vmcb(svm); 624 625 if (vmcb) 626 vmcb->control.int_ctl &= ~V_GIF_MASK; 627 else 628 svm->guest_gif = false; 629 } 630 631 static inline bool gif_set(struct vcpu_svm *svm) 632 { 633 struct vmcb *vmcb = get_vgif_vmcb(svm); 634 635 if (vmcb) 636 return !!(vmcb->control.int_ctl & V_GIF_MASK); 637 else 638 return svm->guest_gif; 639 } 640 641 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 642 { 643 return svm->nested.ctl.misc_ctl & SVM_MISC_ENABLE_NP; 644 } 645 646 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 647 { 648 return guest_cpu_cap_has(&svm->vcpu, X86_FEATURE_VNMI) && 649 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 650 } 651 652 static inline bool is_x2apic_msrpm_offset(u32 offset) 653 { 654 /* 4 msrs per u8, and 4 u8 in u32 */ 655 u32 msr = offset * 16; 656 657 return (msr >= APIC_BASE_MSR) && 658 (msr < (APIC_BASE_MSR + 0x100)); 659 } 660 661 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 662 { 663 if (!vnmi) 664 return NULL; 665 666 if (is_guest_mode(&svm->vcpu)) 667 return NULL; 668 else 669 return svm->vmcb01.ptr; 670 } 671 672 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 673 { 674 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 675 676 if (vmcb) 677 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 678 else 679 return false; 680 } 681 682 static inline void svm_vmgexit_set_return_code(struct vcpu_svm *svm, 683 u64 response, u64 data) 684 { 685 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, response); 686 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, data); 687 } 688 689 static inline void svm_vmgexit_inject_exception(struct vcpu_svm *svm, u8 vector) 690 { 691 u64 data = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT | vector; 692 693 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_ISSUE_EXCEPTION, data); 694 } 695 696 static inline void svm_vmgexit_bad_input(struct vcpu_svm *svm, u64 suberror) 697 { 698 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_MALFORMED_INPUT, suberror); 699 } 700 701 static inline void svm_vmgexit_success(struct vcpu_svm *svm, u64 data) 702 { 703 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 704 } 705 706 static inline void svm_vmgexit_no_action(struct vcpu_svm *svm, u64 data) 707 { 708 svm_vmgexit_set_return_code(svm, GHCB_HV_RESP_NO_ACTION, data); 709 } 710 711 /* 712 * The MSRPM is 8KiB in size, divided into four 2KiB ranges (the fourth range 713 * is reserved). Each MSR within a range is covered by two bits, one each for 714 * read (bit 0) and write (bit 1), where a bit value of '1' means intercepted. 715 */ 716 #define SVM_MSRPM_BYTES_PER_RANGE 2048 717 #define SVM_BITS_PER_MSR 2 718 #define SVM_MSRS_PER_BYTE (BITS_PER_BYTE / SVM_BITS_PER_MSR) 719 #define SVM_MSRS_PER_RANGE (SVM_MSRPM_BYTES_PER_RANGE * SVM_MSRS_PER_BYTE) 720 static_assert(SVM_MSRS_PER_RANGE == 8192); 721 #define SVM_MSRPM_OFFSET_MASK (SVM_MSRS_PER_RANGE - 1) 722 723 static __always_inline int svm_msrpm_bit_nr(u32 msr) 724 { 725 int range_nr; 726 727 switch (msr & ~SVM_MSRPM_OFFSET_MASK) { 728 case 0: 729 range_nr = 0; 730 break; 731 case 0xc0000000: 732 range_nr = 1; 733 break; 734 case 0xc0010000: 735 range_nr = 2; 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 return range_nr * SVM_MSRPM_BYTES_PER_RANGE * BITS_PER_BYTE + 742 (msr & SVM_MSRPM_OFFSET_MASK) * SVM_BITS_PER_MSR; 743 } 744 745 #define __BUILD_SVM_MSR_BITMAP_HELPER(rtype, action, bitop, access, bit_rw) \ 746 static inline rtype svm_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 747 u32 msr) \ 748 { \ 749 int bit_nr; \ 750 \ 751 bit_nr = svm_msrpm_bit_nr(msr); \ 752 if (bit_nr < 0) \ 753 return (rtype)true; \ 754 \ 755 return bitop##_bit(bit_nr + bit_rw, bitmap); \ 756 } 757 758 #define BUILD_SVM_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 759 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0) \ 760 __BUILD_SVM_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 1) 761 762 BUILD_SVM_MSR_BITMAP_HELPERS(bool, test, test) 763 BUILD_SVM_MSR_BITMAP_HELPERS(void, clear, __clear) 764 BUILD_SVM_MSR_BITMAP_HELPERS(void, set, __set) 765 766 #define DEBUGCTL_RESERVED_BITS (~DEBUGCTLMSR_LBR) 767 768 /* svm.c */ 769 extern bool dump_invalid_vmcb; 770 771 void *svm_alloc_permissions_map(unsigned long size, gfp_t gfp_mask); 772 773 static inline void *svm_vcpu_alloc_msrpm(void) 774 { 775 return svm_alloc_permissions_map(MSRPM_SIZE, GFP_KERNEL_ACCOUNT); 776 } 777 778 #define svm_copy_lbrs(to, from) \ 779 do { \ 780 (to)->dbgctl = (from)->dbgctl; \ 781 (to)->br_from = (from)->br_from; \ 782 (to)->br_to = (from)->br_to; \ 783 (to)->last_excp_from = (from)->last_excp_from; \ 784 (to)->last_excp_to = (from)->last_excp_to; \ 785 } while (0) 786 787 void svm_vcpu_free_msrpm(void *msrpm); 788 void svm_enable_lbrv(struct kvm_vcpu *vcpu); 789 void svm_update_lbrv(struct kvm_vcpu *vcpu); 790 791 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 792 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 793 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 794 void disable_nmi_singlestep(struct vcpu_svm *svm); 795 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 796 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 797 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 798 void svm_set_gif(struct vcpu_svm *svm, bool value); 799 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 800 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 801 int read, int write); 802 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 803 int trig_mode, int vec); 804 805 void svm_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 806 807 static inline void svm_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 808 u32 msr, int type) 809 { 810 svm_set_intercept_for_msr(vcpu, msr, type, false); 811 } 812 813 static inline void svm_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 814 u32 msr, int type) 815 { 816 svm_set_intercept_for_msr(vcpu, msr, type, true); 817 } 818 819 /* nested.c */ 820 821 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 822 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 823 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 824 825 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 826 { 827 struct vcpu_svm *svm = to_svm(vcpu); 828 829 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 830 } 831 832 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 833 { 834 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 835 } 836 837 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 838 { 839 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 840 } 841 842 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 843 { 844 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 845 } 846 847 int __init nested_svm_init_msrpm_merge_offsets(void); 848 849 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb_gpa, bool from_vmrun); 850 void svm_leave_nested(struct kvm_vcpu *vcpu); 851 void svm_free_nested(struct vcpu_svm *svm); 852 int svm_allocate_nested(struct vcpu_svm *svm); 853 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 854 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 855 struct vmcb_save_area *from_save); 856 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 857 void nested_svm_vmexit(struct vcpu_svm *svm); 858 859 static inline void nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 860 { 861 svm->vmcb->control.exit_code = exit_code; 862 svm->vmcb->control.exit_info_1 = 0; 863 svm->vmcb->control.exit_info_2 = 0; 864 nested_svm_vmexit(svm); 865 } 866 867 int nested_svm_exit_handled(struct vcpu_svm *svm); 868 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 869 int nested_svm_check_cached_vmcb12(struct kvm_vcpu *vcpu); 870 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 871 bool has_error_code, u32 error_code); 872 int nested_svm_exit_special(struct vcpu_svm *svm); 873 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 874 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu); 875 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 876 struct vmcb_control_area *control); 877 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 878 struct vmcb_save_area *save); 879 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 880 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 881 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 882 883 extern struct kvm_x86_nested_ops svm_nested_ops; 884 885 /* avic.c */ 886 #define AVIC_REQUIRED_APICV_INHIBITS \ 887 ( \ 888 BIT(APICV_INHIBIT_REASON_DISABLED) | \ 889 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 890 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 891 BIT(APICV_INHIBIT_REASON_NESTED) | \ 892 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 893 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 894 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 895 BIT(APICV_INHIBIT_REASON_SEV) | \ 896 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 897 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 898 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 899 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \ 900 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG) \ 901 ) 902 903 bool __init avic_hardware_setup(void); 904 void avic_hardware_unsetup(void); 905 int avic_alloc_physical_id_table(struct kvm *kvm); 906 void avic_vm_destroy(struct kvm *kvm); 907 int avic_vm_init(struct kvm *kvm); 908 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 909 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 910 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 911 int avic_init_vcpu(struct vcpu_svm *svm); 912 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 913 void avic_vcpu_put(struct kvm_vcpu *vcpu); 914 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 915 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 916 int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, 917 unsigned int host_irq, uint32_t guest_irq, 918 struct kvm_vcpu *vcpu, u32 vector); 919 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 920 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 921 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 922 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 923 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 924 925 926 /* sev.c */ 927 928 int pre_sev_run(struct vcpu_svm *svm, int cpu); 929 void sev_init_vmcb(struct vcpu_svm *svm, bool init_event); 930 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm); 931 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 932 void sev_es_recalc_msr_intercepts(struct kvm_vcpu *vcpu); 933 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 934 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa); 935 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 936 937 #ifdef CONFIG_KVM_AMD_SEV 938 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 939 int sev_mem_enc_register_region(struct kvm *kvm, 940 struct kvm_enc_region *range); 941 int sev_mem_enc_unregister_region(struct kvm *kvm, 942 struct kvm_enc_region *range); 943 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 944 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 945 void sev_guest_memory_reclaimed(struct kvm *kvm); 946 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 947 948 /* These symbols are used in common code and are stubbed below. */ 949 950 struct page *snp_safe_alloc_page_node(int node, gfp_t gfp); 951 static inline struct page *snp_safe_alloc_page(void) 952 { 953 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 954 } 955 956 int sev_vcpu_create(struct kvm_vcpu *vcpu); 957 void sev_free_vcpu(struct kvm_vcpu *vcpu); 958 void sev_vm_init(struct kvm *kvm); 959 void sev_vm_destroy(struct kvm *kvm); 960 void __init sev_set_cpu_caps(void); 961 void __init sev_hardware_setup(void); 962 void sev_hardware_unsetup(void); 963 int sev_cpu_init(struct svm_cpu_data *sd); 964 int sev_dev_get_attr(u32 group, u64 attr, u64 *val); 965 extern unsigned int max_sev_asid; 966 void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code); 967 int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order); 968 void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end); 969 int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_private); 970 struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu); 971 void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa); 972 #else 973 static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) 974 { 975 return alloc_pages_node(node, gfp | __GFP_ZERO, 0); 976 } 977 978 static inline struct page *snp_safe_alloc_page(void) 979 { 980 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT); 981 } 982 983 static inline int sev_vcpu_create(struct kvm_vcpu *vcpu) { return 0; } 984 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {} 985 static inline void sev_vm_init(struct kvm *kvm) {} 986 static inline void sev_vm_destroy(struct kvm *kvm) {} 987 static inline void __init sev_set_cpu_caps(void) {} 988 static inline void __init sev_hardware_setup(void) {} 989 static inline void sev_hardware_unsetup(void) {} 990 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; } 991 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; } 992 #define max_sev_asid 0 993 static inline void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) {} 994 static inline int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order) 995 { 996 return 0; 997 } 998 static inline void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) {} 999 static inline int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_private) 1000 { 1001 return 0; 1002 } 1003 1004 static inline struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu) 1005 { 1006 return NULL; 1007 } 1008 static inline void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area *vmsa) {} 1009 #endif 1010 1011 /* vmenter.S */ 1012 1013 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted, 1014 struct sev_es_save_area *hostsa); 1015 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 1016 1017 #define DEFINE_KVM_GHCB_ACCESSORS(field) \ 1018 static __always_inline u64 kvm_ghcb_get_##field(struct vcpu_svm *svm) \ 1019 { \ 1020 return READ_ONCE(svm->sev_es.ghcb->save.field); \ 1021 } \ 1022 \ 1023 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \ 1024 { \ 1025 return test_bit(GHCB_BITMAP_IDX(field), \ 1026 (unsigned long *)&svm->sev_es.valid_bitmap); \ 1027 } \ 1028 \ 1029 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm) \ 1030 { \ 1031 return kvm_ghcb_##field##_is_valid(svm) ? kvm_ghcb_get_##field(svm) : 0; \ 1032 } 1033 1034 DEFINE_KVM_GHCB_ACCESSORS(cpl) 1035 DEFINE_KVM_GHCB_ACCESSORS(rax) 1036 DEFINE_KVM_GHCB_ACCESSORS(rcx) 1037 DEFINE_KVM_GHCB_ACCESSORS(rdx) 1038 DEFINE_KVM_GHCB_ACCESSORS(rbx) 1039 DEFINE_KVM_GHCB_ACCESSORS(rsi) 1040 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code) 1041 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1) 1042 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2) 1043 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch) 1044 DEFINE_KVM_GHCB_ACCESSORS(xcr0) 1045 DEFINE_KVM_GHCB_ACCESSORS(xss) 1046 1047 #endif 1048