1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * The R_INTC in Allwinner A31 and newer SoCs manages several types of
4 * interrupts, as shown below:
5 *
6 * NMI IRQ DIRECT IRQs MUXED IRQs
7 * bit 0 bits 1-15^ bits 19-31
8 *
9 * +---------+ +---------+ +---------+ +---------+
10 * | NMI Pad | | IRQ d | | IRQ m | | IRQ m+7 |
11 * +---------+ +---------+ +---------+ +---------+
12 * | | | | | | |
13 * | | | | |......| |
14 * +------V------+ +------------+ | | | +--V------V--+ |
15 * | Invert/ | | Write 1 to | | | | | AND with | |
16 * | Edge Detect | | PENDING[0] | | | | | MUX[m/8] | |
17 * +-------------+ +------------+ | | | +------------+ |
18 * | | | | | | |
19 * +--V-------V--+ +--V--+ | +--V--+ | +--V--+
20 * | Set Reset| | GIC | | | GIC | | | GIC |
21 * | Latch | | SPI | | | SPI |... | ...| SPI |
22 * +-------------+ | N+d | | | m | | | m+7 |
23 * | | +-----+ | +-----+ | +-----+
24 * | | | |
25 * +-------V-+ +-V----------+ +---------V--+ +--------V--------+
26 * | GIC SPI | | AND with | | AND with | | AND with |
27 * | N (=32) | | ENABLE[0] | | ENABLE[d] | | ENABLE[19+m/8] |
28 * +---------+ +------------+ +------------+ +-----------------+
29 * | | |
30 * +------V-----+ +------V-----+ +--------V--------+
31 * | Read | | Read | | Read |
32 * | PENDING[0] | | PENDING[d] | | PENDING[19+m/8] |
33 * +------------+ +------------+ +-----------------+
34 *
35 * ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as
36 * the MSGBOX. These IRQs do not map to any GIC SPI.
37 *
38 * The H6 variant adds two more (banked) direct IRQs and implements the full
39 * set of 128 mux bits. This requires a second set of top-level registers.
40 */
41
42 #include <linux/bitmap.h>
43 #include <linux/interrupt.h>
44 #include <linux/irq.h>
45 #include <linux/irqchip.h>
46 #include <linux/irqdomain.h>
47 #include <linux/of.h>
48 #include <linux/of_address.h>
49 #include <linux/of_irq.h>
50 #include <linux/syscore_ops.h>
51
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53
54 #define SUN6I_NMI_CTRL (0x0c)
55 #define SUN6I_IRQ_PENDING(n) (0x10 + 4 * (n))
56 #define SUN6I_IRQ_ENABLE(n) (0x40 + 4 * (n))
57 #define SUN6I_MUX_ENABLE(n) (0xc0 + 4 * (n))
58
59 #define SUN6I_NMI_SRC_TYPE_LEVEL_LOW 0
60 #define SUN6I_NMI_SRC_TYPE_EDGE_FALLING 1
61 #define SUN6I_NMI_SRC_TYPE_LEVEL_HIGH 2
62 #define SUN6I_NMI_SRC_TYPE_EDGE_RISING 3
63
64 #define SUN6I_NMI_BIT BIT(0)
65
66 #define SUN6I_NMI_NEEDS_ACK ((void *)1)
67
68 #define SUN6I_NR_TOP_LEVEL_IRQS 64
69 #define SUN6I_NR_DIRECT_IRQS 16
70 #define SUN6I_NR_MUX_BITS 128
71
72 struct sun6i_r_intc_variant {
73 u32 first_mux_irq;
74 u32 nr_mux_irqs;
75 u32 mux_valid[BITS_TO_U32(SUN6I_NR_MUX_BITS)];
76 };
77
78 static void __iomem *base;
79 static irq_hw_number_t nmi_hwirq;
80 static DECLARE_BITMAP(wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS);
81 static DECLARE_BITMAP(wake_mux_enabled, SUN6I_NR_MUX_BITS);
82 static DECLARE_BITMAP(wake_mux_valid, SUN6I_NR_MUX_BITS);
83
sun6i_r_intc_ack_nmi(void)84 static void sun6i_r_intc_ack_nmi(void)
85 {
86 writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
87 }
88
sun6i_r_intc_nmi_ack(struct irq_data * data)89 static void sun6i_r_intc_nmi_ack(struct irq_data *data)
90 {
91 if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
92 sun6i_r_intc_ack_nmi();
93 else
94 data->chip_data = SUN6I_NMI_NEEDS_ACK;
95 }
96
sun6i_r_intc_nmi_eoi(struct irq_data * data)97 static void sun6i_r_intc_nmi_eoi(struct irq_data *data)
98 {
99 /* For oneshot IRQs, delay the ack until the IRQ is unmasked. */
100 if (data->chip_data == SUN6I_NMI_NEEDS_ACK && !irqd_irq_masked(data)) {
101 data->chip_data = NULL;
102 sun6i_r_intc_ack_nmi();
103 }
104
105 irq_chip_eoi_parent(data);
106 }
107
sun6i_r_intc_nmi_unmask(struct irq_data * data)108 static void sun6i_r_intc_nmi_unmask(struct irq_data *data)
109 {
110 if (data->chip_data == SUN6I_NMI_NEEDS_ACK) {
111 data->chip_data = NULL;
112 sun6i_r_intc_ack_nmi();
113 }
114
115 irq_chip_unmask_parent(data);
116 }
117
sun6i_r_intc_nmi_set_type(struct irq_data * data,unsigned int type)118 static int sun6i_r_intc_nmi_set_type(struct irq_data *data, unsigned int type)
119 {
120 u32 nmi_src_type;
121
122 switch (type) {
123 case IRQ_TYPE_EDGE_RISING:
124 nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_RISING;
125 break;
126 case IRQ_TYPE_EDGE_FALLING:
127 nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_FALLING;
128 break;
129 case IRQ_TYPE_LEVEL_HIGH:
130 nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_HIGH;
131 break;
132 case IRQ_TYPE_LEVEL_LOW:
133 nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_LOW;
134 break;
135 default:
136 return -EINVAL;
137 }
138
139 writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL);
140
141 /*
142 * The "External NMI" GIC input connects to a latch inside R_INTC, not
143 * directly to the pin. So the GIC trigger type does not depend on the
144 * NMI pin trigger type.
145 */
146 return irq_chip_set_type_parent(data, IRQ_TYPE_LEVEL_HIGH);
147 }
148
sun6i_r_intc_nmi_set_irqchip_state(struct irq_data * data,enum irqchip_irq_state which,bool state)149 static int sun6i_r_intc_nmi_set_irqchip_state(struct irq_data *data,
150 enum irqchip_irq_state which,
151 bool state)
152 {
153 if (which == IRQCHIP_STATE_PENDING && !state)
154 sun6i_r_intc_ack_nmi();
155
156 return irq_chip_set_parent_state(data, which, state);
157 }
158
sun6i_r_intc_irq_set_wake(struct irq_data * data,unsigned int on)159 static int sun6i_r_intc_irq_set_wake(struct irq_data *data, unsigned int on)
160 {
161 unsigned long offset_from_nmi = data->hwirq - nmi_hwirq;
162
163 if (offset_from_nmi < SUN6I_NR_DIRECT_IRQS)
164 assign_bit(offset_from_nmi, wake_irq_enabled, on);
165 else if (test_bit(data->hwirq, wake_mux_valid))
166 assign_bit(data->hwirq, wake_mux_enabled, on);
167 else
168 /* Not wakeup capable. */
169 return -EPERM;
170
171 return 0;
172 }
173
174 static struct irq_chip sun6i_r_intc_nmi_chip = {
175 .name = "sun6i-r-intc",
176 .irq_ack = sun6i_r_intc_nmi_ack,
177 .irq_mask = irq_chip_mask_parent,
178 .irq_unmask = sun6i_r_intc_nmi_unmask,
179 .irq_eoi = sun6i_r_intc_nmi_eoi,
180 .irq_set_affinity = irq_chip_set_affinity_parent,
181 .irq_set_type = sun6i_r_intc_nmi_set_type,
182 .irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state,
183 .irq_set_wake = sun6i_r_intc_irq_set_wake,
184 .flags = IRQCHIP_SET_TYPE_MASKED,
185 };
186
187 static struct irq_chip sun6i_r_intc_wakeup_chip = {
188 .name = "sun6i-r-intc",
189 .irq_mask = irq_chip_mask_parent,
190 .irq_unmask = irq_chip_unmask_parent,
191 .irq_eoi = irq_chip_eoi_parent,
192 .irq_set_affinity = irq_chip_set_affinity_parent,
193 .irq_set_type = irq_chip_set_type_parent,
194 .irq_set_wake = sun6i_r_intc_irq_set_wake,
195 .flags = IRQCHIP_SET_TYPE_MASKED,
196 };
197
sun6i_r_intc_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)198 static int sun6i_r_intc_domain_translate(struct irq_domain *domain,
199 struct irq_fwspec *fwspec,
200 unsigned long *hwirq,
201 unsigned int *type)
202 {
203 /* Accept the old two-cell binding for the NMI only. */
204 if (fwspec->param_count == 2 && fwspec->param[0] == 0) {
205 *hwirq = nmi_hwirq;
206 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
207 return 0;
208 }
209
210 /* Otherwise this binding should match the GIC SPI binding. */
211 if (fwspec->param_count < 3)
212 return -EINVAL;
213 if (fwspec->param[0] != GIC_SPI)
214 return -EINVAL;
215
216 *hwirq = fwspec->param[1];
217 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
218
219 return 0;
220 }
221
sun6i_r_intc_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)222 static int sun6i_r_intc_domain_alloc(struct irq_domain *domain,
223 unsigned int virq,
224 unsigned int nr_irqs, void *arg)
225 {
226 struct irq_fwspec *fwspec = arg;
227 struct irq_fwspec gic_fwspec;
228 unsigned long hwirq;
229 unsigned int type;
230 int i, ret;
231
232 ret = sun6i_r_intc_domain_translate(domain, fwspec, &hwirq, &type);
233 if (ret)
234 return ret;
235 if (hwirq + nr_irqs > SUN6I_NR_MUX_BITS)
236 return -EINVAL;
237
238 /* Construct a GIC-compatible fwspec from this fwspec. */
239 gic_fwspec = (struct irq_fwspec) {
240 .fwnode = domain->parent->fwnode,
241 .param_count = 3,
242 .param = { GIC_SPI, hwirq, type },
243 };
244
245 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
246 if (ret)
247 return ret;
248
249 for (i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) {
250 if (hwirq == nmi_hwirq) {
251 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
252 &sun6i_r_intc_nmi_chip,
253 NULL);
254 irq_set_handler(virq, handle_fasteoi_ack_irq);
255 } else {
256 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
257 &sun6i_r_intc_wakeup_chip,
258 NULL);
259 }
260 }
261
262 return 0;
263 }
264
265 static const struct irq_domain_ops sun6i_r_intc_domain_ops = {
266 .translate = sun6i_r_intc_domain_translate,
267 .alloc = sun6i_r_intc_domain_alloc,
268 .free = irq_domain_free_irqs_common,
269 };
270
sun6i_r_intc_suspend(void)271 static int sun6i_r_intc_suspend(void)
272 {
273 u32 buf[BITS_TO_U32(MAX(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))];
274 int i;
275
276 /* Wake IRQs are enabled during system sleep and shutdown. */
277 bitmap_to_arr32(buf, wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS);
278 for (i = 0; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i)
279 writel_relaxed(buf[i], base + SUN6I_IRQ_ENABLE(i));
280 bitmap_to_arr32(buf, wake_mux_enabled, SUN6I_NR_MUX_BITS);
281 for (i = 0; i < BITS_TO_U32(SUN6I_NR_MUX_BITS); ++i)
282 writel_relaxed(buf[i], base + SUN6I_MUX_ENABLE(i));
283
284 return 0;
285 }
286
sun6i_r_intc_resume(void)287 static void sun6i_r_intc_resume(void)
288 {
289 int i;
290
291 /* Only the NMI is relevant during normal operation. */
292 writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0));
293 for (i = 1; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i)
294 writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i));
295 }
296
sun6i_r_intc_shutdown(void)297 static void sun6i_r_intc_shutdown(void)
298 {
299 sun6i_r_intc_suspend();
300 }
301
302 static struct syscore_ops sun6i_r_intc_syscore_ops = {
303 .suspend = sun6i_r_intc_suspend,
304 .resume = sun6i_r_intc_resume,
305 .shutdown = sun6i_r_intc_shutdown,
306 };
307
sun6i_r_intc_init(struct device_node * node,struct device_node * parent,const struct sun6i_r_intc_variant * v)308 static int __init sun6i_r_intc_init(struct device_node *node,
309 struct device_node *parent,
310 const struct sun6i_r_intc_variant *v)
311 {
312 struct irq_domain *domain, *parent_domain;
313 struct of_phandle_args nmi_parent;
314 int ret;
315
316 /* Extract the NMI hwirq number from the OF node. */
317 ret = of_irq_parse_one(node, 0, &nmi_parent);
318 if (ret)
319 return ret;
320 if (nmi_parent.args_count < 3 ||
321 nmi_parent.args[0] != GIC_SPI ||
322 nmi_parent.args[2] != IRQ_TYPE_LEVEL_HIGH)
323 return -EINVAL;
324 nmi_hwirq = nmi_parent.args[1];
325
326 bitmap_set(wake_irq_enabled, v->first_mux_irq, v->nr_mux_irqs);
327 bitmap_from_arr32(wake_mux_valid, v->mux_valid, SUN6I_NR_MUX_BITS);
328
329 parent_domain = irq_find_host(parent);
330 if (!parent_domain) {
331 pr_err("%pOF: Failed to obtain parent domain\n", node);
332 return -ENXIO;
333 }
334
335 base = of_io_request_and_map(node, 0, NULL);
336 if (IS_ERR(base)) {
337 pr_err("%pOF: Failed to map MMIO region\n", node);
338 return PTR_ERR(base);
339 }
340
341 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, node,
342 &sun6i_r_intc_domain_ops, NULL);
343 if (!domain) {
344 pr_err("%pOF: Failed to allocate domain\n", node);
345 iounmap(base);
346 return -ENOMEM;
347 }
348
349 register_syscore_ops(&sun6i_r_intc_syscore_ops);
350
351 sun6i_r_intc_ack_nmi();
352 sun6i_r_intc_resume();
353
354 return 0;
355 }
356
357 static const struct sun6i_r_intc_variant sun6i_a31_r_intc_variant __initconst = {
358 .first_mux_irq = 19,
359 .nr_mux_irqs = 13,
360 .mux_valid = { 0xffffffff, 0xfff80000, 0xffffffff, 0x0000000f },
361 };
362
sun6i_a31_r_intc_init(struct device_node * node,struct device_node * parent)363 static int __init sun6i_a31_r_intc_init(struct device_node *node,
364 struct device_node *parent)
365 {
366 return sun6i_r_intc_init(node, parent, &sun6i_a31_r_intc_variant);
367 }
368 IRQCHIP_DECLARE(sun6i_a31_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_a31_r_intc_init);
369
370 static const struct sun6i_r_intc_variant sun50i_h6_r_intc_variant __initconst = {
371 .first_mux_irq = 21,
372 .nr_mux_irqs = 16,
373 .mux_valid = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff },
374 };
375
sun50i_h6_r_intc_init(struct device_node * node,struct device_node * parent)376 static int __init sun50i_h6_r_intc_init(struct device_node *node,
377 struct device_node *parent)
378 {
379 return sun6i_r_intc_init(node, parent, &sun50i_h6_r_intc_variant);
380 }
381 IRQCHIP_DECLARE(sun50i_h6_r_intc, "allwinner,sun50i-h6-r-intc", sun50i_h6_r_intc_init);
382