1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/pci.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_atombios.h"
31 #include "amdgpu_dpm_internal.h"
32 #include "amd_pcie.h"
33 #include "atom.h"
34 #include "gfx_v6_0.h"
35 #include "r600_dpm.h"
36 #include "sid.h"
37 #include "si_dpm.h"
38 #include "../include/pptable.h"
39 #include <linux/math64.h>
40 #include <linux/seq_file.h>
41 #include <linux/firmware.h>
42 #include <legacy_dpm.h>
43
44 #include "bif/bif_3_0_d.h"
45 #include "bif/bif_3_0_sh_mask.h"
46
47 #include "dce/dce_6_0_d.h"
48 #include "dce/dce_6_0_sh_mask.h"
49
50 #include "gca/gfx_6_0_d.h"
51 #include "gca/gfx_6_0_sh_mask.h"
52
53 #include"gmc/gmc_6_0_d.h"
54 #include"gmc/gmc_6_0_sh_mask.h"
55
56 #include "smu/smu_6_0_d.h"
57 #include "smu/smu_6_0_sh_mask.h"
58
59 #define MC_CG_ARB_FREQ_F0 0x0a
60 #define MC_CG_ARB_FREQ_F1 0x0b
61 #define MC_CG_ARB_FREQ_F2 0x0c
62 #define MC_CG_ARB_FREQ_F3 0x0d
63
64 #define SMC_RAM_END 0x20000
65
66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
67
68
69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
76
77 #define BIOS_SCRATCH_4 0x5cd
78
79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
82 MODULE_FIRMWARE("amdgpu/verde_smc.bin");
83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
84 MODULE_FIRMWARE("amdgpu/oland_smc.bin");
85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
89
90 static const struct amd_pm_funcs si_dpm_funcs;
91
92 union power_info {
93 struct _ATOM_POWERPLAY_INFO info;
94 struct _ATOM_POWERPLAY_INFO_V2 info_2;
95 struct _ATOM_POWERPLAY_INFO_V3 info_3;
96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
101 };
102
103 union fan_info {
104 struct _ATOM_PPLIB_FANTABLE fan;
105 struct _ATOM_PPLIB_FANTABLE2 fan2;
106 struct _ATOM_PPLIB_FANTABLE3 fan3;
107 };
108
109 union pplib_clock_info {
110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
114 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
115 };
116
117 enum si_dpm_auto_throttle_src {
118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL,
119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL
120 };
121
122 enum si_dpm_event_src {
123 SI_DPM_EVENT_SRC_ANALOG = 0,
124 SI_DPM_EVENT_SRC_EXTERNAL = 1,
125 SI_DPM_EVENT_SRC_DIGITAL = 2,
126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
128 };
129
130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
131 {
132 R600_UTC_DFLT_00,
133 R600_UTC_DFLT_01,
134 R600_UTC_DFLT_02,
135 R600_UTC_DFLT_03,
136 R600_UTC_DFLT_04,
137 R600_UTC_DFLT_05,
138 R600_UTC_DFLT_06,
139 R600_UTC_DFLT_07,
140 R600_UTC_DFLT_08,
141 R600_UTC_DFLT_09,
142 R600_UTC_DFLT_10,
143 R600_UTC_DFLT_11,
144 R600_UTC_DFLT_12,
145 R600_UTC_DFLT_13,
146 R600_UTC_DFLT_14,
147 };
148
149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
150 {
151 R600_DTC_DFLT_00,
152 R600_DTC_DFLT_01,
153 R600_DTC_DFLT_02,
154 R600_DTC_DFLT_03,
155 R600_DTC_DFLT_04,
156 R600_DTC_DFLT_05,
157 R600_DTC_DFLT_06,
158 R600_DTC_DFLT_07,
159 R600_DTC_DFLT_08,
160 R600_DTC_DFLT_09,
161 R600_DTC_DFLT_10,
162 R600_DTC_DFLT_11,
163 R600_DTC_DFLT_12,
164 R600_DTC_DFLT_13,
165 R600_DTC_DFLT_14,
166 };
167
168 static const struct si_cac_config_reg cac_weights_tahiti[] =
169 {
170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
230 { 0xFFFFFFFF }
231 };
232
233 static const struct si_cac_config_reg lcac_tahiti[] =
234 {
235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
321 { 0xFFFFFFFF }
322
323 };
324
325 static const struct si_cac_config_reg cac_override_tahiti[] =
326 {
327 { 0xFFFFFFFF }
328 };
329
330 static const struct si_powertune_data powertune_data_tahiti =
331 {
332 ((1 << 16) | 27027),
333 6,
334 0,
335 4,
336 95,
337 {
338 0UL,
339 0UL,
340 4521550UL,
341 309631529UL,
342 -1270850L,
343 4513710L,
344 40
345 },
346 595000000UL,
347 12,
348 {
349 0,
350 0,
351 0,
352 0,
353 0,
354 0,
355 0,
356 0
357 },
358 true
359 };
360
361 static const struct si_dte_data dte_data_tahiti =
362 {
363 { 1159409, 0, 0, 0, 0 },
364 { 777, 0, 0, 0, 0 },
365 2,
366 54000,
367 127000,
368 25,
369 2,
370 10,
371 13,
372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
375 85,
376 false
377 };
378
379 static const struct si_dte_data dte_data_tahiti_pro =
380 {
381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
382 { 0x0, 0x0, 0x0, 0x0, 0x0 },
383 5,
384 45000,
385 100,
386 0xA,
387 1,
388 0,
389 0x10,
390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
393 90,
394 true
395 };
396
397 static const struct si_dte_data dte_data_new_zealand =
398 {
399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
401 0x5,
402 0xAFC8,
403 0x69,
404 0x32,
405 1,
406 0,
407 0x10,
408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
411 85,
412 true
413 };
414
415 static const struct si_dte_data dte_data_aruba_pro =
416 {
417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
418 { 0x0, 0x0, 0x0, 0x0, 0x0 },
419 5,
420 45000,
421 100,
422 0xA,
423 1,
424 0,
425 0x10,
426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
429 90,
430 true
431 };
432
433 static const struct si_dte_data dte_data_malta =
434 {
435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
436 { 0x0, 0x0, 0x0, 0x0, 0x0 },
437 5,
438 45000,
439 100,
440 0xA,
441 1,
442 0,
443 0x10,
444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
447 90,
448 true
449 };
450
451 static const struct si_cac_config_reg cac_weights_pitcairn[] =
452 {
453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
513 { 0xFFFFFFFF }
514 };
515
516 static const struct si_cac_config_reg lcac_pitcairn[] =
517 {
518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
604 { 0xFFFFFFFF }
605 };
606
607 static const struct si_cac_config_reg cac_override_pitcairn[] =
608 {
609 { 0xFFFFFFFF }
610 };
611
612 static const struct si_powertune_data powertune_data_pitcairn =
613 {
614 ((1 << 16) | 27027),
615 5,
616 0,
617 6,
618 100,
619 {
620 51600000UL,
621 1800000UL,
622 7194395UL,
623 309631529UL,
624 -1270850L,
625 4513710L,
626 100
627 },
628 117830498UL,
629 12,
630 {
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 0
639 },
640 true
641 };
642
643 static const struct si_dte_data dte_data_pitcairn =
644 {
645 { 0, 0, 0, 0, 0 },
646 { 0, 0, 0, 0, 0 },
647 0,
648 0,
649 0,
650 0,
651 0,
652 0,
653 0,
654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
657 0,
658 false
659 };
660
661 static const struct si_dte_data dte_data_curacao_xt =
662 {
663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
664 { 0x0, 0x0, 0x0, 0x0, 0x0 },
665 5,
666 45000,
667 100,
668 0xA,
669 1,
670 0,
671 0x10,
672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
675 90,
676 true
677 };
678
679 static const struct si_dte_data dte_data_curacao_pro =
680 {
681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
682 { 0x0, 0x0, 0x0, 0x0, 0x0 },
683 5,
684 45000,
685 100,
686 0xA,
687 1,
688 0,
689 0x10,
690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
693 90,
694 true
695 };
696
697 static const struct si_dte_data dte_data_neptune_xt =
698 {
699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
700 { 0x0, 0x0, 0x0, 0x0, 0x0 },
701 5,
702 45000,
703 100,
704 0xA,
705 1,
706 0,
707 0x10,
708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
711 90,
712 true
713 };
714
715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
716 {
717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
777 { 0xFFFFFFFF }
778 };
779
780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
781 {
782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
842 { 0xFFFFFFFF }
843 };
844
845 static const struct si_cac_config_reg cac_weights_heathrow[] =
846 {
847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
907 { 0xFFFFFFFF }
908 };
909
910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
911 {
912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
972 { 0xFFFFFFFF }
973 };
974
975 static const struct si_cac_config_reg cac_weights_cape_verde[] =
976 {
977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1037 { 0xFFFFFFFF }
1038 };
1039
1040 static const struct si_cac_config_reg lcac_cape_verde[] =
1041 {
1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1096 { 0xFFFFFFFF }
1097 };
1098
1099 static const struct si_cac_config_reg cac_override_cape_verde[] =
1100 {
1101 { 0xFFFFFFFF }
1102 };
1103
1104 static const struct si_powertune_data powertune_data_cape_verde =
1105 {
1106 ((1 << 16) | 0x6993),
1107 5,
1108 0,
1109 7,
1110 105,
1111 {
1112 0UL,
1113 0UL,
1114 7194395UL,
1115 309631529UL,
1116 -1270850L,
1117 4513710L,
1118 100
1119 },
1120 117830498UL,
1121 12,
1122 {
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 0
1131 },
1132 true
1133 };
1134
1135 static const struct si_dte_data dte_data_cape_verde =
1136 {
1137 { 0, 0, 0, 0, 0 },
1138 { 0, 0, 0, 0, 0 },
1139 0,
1140 0,
1141 0,
1142 0,
1143 0,
1144 0,
1145 0,
1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1149 0,
1150 false
1151 };
1152
1153 static const struct si_dte_data dte_data_venus_xtx =
1154 {
1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1157 5,
1158 55000,
1159 0x69,
1160 0xA,
1161 1,
1162 0,
1163 0x3,
1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 90,
1168 true
1169 };
1170
1171 static const struct si_dte_data dte_data_venus_xt =
1172 {
1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1175 5,
1176 55000,
1177 0x69,
1178 0xA,
1179 1,
1180 0,
1181 0x3,
1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 90,
1186 true
1187 };
1188
1189 static const struct si_dte_data dte_data_venus_pro =
1190 {
1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1193 5,
1194 55000,
1195 0x69,
1196 0xA,
1197 1,
1198 0,
1199 0x3,
1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1203 90,
1204 true
1205 };
1206
1207 static const struct si_cac_config_reg cac_weights_oland[] =
1208 {
1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1269 { 0xFFFFFFFF }
1270 };
1271
1272 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1273 {
1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1334 { 0xFFFFFFFF }
1335 };
1336
1337 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1338 {
1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1399 { 0xFFFFFFFF }
1400 };
1401
1402 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1403 {
1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1464 { 0xFFFFFFFF }
1465 };
1466
1467 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1468 {
1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1529 { 0xFFFFFFFF }
1530 };
1531
1532 static const struct si_cac_config_reg lcac_oland[] =
1533 {
1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0xFFFFFFFF }
1577 };
1578
1579 static const struct si_cac_config_reg lcac_mars_pro[] =
1580 {
1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1623 { 0xFFFFFFFF }
1624 };
1625
1626 static const struct si_cac_config_reg cac_override_oland[] =
1627 {
1628 { 0xFFFFFFFF }
1629 };
1630
1631 static const struct si_powertune_data powertune_data_oland =
1632 {
1633 ((1 << 16) | 0x6993),
1634 5,
1635 0,
1636 7,
1637 105,
1638 {
1639 0UL,
1640 0UL,
1641 7194395UL,
1642 309631529UL,
1643 -1270850L,
1644 4513710L,
1645 100
1646 },
1647 117830498UL,
1648 12,
1649 {
1650 0,
1651 0,
1652 0,
1653 0,
1654 0,
1655 0,
1656 0,
1657 0
1658 },
1659 true
1660 };
1661
1662 static const struct si_powertune_data powertune_data_mars_pro =
1663 {
1664 ((1 << 16) | 0x6993),
1665 5,
1666 0,
1667 7,
1668 105,
1669 {
1670 0UL,
1671 0UL,
1672 7194395UL,
1673 309631529UL,
1674 -1270850L,
1675 4513710L,
1676 100
1677 },
1678 117830498UL,
1679 12,
1680 {
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 0
1689 },
1690 true
1691 };
1692
1693 static const struct si_dte_data dte_data_oland =
1694 {
1695 { 0, 0, 0, 0, 0 },
1696 { 0, 0, 0, 0, 0 },
1697 0,
1698 0,
1699 0,
1700 0,
1701 0,
1702 0,
1703 0,
1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1707 0,
1708 false
1709 };
1710
1711 static const struct si_dte_data dte_data_mars_pro =
1712 {
1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1714 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1715 5,
1716 55000,
1717 105,
1718 0xA,
1719 1,
1720 0,
1721 0x10,
1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1725 90,
1726 true
1727 };
1728
1729 static const struct si_dte_data dte_data_sun_xt =
1730 {
1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1732 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1733 5,
1734 55000,
1735 105,
1736 0xA,
1737 1,
1738 0,
1739 0x10,
1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1743 90,
1744 true
1745 };
1746
1747
1748 static const struct si_cac_config_reg cac_weights_hainan[] =
1749 {
1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1810 { 0xFFFFFFFF }
1811 };
1812
1813 static const struct si_powertune_data powertune_data_hainan =
1814 {
1815 ((1 << 16) | 0x6993),
1816 5,
1817 0,
1818 9,
1819 105,
1820 {
1821 0UL,
1822 0UL,
1823 7194395UL,
1824 309631529UL,
1825 -1270850L,
1826 4513710L,
1827 100
1828 },
1829 117830498UL,
1830 12,
1831 {
1832 0,
1833 0,
1834 0,
1835 0,
1836 0,
1837 0,
1838 0,
1839 0
1840 },
1841 true
1842 };
1843
1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1848
1849 static int si_populate_voltage_value(struct amdgpu_device *adev,
1850 const struct atom_voltage_table *table,
1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1852 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1854 u16 *std_voltage);
1855 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1856 u16 reg_offset, u32 value);
1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1858 struct rv7xx_pl *pl,
1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1860 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1861 u32 engine_clock,
1862 SISLANDS_SMC_SCLK_VALUE *sclk);
1863
1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1867
si_get_pi(struct amdgpu_device * adev)1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1869 {
1870 struct si_power_info *pi = adev->pm.dpm.priv;
1871 return pi;
1872 }
1873
si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 ileakage,u32 * leakage)1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1875 u16 v, s32 t, u32 ileakage, u32 *leakage)
1876 {
1877 s64 kt, kv, leakage_w, i_leakage, vddc;
1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1879 s64 tmp;
1880
1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1882 vddc = div64_s64(drm_int2fixp(v), 1000);
1883 temperature = div64_s64(drm_int2fixp(t), 1000);
1884
1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1889 t_ref = drm_int2fixp(coeff->t_ref);
1890
1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1895
1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1897
1898 *leakage = drm_fixp2int(leakage_w * 1000);
1899 }
1900
si_calculate_leakage_for_v_and_t(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 i_leakage,u32 * leakage)1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1902 const struct ni_leakage_coeffients *coeff,
1903 u16 v,
1904 s32 t,
1905 u32 i_leakage,
1906 u32 *leakage)
1907 {
1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1909 }
1910
si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 ileakage,u32 * leakage)1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1912 const u32 fixed_kt, u16 v,
1913 u32 ileakage, u32 *leakage)
1914 {
1915 s64 kt, kv, leakage_w, i_leakage, vddc;
1916
1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1918 vddc = div64_s64(drm_int2fixp(v), 1000);
1919
1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1923
1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1925
1926 *leakage = drm_fixp2int(leakage_w * 1000);
1927 }
1928
si_calculate_leakage_for_v(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 i_leakage,u32 * leakage)1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1930 const struct ni_leakage_coeffients *coeff,
1931 const u32 fixed_kt,
1932 u16 v,
1933 u32 i_leakage,
1934 u32 *leakage)
1935 {
1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1937 }
1938
1939
si_update_dte_from_pl2(struct amdgpu_device * adev,struct si_dte_data * dte_data)1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1941 struct si_dte_data *dte_data)
1942 {
1943 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1945 u32 k = dte_data->k;
1946 u32 t_max = dte_data->max_t;
1947 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1948 u32 t_0 = dte_data->t0;
1949 u32 i;
1950
1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1952 dte_data->tdep_count = 3;
1953
1954 for (i = 0; i < k; i++) {
1955 dte_data->r[i] =
1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1957 (p_limit2 * (u32)100);
1958 }
1959
1960 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1961
1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1963 dte_data->tdep_r[i] = dte_data->r[4];
1964 }
1965 } else {
1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1967 }
1968 }
1969
rv770_get_pi(struct amdgpu_device * adev)1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1971 {
1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1973
1974 return pi;
1975 }
1976
ni_get_pi(struct amdgpu_device * adev)1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1978 {
1979 struct ni_power_info *pi = adev->pm.dpm.priv;
1980
1981 return pi;
1982 }
1983
si_get_ps(struct amdgpu_ps * aps)1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1985 {
1986 struct si_ps *ps = aps->ps_priv;
1987
1988 return ps;
1989 }
1990
si_initialize_powertune_defaults(struct amdgpu_device * adev)1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1992 {
1993 struct ni_power_info *ni_pi = ni_get_pi(adev);
1994 struct si_power_info *si_pi = si_get_pi(adev);
1995 bool update_dte_from_pl2 = false;
1996
1997 if (adev->asic_type == CHIP_TAHITI) {
1998 si_pi->cac_weights = cac_weights_tahiti;
1999 si_pi->lcac_config = lcac_tahiti;
2000 si_pi->cac_override = cac_override_tahiti;
2001 si_pi->powertune_data = &powertune_data_tahiti;
2002 si_pi->dte_data = dte_data_tahiti;
2003
2004 switch (adev->pdev->device) {
2005 case 0x6798:
2006 si_pi->dte_data.enable_dte_by_default = true;
2007 break;
2008 case 0x6799:
2009 si_pi->dte_data = dte_data_new_zealand;
2010 break;
2011 case 0x6790:
2012 case 0x6791:
2013 case 0x6792:
2014 case 0x679E:
2015 si_pi->dte_data = dte_data_aruba_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x679B:
2019 si_pi->dte_data = dte_data_malta;
2020 update_dte_from_pl2 = true;
2021 break;
2022 case 0x679A:
2023 si_pi->dte_data = dte_data_tahiti_pro;
2024 update_dte_from_pl2 = true;
2025 break;
2026 default:
2027 if (si_pi->dte_data.enable_dte_by_default == true)
2028 DRM_ERROR("DTE is not enabled!\n");
2029 break;
2030 }
2031 } else if (adev->asic_type == CHIP_PITCAIRN) {
2032 si_pi->cac_weights = cac_weights_pitcairn;
2033 si_pi->lcac_config = lcac_pitcairn;
2034 si_pi->cac_override = cac_override_pitcairn;
2035 si_pi->powertune_data = &powertune_data_pitcairn;
2036
2037 switch (adev->pdev->device) {
2038 case 0x6810:
2039 case 0x6818:
2040 si_pi->dte_data = dte_data_curacao_xt;
2041 update_dte_from_pl2 = true;
2042 break;
2043 case 0x6819:
2044 case 0x6811:
2045 si_pi->dte_data = dte_data_curacao_pro;
2046 update_dte_from_pl2 = true;
2047 break;
2048 case 0x6800:
2049 case 0x6806:
2050 si_pi->dte_data = dte_data_neptune_xt;
2051 update_dte_from_pl2 = true;
2052 break;
2053 default:
2054 si_pi->dte_data = dte_data_pitcairn;
2055 break;
2056 }
2057 } else if (adev->asic_type == CHIP_VERDE) {
2058 si_pi->lcac_config = lcac_cape_verde;
2059 si_pi->cac_override = cac_override_cape_verde;
2060 si_pi->powertune_data = &powertune_data_cape_verde;
2061
2062 switch (adev->pdev->device) {
2063 case 0x683B:
2064 case 0x683F:
2065 case 0x6829:
2066 case 0x6835:
2067 si_pi->cac_weights = cac_weights_cape_verde_pro;
2068 si_pi->dte_data = dte_data_cape_verde;
2069 break;
2070 case 0x682C:
2071 si_pi->cac_weights = cac_weights_cape_verde_pro;
2072 si_pi->dte_data = dte_data_sun_xt;
2073 update_dte_from_pl2 = true;
2074 break;
2075 case 0x6825:
2076 case 0x6827:
2077 si_pi->cac_weights = cac_weights_heathrow;
2078 si_pi->dte_data = dte_data_cape_verde;
2079 break;
2080 case 0x6824:
2081 case 0x682D:
2082 si_pi->cac_weights = cac_weights_chelsea_xt;
2083 si_pi->dte_data = dte_data_cape_verde;
2084 break;
2085 case 0x682F:
2086 si_pi->cac_weights = cac_weights_chelsea_pro;
2087 si_pi->dte_data = dte_data_cape_verde;
2088 break;
2089 case 0x6820:
2090 si_pi->cac_weights = cac_weights_heathrow;
2091 si_pi->dte_data = dte_data_venus_xtx;
2092 break;
2093 case 0x6821:
2094 si_pi->cac_weights = cac_weights_heathrow;
2095 si_pi->dte_data = dte_data_venus_xt;
2096 break;
2097 case 0x6823:
2098 case 0x682B:
2099 case 0x6822:
2100 case 0x682A:
2101 si_pi->cac_weights = cac_weights_chelsea_pro;
2102 si_pi->dte_data = dte_data_venus_pro;
2103 break;
2104 default:
2105 si_pi->cac_weights = cac_weights_cape_verde;
2106 si_pi->dte_data = dte_data_cape_verde;
2107 break;
2108 }
2109 } else if (adev->asic_type == CHIP_OLAND) {
2110 si_pi->lcac_config = lcac_mars_pro;
2111 si_pi->cac_override = cac_override_oland;
2112 si_pi->powertune_data = &powertune_data_mars_pro;
2113 si_pi->dte_data = dte_data_mars_pro;
2114
2115 switch (adev->pdev->device) {
2116 case 0x6601:
2117 case 0x6621:
2118 case 0x6603:
2119 case 0x6605:
2120 si_pi->cac_weights = cac_weights_mars_pro;
2121 update_dte_from_pl2 = true;
2122 break;
2123 case 0x6600:
2124 case 0x6606:
2125 case 0x6620:
2126 case 0x6604:
2127 si_pi->cac_weights = cac_weights_mars_xt;
2128 update_dte_from_pl2 = true;
2129 break;
2130 case 0x6611:
2131 case 0x6613:
2132 case 0x6608:
2133 si_pi->cac_weights = cac_weights_oland_pro;
2134 update_dte_from_pl2 = true;
2135 break;
2136 case 0x6610:
2137 si_pi->cac_weights = cac_weights_oland_xt;
2138 update_dte_from_pl2 = true;
2139 break;
2140 default:
2141 si_pi->cac_weights = cac_weights_oland;
2142 si_pi->lcac_config = lcac_oland;
2143 si_pi->cac_override = cac_override_oland;
2144 si_pi->powertune_data = &powertune_data_oland;
2145 si_pi->dte_data = dte_data_oland;
2146 break;
2147 }
2148 } else if (adev->asic_type == CHIP_HAINAN) {
2149 si_pi->cac_weights = cac_weights_hainan;
2150 si_pi->lcac_config = lcac_oland;
2151 si_pi->cac_override = cac_override_oland;
2152 si_pi->powertune_data = &powertune_data_hainan;
2153 si_pi->dte_data = dte_data_sun_xt;
2154 update_dte_from_pl2 = true;
2155 } else {
2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2157 return;
2158 }
2159
2160 ni_pi->enable_power_containment = false;
2161 ni_pi->enable_cac = false;
2162 ni_pi->enable_sq_ramping = false;
2163 si_pi->enable_dte = false;
2164
2165 if (si_pi->powertune_data->enable_powertune_by_default) {
2166 ni_pi->enable_power_containment = true;
2167 ni_pi->enable_cac = true;
2168 if (si_pi->dte_data.enable_dte_by_default) {
2169 si_pi->enable_dte = true;
2170 if (update_dte_from_pl2)
2171 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2172
2173 }
2174 ni_pi->enable_sq_ramping = true;
2175 }
2176
2177 ni_pi->driver_calculate_cac_leakage = true;
2178 ni_pi->cac_configuration_required = true;
2179
2180 if (ni_pi->cac_configuration_required) {
2181 ni_pi->support_cac_long_term_average = true;
2182 si_pi->dyn_powertune_data.l2_lta_window_size =
2183 si_pi->powertune_data->l2_lta_window_size_default;
2184 si_pi->dyn_powertune_data.lts_truncate =
2185 si_pi->powertune_data->lts_truncate_default;
2186 } else {
2187 ni_pi->support_cac_long_term_average = false;
2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2189 si_pi->dyn_powertune_data.lts_truncate = 0;
2190 }
2191
2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2193 }
2194
si_get_smc_power_scaling_factor(struct amdgpu_device * adev)2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2196 {
2197 return 1;
2198 }
2199
si_calculate_cac_wintime(struct amdgpu_device * adev)2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2201 {
2202 u32 xclk;
2203 u32 wintime;
2204 u32 cac_window;
2205 u32 cac_window_size;
2206
2207 xclk = amdgpu_asic_get_xclk(adev);
2208
2209 if (xclk == 0)
2210 return 0;
2211
2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK;
2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2214
2215 wintime = (cac_window_size * 100) / xclk;
2216
2217 return wintime;
2218 }
2219
si_scale_power_for_smc(u32 power_in_watts,u32 scaling_factor)2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2221 {
2222 return power_in_watts;
2223 }
2224
si_calculate_adjusted_tdp_limits(struct amdgpu_device * adev,bool adjust_polarity,u32 tdp_adjustment,u32 * tdp_limit,u32 * near_tdp_limit)2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2226 bool adjust_polarity,
2227 u32 tdp_adjustment,
2228 u32 *tdp_limit,
2229 u32 *near_tdp_limit)
2230 {
2231 u32 adjustment_delta, max_tdp_limit;
2232
2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2234 return -EINVAL;
2235
2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2237
2238 if (adjust_polarity) {
2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2241 } else {
2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2246 else
2247 *near_tdp_limit = 0;
2248 }
2249
2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2251 return -EINVAL;
2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2253 return -EINVAL;
2254
2255 return 0;
2256 }
2257
si_populate_smc_tdp_limits(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2259 struct amdgpu_ps *amdgpu_state)
2260 {
2261 struct ni_power_info *ni_pi = ni_get_pi(adev);
2262 struct si_power_info *si_pi = si_get_pi(adev);
2263
2264 if (ni_pi->enable_power_containment) {
2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2266 PP_SIslands_PAPMParameters *papm_parm;
2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2269 u32 tdp_limit;
2270 u32 near_tdp_limit;
2271 int ret;
2272
2273 if (scaling_factor == 0)
2274 return -EINVAL;
2275
2276 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2277
2278 ret = si_calculate_adjusted_tdp_limits(adev,
2279 false, /* ??? */
2280 adev->pm.dpm.tdp_adjustment,
2281 &tdp_limit,
2282 &near_tdp_limit);
2283 if (ret)
2284 return ret;
2285
2286 smc_table->dpm2Params.TDPLimit =
2287 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2288 smc_table->dpm2Params.NearTDPLimit =
2289 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2290 smc_table->dpm2Params.SafePowerLimit =
2291 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2292
2293 ret = amdgpu_si_copy_bytes_to_smc(adev,
2294 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2295 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2296 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2297 sizeof(u32) * 3,
2298 si_pi->sram_end);
2299 if (ret)
2300 return ret;
2301
2302 if (si_pi->enable_ppm) {
2303 papm_parm = &si_pi->papm_parm;
2304 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2305 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2306 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2307 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2308 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2309 papm_parm->PlatformPowerLimit = 0xffffffff;
2310 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2311
2312 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2313 (u8 *)papm_parm,
2314 sizeof(PP_SIslands_PAPMParameters),
2315 si_pi->sram_end);
2316 if (ret)
2317 return ret;
2318 }
2319 }
2320 return 0;
2321 }
2322
si_populate_smc_tdp_limits_2(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2323 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2324 struct amdgpu_ps *amdgpu_state)
2325 {
2326 struct ni_power_info *ni_pi = ni_get_pi(adev);
2327 struct si_power_info *si_pi = si_get_pi(adev);
2328
2329 if (ni_pi->enable_power_containment) {
2330 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2331 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2332 int ret;
2333
2334 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2335
2336 smc_table->dpm2Params.NearTDPLimit =
2337 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2338 smc_table->dpm2Params.SafePowerLimit =
2339 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2340
2341 ret = amdgpu_si_copy_bytes_to_smc(adev,
2342 (si_pi->state_table_start +
2343 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2344 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2345 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2346 sizeof(u32) * 2,
2347 si_pi->sram_end);
2348 if (ret)
2349 return ret;
2350 }
2351
2352 return 0;
2353 }
2354
si_calculate_power_efficiency_ratio(struct amdgpu_device * adev,const u16 prev_std_vddc,const u16 curr_std_vddc)2355 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2356 const u16 prev_std_vddc,
2357 const u16 curr_std_vddc)
2358 {
2359 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2360 u64 prev_vddc = (u64)prev_std_vddc;
2361 u64 curr_vddc = (u64)curr_std_vddc;
2362 u64 pwr_efficiency_ratio, n, d;
2363
2364 if ((prev_vddc == 0) || (curr_vddc == 0))
2365 return 0;
2366
2367 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2368 d = prev_vddc * prev_vddc;
2369 pwr_efficiency_ratio = div64_u64(n, d);
2370
2371 if (pwr_efficiency_ratio > (u64)0xFFFF)
2372 return 0;
2373
2374 return (u16)pwr_efficiency_ratio;
2375 }
2376
si_should_disable_uvd_powertune(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2377 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2378 struct amdgpu_ps *amdgpu_state)
2379 {
2380 struct si_power_info *si_pi = si_get_pi(adev);
2381
2382 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2383 amdgpu_state->vclk && amdgpu_state->dclk)
2384 return true;
2385
2386 return false;
2387 }
2388
evergreen_get_pi(struct amdgpu_device * adev)2389 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2390 {
2391 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2392
2393 return pi;
2394 }
2395
si_populate_power_containment_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2396 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2397 struct amdgpu_ps *amdgpu_state,
2398 SISLANDS_SMC_SWSTATE *smc_state)
2399 {
2400 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2401 struct ni_power_info *ni_pi = ni_get_pi(adev);
2402 struct si_ps *state = si_get_ps(amdgpu_state);
2403 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2404 u32 prev_sclk;
2405 u32 max_sclk;
2406 u32 min_sclk;
2407 u16 prev_std_vddc;
2408 u16 curr_std_vddc;
2409 int i;
2410 u16 pwr_efficiency_ratio;
2411 u8 max_ps_percent;
2412 bool disable_uvd_power_tune;
2413 int ret;
2414
2415 if (ni_pi->enable_power_containment == false)
2416 return 0;
2417
2418 if (state->performance_level_count == 0)
2419 return -EINVAL;
2420
2421 if (smc_state->levelCount != state->performance_level_count)
2422 return -EINVAL;
2423
2424 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2425
2426 smc_state->levels[0].dpm2.MaxPS = 0;
2427 smc_state->levels[0].dpm2.NearTDPDec = 0;
2428 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2429 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2430 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2431
2432 for (i = 1; i < state->performance_level_count; i++) {
2433 prev_sclk = state->performance_levels[i-1].sclk;
2434 max_sclk = state->performance_levels[i].sclk;
2435 if (i == 1)
2436 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2437 else
2438 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2439
2440 if (prev_sclk > max_sclk)
2441 return -EINVAL;
2442
2443 if ((max_ps_percent == 0) ||
2444 (prev_sclk == max_sclk) ||
2445 disable_uvd_power_tune)
2446 min_sclk = max_sclk;
2447 else if (i == 1)
2448 min_sclk = prev_sclk;
2449 else
2450 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2451
2452 if (min_sclk < state->performance_levels[0].sclk)
2453 min_sclk = state->performance_levels[0].sclk;
2454
2455 if (min_sclk == 0)
2456 return -EINVAL;
2457
2458 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2459 state->performance_levels[i-1].vddc, &vddc);
2460 if (ret)
2461 return ret;
2462
2463 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2464 if (ret)
2465 return ret;
2466
2467 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2468 state->performance_levels[i].vddc, &vddc);
2469 if (ret)
2470 return ret;
2471
2472 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2473 if (ret)
2474 return ret;
2475
2476 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2477 prev_std_vddc, curr_std_vddc);
2478
2479 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2480 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2481 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2482 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2483 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2484 }
2485
2486 return 0;
2487 }
2488
si_populate_sq_ramping_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2489 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2490 struct amdgpu_ps *amdgpu_state,
2491 SISLANDS_SMC_SWSTATE *smc_state)
2492 {
2493 struct ni_power_info *ni_pi = ni_get_pi(adev);
2494 struct si_ps *state = si_get_ps(amdgpu_state);
2495 u32 sq_power_throttle, sq_power_throttle2;
2496 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2497 int i;
2498
2499 if (state->performance_level_count == 0)
2500 return -EINVAL;
2501
2502 if (smc_state->levelCount != state->performance_level_count)
2503 return -EINVAL;
2504
2505 if (adev->pm.dpm.sq_ramping_threshold == 0)
2506 return -EINVAL;
2507
2508 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT))
2509 enable_sq_ramping = false;
2510
2511 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT))
2512 enable_sq_ramping = false;
2513
2514 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT))
2515 enable_sq_ramping = false;
2516
2517 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT))
2518 enable_sq_ramping = false;
2519
2520 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT))
2521 enable_sq_ramping = false;
2522
2523 for (i = 0; i < state->performance_level_count; i++) {
2524 sq_power_throttle = 0;
2525 sq_power_throttle2 = 0;
2526
2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2528 enable_sq_ramping) {
2529 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT;
2530 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT;
2531 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT;
2532 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT;
2533 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT;
2534 } else {
2535 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK |
2536 SQ_POWER_THROTTLE__MIN_POWER_MASK;
2537 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
2538 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
2539 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
2540 }
2541
2542 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2543 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2544 }
2545
2546 return 0;
2547 }
2548
si_enable_power_containment(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2549 static int si_enable_power_containment(struct amdgpu_device *adev,
2550 struct amdgpu_ps *amdgpu_new_state,
2551 bool enable)
2552 {
2553 struct ni_power_info *ni_pi = ni_get_pi(adev);
2554 PPSMC_Result smc_result;
2555 int ret = 0;
2556
2557 if (ni_pi->enable_power_containment) {
2558 if (enable) {
2559 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2560 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2561 if (smc_result != PPSMC_Result_OK)
2562 ret = -EINVAL;
2563 }
2564 } else {
2565 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2566 if (smc_result != PPSMC_Result_OK)
2567 ret = -EINVAL;
2568 }
2569 }
2570
2571 return ret;
2572 }
2573
si_initialize_smc_dte_tables(struct amdgpu_device * adev)2574 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2575 {
2576 struct si_power_info *si_pi = si_get_pi(adev);
2577 int ret = 0;
2578 struct si_dte_data *dte_data = &si_pi->dte_data;
2579 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2580 u32 table_size;
2581 u8 tdep_count;
2582 u32 i;
2583
2584 if (dte_data == NULL)
2585 si_pi->enable_dte = false;
2586
2587 if (si_pi->enable_dte == false)
2588 return 0;
2589
2590 if (dte_data->k <= 0)
2591 return -EINVAL;
2592
2593 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2594 if (dte_tables == NULL) {
2595 si_pi->enable_dte = false;
2596 return -ENOMEM;
2597 }
2598
2599 table_size = dte_data->k;
2600
2601 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2602 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2603
2604 tdep_count = dte_data->tdep_count;
2605 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2606 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2607
2608 dte_tables->K = cpu_to_be32(table_size);
2609 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2610 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2611 dte_tables->WindowSize = dte_data->window_size;
2612 dte_tables->temp_select = dte_data->temp_select;
2613 dte_tables->DTE_mode = dte_data->dte_mode;
2614 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2615
2616 if (tdep_count > 0)
2617 table_size--;
2618
2619 for (i = 0; i < table_size; i++) {
2620 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2621 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2622 }
2623
2624 dte_tables->Tdep_count = tdep_count;
2625
2626 for (i = 0; i < (u32)tdep_count; i++) {
2627 dte_tables->T_limits[i] = dte_data->t_limits[i];
2628 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2629 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2630 }
2631
2632 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2633 (u8 *)dte_tables,
2634 sizeof(Smc_SIslands_DTE_Configuration),
2635 si_pi->sram_end);
2636 kfree(dte_tables);
2637
2638 return ret;
2639 }
2640
si_get_cac_std_voltage_max_min(struct amdgpu_device * adev,u16 * max,u16 * min)2641 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2642 u16 *max, u16 *min)
2643 {
2644 struct si_power_info *si_pi = si_get_pi(adev);
2645 struct amdgpu_cac_leakage_table *table =
2646 &adev->pm.dpm.dyn_state.cac_leakage_table;
2647 u32 i;
2648 u32 v0_loadline;
2649
2650 if (table == NULL)
2651 return -EINVAL;
2652
2653 *max = 0;
2654 *min = 0xFFFF;
2655
2656 for (i = 0; i < table->count; i++) {
2657 if (table->entries[i].vddc > *max)
2658 *max = table->entries[i].vddc;
2659 if (table->entries[i].vddc < *min)
2660 *min = table->entries[i].vddc;
2661 }
2662
2663 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2664 return -EINVAL;
2665
2666 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2667
2668 if (v0_loadline > 0xFFFFUL)
2669 return -EINVAL;
2670
2671 *min = (u16)v0_loadline;
2672
2673 if ((*min > *max) || (*max == 0) || (*min == 0))
2674 return -EINVAL;
2675
2676 return 0;
2677 }
2678
si_get_cac_std_voltage_step(u16 max,u16 min)2679 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2680 {
2681 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2682 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2683 }
2684
si_init_dte_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step,u16 t0,u16 t_step)2685 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2686 PP_SIslands_CacConfig *cac_tables,
2687 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2688 u16 t0, u16 t_step)
2689 {
2690 struct si_power_info *si_pi = si_get_pi(adev);
2691 u32 leakage;
2692 unsigned int i, j;
2693 s32 t;
2694 u32 smc_leakage;
2695 u32 scaling_factor;
2696 u16 voltage;
2697
2698 scaling_factor = si_get_smc_power_scaling_factor(adev);
2699
2700 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2701 t = (1000 * (i * t_step + t0));
2702
2703 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2704 voltage = vddc_max - (vddc_step * j);
2705
2706 si_calculate_leakage_for_v_and_t(adev,
2707 &si_pi->powertune_data->leakage_coefficients,
2708 voltage,
2709 t,
2710 si_pi->dyn_powertune_data.cac_leakage,
2711 &leakage);
2712
2713 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2714
2715 if (smc_leakage > 0xFFFF)
2716 smc_leakage = 0xFFFF;
2717
2718 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2719 cpu_to_be16((u16)smc_leakage);
2720 }
2721 }
2722 return 0;
2723 }
2724
si_init_simplified_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step)2725 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2726 PP_SIslands_CacConfig *cac_tables,
2727 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2728 {
2729 struct si_power_info *si_pi = si_get_pi(adev);
2730 u32 leakage;
2731 unsigned int i, j;
2732 u32 smc_leakage;
2733 u32 scaling_factor;
2734 u16 voltage;
2735
2736 scaling_factor = si_get_smc_power_scaling_factor(adev);
2737
2738 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2739 voltage = vddc_max - (vddc_step * j);
2740
2741 si_calculate_leakage_for_v(adev,
2742 &si_pi->powertune_data->leakage_coefficients,
2743 si_pi->powertune_data->fixed_kt,
2744 voltage,
2745 si_pi->dyn_powertune_data.cac_leakage,
2746 &leakage);
2747
2748 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2749
2750 if (smc_leakage > 0xFFFF)
2751 smc_leakage = 0xFFFF;
2752
2753 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2754 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2755 cpu_to_be16((u16)smc_leakage);
2756 }
2757 return 0;
2758 }
2759
si_initialize_smc_cac_tables(struct amdgpu_device * adev)2760 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2761 {
2762 struct ni_power_info *ni_pi = ni_get_pi(adev);
2763 struct si_power_info *si_pi = si_get_pi(adev);
2764 PP_SIslands_CacConfig *cac_tables = NULL;
2765 u16 vddc_max, vddc_min, vddc_step;
2766 u16 t0, t_step;
2767 u32 load_line_slope, reg;
2768 int ret = 0;
2769 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2770
2771 if (ni_pi->enable_cac == false)
2772 return 0;
2773
2774 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2775 if (!cac_tables)
2776 return -ENOMEM;
2777
2778 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;
2779 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT);
2780 WREG32(mmCG_CAC_CTRL, reg);
2781
2782 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2783 si_pi->dyn_powertune_data.dc_pwr_value =
2784 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2785 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2786 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2787
2788 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2789
2790 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2791 if (ret)
2792 goto done_free;
2793
2794 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2795 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2796 t_step = 4;
2797 t0 = 60;
2798
2799 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2800 ret = si_init_dte_leakage_table(adev, cac_tables,
2801 vddc_max, vddc_min, vddc_step,
2802 t0, t_step);
2803 else
2804 ret = si_init_simplified_leakage_table(adev, cac_tables,
2805 vddc_max, vddc_min, vddc_step);
2806 if (ret)
2807 goto done_free;
2808
2809 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2810
2811 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2812 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2813 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2814 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2815 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2816 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2817 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2818 cac_tables->calculation_repeats = cpu_to_be32(2);
2819 cac_tables->dc_cac = cpu_to_be32(0);
2820 cac_tables->log2_PG_LKG_SCALE = 12;
2821 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2822 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2823 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2824
2825 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2826 (u8 *)cac_tables,
2827 sizeof(PP_SIslands_CacConfig),
2828 si_pi->sram_end);
2829
2830 if (ret)
2831 goto done_free;
2832
2833 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2834
2835 done_free:
2836 if (ret) {
2837 ni_pi->enable_cac = false;
2838 ni_pi->enable_power_containment = false;
2839 }
2840
2841 kfree(cac_tables);
2842
2843 return ret;
2844 }
2845
si_program_cac_config_registers(struct amdgpu_device * adev,const struct si_cac_config_reg * cac_config_regs)2846 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2847 const struct si_cac_config_reg *cac_config_regs)
2848 {
2849 const struct si_cac_config_reg *config_regs = cac_config_regs;
2850 u32 data = 0, offset;
2851
2852 if (!config_regs)
2853 return -EINVAL;
2854
2855 while (config_regs->offset != 0xFFFFFFFF) {
2856 switch (config_regs->type) {
2857 case SISLANDS_CACCONFIG_CGIND:
2858 offset = SMC_CG_IND_START + config_regs->offset;
2859 if (offset < SMC_CG_IND_END)
2860 data = RREG32_SMC(offset);
2861 break;
2862 default:
2863 data = RREG32(config_regs->offset);
2864 break;
2865 }
2866
2867 data &= ~config_regs->mask;
2868 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2869
2870 switch (config_regs->type) {
2871 case SISLANDS_CACCONFIG_CGIND:
2872 offset = SMC_CG_IND_START + config_regs->offset;
2873 if (offset < SMC_CG_IND_END)
2874 WREG32_SMC(offset, data);
2875 break;
2876 default:
2877 WREG32(config_regs->offset, data);
2878 break;
2879 }
2880 config_regs++;
2881 }
2882 return 0;
2883 }
2884
si_initialize_hardware_cac_manager(struct amdgpu_device * adev)2885 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2886 {
2887 struct ni_power_info *ni_pi = ni_get_pi(adev);
2888 struct si_power_info *si_pi = si_get_pi(adev);
2889 int ret;
2890
2891 if ((ni_pi->enable_cac == false) ||
2892 (ni_pi->cac_configuration_required == false))
2893 return 0;
2894
2895 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2896 if (ret)
2897 return ret;
2898 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2899 if (ret)
2900 return ret;
2901 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2902 if (ret)
2903 return ret;
2904
2905 return 0;
2906 }
2907
si_enable_smc_cac(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2908 static int si_enable_smc_cac(struct amdgpu_device *adev,
2909 struct amdgpu_ps *amdgpu_new_state,
2910 bool enable)
2911 {
2912 struct ni_power_info *ni_pi = ni_get_pi(adev);
2913 struct si_power_info *si_pi = si_get_pi(adev);
2914 PPSMC_Result smc_result;
2915 int ret = 0;
2916
2917 if (ni_pi->enable_cac) {
2918 if (enable) {
2919 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2920 if (ni_pi->support_cac_long_term_average) {
2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2922 if (smc_result != PPSMC_Result_OK)
2923 ni_pi->support_cac_long_term_average = false;
2924 }
2925
2926 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2927 if (smc_result != PPSMC_Result_OK) {
2928 ret = -EINVAL;
2929 ni_pi->cac_enabled = false;
2930 } else {
2931 ni_pi->cac_enabled = true;
2932 }
2933
2934 if (si_pi->enable_dte) {
2935 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2936 if (smc_result != PPSMC_Result_OK)
2937 ret = -EINVAL;
2938 }
2939 }
2940 } else if (ni_pi->cac_enabled) {
2941 if (si_pi->enable_dte)
2942 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2943
2944 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2945
2946 ni_pi->cac_enabled = false;
2947
2948 if (ni_pi->support_cac_long_term_average)
2949 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2950 }
2951 }
2952 return ret;
2953 }
2954
si_init_smc_spll_table(struct amdgpu_device * adev)2955 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2956 {
2957 struct ni_power_info *ni_pi = ni_get_pi(adev);
2958 struct si_power_info *si_pi = si_get_pi(adev);
2959 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2960 SISLANDS_SMC_SCLK_VALUE sclk_params;
2961 u32 fb_div, p_div;
2962 u32 clk_s, clk_v;
2963 u32 sclk = 0;
2964 int ret = 0;
2965 u32 tmp;
2966 int i;
2967
2968 if (si_pi->spll_table_start == 0)
2969 return -EINVAL;
2970
2971 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2972 if (spll_table == NULL)
2973 return -ENOMEM;
2974
2975 for (i = 0; i < 256; i++) {
2976 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2977 if (ret)
2978 break;
2979 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
2980 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
2981 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
2982 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
2983
2984 fb_div &= ~0x00001FFF;
2985 fb_div >>= 1;
2986 clk_v >>= 6;
2987
2988 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2989 ret = -EINVAL;
2990 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2991 ret = -EINVAL;
2992 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2993 ret = -EINVAL;
2994 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2995 ret = -EINVAL;
2996
2997 if (ret)
2998 break;
2999
3000 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
3001 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
3002 spll_table->freq[i] = cpu_to_be32(tmp);
3003
3004 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
3005 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
3006 spll_table->ss[i] = cpu_to_be32(tmp);
3007
3008 sclk += 512;
3009 }
3010
3011
3012 if (!ret)
3013 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3014 (u8 *)spll_table,
3015 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3016 si_pi->sram_end);
3017
3018 if (ret)
3019 ni_pi->enable_power_containment = false;
3020
3021 kfree(spll_table);
3022
3023 return ret;
3024 }
3025
si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device * adev,u16 vce_voltage)3026 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3027 u16 vce_voltage)
3028 {
3029 u16 highest_leakage = 0;
3030 struct si_power_info *si_pi = si_get_pi(adev);
3031 int i;
3032
3033 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3034 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3035 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3036 }
3037
3038 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3039 return highest_leakage;
3040
3041 return vce_voltage;
3042 }
3043
si_get_vce_clock_voltage(struct amdgpu_device * adev,u32 evclk,u32 ecclk,u16 * voltage)3044 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3045 u32 evclk, u32 ecclk, u16 *voltage)
3046 {
3047 u32 i;
3048 int ret = -EINVAL;
3049 struct amdgpu_vce_clock_voltage_dependency_table *table =
3050 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3051
3052 if (((evclk == 0) && (ecclk == 0)) ||
3053 (table && (table->count == 0))) {
3054 *voltage = 0;
3055 return 0;
3056 }
3057
3058 for (i = 0; i < table->count; i++) {
3059 if ((evclk <= table->entries[i].evclk) &&
3060 (ecclk <= table->entries[i].ecclk)) {
3061 *voltage = table->entries[i].v;
3062 ret = 0;
3063 break;
3064 }
3065 }
3066
3067 /* if no match return the highest voltage */
3068 if (ret)
3069 *voltage = table->entries[table->count - 1].v;
3070
3071 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3072
3073 return ret;
3074 }
3075
si_dpm_vblank_too_short(void * handle)3076 static bool si_dpm_vblank_too_short(void *handle)
3077 {
3078 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3079 u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time;
3080 /* we never hit the non-gddr5 limit so disable it */
3081 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3082
3083 /* Consider zero vblank time too short and disable MCLK switching.
3084 * Note that the vblank time is set to maximum when no displays are attached,
3085 * so we'll still enable MCLK switching in that case.
3086 */
3087 if (vblank_time == 0)
3088 return true;
3089 else if (vblank_time < switch_limit)
3090 return true;
3091 else
3092 return false;
3093
3094 }
3095
ni_copy_and_switch_arb_sets(struct amdgpu_device * adev,u32 arb_freq_src,u32 arb_freq_dest)3096 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3097 u32 arb_freq_src, u32 arb_freq_dest)
3098 {
3099 u32 mc_arb_dram_timing;
3100 u32 mc_arb_dram_timing2;
3101 u32 burst_time;
3102 u32 mc_cg_config;
3103
3104 switch (arb_freq_src) {
3105 case MC_CG_ARB_FREQ_F0:
3106 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3107 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3108 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3109 break;
3110 case MC_CG_ARB_FREQ_F1:
3111 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3113 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3114 break;
3115 case MC_CG_ARB_FREQ_F2:
3116 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3117 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3118 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3119 break;
3120 case MC_CG_ARB_FREQ_F3:
3121 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3122 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3123 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3124 break;
3125 default:
3126 return -EINVAL;
3127 }
3128
3129 switch (arb_freq_dest) {
3130 case MC_CG_ARB_FREQ_F0:
3131 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3132 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3133 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3134 break;
3135 case MC_CG_ARB_FREQ_F1:
3136 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3137 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3138 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3139 break;
3140 case MC_CG_ARB_FREQ_F2:
3141 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3142 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3143 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3144 break;
3145 case MC_CG_ARB_FREQ_F3:
3146 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3147 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3148 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3149 break;
3150 default:
3151 return -EINVAL;
3152 }
3153
3154 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3155 WREG32(MC_CG_CONFIG, mc_cg_config);
3156 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3157
3158 return 0;
3159 }
3160
ni_update_current_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3161 static void ni_update_current_ps(struct amdgpu_device *adev,
3162 struct amdgpu_ps *rps)
3163 {
3164 struct si_ps *new_ps = si_get_ps(rps);
3165 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3166 struct ni_power_info *ni_pi = ni_get_pi(adev);
3167
3168 eg_pi->current_rps = *rps;
3169 ni_pi->current_ps = *new_ps;
3170 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3171 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3172 }
3173
ni_update_requested_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3174 static void ni_update_requested_ps(struct amdgpu_device *adev,
3175 struct amdgpu_ps *rps)
3176 {
3177 struct si_ps *new_ps = si_get_ps(rps);
3178 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3179 struct ni_power_info *ni_pi = ni_get_pi(adev);
3180
3181 eg_pi->requested_rps = *rps;
3182 ni_pi->requested_ps = *new_ps;
3183 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3184 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3185 }
3186
ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3187 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3188 struct amdgpu_ps *new_ps,
3189 struct amdgpu_ps *old_ps)
3190 {
3191 struct si_ps *new_state = si_get_ps(new_ps);
3192 struct si_ps *current_state = si_get_ps(old_ps);
3193
3194 if ((new_ps->vclk == old_ps->vclk) &&
3195 (new_ps->dclk == old_ps->dclk))
3196 return;
3197
3198 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3199 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3200 return;
3201
3202 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3203 }
3204
ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3205 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3206 struct amdgpu_ps *new_ps,
3207 struct amdgpu_ps *old_ps)
3208 {
3209 struct si_ps *new_state = si_get_ps(new_ps);
3210 struct si_ps *current_state = si_get_ps(old_ps);
3211
3212 if ((new_ps->vclk == old_ps->vclk) &&
3213 (new_ps->dclk == old_ps->dclk))
3214 return;
3215
3216 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3217 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3218 return;
3219
3220 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3221 }
3222
btc_find_voltage(struct atom_voltage_table * table,u16 voltage)3223 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3224 {
3225 unsigned int i;
3226
3227 for (i = 0; i < table->count; i++)
3228 if (voltage <= table->entries[i].value)
3229 return table->entries[i].value;
3230
3231 return table->entries[table->count - 1].value;
3232 }
3233
btc_find_valid_clock(struct amdgpu_clock_array * clocks,u32 max_clock,u32 requested_clock)3234 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3235 u32 max_clock, u32 requested_clock)
3236 {
3237 unsigned int i;
3238
3239 if ((clocks == NULL) || (clocks->count == 0))
3240 return (requested_clock < max_clock) ? requested_clock : max_clock;
3241
3242 for (i = 0; i < clocks->count; i++) {
3243 if (clocks->values[i] >= requested_clock)
3244 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3245 }
3246
3247 return (clocks->values[clocks->count - 1] < max_clock) ?
3248 clocks->values[clocks->count - 1] : max_clock;
3249 }
3250
btc_get_valid_mclk(struct amdgpu_device * adev,u32 max_mclk,u32 requested_mclk)3251 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3252 u32 max_mclk, u32 requested_mclk)
3253 {
3254 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3255 max_mclk, requested_mclk);
3256 }
3257
btc_get_valid_sclk(struct amdgpu_device * adev,u32 max_sclk,u32 requested_sclk)3258 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3259 u32 max_sclk, u32 requested_sclk)
3260 {
3261 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3262 max_sclk, requested_sclk);
3263 }
3264
btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table * table,u32 * max_clock)3265 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3266 u32 *max_clock)
3267 {
3268 u32 i, clock = 0;
3269
3270 if ((table == NULL) || (table->count == 0)) {
3271 *max_clock = clock;
3272 return;
3273 }
3274
3275 for (i = 0; i < table->count; i++) {
3276 if (clock < table->entries[i].clk)
3277 clock = table->entries[i].clk;
3278 }
3279 *max_clock = clock;
3280 }
3281
btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table * table,u32 clock,u16 max_voltage,u16 * voltage)3282 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3283 u32 clock, u16 max_voltage, u16 *voltage)
3284 {
3285 u32 i;
3286
3287 if ((table == NULL) || (table->count == 0))
3288 return;
3289
3290 for (i= 0; i < table->count; i++) {
3291 if (clock <= table->entries[i].clk) {
3292 if (*voltage < table->entries[i].v)
3293 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3294 table->entries[i].v : max_voltage);
3295 return;
3296 }
3297 }
3298
3299 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3300 }
3301
btc_adjust_clock_combinations(struct amdgpu_device * adev,const struct amdgpu_clock_and_voltage_limits * max_limits,struct rv7xx_pl * pl)3302 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3303 const struct amdgpu_clock_and_voltage_limits *max_limits,
3304 struct rv7xx_pl *pl)
3305 {
3306
3307 if ((pl->mclk == 0) || (pl->sclk == 0))
3308 return;
3309
3310 if (pl->mclk == pl->sclk)
3311 return;
3312
3313 if (pl->mclk > pl->sclk) {
3314 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3315 pl->sclk = btc_get_valid_sclk(adev,
3316 max_limits->sclk,
3317 (pl->mclk +
3318 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3319 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3320 } else {
3321 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3322 pl->mclk = btc_get_valid_mclk(adev,
3323 max_limits->mclk,
3324 pl->sclk -
3325 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3326 }
3327 }
3328
btc_apply_voltage_delta_rules(struct amdgpu_device * adev,u16 max_vddc,u16 max_vddci,u16 * vddc,u16 * vddci)3329 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3330 u16 max_vddc, u16 max_vddci,
3331 u16 *vddc, u16 *vddci)
3332 {
3333 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3334 u16 new_voltage;
3335
3336 if ((0 == *vddc) || (0 == *vddci))
3337 return;
3338
3339 if (*vddc > *vddci) {
3340 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3341 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3342 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3343 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3344 }
3345 } else {
3346 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3347 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3348 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3349 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3350 }
3351 }
3352 }
3353
r600_calculate_u_and_p(u32 i,u32 r_c,u32 p_b,u32 * p,u32 * u)3354 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3355 u32 *p, u32 *u)
3356 {
3357 u32 b_c = 0;
3358 u32 i_c;
3359 u32 tmp;
3360
3361 i_c = (i * r_c) / 100;
3362 tmp = i_c >> p_b;
3363
3364 while (tmp) {
3365 b_c++;
3366 tmp >>= 1;
3367 }
3368
3369 *u = (b_c + 1) / 2;
3370 *p = i_c / (1 << (2 * (*u)));
3371 }
3372
r600_calculate_at(u32 t,u32 h,u32 fh,u32 fl,u32 * tl,u32 * th)3373 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3374 {
3375 u32 k, a, ah, al;
3376 u32 t1;
3377
3378 if ((fl == 0) || (fh == 0) || (fl > fh))
3379 return -EINVAL;
3380
3381 k = (100 * fh) / fl;
3382 t1 = (t * (k - 100));
3383 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3384 a = (a + 5) / 10;
3385 ah = ((a * t) + 5000) / 10000;
3386 al = a - ah;
3387
3388 *th = t - ah;
3389 *tl = t + al;
3390
3391 return 0;
3392 }
3393
r600_is_uvd_state(u32 class,u32 class2)3394 static bool r600_is_uvd_state(u32 class, u32 class2)
3395 {
3396 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3397 return true;
3398 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3399 return true;
3400 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3401 return true;
3402 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3403 return true;
3404 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3405 return true;
3406 return false;
3407 }
3408
rv770_get_memory_module_index(struct amdgpu_device * adev)3409 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3410 {
3411 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3412 }
3413
rv770_get_max_vddc(struct amdgpu_device * adev)3414 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3415 {
3416 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3417 u16 vddc;
3418
3419 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3420 pi->max_vddc = 0;
3421 else
3422 pi->max_vddc = vddc;
3423 }
3424
rv770_get_engine_memory_ss(struct amdgpu_device * adev)3425 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3426 {
3427 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3428 struct amdgpu_atom_ss ss;
3429
3430 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3431 ASIC_INTERNAL_ENGINE_SS, 0);
3432 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3433 ASIC_INTERNAL_MEMORY_SS, 0);
3434
3435 if (pi->sclk_ss || pi->mclk_ss)
3436 pi->dynamic_ss = true;
3437 else
3438 pi->dynamic_ss = false;
3439 }
3440
3441
si_apply_state_adjust_rules(struct amdgpu_device * adev,struct amdgpu_ps * rps)3442 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3443 struct amdgpu_ps *rps)
3444 {
3445 const struct amd_pp_display_configuration *display_cfg =
3446 &adev->pm.pm_display_cfg;
3447 struct si_ps *ps = si_get_ps(rps);
3448 struct amdgpu_clock_and_voltage_limits *max_limits;
3449 bool disable_mclk_switching = false;
3450 bool disable_sclk_switching = false;
3451 u32 mclk, sclk;
3452 u16 vddc, vddci, min_vce_voltage = 0;
3453 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3454 u32 max_sclk = 0, max_mclk = 0;
3455 u32 high_pixelclock_count = 0;
3456 int i;
3457
3458 if (adev->asic_type == CHIP_HAINAN) {
3459 if ((adev->pdev->revision == 0x81) ||
3460 (adev->pdev->revision == 0xC3) ||
3461 (adev->pdev->device == 0x6664) ||
3462 (adev->pdev->device == 0x6665) ||
3463 (adev->pdev->device == 0x6667)) {
3464 max_sclk = 75000;
3465 }
3466 if ((adev->pdev->revision == 0xC3) ||
3467 (adev->pdev->device == 0x6665)) {
3468 max_sclk = 60000;
3469 max_mclk = 80000;
3470 }
3471 } else if (adev->asic_type == CHIP_OLAND) {
3472 if ((adev->pdev->revision == 0xC7) ||
3473 (adev->pdev->revision == 0x80) ||
3474 (adev->pdev->revision == 0x81) ||
3475 (adev->pdev->revision == 0x83) ||
3476 (adev->pdev->revision == 0x87) ||
3477 (adev->pdev->device == 0x6604) ||
3478 (adev->pdev->device == 0x6605)) {
3479 max_sclk = 75000;
3480 }
3481 }
3482
3483 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz.
3484 * For example, 4K 60Hz and 1080p 144Hz fall into this category.
3485 * Find number of such displays connected.
3486 */
3487 for (i = 0; i < display_cfg->num_display; i++) {
3488 /* The array only contains active displays. */
3489 if (display_cfg->displays[i].pixel_clock > 297000)
3490 high_pixelclock_count++;
3491 }
3492
3493 /* These are some ad-hoc fixes to some issues observed with SI GPUs.
3494 * They are necessary because we don't have something like dce_calcs
3495 * for these GPUs to calculate bandwidth requirements.
3496 */
3497 if (high_pixelclock_count) {
3498 /* Work around flickering lines at the bottom edge
3499 * of the screen when using a single 4K 60Hz monitor.
3500 */
3501 disable_mclk_switching = true;
3502
3503 /* On Oland, we observe some flickering when two 4K 60Hz
3504 * displays are connected, possibly because voltage is too low.
3505 * Raise the voltage by requiring a higher SCLK.
3506 * (Voltage cannot be adjusted independently without also SCLK.)
3507 */
3508 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND)
3509 disable_sclk_switching = true;
3510 }
3511
3512 if (rps->vce_active) {
3513 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3514 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3515 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3516 &min_vce_voltage);
3517 } else {
3518 rps->evclk = 0;
3519 rps->ecclk = 0;
3520 }
3521
3522 if ((adev->pm.pm_display_cfg.num_display > 1) ||
3523 si_dpm_vblank_too_short(adev))
3524 disable_mclk_switching = true;
3525
3526 if (rps->vclk || rps->dclk) {
3527 disable_mclk_switching = true;
3528 disable_sclk_switching = true;
3529 }
3530
3531 if (adev->pm.ac_power)
3532 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3533 else
3534 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3535
3536 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3537 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3538 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3539 }
3540 if (adev->pm.ac_power == false) {
3541 for (i = 0; i < ps->performance_level_count; i++) {
3542 if (ps->performance_levels[i].mclk > max_limits->mclk)
3543 ps->performance_levels[i].mclk = max_limits->mclk;
3544 if (ps->performance_levels[i].sclk > max_limits->sclk)
3545 ps->performance_levels[i].sclk = max_limits->sclk;
3546 if (ps->performance_levels[i].vddc > max_limits->vddc)
3547 ps->performance_levels[i].vddc = max_limits->vddc;
3548 if (ps->performance_levels[i].vddci > max_limits->vddci)
3549 ps->performance_levels[i].vddci = max_limits->vddci;
3550 }
3551 }
3552
3553 /* limit clocks to max supported clocks based on voltage dependency tables */
3554 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3555 &max_sclk_vddc);
3556 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3557 &max_mclk_vddci);
3558 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3559 &max_mclk_vddc);
3560
3561 for (i = 0; i < ps->performance_level_count; i++) {
3562 if (max_sclk_vddc) {
3563 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3564 ps->performance_levels[i].sclk = max_sclk_vddc;
3565 }
3566 if (max_mclk_vddci) {
3567 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3568 ps->performance_levels[i].mclk = max_mclk_vddci;
3569 }
3570 if (max_mclk_vddc) {
3571 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3572 ps->performance_levels[i].mclk = max_mclk_vddc;
3573 }
3574 if (max_mclk) {
3575 if (ps->performance_levels[i].mclk > max_mclk)
3576 ps->performance_levels[i].mclk = max_mclk;
3577 }
3578 if (max_sclk) {
3579 if (ps->performance_levels[i].sclk > max_sclk)
3580 ps->performance_levels[i].sclk = max_sclk;
3581 }
3582 }
3583
3584 /* XXX validate the min clocks required for display */
3585
3586 if (disable_mclk_switching) {
3587 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3588 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3589 } else {
3590 mclk = ps->performance_levels[0].mclk;
3591 vddci = ps->performance_levels[0].vddci;
3592 }
3593
3594 if (disable_sclk_switching) {
3595 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3596 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3597 } else {
3598 sclk = ps->performance_levels[0].sclk;
3599 vddc = ps->performance_levels[0].vddc;
3600 }
3601
3602 if (rps->vce_active) {
3603 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3604 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3605 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3606 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3607 }
3608
3609 /* adjusted low state */
3610 ps->performance_levels[0].sclk = sclk;
3611 ps->performance_levels[0].mclk = mclk;
3612 ps->performance_levels[0].vddc = vddc;
3613 ps->performance_levels[0].vddci = vddci;
3614
3615 if (disable_sclk_switching) {
3616 sclk = ps->performance_levels[0].sclk;
3617 for (i = 1; i < ps->performance_level_count; i++) {
3618 if (sclk < ps->performance_levels[i].sclk)
3619 sclk = ps->performance_levels[i].sclk;
3620 }
3621 for (i = 0; i < ps->performance_level_count; i++) {
3622 ps->performance_levels[i].sclk = sclk;
3623 ps->performance_levels[i].vddc = vddc;
3624 }
3625 } else {
3626 for (i = 1; i < ps->performance_level_count; i++) {
3627 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3628 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3629 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3630 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3631 }
3632 }
3633
3634 if (disable_mclk_switching) {
3635 mclk = ps->performance_levels[0].mclk;
3636 for (i = 1; i < ps->performance_level_count; i++) {
3637 if (mclk < ps->performance_levels[i].mclk)
3638 mclk = ps->performance_levels[i].mclk;
3639 }
3640 for (i = 0; i < ps->performance_level_count; i++) {
3641 ps->performance_levels[i].mclk = mclk;
3642 ps->performance_levels[i].vddci = vddci;
3643 }
3644 } else {
3645 for (i = 1; i < ps->performance_level_count; i++) {
3646 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3647 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3648 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3649 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3650 }
3651 }
3652
3653 for (i = 0; i < ps->performance_level_count; i++)
3654 btc_adjust_clock_combinations(adev, max_limits,
3655 &ps->performance_levels[i]);
3656
3657 for (i = 0; i < ps->performance_level_count; i++) {
3658 if (ps->performance_levels[i].vddc < min_vce_voltage)
3659 ps->performance_levels[i].vddc = min_vce_voltage;
3660 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3661 ps->performance_levels[i].sclk,
3662 max_limits->vddc, &ps->performance_levels[i].vddc);
3663 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3664 ps->performance_levels[i].mclk,
3665 max_limits->vddci, &ps->performance_levels[i].vddci);
3666 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3667 ps->performance_levels[i].mclk,
3668 max_limits->vddc, &ps->performance_levels[i].vddc);
3669 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3670 display_cfg->display_clk,
3671 max_limits->vddc, &ps->performance_levels[i].vddc);
3672 }
3673
3674 for (i = 0; i < ps->performance_level_count; i++) {
3675 btc_apply_voltage_delta_rules(adev,
3676 max_limits->vddc, max_limits->vddci,
3677 &ps->performance_levels[i].vddc,
3678 &ps->performance_levels[i].vddci);
3679 }
3680
3681 ps->dc_compatible = true;
3682 for (i = 0; i < ps->performance_level_count; i++) {
3683 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3684 ps->dc_compatible = false;
3685 }
3686 }
3687
3688 #if 0
3689 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3690 u16 reg_offset, u32 *value)
3691 {
3692 struct si_power_info *si_pi = si_get_pi(adev);
3693
3694 return amdgpu_si_read_smc_sram_dword(adev,
3695 si_pi->soft_regs_start + reg_offset, value,
3696 si_pi->sram_end);
3697 }
3698 #endif
3699
si_write_smc_soft_register(struct amdgpu_device * adev,u16 reg_offset,u32 value)3700 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3701 u16 reg_offset, u32 value)
3702 {
3703 struct si_power_info *si_pi = si_get_pi(adev);
3704
3705 return amdgpu_si_write_smc_sram_dword(adev,
3706 si_pi->soft_regs_start + reg_offset,
3707 value, si_pi->sram_end);
3708 }
3709
si_is_special_1gb_platform(struct amdgpu_device * adev)3710 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3711 {
3712 bool ret = false;
3713 u32 tmp, width, row, column, bank, density;
3714 bool is_memory_gddr5, is_special;
3715
3716 tmp = RREG32(MC_SEQ_MISC0);
3717 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3718 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3719 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3720
3721 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3722 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3723
3724 tmp = RREG32(mmMC_ARB_RAMCFG);
3725 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10;
3726 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8;
3727 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2;
3728
3729 density = (1 << (row + column - 20 + bank)) * width;
3730
3731 if ((adev->pdev->device == 0x6819) &&
3732 is_memory_gddr5 && is_special && (density == 0x400))
3733 ret = true;
3734
3735 return ret;
3736 }
3737
si_get_leakage_vddc(struct amdgpu_device * adev)3738 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3739 {
3740 struct si_power_info *si_pi = si_get_pi(adev);
3741 u16 vddc, count = 0;
3742 int i, ret;
3743
3744 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3745 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3746
3747 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3748 si_pi->leakage_voltage.entries[count].voltage = vddc;
3749 si_pi->leakage_voltage.entries[count].leakage_index =
3750 SISLANDS_LEAKAGE_INDEX0 + i;
3751 count++;
3752 }
3753 }
3754 si_pi->leakage_voltage.count = count;
3755 }
3756
si_get_leakage_voltage_from_leakage_index(struct amdgpu_device * adev,u32 index,u16 * leakage_voltage)3757 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3758 u32 index, u16 *leakage_voltage)
3759 {
3760 struct si_power_info *si_pi = si_get_pi(adev);
3761 int i;
3762
3763 if (leakage_voltage == NULL)
3764 return -EINVAL;
3765
3766 if ((index & 0xff00) != 0xff00)
3767 return -EINVAL;
3768
3769 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3770 return -EINVAL;
3771
3772 if (index < SISLANDS_LEAKAGE_INDEX0)
3773 return -EINVAL;
3774
3775 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3776 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3777 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3778 return 0;
3779 }
3780 }
3781 return -EAGAIN;
3782 }
3783
si_set_dpm_event_sources(struct amdgpu_device * adev,u32 sources)3784 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3785 {
3786 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3787 bool want_thermal_protection;
3788 enum si_dpm_event_src dpm_event_src;
3789
3790 switch (sources) {
3791 case 0:
3792 default:
3793 want_thermal_protection = false;
3794 break;
3795 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL):
3796 want_thermal_protection = true;
3797 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL;
3798 break;
3799 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3800 want_thermal_protection = true;
3801 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL;
3802 break;
3803 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3804 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3805 want_thermal_protection = true;
3806 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3807 break;
3808 }
3809
3810 if (want_thermal_protection) {
3811 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK);
3812 if (pi->thermal_protection)
3813 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3814 } else {
3815 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3816 }
3817 }
3818
si_enable_auto_throttle_source(struct amdgpu_device * adev,enum si_dpm_auto_throttle_src source,bool enable)3819 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3820 enum si_dpm_auto_throttle_src source,
3821 bool enable)
3822 {
3823 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3824
3825 if (enable) {
3826 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3827 pi->active_auto_throttle_sources |= 1 << source;
3828 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3829 }
3830 } else {
3831 if (pi->active_auto_throttle_sources & (1 << source)) {
3832 pi->active_auto_throttle_sources &= ~(1 << source);
3833 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3834 }
3835 }
3836 }
3837
si_start_dpm(struct amdgpu_device * adev)3838 static void si_start_dpm(struct amdgpu_device *adev)
3839 {
3840 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3841 }
3842
si_stop_dpm(struct amdgpu_device * adev)3843 static void si_stop_dpm(struct amdgpu_device *adev)
3844 {
3845 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3846 }
3847
si_enable_sclk_control(struct amdgpu_device * adev,bool enable)3848 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3849 {
3850 if (enable)
3851 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3852 else
3853 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3854
3855 }
3856
3857 #if 0
3858 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3859 u32 thermal_level)
3860 {
3861 PPSMC_Result ret;
3862
3863 if (thermal_level == 0) {
3864 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3865 if (ret == PPSMC_Result_OK)
3866 return 0;
3867 else
3868 return -EINVAL;
3869 }
3870 return 0;
3871 }
3872
3873 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3874 {
3875 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3876 }
3877 #endif
3878
3879 #if 0
3880 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3881 {
3882 if (ac_power)
3883 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3884 0 : -EINVAL;
3885
3886 return 0;
3887 }
3888 #endif
3889
si_send_msg_to_smc_with_parameter(struct amdgpu_device * adev,PPSMC_Msg msg,u32 parameter)3890 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3891 PPSMC_Msg msg, u32 parameter)
3892 {
3893 WREG32(mmSMC_SCRATCH0, parameter);
3894 return amdgpu_si_send_msg_to_smc(adev, msg);
3895 }
3896
si_restrict_performance_levels_before_switch(struct amdgpu_device * adev)3897 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3898 {
3899 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3900 return -EINVAL;
3901
3902 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3903 0 : -EINVAL;
3904 }
3905
si_dpm_force_performance_level(void * handle,enum amd_dpm_forced_level level)3906 static int si_dpm_force_performance_level(void *handle,
3907 enum amd_dpm_forced_level level)
3908 {
3909 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3910 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3911 struct si_ps *ps = si_get_ps(rps);
3912 u32 levels = ps->performance_level_count;
3913
3914 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3915 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3916 return -EINVAL;
3917
3918 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3919 return -EINVAL;
3920 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3921 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3922 return -EINVAL;
3923
3924 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3925 return -EINVAL;
3926 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3927 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3928 return -EINVAL;
3929
3930 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3931 return -EINVAL;
3932 }
3933
3934 adev->pm.dpm.forced_level = level;
3935
3936 return 0;
3937 }
3938
3939 #if 0
3940 static int si_set_boot_state(struct amdgpu_device *adev)
3941 {
3942 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3943 0 : -EINVAL;
3944 }
3945 #endif
3946
si_set_sw_state(struct amdgpu_device * adev)3947 static int si_set_sw_state(struct amdgpu_device *adev)
3948 {
3949 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3950 0 : -EINVAL;
3951 }
3952
si_halt_smc(struct amdgpu_device * adev)3953 static int si_halt_smc(struct amdgpu_device *adev)
3954 {
3955 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3956 return -EINVAL;
3957
3958 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3959 0 : -EINVAL;
3960 }
3961
si_resume_smc(struct amdgpu_device * adev)3962 static int si_resume_smc(struct amdgpu_device *adev)
3963 {
3964 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3965 return -EINVAL;
3966
3967 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3968 0 : -EINVAL;
3969 }
3970
si_dpm_start_smc(struct amdgpu_device * adev)3971 static void si_dpm_start_smc(struct amdgpu_device *adev)
3972 {
3973 amdgpu_si_program_jump_on_start(adev);
3974 amdgpu_si_start_smc(adev);
3975 amdgpu_si_smc_clock(adev, true);
3976 }
3977
si_dpm_stop_smc(struct amdgpu_device * adev)3978 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3979 {
3980 amdgpu_si_reset_smc(adev);
3981 amdgpu_si_smc_clock(adev, false);
3982 }
3983
si_process_firmware_header(struct amdgpu_device * adev)3984 static int si_process_firmware_header(struct amdgpu_device *adev)
3985 {
3986 struct si_power_info *si_pi = si_get_pi(adev);
3987 u32 tmp;
3988 int ret;
3989
3990 ret = amdgpu_si_read_smc_sram_dword(adev,
3991 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3992 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3993 &tmp, si_pi->sram_end);
3994 if (ret)
3995 return ret;
3996
3997 si_pi->state_table_start = tmp;
3998
3999 ret = amdgpu_si_read_smc_sram_dword(adev,
4000 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4001 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4002 &tmp, si_pi->sram_end);
4003 if (ret)
4004 return ret;
4005
4006 si_pi->soft_regs_start = tmp;
4007
4008 ret = amdgpu_si_read_smc_sram_dword(adev,
4009 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4010 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4011 &tmp, si_pi->sram_end);
4012 if (ret)
4013 return ret;
4014
4015 si_pi->mc_reg_table_start = tmp;
4016
4017 ret = amdgpu_si_read_smc_sram_dword(adev,
4018 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4019 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4020 &tmp, si_pi->sram_end);
4021 if (ret)
4022 return ret;
4023
4024 si_pi->fan_table_start = tmp;
4025
4026 ret = amdgpu_si_read_smc_sram_dword(adev,
4027 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4028 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4029 &tmp, si_pi->sram_end);
4030 if (ret)
4031 return ret;
4032
4033 si_pi->arb_table_start = tmp;
4034
4035 ret = amdgpu_si_read_smc_sram_dword(adev,
4036 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4037 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4038 &tmp, si_pi->sram_end);
4039 if (ret)
4040 return ret;
4041
4042 si_pi->cac_table_start = tmp;
4043
4044 ret = amdgpu_si_read_smc_sram_dword(adev,
4045 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4046 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4047 &tmp, si_pi->sram_end);
4048 if (ret)
4049 return ret;
4050
4051 si_pi->dte_table_start = tmp;
4052
4053 ret = amdgpu_si_read_smc_sram_dword(adev,
4054 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4055 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4056 &tmp, si_pi->sram_end);
4057 if (ret)
4058 return ret;
4059
4060 si_pi->spll_table_start = tmp;
4061
4062 ret = amdgpu_si_read_smc_sram_dword(adev,
4063 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4064 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4065 &tmp, si_pi->sram_end);
4066 if (ret)
4067 return ret;
4068
4069 si_pi->papm_cfg_table_start = tmp;
4070
4071 return ret;
4072 }
4073
si_read_clock_registers(struct amdgpu_device * adev)4074 static void si_read_clock_registers(struct amdgpu_device *adev)
4075 {
4076 struct si_power_info *si_pi = si_get_pi(adev);
4077
4078 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL);
4079 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2);
4080 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3);
4081 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4);
4082 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM);
4083 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2);
4084 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4085 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4086 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4087 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4088 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4089 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4090 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4091 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4092 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4093 }
4094
si_enable_thermal_protection(struct amdgpu_device * adev,bool enable)4095 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4096 bool enable)
4097 {
4098 if (enable)
4099 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4100 else
4101 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4102 }
4103
si_enable_acpi_power_management(struct amdgpu_device * adev)4104 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4105 {
4106 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK);
4107 }
4108
4109 #if 0
4110 static int si_enter_ulp_state(struct amdgpu_device *adev)
4111 {
4112 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4113
4114 udelay(25000);
4115
4116 return 0;
4117 }
4118
4119 static int si_exit_ulp_state(struct amdgpu_device *adev)
4120 {
4121 int i;
4122
4123 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4124
4125 udelay(7000);
4126
4127 for (i = 0; i < adev->usec_timeout; i++) {
4128 if (RREG32(SMC_RESP_0) == 1)
4129 break;
4130 udelay(1000);
4131 }
4132
4133 return 0;
4134 }
4135 #endif
4136
si_notify_smc_display_change(struct amdgpu_device * adev,bool has_display)4137 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4138 bool has_display)
4139 {
4140 PPSMC_Msg msg = has_display ?
4141 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4142
4143 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4144 0 : -EINVAL;
4145 }
4146
si_program_response_times(struct amdgpu_device * adev)4147 static void si_program_response_times(struct amdgpu_device *adev)
4148 {
4149 u32 voltage_response_time, acpi_delay_time, vbi_time_out;
4150 u32 vddc_dly, acpi_dly, vbi_dly;
4151 u32 reference_clock;
4152
4153 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4154
4155 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4156
4157 if (voltage_response_time == 0)
4158 voltage_response_time = 1000;
4159
4160 acpi_delay_time = 15000;
4161 vbi_time_out = 100000;
4162
4163 reference_clock = amdgpu_asic_get_xclk(adev);
4164
4165 vddc_dly = (voltage_response_time * reference_clock) / 100;
4166 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4167 vbi_dly = (vbi_time_out * reference_clock) / 100;
4168
4169 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4170 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4171 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4172 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4173 }
4174
si_program_ds_registers(struct amdgpu_device * adev)4175 static void si_program_ds_registers(struct amdgpu_device *adev)
4176 {
4177 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4178 u32 tmp;
4179
4180 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4181 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4182 tmp = 0x10;
4183 else
4184 tmp = 0x1;
4185
4186 if (eg_pi->sclk_deep_sleep) {
4187 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK);
4188 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK,
4189 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK);
4190 }
4191 }
4192
si_program_display_gap(struct amdgpu_device * adev)4193 static void si_program_display_gap(struct amdgpu_device *adev)
4194 {
4195 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
4196 u32 tmp, pipe;
4197
4198 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4199 if (cfg->num_display > 0)
4200 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4201 else
4202 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4203
4204 if (cfg->num_display > 1)
4205 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4206 else
4207 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4208
4209 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4210
4211 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4212 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4213
4214 if (cfg->num_display > 0 && pipe != cfg->crtc_index) {
4215 pipe = cfg->crtc_index;
4216
4217 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4218 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4219 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4220 }
4221
4222 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4223 * This can be a problem on PowerXpress systems or if you want to use the card
4224 * for offscreen rendering or compute if there are no crtcs enabled.
4225 */
4226 si_notify_smc_display_change(adev, cfg->num_display > 0);
4227 }
4228
si_enable_spread_spectrum(struct amdgpu_device * adev,bool enable)4229 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4230 {
4231 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4232
4233 if (enable) {
4234 if (pi->sclk_ss)
4235 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4236 } else {
4237 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
4238 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4239 }
4240 }
4241
si_setup_bsp(struct amdgpu_device * adev)4242 static void si_setup_bsp(struct amdgpu_device *adev)
4243 {
4244 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4245 u32 xclk = amdgpu_asic_get_xclk(adev);
4246
4247 r600_calculate_u_and_p(pi->asi,
4248 xclk,
4249 16,
4250 &pi->bsp,
4251 &pi->bsu);
4252
4253 r600_calculate_u_and_p(pi->pasi,
4254 xclk,
4255 16,
4256 &pi->pbsp,
4257 &pi->pbsu);
4258
4259
4260 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT);
4261 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT);
4262
4263 WREG32(mmCG_BSP, pi->dsp);
4264 }
4265
si_program_git(struct amdgpu_device * adev)4266 static void si_program_git(struct amdgpu_device *adev)
4267 {
4268 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK);
4269 }
4270
si_program_tp(struct amdgpu_device * adev)4271 static void si_program_tp(struct amdgpu_device *adev)
4272 {
4273 int i;
4274 enum r600_td td = R600_TD_DFLT;
4275
4276 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4277 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT));
4278
4279 if (td == R600_TD_AUTO)
4280 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4281 else
4282 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4283
4284 if (td == R600_TD_UP)
4285 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4286
4287 if (td == R600_TD_DOWN)
4288 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4289 }
4290
si_program_tpp(struct amdgpu_device * adev)4291 static void si_program_tpp(struct amdgpu_device *adev)
4292 {
4293 WREG32(mmCG_TPC, R600_TPC_DFLT);
4294 }
4295
si_program_sstp(struct amdgpu_device * adev)4296 static void si_program_sstp(struct amdgpu_device *adev)
4297 {
4298 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT));
4299 }
4300
si_enable_display_gap(struct amdgpu_device * adev)4301 static void si_enable_display_gap(struct amdgpu_device *adev)
4302 {
4303 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);
4304
4305 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4306 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT |
4307 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT);
4308
4309 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK);
4310 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT |
4311 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT);
4312 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4313 }
4314
si_program_vc(struct amdgpu_device * adev)4315 static void si_program_vc(struct amdgpu_device *adev)
4316 {
4317 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4318
4319 WREG32(mmCG_FTV, pi->vrc);
4320 }
4321
si_clear_vc(struct amdgpu_device * adev)4322 static void si_clear_vc(struct amdgpu_device *adev)
4323 {
4324 WREG32(mmCG_FTV, 0);
4325 }
4326
si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)4327 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4328 {
4329 u8 mc_para_index;
4330
4331 if (memory_clock < 10000)
4332 mc_para_index = 0;
4333 else if (memory_clock >= 80000)
4334 mc_para_index = 0x0f;
4335 else
4336 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4337 return mc_para_index;
4338 }
4339
si_get_mclk_frequency_ratio(u32 memory_clock,bool strobe_mode)4340 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4341 {
4342 u8 mc_para_index;
4343
4344 if (strobe_mode) {
4345 if (memory_clock < 12500)
4346 mc_para_index = 0x00;
4347 else if (memory_clock > 47500)
4348 mc_para_index = 0x0f;
4349 else
4350 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4351 } else {
4352 if (memory_clock < 65000)
4353 mc_para_index = 0x00;
4354 else if (memory_clock > 135000)
4355 mc_para_index = 0x0f;
4356 else
4357 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4358 }
4359 return mc_para_index;
4360 }
4361
si_get_strobe_mode_settings(struct amdgpu_device * adev,u32 mclk)4362 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4363 {
4364 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4365 bool strobe_mode = false;
4366 u8 result = 0;
4367
4368 if (mclk <= pi->mclk_strobe_mode_threshold)
4369 strobe_mode = true;
4370
4371 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4372 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4373 else
4374 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4375
4376 if (strobe_mode)
4377 result |= SISLANDS_SMC_STROBE_ENABLE;
4378
4379 return result;
4380 }
4381
si_upload_firmware(struct amdgpu_device * adev)4382 static int si_upload_firmware(struct amdgpu_device *adev)
4383 {
4384 struct si_power_info *si_pi = si_get_pi(adev);
4385
4386 amdgpu_si_reset_smc(adev);
4387 amdgpu_si_smc_clock(adev, false);
4388
4389 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4390 }
4391
si_validate_phase_shedding_tables(struct amdgpu_device * adev,const struct atom_voltage_table * table,const struct amdgpu_phase_shedding_limits_table * limits)4392 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4393 const struct atom_voltage_table *table,
4394 const struct amdgpu_phase_shedding_limits_table *limits)
4395 {
4396 u32 data, num_bits, num_levels;
4397
4398 if ((table == NULL) || (limits == NULL))
4399 return false;
4400
4401 data = table->mask_low;
4402
4403 num_bits = hweight32(data);
4404
4405 if (num_bits == 0)
4406 return false;
4407
4408 num_levels = (1 << num_bits);
4409
4410 if (table->count != num_levels)
4411 return false;
4412
4413 if (limits->count != (num_levels - 1))
4414 return false;
4415
4416 return true;
4417 }
4418
si_trim_voltage_table_to_fit_state_table(struct amdgpu_device * adev,u32 max_voltage_steps,struct atom_voltage_table * voltage_table)4419 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4420 u32 max_voltage_steps,
4421 struct atom_voltage_table *voltage_table)
4422 {
4423 unsigned int i, diff;
4424
4425 if (voltage_table->count <= max_voltage_steps)
4426 return;
4427
4428 diff = voltage_table->count - max_voltage_steps;
4429
4430 for (i= 0; i < max_voltage_steps; i++)
4431 voltage_table->entries[i] = voltage_table->entries[i + diff];
4432
4433 voltage_table->count = max_voltage_steps;
4434 }
4435
si_get_svi2_voltage_table(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * voltage_dependency_table,struct atom_voltage_table * voltage_table)4436 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4437 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4438 struct atom_voltage_table *voltage_table)
4439 {
4440 u32 i;
4441
4442 if (voltage_dependency_table == NULL)
4443 return -EINVAL;
4444
4445 voltage_table->mask_low = 0;
4446 voltage_table->phase_delay = 0;
4447
4448 voltage_table->count = voltage_dependency_table->count;
4449 for (i = 0; i < voltage_table->count; i++) {
4450 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4451 voltage_table->entries[i].smio_low = 0;
4452 }
4453
4454 return 0;
4455 }
4456
si_construct_voltage_tables(struct amdgpu_device * adev)4457 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4458 {
4459 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4460 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4461 struct si_power_info *si_pi = si_get_pi(adev);
4462 int ret;
4463
4464 if (pi->voltage_control) {
4465 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4466 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4467 if (ret)
4468 return ret;
4469
4470 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4471 si_trim_voltage_table_to_fit_state_table(adev,
4472 SISLANDS_MAX_NO_VREG_STEPS,
4473 &eg_pi->vddc_voltage_table);
4474 } else if (si_pi->voltage_control_svi2) {
4475 ret = si_get_svi2_voltage_table(adev,
4476 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4477 &eg_pi->vddc_voltage_table);
4478 if (ret)
4479 return ret;
4480 } else {
4481 return -EINVAL;
4482 }
4483
4484 if (eg_pi->vddci_control) {
4485 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4486 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4487 if (ret)
4488 return ret;
4489
4490 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4491 si_trim_voltage_table_to_fit_state_table(adev,
4492 SISLANDS_MAX_NO_VREG_STEPS,
4493 &eg_pi->vddci_voltage_table);
4494 }
4495 if (si_pi->vddci_control_svi2) {
4496 ret = si_get_svi2_voltage_table(adev,
4497 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4498 &eg_pi->vddci_voltage_table);
4499 if (ret)
4500 return ret;
4501 }
4502
4503 if (pi->mvdd_control) {
4504 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4505 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4506
4507 if (ret) {
4508 pi->mvdd_control = false;
4509 return ret;
4510 }
4511
4512 if (si_pi->mvdd_voltage_table.count == 0) {
4513 pi->mvdd_control = false;
4514 return -EINVAL;
4515 }
4516
4517 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4518 si_trim_voltage_table_to_fit_state_table(adev,
4519 SISLANDS_MAX_NO_VREG_STEPS,
4520 &si_pi->mvdd_voltage_table);
4521 }
4522
4523 if (si_pi->vddc_phase_shed_control) {
4524 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4525 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4526 if (ret)
4527 si_pi->vddc_phase_shed_control = false;
4528
4529 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4530 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4531 si_pi->vddc_phase_shed_control = false;
4532 }
4533
4534 return 0;
4535 }
4536
si_populate_smc_voltage_table(struct amdgpu_device * adev,const struct atom_voltage_table * voltage_table,SISLANDS_SMC_STATETABLE * table)4537 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4538 const struct atom_voltage_table *voltage_table,
4539 SISLANDS_SMC_STATETABLE *table)
4540 {
4541 unsigned int i;
4542
4543 for (i = 0; i < voltage_table->count; i++)
4544 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4545 }
4546
si_populate_smc_voltage_tables(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)4547 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4548 SISLANDS_SMC_STATETABLE *table)
4549 {
4550 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4551 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4552 struct si_power_info *si_pi = si_get_pi(adev);
4553 u8 i;
4554
4555 if (si_pi->voltage_control_svi2) {
4556 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4557 si_pi->svc_gpio_id);
4558 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4559 si_pi->svd_gpio_id);
4560 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4561 2);
4562 } else {
4563 if (eg_pi->vddc_voltage_table.count) {
4564 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4565 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4566 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4567
4568 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4569 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4570 table->maxVDDCIndexInPPTable = i;
4571 break;
4572 }
4573 }
4574 }
4575
4576 if (eg_pi->vddci_voltage_table.count) {
4577 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4578
4579 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4580 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4581 }
4582
4583
4584 if (si_pi->mvdd_voltage_table.count) {
4585 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4586
4587 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4588 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4589 }
4590
4591 if (si_pi->vddc_phase_shed_control) {
4592 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4593 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4594 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4595
4596 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4597 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4598
4599 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4600 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4601 } else {
4602 si_pi->vddc_phase_shed_control = false;
4603 }
4604 }
4605 }
4606
4607 return 0;
4608 }
4609
si_populate_voltage_value(struct amdgpu_device * adev,const struct atom_voltage_table * table,u16 value,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4610 static int si_populate_voltage_value(struct amdgpu_device *adev,
4611 const struct atom_voltage_table *table,
4612 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4613 {
4614 unsigned int i;
4615
4616 for (i = 0; i < table->count; i++) {
4617 if (value <= table->entries[i].value) {
4618 voltage->index = (u8)i;
4619 voltage->value = cpu_to_be16(table->entries[i].value);
4620 break;
4621 }
4622 }
4623
4624 if (i >= table->count)
4625 return -EINVAL;
4626
4627 return 0;
4628 }
4629
si_populate_mvdd_value(struct amdgpu_device * adev,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4630 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4631 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4632 {
4633 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4634 struct si_power_info *si_pi = si_get_pi(adev);
4635
4636 if (pi->mvdd_control) {
4637 if (mclk <= pi->mvdd_split_frequency)
4638 voltage->index = 0;
4639 else
4640 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4641
4642 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4643 }
4644 return 0;
4645 }
4646
si_get_std_voltage_value(struct amdgpu_device * adev,SISLANDS_SMC_VOLTAGE_VALUE * voltage,u16 * std_voltage)4647 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4648 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4649 u16 *std_voltage)
4650 {
4651 u16 v_index;
4652 bool voltage_found = false;
4653 *std_voltage = be16_to_cpu(voltage->value);
4654
4655 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4656 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4657 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4658 return -EINVAL;
4659
4660 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4661 if (be16_to_cpu(voltage->value) ==
4662 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4663 voltage_found = true;
4664 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4665 *std_voltage =
4666 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4667 else
4668 *std_voltage =
4669 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4670 break;
4671 }
4672 }
4673
4674 if (!voltage_found) {
4675 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4676 if (be16_to_cpu(voltage->value) <=
4677 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4678 voltage_found = true;
4679 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4680 *std_voltage =
4681 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4682 else
4683 *std_voltage =
4684 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4685 break;
4686 }
4687 }
4688 }
4689 } else {
4690 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4691 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4692 }
4693 }
4694
4695 return 0;
4696 }
4697
si_populate_std_voltage_value(struct amdgpu_device * adev,u16 value,u8 index,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4698 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4699 u16 value, u8 index,
4700 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4701 {
4702 voltage->index = index;
4703 voltage->value = cpu_to_be16(value);
4704
4705 return 0;
4706 }
4707
si_populate_phase_shedding_value(struct amdgpu_device * adev,const struct amdgpu_phase_shedding_limits_table * limits,u16 voltage,u32 sclk,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * smc_voltage)4708 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4709 const struct amdgpu_phase_shedding_limits_table *limits,
4710 u16 voltage, u32 sclk, u32 mclk,
4711 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4712 {
4713 unsigned int i;
4714
4715 for (i = 0; i < limits->count; i++) {
4716 if ((voltage <= limits->entries[i].voltage) &&
4717 (sclk <= limits->entries[i].sclk) &&
4718 (mclk <= limits->entries[i].mclk))
4719 break;
4720 }
4721
4722 smc_voltage->phase_settings = (u8)i;
4723
4724 return 0;
4725 }
4726
si_init_arb_table_index(struct amdgpu_device * adev)4727 static int si_init_arb_table_index(struct amdgpu_device *adev)
4728 {
4729 struct si_power_info *si_pi = si_get_pi(adev);
4730 u32 tmp;
4731 int ret;
4732
4733 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4734 &tmp, si_pi->sram_end);
4735 if (ret)
4736 return ret;
4737
4738 tmp &= 0x00FFFFFF;
4739 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4740
4741 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4742 tmp, si_pi->sram_end);
4743 }
4744
si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device * adev)4745 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4746 {
4747 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4748 }
4749
si_reset_to_default(struct amdgpu_device * adev)4750 static int si_reset_to_default(struct amdgpu_device *adev)
4751 {
4752 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4753 0 : -EINVAL;
4754 }
4755
si_force_switch_to_arb_f0(struct amdgpu_device * adev)4756 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4757 {
4758 struct si_power_info *si_pi = si_get_pi(adev);
4759 u32 tmp;
4760 int ret;
4761
4762 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4763 &tmp, si_pi->sram_end);
4764 if (ret)
4765 return ret;
4766
4767 tmp = (tmp >> 24) & 0xff;
4768
4769 if (tmp == MC_CG_ARB_FREQ_F0)
4770 return 0;
4771
4772 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4773 }
4774
si_calculate_memory_refresh_rate(struct amdgpu_device * adev,u32 engine_clock)4775 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4776 u32 engine_clock)
4777 {
4778 u32 dram_rows;
4779 u32 dram_refresh_rate;
4780 u32 mc_arb_rfsh_rate;
4781 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;
4782
4783 if (tmp >= 4)
4784 dram_rows = 16384;
4785 else
4786 dram_rows = 1 << (tmp + 10);
4787
4788 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4789 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4790
4791 return mc_arb_rfsh_rate;
4792 }
4793
si_populate_memory_timing_parameters(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCArbDramTimingRegisterSet * arb_regs)4794 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4795 struct rv7xx_pl *pl,
4796 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4797 {
4798 u32 dram_timing;
4799 u32 dram_timing2;
4800 u32 burst_time;
4801 int ret;
4802
4803 arb_regs->mc_arb_rfsh_rate =
4804 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4805
4806 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk,
4807 pl->mclk);
4808 if (ret)
4809 return ret;
4810
4811 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4812 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4813 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4814
4815 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4816 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4817 arb_regs->mc_arb_burst_time = (u8)burst_time;
4818
4819 return 0;
4820 }
4821
si_do_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,unsigned int first_arb_set)4822 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4823 struct amdgpu_ps *amdgpu_state,
4824 unsigned int first_arb_set)
4825 {
4826 struct si_power_info *si_pi = si_get_pi(adev);
4827 struct si_ps *state = si_get_ps(amdgpu_state);
4828 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4829 int i, ret = 0;
4830
4831 for (i = 0; i < state->performance_level_count; i++) {
4832 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4833 if (ret)
4834 break;
4835 ret = amdgpu_si_copy_bytes_to_smc(adev,
4836 si_pi->arb_table_start +
4837 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4838 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4839 (u8 *)&arb_regs,
4840 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4841 si_pi->sram_end);
4842 if (ret)
4843 break;
4844 }
4845
4846 return ret;
4847 }
4848
si_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)4849 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4850 struct amdgpu_ps *amdgpu_new_state)
4851 {
4852 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4853 SISLANDS_DRIVER_STATE_ARB_INDEX);
4854 }
4855
si_populate_initial_mvdd_value(struct amdgpu_device * adev,struct SISLANDS_SMC_VOLTAGE_VALUE * voltage)4856 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4857 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4858 {
4859 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4860 struct si_power_info *si_pi = si_get_pi(adev);
4861
4862 if (pi->mvdd_control)
4863 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4864 si_pi->mvdd_bootup_value, voltage);
4865
4866 return 0;
4867 }
4868
si_populate_smc_initial_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_initial_state,SISLANDS_SMC_STATETABLE * table)4869 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4870 struct amdgpu_ps *amdgpu_initial_state,
4871 SISLANDS_SMC_STATETABLE *table)
4872 {
4873 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4874 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4875 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4876 struct si_power_info *si_pi = si_get_pi(adev);
4877 u32 reg;
4878 int ret;
4879
4880 table->initialState.level.mclk.vDLL_CNTL =
4881 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4882 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4883 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4884 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4885 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4886 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4887 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4888 table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4889 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4890 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4891 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4892 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4893 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4894 table->initialState.level.mclk.vMPLL_SS =
4895 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4896 table->initialState.level.mclk.vMPLL_SS2 =
4897 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4898
4899 table->initialState.level.mclk.mclk_value =
4900 cpu_to_be32(initial_state->performance_levels[0].mclk);
4901
4902 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4903 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4904 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4905 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4906 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4907 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4908 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4909 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4910 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4911 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4912 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4913 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4914
4915 table->initialState.level.sclk.sclk_value =
4916 cpu_to_be32(initial_state->performance_levels[0].sclk);
4917
4918 table->initialState.level.arbRefreshState =
4919 SISLANDS_INITIAL_STATE_ARB_INDEX;
4920
4921 table->initialState.level.ACIndex = 0;
4922
4923 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4924 initial_state->performance_levels[0].vddc,
4925 &table->initialState.level.vddc);
4926
4927 if (!ret) {
4928 u16 std_vddc;
4929
4930 ret = si_get_std_voltage_value(adev,
4931 &table->initialState.level.vddc,
4932 &std_vddc);
4933 if (!ret)
4934 si_populate_std_voltage_value(adev, std_vddc,
4935 table->initialState.level.vddc.index,
4936 &table->initialState.level.std_vddc);
4937 }
4938
4939 if (eg_pi->vddci_control)
4940 si_populate_voltage_value(adev,
4941 &eg_pi->vddci_voltage_table,
4942 initial_state->performance_levels[0].vddci,
4943 &table->initialState.level.vddci);
4944
4945 if (si_pi->vddc_phase_shed_control)
4946 si_populate_phase_shedding_value(adev,
4947 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4948 initial_state->performance_levels[0].vddc,
4949 initial_state->performance_levels[0].sclk,
4950 initial_state->performance_levels[0].mclk,
4951 &table->initialState.level.vddc);
4952
4953 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd);
4954
4955 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
4956 table->initialState.level.aT = cpu_to_be32(reg);
4957 table->initialState.level.bSP = cpu_to_be32(pi->dsp);
4958 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4959
4960 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4961 table->initialState.level.strobeMode =
4962 si_get_strobe_mode_settings(adev,
4963 initial_state->performance_levels[0].mclk);
4964
4965 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4966 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4967 else
4968 table->initialState.level.mcFlags = 0;
4969 }
4970
4971 table->initialState.levelCount = 1;
4972
4973 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4974
4975 table->initialState.level.dpm2.MaxPS = 0;
4976 table->initialState.level.dpm2.NearTDPDec = 0;
4977 table->initialState.level.dpm2.AboveSafeInc = 0;
4978 table->initialState.level.dpm2.BelowSafeInc = 0;
4979 table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4980
4981 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK |
4982 SQ_POWER_THROTTLE__MAX_POWER_MASK;
4983 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4984
4985 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
4986 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
4987 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
4988 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4989
4990 return 0;
4991 }
4992
si_gen_pcie_gen_support(struct amdgpu_device * adev,u32 sys_mask,enum si_pcie_gen asic_gen,enum si_pcie_gen default_gen)4993 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev,
4994 u32 sys_mask,
4995 enum si_pcie_gen asic_gen,
4996 enum si_pcie_gen default_gen)
4997 {
4998 switch (asic_gen) {
4999 case SI_PCIE_GEN1:
5000 return SI_PCIE_GEN1;
5001 case SI_PCIE_GEN2:
5002 return SI_PCIE_GEN2;
5003 case SI_PCIE_GEN3:
5004 return SI_PCIE_GEN3;
5005 default:
5006 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
5007 (default_gen == SI_PCIE_GEN3))
5008 return SI_PCIE_GEN3;
5009 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
5010 (default_gen == SI_PCIE_GEN2))
5011 return SI_PCIE_GEN2;
5012 else
5013 return SI_PCIE_GEN1;
5014 }
5015 return SI_PCIE_GEN1;
5016 }
5017
si_populate_smc_acpi_state(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)5018 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5019 SISLANDS_SMC_STATETABLE *table)
5020 {
5021 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5022 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5023 struct si_power_info *si_pi = si_get_pi(adev);
5024 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5025 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5026 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5027 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5028 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5029 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5030 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5031 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5032 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5033 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5034 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5035 u32 reg;
5036 int ret;
5037
5038 table->ACPIState = table->initialState;
5039
5040 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5041
5042 if (pi->acpi_vddc) {
5043 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5044 pi->acpi_vddc, &table->ACPIState.level.vddc);
5045 if (!ret) {
5046 u16 std_vddc;
5047
5048 ret = si_get_std_voltage_value(adev,
5049 &table->ACPIState.level.vddc, &std_vddc);
5050 if (!ret)
5051 si_populate_std_voltage_value(adev, std_vddc,
5052 table->ACPIState.level.vddc.index,
5053 &table->ACPIState.level.std_vddc);
5054 }
5055 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
5056
5057 if (si_pi->vddc_phase_shed_control) {
5058 si_populate_phase_shedding_value(adev,
5059 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5060 pi->acpi_vddc,
5061 0,
5062 0,
5063 &table->ACPIState.level.vddc);
5064 }
5065 } else {
5066 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5067 pi->min_vddc_in_table, &table->ACPIState.level.vddc);
5068 if (!ret) {
5069 u16 std_vddc;
5070
5071 ret = si_get_std_voltage_value(adev,
5072 &table->ACPIState.level.vddc, &std_vddc);
5073
5074 if (!ret)
5075 si_populate_std_voltage_value(adev, std_vddc,
5076 table->ACPIState.level.vddc.index,
5077 &table->ACPIState.level.std_vddc);
5078 }
5079 table->ACPIState.level.gen2PCIE =
5080 (u8)si_gen_pcie_gen_support(adev,
5081 si_pi->sys_pcie_mask,
5082 si_pi->boot_pcie_gen,
5083 SI_PCIE_GEN1);
5084
5085 if (si_pi->vddc_phase_shed_control)
5086 si_populate_phase_shedding_value(adev,
5087 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5088 pi->min_vddc_in_table,
5089 0,
5090 0,
5091 &table->ACPIState.level.vddc);
5092 }
5093
5094 if (pi->acpi_vddc) {
5095 if (eg_pi->acpi_vddci)
5096 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5097 eg_pi->acpi_vddci,
5098 &table->ACPIState.level.vddci);
5099 }
5100
5101 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5102 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5103
5104 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5105
5106 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5107 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5108
5109 table->ACPIState.level.mclk.vDLL_CNTL =
5110 cpu_to_be32(dll_cntl);
5111 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
5112 cpu_to_be32(mclk_pwrmgt_cntl);
5113 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
5114 cpu_to_be32(mpll_ad_func_cntl);
5115 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
5116 cpu_to_be32(mpll_dq_func_cntl);
5117 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
5118 cpu_to_be32(mpll_func_cntl);
5119 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
5120 cpu_to_be32(mpll_func_cntl_1);
5121 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
5122 cpu_to_be32(mpll_func_cntl_2);
5123 table->ACPIState.level.mclk.vMPLL_SS =
5124 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5125 table->ACPIState.level.mclk.vMPLL_SS2 =
5126 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5127
5128 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
5129 cpu_to_be32(spll_func_cntl);
5130 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
5131 cpu_to_be32(spll_func_cntl_2);
5132 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
5133 cpu_to_be32(spll_func_cntl_3);
5134 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
5135 cpu_to_be32(spll_func_cntl_4);
5136
5137 table->ACPIState.level.mclk.mclk_value = 0;
5138 table->ACPIState.level.sclk.sclk_value = 0;
5139
5140 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd);
5141
5142 if (eg_pi->dynamic_ac_timing)
5143 table->ACPIState.level.ACIndex = 0;
5144
5145 table->ACPIState.level.dpm2.MaxPS = 0;
5146 table->ACPIState.level.dpm2.NearTDPDec = 0;
5147 table->ACPIState.level.dpm2.AboveSafeInc = 0;
5148 table->ACPIState.level.dpm2.BelowSafeInc = 0;
5149 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
5150
5151 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK;
5152 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
5153
5154 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
5155 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5156
5157 return 0;
5158 }
5159
si_populate_ulv_state(struct amdgpu_device * adev,struct SISLANDS_SMC_SWSTATE_SINGLE * state)5160 static int si_populate_ulv_state(struct amdgpu_device *adev,
5161 struct SISLANDS_SMC_SWSTATE_SINGLE *state)
5162 {
5163 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5164 struct si_power_info *si_pi = si_get_pi(adev);
5165 struct si_ulv_param *ulv = &si_pi->ulv;
5166 u32 sclk_in_sr = 1350; /* ??? */
5167 int ret;
5168
5169 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5170 &state->level);
5171 if (!ret) {
5172 if (eg_pi->sclk_deep_sleep) {
5173 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5174 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5175 else
5176 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5177 }
5178 if (ulv->one_pcie_lane_in_ulv)
5179 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5180 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5181 state->level.ACIndex = 1;
5182 state->level.std_vddc = state->level.vddc;
5183 state->levelCount = 1;
5184
5185 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5186 }
5187
5188 return ret;
5189 }
5190
si_program_ulv_memory_timing_parameters(struct amdgpu_device * adev)5191 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5192 {
5193 struct si_power_info *si_pi = si_get_pi(adev);
5194 struct si_ulv_param *ulv = &si_pi->ulv;
5195 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5196 int ret;
5197
5198 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5199 &arb_regs);
5200 if (ret)
5201 return ret;
5202
5203 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5204 ulv->volt_change_delay);
5205
5206 ret = amdgpu_si_copy_bytes_to_smc(adev,
5207 si_pi->arb_table_start +
5208 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5209 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5210 (u8 *)&arb_regs,
5211 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5212 si_pi->sram_end);
5213
5214 return ret;
5215 }
5216
si_get_mvdd_configuration(struct amdgpu_device * adev)5217 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5218 {
5219 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5220
5221 pi->mvdd_split_frequency = 30000;
5222 }
5223
si_init_smc_table(struct amdgpu_device * adev)5224 static int si_init_smc_table(struct amdgpu_device *adev)
5225 {
5226 struct si_power_info *si_pi = si_get_pi(adev);
5227 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5228 const struct si_ulv_param *ulv = &si_pi->ulv;
5229 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5230 int ret;
5231 u32 lane_width;
5232 u32 vr_hot_gpio;
5233
5234 si_populate_smc_voltage_tables(adev, table);
5235
5236 switch (adev->pm.int_thermal_type) {
5237 case THERMAL_TYPE_SI:
5238 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5239 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5240 break;
5241 case THERMAL_TYPE_NONE:
5242 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5243 break;
5244 default:
5245 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5246 break;
5247 }
5248
5249 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5250 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5251
5252 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5253 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5254 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5255 }
5256
5257 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5258 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5259
5260 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5261 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5262
5263 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5264 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5265
5266 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5267 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5268 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5269 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5270 vr_hot_gpio);
5271 }
5272
5273 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5274 if (ret)
5275 return ret;
5276
5277 ret = si_populate_smc_acpi_state(adev, table);
5278 if (ret)
5279 return ret;
5280
5281 table->driverState.flags = table->initialState.flags;
5282 table->driverState.levelCount = table->initialState.levelCount;
5283 table->driverState.levels[0] = table->initialState.level;
5284
5285 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5286 SISLANDS_INITIAL_STATE_ARB_INDEX);
5287 if (ret)
5288 return ret;
5289
5290 if (ulv->supported && ulv->pl.vddc) {
5291 ret = si_populate_ulv_state(adev, &table->ULVState);
5292 if (ret)
5293 return ret;
5294
5295 ret = si_program_ulv_memory_timing_parameters(adev);
5296 if (ret)
5297 return ret;
5298
5299 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control);
5300 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5301
5302 lane_width = amdgpu_get_pcie_lanes(adev);
5303 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5304 } else {
5305 table->ULVState = table->initialState;
5306 }
5307
5308 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5309 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5310 si_pi->sram_end);
5311 }
5312
si_calculate_sclk_params(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5313 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5314 u32 engine_clock,
5315 SISLANDS_SMC_SCLK_VALUE *sclk)
5316 {
5317 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5318 struct si_power_info *si_pi = si_get_pi(adev);
5319 struct atom_clock_dividers dividers;
5320 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5321 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5322 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5323 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5324 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5325 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5326 u64 tmp;
5327 u32 reference_clock = adev->clock.spll.reference_freq;
5328 u32 reference_divider;
5329 u32 fbdiv;
5330 int ret;
5331
5332 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5333 engine_clock, false, ÷rs);
5334 if (ret)
5335 return ret;
5336
5337 reference_divider = 1 + dividers.ref_div;
5338
5339 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5340 do_div(tmp, reference_clock);
5341 fbdiv = (u32) tmp;
5342
5343 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK);
5344 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT;
5345 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
5346
5347 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5348 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5349
5350 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
5351 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
5352 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
5353
5354 if (pi->sclk_ss) {
5355 struct amdgpu_atom_ss ss;
5356 u32 vco_freq = engine_clock * dividers.post_div;
5357
5358 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5359 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5360 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5361 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5362
5363 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK;
5364 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
5365 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
5366
5367 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK;
5368 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
5369 }
5370 }
5371
5372 sclk->sclk_value = engine_clock;
5373 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5374 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5375 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5376 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5377 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5378 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5379
5380 return 0;
5381 }
5382
si_populate_sclk_value(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5383 static int si_populate_sclk_value(struct amdgpu_device *adev,
5384 u32 engine_clock,
5385 SISLANDS_SMC_SCLK_VALUE *sclk)
5386 {
5387 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5388 int ret;
5389
5390 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5391 if (!ret) {
5392 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5393 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5394 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5395 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5396 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5397 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5398 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5399 }
5400
5401 return ret;
5402 }
5403
si_populate_mclk_value(struct amdgpu_device * adev,u32 engine_clock,u32 memory_clock,SISLANDS_SMC_MCLK_VALUE * mclk,bool strobe_mode,bool dll_state_on)5404 static int si_populate_mclk_value(struct amdgpu_device *adev,
5405 u32 engine_clock,
5406 u32 memory_clock,
5407 SISLANDS_SMC_MCLK_VALUE *mclk,
5408 bool strobe_mode,
5409 bool dll_state_on)
5410 {
5411 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5412 struct si_power_info *si_pi = si_get_pi(adev);
5413 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5414 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5415 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5416 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5417 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5418 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5419 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5420 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5421 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5422 struct atom_mpll_param mpll_param;
5423 int ret;
5424
5425 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5426 if (ret)
5427 return ret;
5428
5429 mpll_func_cntl &= ~BWCTRL_MASK;
5430 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5431
5432 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5433 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5434 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5435
5436 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5437 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5438
5439 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5440 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5441 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5442 YCLK_POST_DIV(mpll_param.post_div);
5443 }
5444
5445 if (pi->mclk_ss) {
5446 struct amdgpu_atom_ss ss;
5447 u32 freq_nom;
5448 u32 tmp;
5449 u32 reference_clock = adev->clock.mpll.reference_freq;
5450
5451 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5452 freq_nom = memory_clock * 4;
5453 else
5454 freq_nom = memory_clock * 2;
5455
5456 tmp = freq_nom / reference_clock;
5457 tmp = tmp * tmp;
5458 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5459 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5460 u32 clks = reference_clock * 5 / ss.rate;
5461 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5462
5463 mpll_ss1 &= ~CLKV_MASK;
5464 mpll_ss1 |= CLKV(clkv);
5465
5466 mpll_ss2 &= ~CLKS_MASK;
5467 mpll_ss2 |= CLKS(clks);
5468 }
5469 }
5470
5471 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5472 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5473
5474 if (dll_state_on)
5475 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5476 else
5477 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5478
5479 mclk->mclk_value = cpu_to_be32(memory_clock);
5480 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5481 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5482 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5483 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5484 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5485 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5486 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5487 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5488 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5489
5490 return 0;
5491 }
5492
si_populate_smc_sp(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5493 static void si_populate_smc_sp(struct amdgpu_device *adev,
5494 struct amdgpu_ps *amdgpu_state,
5495 SISLANDS_SMC_SWSTATE *smc_state)
5496 {
5497 struct si_ps *ps = si_get_ps(amdgpu_state);
5498 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5499 int i;
5500
5501 for (i = 0; i < ps->performance_level_count - 1; i++)
5502 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5503
5504 smc_state->levels[ps->performance_level_count - 1].bSP =
5505 cpu_to_be32(pi->psp);
5506 }
5507
si_convert_power_level_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SISLANDS_SMC_HW_PERFORMANCE_LEVEL * level)5508 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5509 struct rv7xx_pl *pl,
5510 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5511 {
5512 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5513 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5514 struct si_power_info *si_pi = si_get_pi(adev);
5515 int ret;
5516 bool dll_state_on;
5517 u16 std_vddc;
5518
5519 if (eg_pi->pcie_performance_request &&
5520 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID))
5521 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5522 else
5523 level->gen2PCIE = (u8)pl->pcie_gen;
5524
5525 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5526 if (ret)
5527 return ret;
5528
5529 level->mcFlags = 0;
5530
5531 if (pi->mclk_stutter_mode_threshold &&
5532 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5533 !eg_pi->uvd_enabled &&
5534 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
5535 (adev->pm.pm_display_cfg.num_display <= 2)) {
5536 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5537 }
5538
5539 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5540 if (pl->mclk > pi->mclk_edc_enable_threshold)
5541 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5542
5543 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5544 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5545
5546 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5547
5548 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5549 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5550 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5551 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5552 else
5553 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5554 } else {
5555 dll_state_on = false;
5556 }
5557 } else {
5558 level->strobeMode = si_get_strobe_mode_settings(adev,
5559 pl->mclk);
5560
5561 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5562 }
5563
5564 ret = si_populate_mclk_value(adev,
5565 pl->sclk,
5566 pl->mclk,
5567 &level->mclk,
5568 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5569 if (ret)
5570 return ret;
5571
5572 ret = si_populate_voltage_value(adev,
5573 &eg_pi->vddc_voltage_table,
5574 pl->vddc, &level->vddc);
5575 if (ret)
5576 return ret;
5577
5578
5579 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5580 if (ret)
5581 return ret;
5582
5583 ret = si_populate_std_voltage_value(adev, std_vddc,
5584 level->vddc.index, &level->std_vddc);
5585 if (ret)
5586 return ret;
5587
5588 if (eg_pi->vddci_control) {
5589 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5590 pl->vddci, &level->vddci);
5591 if (ret)
5592 return ret;
5593 }
5594
5595 if (si_pi->vddc_phase_shed_control) {
5596 ret = si_populate_phase_shedding_value(adev,
5597 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5598 pl->vddc,
5599 pl->sclk,
5600 pl->mclk,
5601 &level->vddc);
5602 if (ret)
5603 return ret;
5604 }
5605
5606 level->MaxPoweredUpCU = si_pi->max_cu;
5607
5608 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5609
5610 return ret;
5611 }
5612
si_populate_smc_t(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5613 static int si_populate_smc_t(struct amdgpu_device *adev,
5614 struct amdgpu_ps *amdgpu_state,
5615 SISLANDS_SMC_SWSTATE *smc_state)
5616 {
5617 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5618 struct si_ps *state = si_get_ps(amdgpu_state);
5619 u32 a_t;
5620 u32 t_l, t_h;
5621 u32 high_bsp;
5622 int i, ret;
5623
5624 if (state->performance_level_count >= 9)
5625 return -EINVAL;
5626
5627 if (state->performance_level_count < 2) {
5628 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
5629 smc_state->levels[0].aT = cpu_to_be32(a_t);
5630 return 0;
5631 }
5632
5633 smc_state->levels[0].aT = cpu_to_be32(0);
5634
5635 for (i = 0; i <= state->performance_level_count - 2; i++) {
5636 ret = r600_calculate_at(
5637 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5638 100 * R600_AH_DFLT,
5639 state->performance_levels[i + 1].sclk,
5640 state->performance_levels[i].sclk,
5641 &t_l,
5642 &t_h);
5643
5644 if (ret) {
5645 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5646 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5647 }
5648
5649 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK;
5650 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT;
5651 smc_state->levels[i].aT = cpu_to_be32(a_t);
5652
5653 high_bsp = (i == state->performance_level_count - 2) ?
5654 pi->pbsp : pi->bsp;
5655 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT;
5656 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5657 }
5658
5659 return 0;
5660 }
5661
si_disable_ulv(struct amdgpu_device * adev)5662 static int si_disable_ulv(struct amdgpu_device *adev)
5663 {
5664 PPSMC_Result r;
5665
5666 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV);
5667 return (r == PPSMC_Result_OK) ? 0 : -EINVAL;
5668 }
5669
si_is_state_ulv_compatible(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)5670 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5671 struct amdgpu_ps *amdgpu_state)
5672 {
5673 const struct si_power_info *si_pi = si_get_pi(adev);
5674 const struct si_ulv_param *ulv = &si_pi->ulv;
5675 const struct si_ps *state = si_get_ps(amdgpu_state);
5676 int i;
5677
5678 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5679 return false;
5680
5681 /* XXX validate against display requirements! */
5682
5683 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5684 if (adev->pm.pm_display_cfg.display_clk <=
5685 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5686 if (ulv->pl.vddc <
5687 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5688 return false;
5689 }
5690 }
5691
5692 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5693 return false;
5694
5695 return true;
5696 }
5697
si_set_power_state_conditionally_enable_ulv(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5698 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5699 struct amdgpu_ps *amdgpu_new_state)
5700 {
5701 const struct si_power_info *si_pi = si_get_pi(adev);
5702 const struct si_ulv_param *ulv = &si_pi->ulv;
5703
5704 if (ulv->supported) {
5705 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5706 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5707 0 : -EINVAL;
5708 }
5709 return 0;
5710 }
5711
si_convert_power_state_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5712 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5713 struct amdgpu_ps *amdgpu_state,
5714 SISLANDS_SMC_SWSTATE *smc_state)
5715 {
5716 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5717 struct ni_power_info *ni_pi = ni_get_pi(adev);
5718 struct si_power_info *si_pi = si_get_pi(adev);
5719 struct si_ps *state = si_get_ps(amdgpu_state);
5720 int i, ret;
5721 u32 threshold;
5722 u32 sclk_in_sr = 1350; /* ??? */
5723
5724 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5725 return -EINVAL;
5726
5727 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5728
5729 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5730 eg_pi->uvd_enabled = true;
5731 if (eg_pi->smu_uvd_hs)
5732 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5733 } else {
5734 eg_pi->uvd_enabled = false;
5735 }
5736
5737 if (state->dc_compatible)
5738 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5739
5740 smc_state->levelCount = 0;
5741 for (i = 0; i < state->performance_level_count; i++) {
5742 if (eg_pi->sclk_deep_sleep) {
5743 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5744 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5745 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5746 else
5747 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5748 }
5749 }
5750
5751 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5752 &smc_state->levels[i]);
5753 smc_state->levels[i].arbRefreshState =
5754 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5755
5756 if (ret)
5757 return ret;
5758
5759 if (ni_pi->enable_power_containment)
5760 smc_state->levels[i].displayWatermark =
5761 (state->performance_levels[i].sclk < threshold) ?
5762 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5763 else
5764 smc_state->levels[i].displayWatermark = (i < 2) ?
5765 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5766
5767 if (eg_pi->dynamic_ac_timing)
5768 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5769 else
5770 smc_state->levels[i].ACIndex = 0;
5771
5772 smc_state->levelCount++;
5773 }
5774
5775 si_write_smc_soft_register(adev,
5776 SI_SMC_SOFT_REGISTER_watermark_threshold,
5777 threshold / 512);
5778
5779 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5780
5781 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5782 if (ret)
5783 ni_pi->enable_power_containment = false;
5784
5785 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5786 if (ret)
5787 ni_pi->enable_sq_ramping = false;
5788
5789 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5790 }
5791
si_upload_sw_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5792 static int si_upload_sw_state(struct amdgpu_device *adev,
5793 struct amdgpu_ps *amdgpu_new_state)
5794 {
5795 struct si_power_info *si_pi = si_get_pi(adev);
5796 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5797 int ret;
5798 u32 address = si_pi->state_table_start +
5799 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5800 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5801 size_t state_size = struct_size(smc_state, levels,
5802 new_state->performance_level_count);
5803 memset(smc_state, 0, state_size);
5804
5805 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5806 if (ret)
5807 return ret;
5808
5809 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5810 state_size, si_pi->sram_end);
5811 }
5812
si_upload_ulv_state(struct amdgpu_device * adev)5813 static int si_upload_ulv_state(struct amdgpu_device *adev)
5814 {
5815 struct si_power_info *si_pi = si_get_pi(adev);
5816 struct si_ulv_param *ulv = &si_pi->ulv;
5817 int ret = 0;
5818
5819 if (ulv->supported && ulv->pl.vddc) {
5820 u32 address = si_pi->state_table_start +
5821 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5822 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
5823 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5824
5825 memset(smc_state, 0, state_size);
5826
5827 ret = si_populate_ulv_state(adev, smc_state);
5828 if (!ret)
5829 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5830 state_size, si_pi->sram_end);
5831 }
5832
5833 return ret;
5834 }
5835
si_upload_smc_data(struct amdgpu_device * adev)5836 static int si_upload_smc_data(struct amdgpu_device *adev)
5837 {
5838 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
5839 u32 crtc_index = 0;
5840 u32 mclk_change_block_cp_min = 0;
5841 u32 mclk_change_block_cp_max = 0;
5842
5843 /* When a display is plugged in, program these so that the SMC
5844 * performs MCLK switching when it doesn't cause flickering.
5845 * When no display is plugged in, there is no need to restrict
5846 * MCLK switching, so program them to zero.
5847 */
5848 if (cfg->num_display) {
5849 crtc_index = cfg->crtc_index;
5850
5851 if (cfg->line_time_in_us) {
5852 mclk_change_block_cp_min = 200 / cfg->line_time_in_us;
5853 mclk_change_block_cp_max = 100 / cfg->line_time_in_us;
5854 }
5855 }
5856
5857 si_write_smc_soft_register(adev,
5858 SI_SMC_SOFT_REGISTER_crtc_index,
5859 crtc_index);
5860
5861 si_write_smc_soft_register(adev,
5862 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5863 mclk_change_block_cp_min);
5864
5865 si_write_smc_soft_register(adev,
5866 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5867 mclk_change_block_cp_max);
5868
5869 return 0;
5870 }
5871
si_set_mc_special_registers(struct amdgpu_device * adev,struct si_mc_reg_table * table)5872 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5873 struct si_mc_reg_table *table)
5874 {
5875 u8 i, j, k;
5876 u32 temp_reg;
5877
5878 for (i = 0, j = table->last; i < table->last; i++) {
5879 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5880 return -EINVAL;
5881 switch (table->mc_reg_address[i].s1) {
5882 case MC_SEQ_MISC1:
5883 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5884 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5885 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5886 for (k = 0; k < table->num_entries; k++)
5887 table->mc_reg_table_entry[k].mc_data[j] =
5888 ((temp_reg & 0xffff0000)) |
5889 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5890 j++;
5891
5892 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5893 return -EINVAL;
5894 temp_reg = RREG32(MC_PMG_CMD_MRS);
5895 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5896 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5897 for (k = 0; k < table->num_entries; k++) {
5898 table->mc_reg_table_entry[k].mc_data[j] =
5899 (temp_reg & 0xffff0000) |
5900 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5901 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5902 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5903 }
5904 j++;
5905
5906 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5907 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5908 return -EINVAL;
5909 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5910 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5911 for (k = 0; k < table->num_entries; k++)
5912 table->mc_reg_table_entry[k].mc_data[j] =
5913 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5914 j++;
5915 }
5916 break;
5917 case MC_SEQ_RESERVE_M:
5918 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5919 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5920 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5921 for(k = 0; k < table->num_entries; k++)
5922 table->mc_reg_table_entry[k].mc_data[j] =
5923 (temp_reg & 0xffff0000) |
5924 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5925 j++;
5926 break;
5927 default:
5928 break;
5929 }
5930 }
5931
5932 table->last = j;
5933
5934 return 0;
5935 }
5936
si_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)5937 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5938 {
5939 bool result = true;
5940 switch (in_reg) {
5941 case MC_SEQ_RAS_TIMING:
5942 *out_reg = MC_SEQ_RAS_TIMING_LP;
5943 break;
5944 case MC_SEQ_CAS_TIMING:
5945 *out_reg = MC_SEQ_CAS_TIMING_LP;
5946 break;
5947 case MC_SEQ_MISC_TIMING:
5948 *out_reg = MC_SEQ_MISC_TIMING_LP;
5949 break;
5950 case MC_SEQ_MISC_TIMING2:
5951 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5952 break;
5953 case MC_SEQ_RD_CTL_D0:
5954 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5955 break;
5956 case MC_SEQ_RD_CTL_D1:
5957 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5958 break;
5959 case MC_SEQ_WR_CTL_D0:
5960 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5961 break;
5962 case MC_SEQ_WR_CTL_D1:
5963 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5964 break;
5965 case MC_PMG_CMD_EMRS:
5966 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5967 break;
5968 case MC_PMG_CMD_MRS:
5969 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5970 break;
5971 case MC_PMG_CMD_MRS1:
5972 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5973 break;
5974 case MC_SEQ_PMG_TIMING:
5975 *out_reg = MC_SEQ_PMG_TIMING_LP;
5976 break;
5977 case MC_PMG_CMD_MRS2:
5978 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5979 break;
5980 case MC_SEQ_WR_CTL_2:
5981 *out_reg = MC_SEQ_WR_CTL_2_LP;
5982 break;
5983 default:
5984 result = false;
5985 break;
5986 }
5987
5988 return result;
5989 }
5990
si_set_valid_flag(struct si_mc_reg_table * table)5991 static void si_set_valid_flag(struct si_mc_reg_table *table)
5992 {
5993 u8 i, j;
5994
5995 for (i = 0; i < table->last; i++) {
5996 for (j = 1; j < table->num_entries; j++) {
5997 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5998 table->valid_flag |= 1 << i;
5999 break;
6000 }
6001 }
6002 }
6003 }
6004
si_set_s0_mc_reg_index(struct si_mc_reg_table * table)6005 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6006 {
6007 u32 i;
6008 u16 address;
6009
6010 for (i = 0; i < table->last; i++)
6011 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6012 address : table->mc_reg_address[i].s1;
6013
6014 }
6015
si_copy_vbios_mc_reg_table(struct atom_mc_reg_table * table,struct si_mc_reg_table * si_table)6016 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6017 struct si_mc_reg_table *si_table)
6018 {
6019 u8 i, j;
6020
6021 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6022 return -EINVAL;
6023 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6024 return -EINVAL;
6025
6026 for (i = 0; i < table->last; i++)
6027 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6028 si_table->last = table->last;
6029
6030 for (i = 0; i < table->num_entries; i++) {
6031 si_table->mc_reg_table_entry[i].mclk_max =
6032 table->mc_reg_table_entry[i].mclk_max;
6033 for (j = 0; j < table->last; j++) {
6034 si_table->mc_reg_table_entry[i].mc_data[j] =
6035 table->mc_reg_table_entry[i].mc_data[j];
6036 }
6037 }
6038 si_table->num_entries = table->num_entries;
6039
6040 return 0;
6041 }
6042
si_initialize_mc_reg_table(struct amdgpu_device * adev)6043 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6044 {
6045 struct si_power_info *si_pi = si_get_pi(adev);
6046 struct atom_mc_reg_table *table;
6047 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6048 u8 module_index = rv770_get_memory_module_index(adev);
6049 int ret;
6050
6051 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6052 if (!table)
6053 return -ENOMEM;
6054
6055 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6056 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6057 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6058 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6059 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6060 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6061 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6062 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6063 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6064 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6065 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6066 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6067 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6068 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6069
6070 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6071 if (ret)
6072 goto init_mc_done;
6073
6074 ret = si_copy_vbios_mc_reg_table(table, si_table);
6075 if (ret)
6076 goto init_mc_done;
6077
6078 si_set_s0_mc_reg_index(si_table);
6079
6080 ret = si_set_mc_special_registers(adev, si_table);
6081 if (ret)
6082 goto init_mc_done;
6083
6084 si_set_valid_flag(si_table);
6085
6086 init_mc_done:
6087 kfree(table);
6088
6089 return ret;
6090
6091 }
6092
si_populate_mc_reg_addresses(struct amdgpu_device * adev,SMC_SIslands_MCRegisters * mc_reg_table)6093 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6094 SMC_SIslands_MCRegisters *mc_reg_table)
6095 {
6096 struct si_power_info *si_pi = si_get_pi(adev);
6097 u32 i, j;
6098
6099 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6100 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6101 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6102 break;
6103 mc_reg_table->address[i].s0 =
6104 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6105 mc_reg_table->address[i].s1 =
6106 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6107 i++;
6108 }
6109 }
6110 mc_reg_table->last = (u8)i;
6111 }
6112
si_convert_mc_registers(const struct si_mc_reg_entry * entry,SMC_SIslands_MCRegisterSet * data,u32 num_entries,u32 valid_flag)6113 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6114 SMC_SIslands_MCRegisterSet *data,
6115 u32 num_entries, u32 valid_flag)
6116 {
6117 u32 i, j;
6118
6119 for(i = 0, j = 0; j < num_entries; j++) {
6120 if (valid_flag & (1 << j)) {
6121 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6122 i++;
6123 }
6124 }
6125 }
6126
si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCRegisterSet * mc_reg_table_data)6127 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6128 struct rv7xx_pl *pl,
6129 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6130 {
6131 struct si_power_info *si_pi = si_get_pi(adev);
6132 u32 i = 0;
6133
6134 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6135 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6136 break;
6137 }
6138
6139 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6140 --i;
6141
6142 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6143 mc_reg_table_data, si_pi->mc_reg_table.last,
6144 si_pi->mc_reg_table.valid_flag);
6145 }
6146
si_convert_mc_reg_table_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SMC_SIslands_MCRegisters * mc_reg_table)6147 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6148 struct amdgpu_ps *amdgpu_state,
6149 SMC_SIslands_MCRegisters *mc_reg_table)
6150 {
6151 struct si_ps *state = si_get_ps(amdgpu_state);
6152 int i;
6153
6154 for (i = 0; i < state->performance_level_count; i++) {
6155 si_convert_mc_reg_table_entry_to_smc(adev,
6156 &state->performance_levels[i],
6157 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6158 }
6159 }
6160
si_populate_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_boot_state)6161 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6162 struct amdgpu_ps *amdgpu_boot_state)
6163 {
6164 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6165 struct si_power_info *si_pi = si_get_pi(adev);
6166 struct si_ulv_param *ulv = &si_pi->ulv;
6167 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6168
6169 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6170
6171 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6172
6173 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6174
6175 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6176 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6177
6178 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6179 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6180 si_pi->mc_reg_table.last,
6181 si_pi->mc_reg_table.valid_flag);
6182
6183 if (ulv->supported && ulv->pl.vddc != 0)
6184 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6185 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6186 else
6187 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6188 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6189 si_pi->mc_reg_table.last,
6190 si_pi->mc_reg_table.valid_flag);
6191
6192 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6193
6194 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6195 (u8 *)smc_mc_reg_table,
6196 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6197 }
6198
si_upload_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)6199 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6200 struct amdgpu_ps *amdgpu_new_state)
6201 {
6202 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6203 struct si_power_info *si_pi = si_get_pi(adev);
6204 u32 address = si_pi->mc_reg_table_start +
6205 offsetof(SMC_SIslands_MCRegisters,
6206 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6207 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6208
6209 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6210
6211 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6212
6213 return amdgpu_si_copy_bytes_to_smc(adev, address,
6214 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6215 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6216 si_pi->sram_end);
6217 }
6218
si_enable_voltage_control(struct amdgpu_device * adev,bool enable)6219 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6220 {
6221 if (enable)
6222 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6223 else
6224 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6225 }
6226
si_get_maximum_link_speed(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)6227 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6228 struct amdgpu_ps *amdgpu_state)
6229 {
6230 struct si_ps *state = si_get_ps(amdgpu_state);
6231 int i;
6232 u16 pcie_speed, max_speed = 0;
6233
6234 for (i = 0; i < state->performance_level_count; i++) {
6235 pcie_speed = state->performance_levels[i].pcie_gen;
6236 if (max_speed < pcie_speed)
6237 max_speed = pcie_speed;
6238 }
6239 return max_speed;
6240 }
6241
si_get_current_pcie_speed(struct amdgpu_device * adev)6242 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6243 {
6244 u32 speed_cntl;
6245
6246 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
6247 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
6248
6249 return (u16)speed_cntl;
6250 }
6251
si_request_link_speed_change_before_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6252 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6253 struct amdgpu_ps *amdgpu_new_state,
6254 struct amdgpu_ps *amdgpu_current_state)
6255 {
6256 struct si_power_info *si_pi = si_get_pi(adev);
6257 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6258 enum si_pcie_gen current_link_speed;
6259
6260 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID)
6261 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6262 else
6263 current_link_speed = si_pi->force_pcie_gen;
6264
6265 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
6266 si_pi->pspp_notify_required = false;
6267 if (target_link_speed > current_link_speed) {
6268 switch (target_link_speed) {
6269 #if defined(CONFIG_ACPI)
6270 case SI_PCIE_GEN3:
6271 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6272 break;
6273 si_pi->force_pcie_gen = SI_PCIE_GEN2;
6274 if (current_link_speed == SI_PCIE_GEN2)
6275 break;
6276 fallthrough;
6277 case SI_PCIE_GEN2:
6278 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6279 break;
6280 fallthrough;
6281 #endif
6282 default:
6283 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6284 break;
6285 }
6286 } else {
6287 if (target_link_speed < current_link_speed)
6288 si_pi->pspp_notify_required = true;
6289 }
6290 }
6291
si_notify_link_speed_change_after_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6292 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6293 struct amdgpu_ps *amdgpu_new_state,
6294 struct amdgpu_ps *amdgpu_current_state)
6295 {
6296 struct si_power_info *si_pi = si_get_pi(adev);
6297 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6298 u8 request;
6299
6300 if (si_pi->pspp_notify_required) {
6301 if (target_link_speed == SI_PCIE_GEN3)
6302 request = PCIE_PERF_REQ_PECI_GEN3;
6303 else if (target_link_speed == SI_PCIE_GEN2)
6304 request = PCIE_PERF_REQ_PECI_GEN2;
6305 else
6306 request = PCIE_PERF_REQ_PECI_GEN1;
6307
6308 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6309 (si_get_current_pcie_speed(adev) > 0))
6310 return;
6311
6312 #if defined(CONFIG_ACPI)
6313 amdgpu_acpi_pcie_performance_request(adev, request, false);
6314 #endif
6315 }
6316 }
6317
6318 #if 0
6319 static int si_ds_request(struct amdgpu_device *adev,
6320 bool ds_status_on, u32 count_write)
6321 {
6322 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6323
6324 if (eg_pi->sclk_deep_sleep) {
6325 if (ds_status_on)
6326 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6327 PPSMC_Result_OK) ?
6328 0 : -EINVAL;
6329 else
6330 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6331 PPSMC_Result_OK) ? 0 : -EINVAL;
6332 }
6333 return 0;
6334 }
6335 #endif
6336
si_set_max_cu_value(struct amdgpu_device * adev)6337 static void si_set_max_cu_value(struct amdgpu_device *adev)
6338 {
6339 struct si_power_info *si_pi = si_get_pi(adev);
6340
6341 if (adev->asic_type == CHIP_VERDE) {
6342 switch (adev->pdev->device) {
6343 case 0x6820:
6344 case 0x6825:
6345 case 0x6821:
6346 case 0x6823:
6347 case 0x6827:
6348 si_pi->max_cu = 10;
6349 break;
6350 case 0x682D:
6351 case 0x6824:
6352 case 0x682F:
6353 case 0x6826:
6354 si_pi->max_cu = 8;
6355 break;
6356 case 0x6828:
6357 case 0x6830:
6358 case 0x6831:
6359 case 0x6838:
6360 case 0x6839:
6361 case 0x683D:
6362 si_pi->max_cu = 10;
6363 break;
6364 case 0x683B:
6365 case 0x683F:
6366 case 0x6829:
6367 si_pi->max_cu = 8;
6368 break;
6369 default:
6370 si_pi->max_cu = 0;
6371 break;
6372 }
6373 } else {
6374 si_pi->max_cu = 0;
6375 }
6376 }
6377
si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * table)6378 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6379 struct amdgpu_clock_voltage_dependency_table *table)
6380 {
6381 u32 i;
6382 int j;
6383 u16 leakage_voltage;
6384
6385 if (table) {
6386 for (i = 0; i < table->count; i++) {
6387 switch (si_get_leakage_voltage_from_leakage_index(adev,
6388 table->entries[i].v,
6389 &leakage_voltage)) {
6390 case 0:
6391 table->entries[i].v = leakage_voltage;
6392 break;
6393 case -EAGAIN:
6394 return -EINVAL;
6395 case -EINVAL:
6396 default:
6397 break;
6398 }
6399 }
6400
6401 for (j = (table->count - 2); j >= 0; j--) {
6402 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6403 table->entries[j].v : table->entries[j + 1].v;
6404 }
6405 }
6406 return 0;
6407 }
6408
si_patch_dependency_tables_based_on_leakage(struct amdgpu_device * adev)6409 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6410 {
6411 int ret = 0;
6412
6413 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6414 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6415 if (ret)
6416 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6417 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6418 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6419 if (ret)
6420 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6421 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6422 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6423 if (ret)
6424 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6425 return ret;
6426 }
6427
si_set_pcie_lane_width_in_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6428 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6429 struct amdgpu_ps *amdgpu_new_state,
6430 struct amdgpu_ps *amdgpu_current_state)
6431 {
6432 u32 lane_width;
6433 u32 new_lane_width =
6434 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6435 u32 current_lane_width =
6436 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6437
6438 if (new_lane_width != current_lane_width) {
6439 amdgpu_set_pcie_lanes(adev, new_lane_width);
6440 lane_width = amdgpu_get_pcie_lanes(adev);
6441 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6442 }
6443 }
6444
si_dpm_setup_asic(struct amdgpu_device * adev)6445 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6446 {
6447 si_read_clock_registers(adev);
6448 si_enable_acpi_power_management(adev);
6449 }
6450
si_thermal_enable_alert(struct amdgpu_device * adev,bool enable)6451 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6452 bool enable)
6453 {
6454 u32 thermal_int = RREG32(mmCG_THERMAL_INT);
6455
6456 if (enable) {
6457 PPSMC_Result result;
6458
6459 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK);
6460 WREG32(mmCG_THERMAL_INT, thermal_int);
6461 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6462 if (result != PPSMC_Result_OK) {
6463 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6464 return -EINVAL;
6465 }
6466 } else {
6467 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
6468 WREG32(mmCG_THERMAL_INT, thermal_int);
6469 }
6470
6471 return 0;
6472 }
6473
si_thermal_set_temperature_range(struct amdgpu_device * adev,int min_temp,int max_temp)6474 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6475 int min_temp, int max_temp)
6476 {
6477 int low_temp = 0 * 1000;
6478 int high_temp = 255 * 1000;
6479
6480 if (low_temp < min_temp)
6481 low_temp = min_temp;
6482 if (high_temp > max_temp)
6483 high_temp = max_temp;
6484 if (high_temp < low_temp) {
6485 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6486 return -EINVAL;
6487 }
6488
6489 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK);
6490 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK);
6491 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK);
6492
6493 adev->pm.dpm.thermal.min_temp = low_temp;
6494 adev->pm.dpm.thermal.max_temp = high_temp;
6495
6496 return 0;
6497 }
6498
si_fan_ctrl_set_static_mode(struct amdgpu_device * adev,u32 mode)6499 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6500 {
6501 struct si_power_info *si_pi = si_get_pi(adev);
6502 u32 tmp;
6503
6504 if (si_pi->fan_ctrl_is_in_default_mode) {
6505 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6506 si_pi->fan_ctrl_default_mode = tmp;
6507 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;
6508 si_pi->t_min = tmp;
6509 si_pi->fan_ctrl_is_in_default_mode = false;
6510 }
6511
6512 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6513 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
6514 WREG32(mmCG_FDO_CTRL2, tmp);
6515
6516 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6517 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6518 WREG32(mmCG_FDO_CTRL2, tmp);
6519 }
6520
si_thermal_setup_fan_table(struct amdgpu_device * adev)6521 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6522 {
6523 struct si_power_info *si_pi = si_get_pi(adev);
6524 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6525 u32 duty100;
6526 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6527 u16 fdo_min, slope1, slope2;
6528 u32 reference_clock, tmp;
6529 int ret;
6530 u64 tmp64;
6531
6532 if (!si_pi->fan_table_start) {
6533 adev->pm.dpm.fan.ucode_fan_control = false;
6534 return 0;
6535 }
6536
6537 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6538
6539 if (duty100 == 0) {
6540 adev->pm.dpm.fan.ucode_fan_control = false;
6541 return 0;
6542 }
6543
6544 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6545 do_div(tmp64, 10000);
6546 fdo_min = (u16)tmp64;
6547
6548 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6549 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6550
6551 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6552 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6553
6554 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6555 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6556
6557 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6558 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6559 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6560 fan_table.slope1 = cpu_to_be16(slope1);
6561 fan_table.slope2 = cpu_to_be16(slope2);
6562 fan_table.fdo_min = cpu_to_be16(fdo_min);
6563 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6564 fan_table.hys_up = cpu_to_be16(1);
6565 fan_table.hys_slope = cpu_to_be16(1);
6566 fan_table.temp_resp_lim = cpu_to_be16(5);
6567 reference_clock = amdgpu_asic_get_xclk(adev);
6568
6569 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6570 reference_clock) / 1600);
6571 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6572
6573 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
6574 fan_table.temp_src = (uint8_t)tmp;
6575
6576 ret = amdgpu_si_copy_bytes_to_smc(adev,
6577 si_pi->fan_table_start,
6578 (u8 *)(&fan_table),
6579 sizeof(fan_table),
6580 si_pi->sram_end);
6581
6582 if (ret) {
6583 DRM_ERROR("Failed to load fan table to the SMC.");
6584 adev->pm.dpm.fan.ucode_fan_control = false;
6585 }
6586
6587 return ret;
6588 }
6589
si_fan_ctrl_start_smc_fan_control(struct amdgpu_device * adev)6590 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6591 {
6592 struct si_power_info *si_pi = si_get_pi(adev);
6593 PPSMC_Result ret;
6594
6595 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6596 if (ret == PPSMC_Result_OK) {
6597 si_pi->fan_is_controlled_by_smc = true;
6598 return 0;
6599 } else {
6600 return -EINVAL;
6601 }
6602 }
6603
si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device * adev)6604 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6605 {
6606 struct si_power_info *si_pi = si_get_pi(adev);
6607 PPSMC_Result ret;
6608
6609 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6610
6611 if (ret == PPSMC_Result_OK) {
6612 si_pi->fan_is_controlled_by_smc = false;
6613 return 0;
6614 } else {
6615 return -EINVAL;
6616 }
6617 }
6618
si_dpm_get_fan_speed_pwm(void * handle,u32 * speed)6619 static int si_dpm_get_fan_speed_pwm(void *handle,
6620 u32 *speed)
6621 {
6622 u32 duty, duty100;
6623 u64 tmp64;
6624 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6625
6626 if (!speed)
6627 return -EINVAL;
6628
6629 if (adev->pm.no_fan)
6630 return -ENOENT;
6631
6632 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6633 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
6634
6635 if (duty100 == 0)
6636 return -EINVAL;
6637
6638 tmp64 = (u64)duty * 255;
6639 do_div(tmp64, duty100);
6640 *speed = min_t(u32, tmp64, 255);
6641
6642 return 0;
6643 }
6644
si_dpm_set_fan_speed_pwm(void * handle,u32 speed)6645 static int si_dpm_set_fan_speed_pwm(void *handle,
6646 u32 speed)
6647 {
6648 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6649 struct si_power_info *si_pi = si_get_pi(adev);
6650 u32 tmp;
6651 u32 duty, duty100;
6652 u64 tmp64;
6653
6654 if (adev->pm.no_fan)
6655 return -ENOENT;
6656
6657 if (si_pi->fan_is_controlled_by_smc)
6658 return -EINVAL;
6659
6660 if (speed > 255)
6661 return -EINVAL;
6662
6663 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6664
6665 if (duty100 == 0)
6666 return -EINVAL;
6667
6668 tmp64 = (u64)speed * duty100;
6669 do_div(tmp64, 255);
6670 duty = (u32)tmp64;
6671
6672 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
6673 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
6674 WREG32(mmCG_FDO_CTRL0, tmp);
6675
6676 return 0;
6677 }
6678
si_dpm_set_fan_control_mode(void * handle,u32 mode)6679 static int si_dpm_set_fan_control_mode(void *handle, u32 mode)
6680 {
6681 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6682
6683 if (mode == U32_MAX)
6684 return -EINVAL;
6685
6686 if (mode) {
6687 /* stop auto-manage */
6688 if (adev->pm.dpm.fan.ucode_fan_control)
6689 si_fan_ctrl_stop_smc_fan_control(adev);
6690 si_fan_ctrl_set_static_mode(adev, mode);
6691 } else {
6692 /* restart auto-manage */
6693 if (adev->pm.dpm.fan.ucode_fan_control)
6694 si_thermal_start_smc_fan_control(adev);
6695 else
6696 si_fan_ctrl_set_default_mode(adev);
6697 }
6698
6699 return 0;
6700 }
6701
si_dpm_get_fan_control_mode(void * handle,u32 * fan_mode)6702 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode)
6703 {
6704 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6705 struct si_power_info *si_pi = si_get_pi(adev);
6706 u32 tmp;
6707
6708 if (!fan_mode)
6709 return -EINVAL;
6710
6711 if (si_pi->fan_is_controlled_by_smc)
6712 return 0;
6713
6714 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6715 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
6716
6717 return 0;
6718 }
6719
6720 #if 0
6721 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6722 u32 *speed)
6723 {
6724 u32 tach_period;
6725 u32 xclk = amdgpu_asic_get_xclk(adev);
6726
6727 if (adev->pm.no_fan)
6728 return -ENOENT;
6729
6730 if (adev->pm.fan_pulses_per_revolution == 0)
6731 return -ENOENT;
6732
6733 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
6734 if (tach_period == 0)
6735 return -ENOENT;
6736
6737 *speed = 60 * xclk * 10000 / tach_period;
6738
6739 return 0;
6740 }
6741
6742 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6743 u32 speed)
6744 {
6745 u32 tach_period, tmp;
6746 u32 xclk = amdgpu_asic_get_xclk(adev);
6747
6748 if (adev->pm.no_fan)
6749 return -ENOENT;
6750
6751 if (adev->pm.fan_pulses_per_revolution == 0)
6752 return -ENOENT;
6753
6754 if ((speed < adev->pm.fan_min_rpm) ||
6755 (speed > adev->pm.fan_max_rpm))
6756 return -EINVAL;
6757
6758 if (adev->pm.dpm.fan.ucode_fan_control)
6759 si_fan_ctrl_stop_smc_fan_control(adev);
6760
6761 tach_period = 60 * xclk * 10000 / (8 * speed);
6762 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
6763 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
6764 WREG32(mmCG_TACH_CTRL, tmp);
6765
6766 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6767
6768 return 0;
6769 }
6770 #endif
6771
si_fan_ctrl_set_default_mode(struct amdgpu_device * adev)6772 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6773 {
6774 struct si_power_info *si_pi = si_get_pi(adev);
6775 u32 tmp;
6776
6777 if (!si_pi->fan_ctrl_is_in_default_mode) {
6778 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6779 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6780 WREG32(mmCG_FDO_CTRL2, tmp);
6781
6782 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6783 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
6784 WREG32(mmCG_FDO_CTRL2, tmp);
6785 si_pi->fan_ctrl_is_in_default_mode = true;
6786 }
6787 }
6788
si_thermal_start_smc_fan_control(struct amdgpu_device * adev)6789 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6790 {
6791 if (adev->pm.dpm.fan.ucode_fan_control) {
6792 si_fan_ctrl_start_smc_fan_control(adev);
6793 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6794 }
6795 }
6796
si_thermal_initialize(struct amdgpu_device * adev)6797 static void si_thermal_initialize(struct amdgpu_device *adev)
6798 {
6799 u32 tmp;
6800
6801 if (adev->pm.fan_pulses_per_revolution) {
6802 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
6803 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
6804 WREG32(mmCG_TACH_CTRL, tmp);
6805 }
6806
6807 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
6808 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
6809 WREG32(mmCG_FDO_CTRL2, tmp);
6810 }
6811
si_thermal_start_thermal_controller(struct amdgpu_device * adev)6812 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6813 {
6814 int ret;
6815
6816 si_thermal_initialize(adev);
6817 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6818 if (ret)
6819 return ret;
6820 ret = si_thermal_enable_alert(adev, true);
6821 if (ret)
6822 return ret;
6823 if (adev->pm.dpm.fan.ucode_fan_control) {
6824 ret = si_halt_smc(adev);
6825 if (ret)
6826 return ret;
6827 ret = si_thermal_setup_fan_table(adev);
6828 if (ret)
6829 return ret;
6830 ret = si_resume_smc(adev);
6831 if (ret)
6832 return ret;
6833 si_thermal_start_smc_fan_control(adev);
6834 }
6835
6836 return 0;
6837 }
6838
si_thermal_stop_thermal_controller(struct amdgpu_device * adev)6839 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6840 {
6841 if (!adev->pm.no_fan) {
6842 si_fan_ctrl_set_default_mode(adev);
6843 si_fan_ctrl_stop_smc_fan_control(adev);
6844 }
6845 }
6846
si_dpm_enable(struct amdgpu_device * adev)6847 static int si_dpm_enable(struct amdgpu_device *adev)
6848 {
6849 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6850 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6851 struct si_power_info *si_pi = si_get_pi(adev);
6852 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6853 int ret;
6854
6855 if (amdgpu_si_is_smc_running(adev))
6856 return -EINVAL;
6857 if (pi->voltage_control || si_pi->voltage_control_svi2)
6858 si_enable_voltage_control(adev, true);
6859 if (pi->mvdd_control)
6860 si_get_mvdd_configuration(adev);
6861 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6862 ret = si_construct_voltage_tables(adev);
6863 if (ret) {
6864 DRM_ERROR("si_construct_voltage_tables failed\n");
6865 return ret;
6866 }
6867 }
6868 if (eg_pi->dynamic_ac_timing) {
6869 ret = si_initialize_mc_reg_table(adev);
6870 if (ret)
6871 eg_pi->dynamic_ac_timing = false;
6872 }
6873 if (pi->dynamic_ss)
6874 si_enable_spread_spectrum(adev, true);
6875 if (pi->thermal_protection)
6876 si_enable_thermal_protection(adev, true);
6877 si_setup_bsp(adev);
6878 si_program_git(adev);
6879 si_program_tp(adev);
6880 si_program_tpp(adev);
6881 si_program_sstp(adev);
6882 si_enable_display_gap(adev);
6883 si_program_vc(adev);
6884 ret = si_upload_firmware(adev);
6885 if (ret) {
6886 DRM_ERROR("si_upload_firmware failed\n");
6887 return ret;
6888 }
6889 ret = si_process_firmware_header(adev);
6890 if (ret) {
6891 DRM_ERROR("si_process_firmware_header failed\n");
6892 return ret;
6893 }
6894 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6895 if (ret) {
6896 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6897 return ret;
6898 }
6899 ret = si_init_smc_table(adev);
6900 if (ret) {
6901 DRM_ERROR("si_init_smc_table failed\n");
6902 return ret;
6903 }
6904 ret = si_init_smc_spll_table(adev);
6905 if (ret) {
6906 DRM_ERROR("si_init_smc_spll_table failed\n");
6907 return ret;
6908 }
6909 ret = si_init_arb_table_index(adev);
6910 if (ret) {
6911 DRM_ERROR("si_init_arb_table_index failed\n");
6912 return ret;
6913 }
6914 if (eg_pi->dynamic_ac_timing) {
6915 ret = si_populate_mc_reg_table(adev, boot_ps);
6916 if (ret) {
6917 DRM_ERROR("si_populate_mc_reg_table failed\n");
6918 return ret;
6919 }
6920 }
6921 ret = si_initialize_smc_cac_tables(adev);
6922 if (ret) {
6923 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6924 return ret;
6925 }
6926 ret = si_initialize_hardware_cac_manager(adev);
6927 if (ret) {
6928 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6929 return ret;
6930 }
6931 ret = si_initialize_smc_dte_tables(adev);
6932 if (ret) {
6933 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6934 return ret;
6935 }
6936 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6937 if (ret) {
6938 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6939 return ret;
6940 }
6941 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6942 if (ret) {
6943 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6944 return ret;
6945 }
6946 si_program_response_times(adev);
6947 si_program_ds_registers(adev);
6948 si_dpm_start_smc(adev);
6949 ret = si_notify_smc_display_change(adev, false);
6950 if (ret) {
6951 DRM_ERROR("si_notify_smc_display_change failed\n");
6952 return ret;
6953 }
6954 si_enable_sclk_control(adev, true);
6955 si_start_dpm(adev);
6956
6957 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6958 si_thermal_start_thermal_controller(adev);
6959
6960 ni_update_current_ps(adev, boot_ps);
6961
6962 return 0;
6963 }
6964
si_set_temperature_range(struct amdgpu_device * adev)6965 static int si_set_temperature_range(struct amdgpu_device *adev)
6966 {
6967 int ret;
6968
6969 ret = si_thermal_enable_alert(adev, false);
6970 if (ret)
6971 return ret;
6972 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6973 if (ret)
6974 return ret;
6975 ret = si_thermal_enable_alert(adev, true);
6976 if (ret)
6977 return ret;
6978
6979 return ret;
6980 }
6981
si_dpm_disable(struct amdgpu_device * adev)6982 static void si_dpm_disable(struct amdgpu_device *adev)
6983 {
6984 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6985 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6986
6987 if (!amdgpu_si_is_smc_running(adev))
6988 return;
6989 si_thermal_stop_thermal_controller(adev);
6990 si_disable_ulv(adev);
6991 si_clear_vc(adev);
6992 if (pi->thermal_protection)
6993 si_enable_thermal_protection(adev, false);
6994 si_enable_power_containment(adev, boot_ps, false);
6995 si_enable_smc_cac(adev, boot_ps, false);
6996 si_enable_spread_spectrum(adev, false);
6997 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6998 si_stop_dpm(adev);
6999 si_reset_to_default(adev);
7000 si_dpm_stop_smc(adev);
7001 si_force_switch_to_arb_f0(adev);
7002
7003 ni_update_current_ps(adev, boot_ps);
7004 }
7005
si_dpm_pre_set_power_state(void * handle)7006 static int si_dpm_pre_set_power_state(void *handle)
7007 {
7008 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7009 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7010 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
7011 struct amdgpu_ps *new_ps = &requested_ps;
7012
7013 ni_update_requested_ps(adev, new_ps);
7014 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7015
7016 return 0;
7017 }
7018
si_power_control_set_level(struct amdgpu_device * adev)7019 static int si_power_control_set_level(struct amdgpu_device *adev)
7020 {
7021 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7022 int ret;
7023
7024 ret = si_restrict_performance_levels_before_switch(adev);
7025 if (ret)
7026 return ret;
7027 ret = si_halt_smc(adev);
7028 if (ret)
7029 return ret;
7030 ret = si_populate_smc_tdp_limits(adev, new_ps);
7031 if (ret)
7032 return ret;
7033 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7034 if (ret)
7035 return ret;
7036 ret = si_resume_smc(adev);
7037 if (ret)
7038 return ret;
7039 return si_set_sw_state(adev);
7040 }
7041
si_set_vce_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_rps,struct amdgpu_ps * old_rps)7042 static void si_set_vce_clock(struct amdgpu_device *adev,
7043 struct amdgpu_ps *new_rps,
7044 struct amdgpu_ps *old_rps)
7045 {
7046 if ((old_rps->evclk != new_rps->evclk) ||
7047 (old_rps->ecclk != new_rps->ecclk)) {
7048 /* Turn the clocks on when encoding, off otherwise */
7049 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk);
7050
7051 if (new_rps->evclk || new_rps->ecclk) {
7052 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);
7053 amdgpu_device_ip_set_clockgating_state(
7054 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE);
7055 amdgpu_device_ip_set_powergating_state(
7056 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE);
7057 } else {
7058 amdgpu_device_ip_set_powergating_state(
7059 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE);
7060 amdgpu_device_ip_set_clockgating_state(
7061 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE);
7062 amdgpu_asic_set_vce_clocks(adev, 0, 0);
7063 }
7064 }
7065 }
7066
si_dpm_set_power_state(void * handle)7067 static int si_dpm_set_power_state(void *handle)
7068 {
7069 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7070 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7071 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7072 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7073 int ret;
7074
7075 ret = si_disable_ulv(adev);
7076 if (ret) {
7077 DRM_ERROR("si_disable_ulv failed\n");
7078 return ret;
7079 }
7080 ret = si_restrict_performance_levels_before_switch(adev);
7081 if (ret) {
7082 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7083 return ret;
7084 }
7085 if (eg_pi->pcie_performance_request)
7086 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7087 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7088 ret = si_enable_power_containment(adev, new_ps, false);
7089 if (ret) {
7090 DRM_ERROR("si_enable_power_containment failed\n");
7091 return ret;
7092 }
7093 ret = si_enable_smc_cac(adev, new_ps, false);
7094 if (ret) {
7095 DRM_ERROR("si_enable_smc_cac failed\n");
7096 return ret;
7097 }
7098 ret = si_halt_smc(adev);
7099 if (ret) {
7100 DRM_ERROR("si_halt_smc failed\n");
7101 return ret;
7102 }
7103 ret = si_upload_sw_state(adev, new_ps);
7104 if (ret) {
7105 DRM_ERROR("si_upload_sw_state failed\n");
7106 return ret;
7107 }
7108 ret = si_upload_smc_data(adev);
7109 if (ret) {
7110 DRM_ERROR("si_upload_smc_data failed\n");
7111 return ret;
7112 }
7113 ret = si_upload_ulv_state(adev);
7114 if (ret) {
7115 DRM_ERROR("si_upload_ulv_state failed\n");
7116 return ret;
7117 }
7118 if (eg_pi->dynamic_ac_timing) {
7119 ret = si_upload_mc_reg_table(adev, new_ps);
7120 if (ret) {
7121 DRM_ERROR("si_upload_mc_reg_table failed\n");
7122 return ret;
7123 }
7124 }
7125 ret = si_program_memory_timing_parameters(adev, new_ps);
7126 if (ret) {
7127 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7128 return ret;
7129 }
7130 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7131
7132 ret = si_resume_smc(adev);
7133 if (ret) {
7134 DRM_ERROR("si_resume_smc failed\n");
7135 return ret;
7136 }
7137 ret = si_set_sw_state(adev);
7138 if (ret) {
7139 DRM_ERROR("si_set_sw_state failed\n");
7140 return ret;
7141 }
7142 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7143 si_set_vce_clock(adev, new_ps, old_ps);
7144 if (eg_pi->pcie_performance_request)
7145 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7146 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7147 if (ret) {
7148 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7149 return ret;
7150 }
7151 ret = si_enable_smc_cac(adev, new_ps, true);
7152 if (ret) {
7153 DRM_ERROR("si_enable_smc_cac failed\n");
7154 return ret;
7155 }
7156 ret = si_enable_power_containment(adev, new_ps, true);
7157 if (ret) {
7158 DRM_ERROR("si_enable_power_containment failed\n");
7159 return ret;
7160 }
7161
7162 ret = si_power_control_set_level(adev);
7163 if (ret) {
7164 DRM_ERROR("si_power_control_set_level failed\n");
7165 return ret;
7166 }
7167
7168 return 0;
7169 }
7170
si_dpm_post_set_power_state(void * handle)7171 static void si_dpm_post_set_power_state(void *handle)
7172 {
7173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7174 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7175 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7176
7177 ni_update_current_ps(adev, new_ps);
7178 }
7179
7180 #if 0
7181 void si_dpm_reset_asic(struct amdgpu_device *adev)
7182 {
7183 si_restrict_performance_levels_before_switch(adev);
7184 si_disable_ulv(adev);
7185 si_set_boot_state(adev);
7186 }
7187 #endif
7188
si_dpm_display_configuration_changed(void * handle)7189 static void si_dpm_display_configuration_changed(void *handle)
7190 {
7191 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7192
7193 si_program_display_gap(adev);
7194 }
7195
7196
si_parse_pplib_non_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)7197 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7198 struct amdgpu_ps *rps,
7199 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7200 u8 table_rev)
7201 {
7202 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7203 rps->class = le16_to_cpu(non_clock_info->usClassification);
7204 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7205
7206 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7207 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7208 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7209 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7210 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7211 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7212 } else {
7213 rps->vclk = 0;
7214 rps->dclk = 0;
7215 }
7216
7217 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7218 adev->pm.dpm.boot_ps = rps;
7219 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7220 adev->pm.dpm.uvd_ps = rps;
7221 }
7222
si_parse_pplib_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,int index,union pplib_clock_info * clock_info)7223 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7224 struct amdgpu_ps *rps, int index,
7225 union pplib_clock_info *clock_info)
7226 {
7227 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7228 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7229 struct si_power_info *si_pi = si_get_pi(adev);
7230 struct si_ps *ps = si_get_ps(rps);
7231 u16 leakage_voltage;
7232 struct rv7xx_pl *pl = &ps->performance_levels[index];
7233 int ret;
7234
7235 ps->performance_level_count = index + 1;
7236
7237 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7238 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7239 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7240 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7241
7242 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7243 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7244 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7245 pl->pcie_gen = si_gen_pcie_gen_support(adev,
7246 si_pi->sys_pcie_mask,
7247 si_pi->boot_pcie_gen,
7248 clock_info->si.ucPCIEGen);
7249
7250 /* patch up vddc if necessary */
7251 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7252 &leakage_voltage);
7253 if (ret == 0)
7254 pl->vddc = leakage_voltage;
7255
7256 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7257 pi->acpi_vddc = pl->vddc;
7258 eg_pi->acpi_vddci = pl->vddci;
7259 si_pi->acpi_pcie_gen = pl->pcie_gen;
7260 }
7261
7262 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7263 index == 0) {
7264 /* XXX disable for A0 tahiti */
7265 si_pi->ulv.supported = false;
7266 si_pi->ulv.pl = *pl;
7267 si_pi->ulv.one_pcie_lane_in_ulv = false;
7268 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7269 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7270 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7271 }
7272
7273 if (pi->min_vddc_in_table > pl->vddc)
7274 pi->min_vddc_in_table = pl->vddc;
7275
7276 if (pi->max_vddc_in_table < pl->vddc)
7277 pi->max_vddc_in_table = pl->vddc;
7278
7279 /* patch up boot state */
7280 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7281 u16 vddc, vddci, mvdd;
7282 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7283 pl->mclk = adev->clock.default_mclk;
7284 pl->sclk = adev->clock.default_sclk;
7285 pl->vddc = vddc;
7286 pl->vddci = vddci;
7287 si_pi->mvdd_bootup_value = mvdd;
7288 }
7289
7290 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7291 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7292 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7293 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7294 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7295 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7296 }
7297 }
7298
7299 union pplib_power_state {
7300 struct _ATOM_PPLIB_STATE v1;
7301 struct _ATOM_PPLIB_STATE_V2 v2;
7302 };
7303
si_parse_power_table(struct amdgpu_device * adev)7304 static int si_parse_power_table(struct amdgpu_device *adev)
7305 {
7306 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7307 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7308 union pplib_power_state *power_state;
7309 int i, j, k, non_clock_array_index, clock_array_index;
7310 union pplib_clock_info *clock_info;
7311 struct _StateArray *state_array;
7312 struct _ClockInfoArray *clock_info_array;
7313 struct _NonClockInfoArray *non_clock_info_array;
7314 union power_info *power_info;
7315 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7316 u16 data_offset;
7317 u8 frev, crev;
7318 u8 *power_state_offset;
7319 struct si_ps *ps;
7320
7321 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7322 &frev, &crev, &data_offset))
7323 return -EINVAL;
7324 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7325
7326 amdgpu_add_thermal_controller(adev);
7327
7328 state_array = (struct _StateArray *)
7329 (mode_info->atom_context->bios + data_offset +
7330 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7331 clock_info_array = (struct _ClockInfoArray *)
7332 (mode_info->atom_context->bios + data_offset +
7333 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7334 non_clock_info_array = (struct _NonClockInfoArray *)
7335 (mode_info->atom_context->bios + data_offset +
7336 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7337
7338 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
7339 sizeof(struct amdgpu_ps),
7340 GFP_KERNEL);
7341 if (!adev->pm.dpm.ps)
7342 return -ENOMEM;
7343 power_state_offset = (u8 *)state_array->states;
7344 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) {
7345 u8 *idx;
7346 power_state = (union pplib_power_state *)power_state_offset;
7347 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7348 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7349 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7350 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7351 if (ps == NULL)
7352 return -ENOMEM;
7353 adev->pm.dpm.ps[i].ps_priv = ps;
7354 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7355 non_clock_info,
7356 non_clock_info_array->ucEntrySize);
7357 k = 0;
7358 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7359 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7360 clock_array_index = idx[j];
7361 if (clock_array_index >= clock_info_array->ucNumEntries)
7362 continue;
7363 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7364 break;
7365 clock_info = (union pplib_clock_info *)
7366 ((u8 *)&clock_info_array->clockInfo[0] +
7367 (clock_array_index * clock_info_array->ucEntrySize));
7368 si_parse_pplib_clock_info(adev,
7369 &adev->pm.dpm.ps[i], k,
7370 clock_info);
7371 k++;
7372 }
7373 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7374 adev->pm.dpm.num_ps++;
7375 }
7376
7377 /* fill in the vce power states */
7378 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7379 u32 sclk, mclk;
7380 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7381 clock_info = (union pplib_clock_info *)
7382 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7383 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7384 sclk |= clock_info->si.ucEngineClockHigh << 16;
7385 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7386 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7387 adev->pm.dpm.vce_states[i].sclk = sclk;
7388 adev->pm.dpm.vce_states[i].mclk = mclk;
7389 }
7390
7391 return 0;
7392 }
7393
si_dpm_init(struct amdgpu_device * adev)7394 static int si_dpm_init(struct amdgpu_device *adev)
7395 {
7396 struct rv7xx_power_info *pi;
7397 struct evergreen_power_info *eg_pi;
7398 struct ni_power_info *ni_pi;
7399 struct si_power_info *si_pi;
7400 struct atom_clock_dividers dividers;
7401 int ret;
7402
7403 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7404 if (si_pi == NULL)
7405 return -ENOMEM;
7406 adev->pm.dpm.priv = si_pi;
7407 ni_pi = &si_pi->ni;
7408 eg_pi = &ni_pi->eg;
7409 pi = &eg_pi->rv7xx;
7410
7411 si_pi->sys_pcie_mask =
7412 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7413 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
7414 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7415
7416 si_set_max_cu_value(adev);
7417
7418 rv770_get_max_vddc(adev);
7419 si_get_leakage_vddc(adev);
7420 si_patch_dependency_tables_based_on_leakage(adev);
7421
7422 pi->acpi_vddc = 0;
7423 eg_pi->acpi_vddci = 0;
7424 pi->min_vddc_in_table = 0;
7425 pi->max_vddc_in_table = 0;
7426
7427 ret = amdgpu_get_platform_caps(adev);
7428 if (ret)
7429 return ret;
7430
7431 ret = amdgpu_parse_extended_power_table(adev);
7432 if (ret)
7433 return ret;
7434
7435 ret = si_parse_power_table(adev);
7436 if (ret)
7437 return ret;
7438
7439 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7440 kcalloc(4,
7441 sizeof(struct amdgpu_clock_voltage_dependency_entry),
7442 GFP_KERNEL);
7443 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)
7444 return -ENOMEM;
7445
7446 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7447 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7448 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7449 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7450 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7451 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7452 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7453 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7454 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7455
7456 if (adev->pm.dpm.voltage_response_time == 0)
7457 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7458 if (adev->pm.dpm.backbias_response_time == 0)
7459 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7460
7461 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7462 0, false, ÷rs);
7463 if (ret)
7464 pi->ref_div = dividers.ref_div + 1;
7465 else
7466 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7467
7468 eg_pi->smu_uvd_hs = false;
7469
7470 pi->mclk_strobe_mode_threshold = 40000;
7471 if (si_is_special_1gb_platform(adev))
7472 pi->mclk_stutter_mode_threshold = 0;
7473 else
7474 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7475 pi->mclk_edc_enable_threshold = 40000;
7476 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7477
7478 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7479
7480 pi->voltage_control =
7481 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7482 VOLTAGE_OBJ_GPIO_LUT);
7483 if (!pi->voltage_control) {
7484 si_pi->voltage_control_svi2 =
7485 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7486 VOLTAGE_OBJ_SVID2);
7487 if (si_pi->voltage_control_svi2)
7488 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7489 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7490 }
7491
7492 pi->mvdd_control =
7493 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7494 VOLTAGE_OBJ_GPIO_LUT);
7495
7496 eg_pi->vddci_control =
7497 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7498 VOLTAGE_OBJ_GPIO_LUT);
7499 if (!eg_pi->vddci_control)
7500 si_pi->vddci_control_svi2 =
7501 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7502 VOLTAGE_OBJ_SVID2);
7503
7504 si_pi->vddc_phase_shed_control =
7505 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7506 VOLTAGE_OBJ_PHASE_LUT);
7507
7508 rv770_get_engine_memory_ss(adev);
7509
7510 pi->asi = RV770_ASI_DFLT;
7511 pi->pasi = CYPRESS_HASI_DFLT;
7512 pi->vrc = SISLANDS_VRC_DFLT;
7513
7514 eg_pi->sclk_deep_sleep = true;
7515 si_pi->sclk_deep_sleep_above_low = false;
7516
7517 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7518 pi->thermal_protection = true;
7519 else
7520 pi->thermal_protection = false;
7521
7522 eg_pi->dynamic_ac_timing = true;
7523
7524 #if defined(CONFIG_ACPI)
7525 eg_pi->pcie_performance_request =
7526 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7527 #else
7528 eg_pi->pcie_performance_request = false;
7529 #endif
7530
7531 si_pi->sram_end = SMC_RAM_END;
7532
7533 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7534 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7535 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7536 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7537 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7538 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7539 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7540
7541 si_initialize_powertune_defaults(adev);
7542
7543 /* make sure dc limits are valid */
7544 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7545 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7546 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7547 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7548
7549 si_pi->fan_ctrl_is_in_default_mode = true;
7550
7551 return 0;
7552 }
7553
si_dpm_fini(struct amdgpu_device * adev)7554 static void si_dpm_fini(struct amdgpu_device *adev)
7555 {
7556 int i;
7557
7558 if (adev->pm.dpm.ps)
7559 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7560 kfree(adev->pm.dpm.ps[i].ps_priv);
7561 kfree(adev->pm.dpm.ps);
7562 kfree(adev->pm.dpm.priv);
7563 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7564 amdgpu_free_extended_power_table(adev);
7565 }
7566
si_dpm_debugfs_print_current_performance_level(void * handle,struct seq_file * m)7567 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7568 struct seq_file *m)
7569 {
7570 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7571 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7572 struct amdgpu_ps *rps = &eg_pi->current_rps;
7573 struct si_ps *ps = si_get_ps(rps);
7574 struct rv7xx_pl *pl;
7575 u32 current_index =
7576 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
7577 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
7578
7579 if (current_index >= ps->performance_level_count) {
7580 seq_printf(m, "invalid dpm profile %d\n", current_index);
7581 } else {
7582 pl = &ps->performance_levels[current_index];
7583 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7584 seq_printf(m, "vce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7585 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7586 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7587 }
7588 }
7589
si_dpm_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)7590 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7591 struct amdgpu_irq_src *source,
7592 unsigned type,
7593 enum amdgpu_interrupt_state state)
7594 {
7595 u32 cg_thermal_int;
7596
7597 switch (type) {
7598 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7599 switch (state) {
7600 case AMDGPU_IRQ_STATE_DISABLE:
7601 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7602 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7603 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7604 break;
7605 case AMDGPU_IRQ_STATE_ENABLE:
7606 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7607 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7608 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7609 break;
7610 default:
7611 break;
7612 }
7613 break;
7614
7615 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7616 switch (state) {
7617 case AMDGPU_IRQ_STATE_DISABLE:
7618 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7619 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7620 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7621 break;
7622 case AMDGPU_IRQ_STATE_ENABLE:
7623 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7624 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7625 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7626 break;
7627 default:
7628 break;
7629 }
7630 break;
7631
7632 default:
7633 break;
7634 }
7635 return 0;
7636 }
7637
si_dpm_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)7638 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7639 struct amdgpu_irq_src *source,
7640 struct amdgpu_iv_entry *entry)
7641 {
7642 bool queue_thermal = false;
7643
7644 if (entry == NULL)
7645 return -EINVAL;
7646
7647 switch (entry->src_id) {
7648 case 230: /* thermal low to high */
7649 DRM_DEBUG("IH: thermal low to high\n");
7650 adev->pm.dpm.thermal.high_to_low = false;
7651 queue_thermal = true;
7652 break;
7653 case 231: /* thermal high to low */
7654 DRM_DEBUG("IH: thermal high to low\n");
7655 adev->pm.dpm.thermal.high_to_low = true;
7656 queue_thermal = true;
7657 break;
7658 default:
7659 break;
7660 }
7661
7662 if (queue_thermal)
7663 schedule_work(&adev->pm.dpm.thermal.work);
7664
7665 return 0;
7666 }
7667
si_dpm_late_init(struct amdgpu_ip_block * ip_block)7668 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block)
7669 {
7670 int ret;
7671 struct amdgpu_device *adev = ip_block->adev;
7672
7673 if (!adev->pm.dpm_enabled)
7674 return 0;
7675
7676 ret = si_set_temperature_range(adev);
7677 if (ret)
7678 return ret;
7679 #if 0 //TODO ?
7680 si_dpm_powergate_uvd(adev, true);
7681 #endif
7682 return 0;
7683 }
7684
7685 /**
7686 * si_dpm_init_microcode - load ucode images from disk
7687 *
7688 * @adev: amdgpu_device pointer
7689 *
7690 * Use the firmware interface to load the ucode images into
7691 * the driver (not loaded into hw).
7692 * Returns 0 on success, error on failure.
7693 */
si_dpm_init_microcode(struct amdgpu_device * adev)7694 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7695 {
7696 const char *chip_name;
7697 int err;
7698
7699 DRM_DEBUG("\n");
7700 switch (adev->asic_type) {
7701 case CHIP_TAHITI:
7702 chip_name = "tahiti";
7703 break;
7704 case CHIP_PITCAIRN:
7705 if ((adev->pdev->revision == 0x81) &&
7706 ((adev->pdev->device == 0x6810) ||
7707 (adev->pdev->device == 0x6811)))
7708 chip_name = "pitcairn_k";
7709 else
7710 chip_name = "pitcairn";
7711 break;
7712 case CHIP_VERDE:
7713 if (((adev->pdev->device == 0x6820) &&
7714 ((adev->pdev->revision == 0x81) ||
7715 (adev->pdev->revision == 0x83))) ||
7716 ((adev->pdev->device == 0x6821) &&
7717 ((adev->pdev->revision == 0x83) ||
7718 (adev->pdev->revision == 0x87))) ||
7719 ((adev->pdev->revision == 0x87) &&
7720 ((adev->pdev->device == 0x6823) ||
7721 (adev->pdev->device == 0x682b))))
7722 chip_name = "verde_k";
7723 else
7724 chip_name = "verde";
7725 break;
7726 case CHIP_OLAND:
7727 if (((adev->pdev->revision == 0x81) &&
7728 ((adev->pdev->device == 0x6600) ||
7729 (adev->pdev->device == 0x6604) ||
7730 (adev->pdev->device == 0x6605) ||
7731 (adev->pdev->device == 0x6610))) ||
7732 ((adev->pdev->revision == 0x83) &&
7733 (adev->pdev->device == 0x6610)))
7734 chip_name = "oland_k";
7735 else
7736 chip_name = "oland";
7737 break;
7738 case CHIP_HAINAN:
7739 if (((adev->pdev->revision == 0x81) &&
7740 (adev->pdev->device == 0x6660)) ||
7741 ((adev->pdev->revision == 0x83) &&
7742 ((adev->pdev->device == 0x6660) ||
7743 (adev->pdev->device == 0x6663) ||
7744 (adev->pdev->device == 0x6665) ||
7745 (adev->pdev->device == 0x6667))))
7746 chip_name = "hainan_k";
7747 else if ((adev->pdev->revision == 0xc3) &&
7748 (adev->pdev->device == 0x6665))
7749 chip_name = "banks_k_2";
7750 else
7751 chip_name = "hainan";
7752 break;
7753 default: BUG();
7754 }
7755
7756 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
7757 "amdgpu/%s_smc.bin", chip_name);
7758 if (err) {
7759 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n",
7760 err, chip_name);
7761 amdgpu_ucode_release(&adev->pm.fw);
7762 }
7763 return err;
7764 }
7765
si_dpm_sw_init(struct amdgpu_ip_block * ip_block)7766 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block)
7767 {
7768 int ret;
7769 struct amdgpu_device *adev = ip_block->adev;
7770
7771 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7772 if (ret)
7773 return ret;
7774
7775 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7776 if (ret)
7777 return ret;
7778
7779 /* default to balanced state */
7780 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7781 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7782 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7783 adev->pm.default_sclk = adev->clock.default_sclk;
7784 adev->pm.default_mclk = adev->clock.default_mclk;
7785 adev->pm.current_sclk = adev->clock.default_sclk;
7786 adev->pm.current_mclk = adev->clock.default_mclk;
7787 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7788
7789 if (amdgpu_dpm == 0)
7790 return 0;
7791
7792 ret = si_dpm_init_microcode(adev);
7793 if (ret)
7794 return ret;
7795
7796 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7797 ret = si_dpm_init(adev);
7798 if (ret)
7799 goto dpm_failed;
7800 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7801 if (amdgpu_dpm == 1)
7802 amdgpu_pm_print_power_states(adev);
7803 DRM_INFO("amdgpu: dpm initialized\n");
7804
7805 return 0;
7806
7807 dpm_failed:
7808 si_dpm_fini(adev);
7809 DRM_ERROR("amdgpu: dpm initialization failed\n");
7810 return ret;
7811 }
7812
si_dpm_sw_fini(struct amdgpu_ip_block * ip_block)7813 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block)
7814 {
7815 struct amdgpu_device *adev = ip_block->adev;
7816
7817 flush_work(&adev->pm.dpm.thermal.work);
7818
7819 si_dpm_fini(adev);
7820
7821 return 0;
7822 }
7823
si_dpm_hw_init(struct amdgpu_ip_block * ip_block)7824 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block)
7825 {
7826 int ret;
7827
7828 struct amdgpu_device *adev = ip_block->adev;
7829
7830 if (!amdgpu_dpm)
7831 return 0;
7832
7833 mutex_lock(&adev->pm.mutex);
7834 si_dpm_setup_asic(adev);
7835 ret = si_dpm_enable(adev);
7836 if (ret)
7837 adev->pm.dpm_enabled = false;
7838 else
7839 adev->pm.dpm_enabled = true;
7840 amdgpu_legacy_dpm_compute_clocks(adev);
7841 mutex_unlock(&adev->pm.mutex);
7842 return ret;
7843 }
7844
si_dpm_hw_fini(struct amdgpu_ip_block * ip_block)7845 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block)
7846 {
7847 struct amdgpu_device *adev = ip_block->adev;
7848
7849 if (adev->pm.dpm_enabled)
7850 si_dpm_disable(adev);
7851
7852 return 0;
7853 }
7854
si_dpm_suspend(struct amdgpu_ip_block * ip_block)7855 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block)
7856 {
7857 struct amdgpu_device *adev = ip_block->adev;
7858
7859 cancel_work_sync(&adev->pm.dpm.thermal.work);
7860
7861 if (adev->pm.dpm_enabled) {
7862 mutex_lock(&adev->pm.mutex);
7863 adev->pm.dpm_enabled = false;
7864 /* disable dpm */
7865 si_dpm_disable(adev);
7866 /* reset the power state */
7867 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7868 mutex_unlock(&adev->pm.mutex);
7869 }
7870
7871 return 0;
7872 }
7873
si_dpm_resume(struct amdgpu_ip_block * ip_block)7874 static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
7875 {
7876 int ret = 0;
7877 struct amdgpu_device *adev = ip_block->adev;
7878
7879 if (!amdgpu_dpm)
7880 return 0;
7881
7882 if (!adev->pm.dpm_enabled) {
7883 /* asic init will reset to the boot state */
7884 mutex_lock(&adev->pm.mutex);
7885 si_dpm_setup_asic(adev);
7886 ret = si_dpm_enable(adev);
7887 if (ret) {
7888 adev->pm.dpm_enabled = false;
7889 } else {
7890 adev->pm.dpm_enabled = true;
7891 amdgpu_legacy_dpm_compute_clocks(adev);
7892 }
7893 mutex_unlock(&adev->pm.mutex);
7894 }
7895
7896 return ret;
7897 }
7898
si_dpm_is_idle(struct amdgpu_ip_block * ip_block)7899 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
7900 {
7901 /* XXX */
7902 return true;
7903 }
7904
si_dpm_wait_for_idle(struct amdgpu_ip_block * ip_block)7905 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block)
7906 {
7907 /* XXX */
7908 return 0;
7909 }
7910
si_dpm_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)7911 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
7912 enum amd_clockgating_state state)
7913 {
7914 return 0;
7915 }
7916
si_dpm_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)7917 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
7918 enum amd_powergating_state state)
7919 {
7920 return 0;
7921 }
7922
7923 /* get temperature in millidegrees */
si_dpm_get_temp(void * handle)7924 static int si_dpm_get_temp(void *handle)
7925 {
7926 u32 temp;
7927 int actual_temp = 0;
7928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7929
7930 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
7931 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
7932
7933 if (temp & 0x200)
7934 actual_temp = 255;
7935 else
7936 actual_temp = temp & 0x1ff;
7937
7938 actual_temp = (actual_temp * 1000);
7939
7940 return actual_temp;
7941 }
7942
si_dpm_get_sclk(void * handle,bool low)7943 static u32 si_dpm_get_sclk(void *handle, bool low)
7944 {
7945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7946 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7947 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7948
7949 if (low)
7950 return requested_state->performance_levels[0].sclk;
7951 else
7952 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7953 }
7954
si_dpm_get_mclk(void * handle,bool low)7955 static u32 si_dpm_get_mclk(void *handle, bool low)
7956 {
7957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7958 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7959 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7960
7961 if (low)
7962 return requested_state->performance_levels[0].mclk;
7963 else
7964 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7965 }
7966
si_dpm_print_power_state(void * handle,void * current_ps)7967 static void si_dpm_print_power_state(void *handle,
7968 void *current_ps)
7969 {
7970 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7971 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7972 struct si_ps *ps = si_get_ps(rps);
7973 struct rv7xx_pl *pl;
7974 int i;
7975
7976 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
7977 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
7978 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7979 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7980 for (i = 0; i < ps->performance_level_count; i++) {
7981 pl = &ps->performance_levels[i];
7982 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7983 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7984 }
7985 amdgpu_dpm_dbg_print_ps_status(adev, rps);
7986 }
7987
si_dpm_early_init(struct amdgpu_ip_block * ip_block)7988 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block)
7989 {
7990
7991 struct amdgpu_device *adev = ip_block->adev;
7992
7993 adev->powerplay.pp_funcs = &si_dpm_funcs;
7994 adev->powerplay.pp_handle = adev;
7995 si_dpm_set_irq_funcs(adev);
7996 return 0;
7997 }
7998
si_are_power_levels_equal(const struct rv7xx_pl * si_cpl1,const struct rv7xx_pl * si_cpl2)7999 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
8000 const struct rv7xx_pl *si_cpl2)
8001 {
8002 return ((si_cpl1->mclk == si_cpl2->mclk) &&
8003 (si_cpl1->sclk == si_cpl2->sclk) &&
8004 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
8005 (si_cpl1->vddc == si_cpl2->vddc) &&
8006 (si_cpl1->vddci == si_cpl2->vddci));
8007 }
8008
si_check_state_equal(void * handle,void * current_ps,void * request_ps,bool * equal)8009 static int si_check_state_equal(void *handle,
8010 void *current_ps,
8011 void *request_ps,
8012 bool *equal)
8013 {
8014 struct si_ps *si_cps;
8015 struct si_ps *si_rps;
8016 int i;
8017 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
8018 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
8019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8020
8021 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
8022 return -EINVAL;
8023
8024 si_cps = si_get_ps((struct amdgpu_ps *)cps);
8025 si_rps = si_get_ps((struct amdgpu_ps *)rps);
8026
8027 if (si_cps == NULL) {
8028 printk("si_cps is NULL\n");
8029 *equal = false;
8030 return 0;
8031 }
8032
8033 if (si_cps->performance_level_count != si_rps->performance_level_count) {
8034 *equal = false;
8035 return 0;
8036 }
8037
8038 for (i = 0; i < si_cps->performance_level_count; i++) {
8039 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8040 &(si_rps->performance_levels[i]))) {
8041 *equal = false;
8042 return 0;
8043 }
8044 }
8045
8046 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8047 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8048 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8049
8050 return 0;
8051 }
8052
si_dpm_read_sensor(void * handle,int idx,void * value,int * size)8053 static int si_dpm_read_sensor(void *handle, int idx,
8054 void *value, int *size)
8055 {
8056 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8057 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
8058 struct amdgpu_ps *rps = &eg_pi->current_rps;
8059 struct si_ps *ps = si_get_ps(rps);
8060 uint32_t sclk, mclk;
8061 u32 pl_index =
8062 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
8063 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
8064
8065 /* size must be at least 4 bytes for all sensors */
8066 if (*size < 4)
8067 return -EINVAL;
8068
8069 switch (idx) {
8070 case AMDGPU_PP_SENSOR_GFX_SCLK:
8071 if (pl_index < ps->performance_level_count) {
8072 sclk = ps->performance_levels[pl_index].sclk;
8073 *((uint32_t *)value) = sclk;
8074 *size = 4;
8075 return 0;
8076 }
8077 return -EINVAL;
8078 case AMDGPU_PP_SENSOR_GFX_MCLK:
8079 if (pl_index < ps->performance_level_count) {
8080 mclk = ps->performance_levels[pl_index].mclk;
8081 *((uint32_t *)value) = mclk;
8082 *size = 4;
8083 return 0;
8084 }
8085 return -EINVAL;
8086 case AMDGPU_PP_SENSOR_GPU_TEMP:
8087 *((uint32_t *)value) = si_dpm_get_temp(adev);
8088 *size = 4;
8089 return 0;
8090 default:
8091 return -EOPNOTSUPP;
8092 }
8093 }
8094
8095 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8096 .name = "si_dpm",
8097 .early_init = si_dpm_early_init,
8098 .late_init = si_dpm_late_init,
8099 .sw_init = si_dpm_sw_init,
8100 .sw_fini = si_dpm_sw_fini,
8101 .hw_init = si_dpm_hw_init,
8102 .hw_fini = si_dpm_hw_fini,
8103 .suspend = si_dpm_suspend,
8104 .resume = si_dpm_resume,
8105 .is_idle = si_dpm_is_idle,
8106 .wait_for_idle = si_dpm_wait_for_idle,
8107 .set_clockgating_state = si_dpm_set_clockgating_state,
8108 .set_powergating_state = si_dpm_set_powergating_state,
8109 };
8110
8111 const struct amdgpu_ip_block_version si_smu_ip_block =
8112 {
8113 .type = AMD_IP_BLOCK_TYPE_SMC,
8114 .major = 6,
8115 .minor = 0,
8116 .rev = 0,
8117 .funcs = &si_dpm_ip_funcs,
8118 };
8119
8120 static const struct amd_pm_funcs si_dpm_funcs = {
8121 .pre_set_power_state = &si_dpm_pre_set_power_state,
8122 .set_power_state = &si_dpm_set_power_state,
8123 .post_set_power_state = &si_dpm_post_set_power_state,
8124 .display_configuration_changed = &si_dpm_display_configuration_changed,
8125 .get_sclk = &si_dpm_get_sclk,
8126 .get_mclk = &si_dpm_get_mclk,
8127 .print_power_state = &si_dpm_print_power_state,
8128 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8129 .force_performance_level = &si_dpm_force_performance_level,
8130 .vblank_too_short = &si_dpm_vblank_too_short,
8131 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8132 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8133 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm,
8134 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm,
8135 .check_state_equal = &si_check_state_equal,
8136 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8137 .read_sensor = &si_dpm_read_sensor,
8138 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks,
8139 };
8140
8141 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8142 .set = si_dpm_set_interrupt_state,
8143 .process = si_dpm_process_interrupt,
8144 };
8145
si_dpm_set_irq_funcs(struct amdgpu_device * adev)8146 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8147 {
8148 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8149 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8150 }
8151
8152