1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <kunit/static_stub.h> 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/wmfw.h> 14 #include <linux/fs.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/stddef.h> 22 #include <linux/string.h> 23 #include <linux/string_choices.h> 24 #include <linux/types.h> 25 #include <sound/cs-amp-lib.h> 26 27 #include "cs35l56.h" 28 29 static const struct reg_sequence cs35l56_asp_patch[] = { 30 /* 31 * Firmware can change these to non-defaults to satisfy SDCA. 32 * Ensure that they are at known defaults. 33 */ 34 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 35 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 36 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 37 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 42 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 43 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 44 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 45 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 46 }; 47 48 int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base) 49 { 50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_asp_patch, 51 ARRAY_SIZE(cs35l56_asp_patch)); 52 } 53 EXPORT_SYMBOL_NS_GPL(cs35l56_set_asp_patch, "SND_SOC_CS35L56_SHARED"); 54 55 static const struct reg_sequence cs35l56_patch[] = { 56 /* 57 * Firmware can change these to non-defaults to satisfy SDCA. 58 * Ensure that they are at known defaults. 59 */ 60 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 61 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 62 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 63 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 64 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 65 }; 66 67 static const struct reg_sequence cs35l56_patch_fw[] = { 68 /* These are not reset by a soft-reset, so patch to defaults. */ 69 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 70 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 71 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 72 }; 73 74 static const struct reg_sequence cs35l63_patch_fw[] = { 75 /* These are not reset by a soft-reset, so patch to defaults. */ 76 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 77 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 78 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 79 }; 80 81 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 82 { 83 int ret; 84 85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 86 ARRAY_SIZE(cs35l56_patch)); 87 if (ret) 88 return ret; 89 90 91 switch (cs35l56_base->type) { 92 case 0x54: 93 case 0x56: 94 case 0x57: 95 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 96 ARRAY_SIZE(cs35l56_patch_fw)); 97 break; 98 case 0x63: 99 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 100 ARRAY_SIZE(cs35l63_patch_fw)); 101 break; 102 default: 103 break; 104 } 105 106 return ret; 107 } 108 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 109 110 static const struct reg_default cs35l56_reg_defaults[] = { 111 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 112 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 113 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 114 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 115 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 116 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 117 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 118 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 119 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 120 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 121 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 122 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 123 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 124 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 125 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 126 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 127 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 128 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 129 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 130 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 131 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 132 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 133 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 134 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 135 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 136 }; 137 138 static const struct reg_default cs35l63_reg_defaults[] = { 139 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 140 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 141 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 142 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 143 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 144 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 145 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 146 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 147 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 148 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 149 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 150 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 151 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 152 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 153 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 154 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 155 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 156 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 157 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 158 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 159 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 160 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 161 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 162 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 163 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 164 }; 165 166 static bool cs35l56_is_dsp_memory(unsigned int reg) 167 { 168 switch (reg) { 169 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 170 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 171 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 172 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 173 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 174 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 175 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 183 { 184 switch (reg) { 185 case CS35L56_DEVID: 186 case CS35L56_REVID: 187 case CS35L56_RELID: 188 case CS35L56_OTPID: 189 case CS35L56_SFT_RESET: 190 case CS35L56_GLOBAL_ENABLES: 191 case CS35L56_BLOCK_ENABLES: 192 case CS35L56_BLOCK_ENABLES2: 193 case CS35L56_REFCLK_INPUT: 194 case CS35L56_GLOBAL_SAMPLE_RATE: 195 case CS35L56_OTP_MEM_53: 196 case CS35L56_OTP_MEM_54: 197 case CS35L56_OTP_MEM_55: 198 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 199 case CS35L56_UPDATE_REGS: 200 case CS35L56_ASP1_ENABLES1: 201 case CS35L56_ASP1_CONTROL1: 202 case CS35L56_ASP1_CONTROL2: 203 case CS35L56_ASP1_CONTROL3: 204 case CS35L56_ASP1_FRAME_CONTROL1: 205 case CS35L56_ASP1_FRAME_CONTROL5: 206 case CS35L56_ASP1_DATA_CONTROL1: 207 case CS35L56_ASP1_DATA_CONTROL5: 208 case CS35L56_DACPCM1_INPUT: 209 case CS35L56_DACPCM2_INPUT: 210 case CS35L56_ASP1TX1_INPUT: 211 case CS35L56_ASP1TX2_INPUT: 212 case CS35L56_ASP1TX3_INPUT: 213 case CS35L56_ASP1TX4_INPUT: 214 case CS35L56_DSP1RX1_INPUT: 215 case CS35L56_DSP1RX2_INPUT: 216 case CS35L56_SWIRE_DP3_CH1_INPUT: 217 case CS35L56_SWIRE_DP3_CH2_INPUT: 218 case CS35L56_SWIRE_DP3_CH3_INPUT: 219 case CS35L56_SWIRE_DP3_CH4_INPUT: 220 case CS35L56_IRQ1_CFG: 221 case CS35L56_IRQ1_STATUS: 222 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 223 case CS35L56_IRQ1_EINT_18: 224 case CS35L56_IRQ1_EINT_20: 225 case CS35L56_IRQ1_MASK_1: 226 case CS35L56_IRQ1_MASK_2: 227 case CS35L56_IRQ1_MASK_4: 228 case CS35L56_IRQ1_MASK_8: 229 case CS35L56_IRQ1_MASK_18: 230 case CS35L56_IRQ1_MASK_20: 231 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 232 case CS35L56_MIXER_NGATE_CH1_CFG: 233 case CS35L56_MIXER_NGATE_CH2_CFG: 234 case CS35L56_DSP_VIRTUAL1_MBOX_1: 235 case CS35L56_DSP_VIRTUAL1_MBOX_2: 236 case CS35L56_DSP_VIRTUAL1_MBOX_3: 237 case CS35L56_DSP_VIRTUAL1_MBOX_4: 238 case CS35L56_DSP_VIRTUAL1_MBOX_5: 239 case CS35L56_DSP_VIRTUAL1_MBOX_6: 240 case CS35L56_DSP_VIRTUAL1_MBOX_7: 241 case CS35L56_DSP_VIRTUAL1_MBOX_8: 242 case CS35L56_DIE_STS1: 243 case CS35L56_DIE_STS2: 244 case CS35L56_DSP_RESTRICT_STS1: 245 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 246 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 247 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 248 case CS35L56_DSP1_SCRATCH1: 249 case CS35L56_DSP1_SCRATCH2: 250 case CS35L56_DSP1_SCRATCH3: 251 case CS35L56_DSP1_SCRATCH4: 252 return true; 253 default: 254 return cs35l56_is_dsp_memory(reg); 255 } 256 } 257 258 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 259 { 260 switch (reg) { 261 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 262 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 263 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 264 return true; 265 default: 266 return false; 267 } 268 } 269 270 static bool cs35l56_common_volatile_reg(unsigned int reg) 271 { 272 switch (reg) { 273 case CS35L56_DEVID: 274 case CS35L56_REVID: 275 case CS35L56_RELID: 276 case CS35L56_OTPID: 277 case CS35L56_SFT_RESET: 278 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 279 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 280 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 281 case CS35L56_OTP_MEM_53: 282 case CS35L56_OTP_MEM_54: 283 case CS35L56_OTP_MEM_55: 284 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 285 case CS35L56_UPDATE_REGS: 286 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 287 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 288 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 289 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 290 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 291 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 292 case CS35L56_IRQ1_STATUS: 293 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 294 case CS35L56_IRQ1_EINT_18: 295 case CS35L56_IRQ1_EINT_20: 296 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 297 case CS35L56_MIXER_NGATE_CH1_CFG: 298 case CS35L56_MIXER_NGATE_CH2_CFG: 299 case CS35L56_DSP_VIRTUAL1_MBOX_1: 300 case CS35L56_DSP_VIRTUAL1_MBOX_2: 301 case CS35L56_DSP_VIRTUAL1_MBOX_3: 302 case CS35L56_DSP_VIRTUAL1_MBOX_4: 303 case CS35L56_DSP_VIRTUAL1_MBOX_5: 304 case CS35L56_DSP_VIRTUAL1_MBOX_6: 305 case CS35L56_DSP_VIRTUAL1_MBOX_7: 306 case CS35L56_DSP_VIRTUAL1_MBOX_8: 307 case CS35L56_DSP_RESTRICT_STS1: 308 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 309 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 310 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 311 case CS35L56_DSP1_SCRATCH1: 312 case CS35L56_DSP1_SCRATCH2: 313 case CS35L56_DSP1_SCRATCH3: 314 case CS35L56_DSP1_SCRATCH4: 315 return true; 316 default: 317 return cs35l56_is_dsp_memory(reg); 318 } 319 } 320 321 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 322 { 323 switch (reg) { 324 case CS35L56_MAIN_RENDER_USER_MUTE: 325 case CS35L56_MAIN_RENDER_USER_VOLUME: 326 case CS35L56_MAIN_POSTURE_NUMBER: 327 return false; 328 default: 329 return cs35l56_common_volatile_reg(reg); 330 } 331 } 332 333 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 334 { 335 switch (reg) { 336 case CS35L63_MAIN_RENDER_USER_MUTE: 337 case CS35L63_MAIN_RENDER_USER_VOLUME: 338 case CS35L63_MAIN_POSTURE_NUMBER: 339 return false; 340 default: 341 return cs35l56_common_volatile_reg(reg); 342 } 343 } 344 345 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 346 .fw_ver = CS35L56_DSP1_FW_VER, 347 .halo_state = CS35L56_DSP1_HALO_STATE, 348 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 349 .prot_sts = CS35L56_PROTECTION_STATUS, 350 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 351 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 352 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 353 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 354 }; 355 356 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 357 .fw_ver = CS35L56_DSP1_FW_VER, 358 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 359 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 360 .prot_sts = CS35L56_PROTECTION_STATUS, 361 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 362 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 363 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 364 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 365 }; 366 367 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 368 .fw_ver = CS35L63_DSP1_FW_VER, 369 .halo_state = CS35L63_DSP1_HALO_STATE, 370 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 371 .prot_sts = CS35L63_PROTECTION_STATUS, 372 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 373 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 374 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 375 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 376 }; 377 378 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 379 { 380 switch (cs35l56_base->type) { 381 default: 382 switch (cs35l56_base->rev) { 383 case 0xb0: 384 cs35l56_base->fw_reg = &cs35l56_fw_reg; 385 break; 386 default: 387 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 388 break; 389 } 390 break; 391 case 0x63: 392 cs35l56_base->fw_reg = &cs35l63_fw_reg; 393 break; 394 } 395 } 396 397 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 398 { 399 unsigned int val; 400 int ret; 401 402 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 403 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 404 val, (val == 0), 405 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 406 if (ret) { 407 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 408 return ret; 409 } 410 411 return 0; 412 } 413 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 414 415 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 416 { 417 int ret; 418 unsigned int val; 419 420 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 421 if (ret) 422 return ret; 423 424 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 425 cs35l56_base->fw_reg->pm_cur_stat, 426 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 427 CS35L56_HALO_STATE_POLL_US, 428 CS35L56_HALO_STATE_TIMEOUT_US); 429 if (ret < 0) 430 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 431 val, ret); 432 return ret; 433 } 434 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 435 436 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 437 { 438 unsigned int val = 0; 439 int read_ret, poll_ret; 440 441 /* 442 * The regmap must remain in cache-only until the chip has 443 * booted, so use a bypassed read of the status register. 444 */ 445 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 446 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 447 CS35L56_HALO_STATE_POLL_US, 448 CS35L56_HALO_STATE_TIMEOUT_US, 449 false, 450 cs35l56_base->regmap, 451 cs35l56_base->fw_reg->halo_state, 452 &val); 453 454 if (poll_ret) { 455 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 456 read_ret, val); 457 return -EIO; 458 } 459 460 return 0; 461 } 462 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 463 464 void cs35l56_wait_control_port_ready(void) 465 { 466 /* Wait for control port to be ready (datasheet tIRS). */ 467 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 468 } 469 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 470 471 void cs35l56_wait_min_reset_pulse(void) 472 { 473 /* Satisfy minimum reset pulse width spec */ 474 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 475 } 476 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 477 478 static const struct { 479 u32 addr; 480 u32 value; 481 } cs35l56_spi_system_reset_stages[] = { 482 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 483 /* The next write is necessary to delimit the soft reset */ 484 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 485 }; 486 487 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 488 struct spi_device *spi) 489 { 490 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 491 struct spi_transfer t = { 492 .tx_buf = buf, 493 .len = sizeof(*buf), 494 }; 495 struct spi_message m; 496 int i, ret; 497 498 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 499 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 500 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 501 spi_message_init_with_transfers(&m, &t, 1); 502 ret = spi_sync_locked(spi, &m); 503 if (ret) 504 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 505 506 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 507 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 508 } 509 } 510 511 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 512 { 513 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 514 unsigned int val; 515 int read_ret, ret; 516 517 /* 518 * There must not be any other SPI bus activity while the amp is 519 * soft-resetting. 520 */ 521 ret = spi_bus_lock(spi->controller); 522 if (ret) { 523 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 524 return; 525 } 526 527 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 528 spi_bus_unlock(spi->controller); 529 530 /* 531 * Check firmware boot by testing for a response in MBOX_2. 532 * HALO_STATE cannot be trusted yet because the reset sequence 533 * can leave it with stale state. But MBOX is reset. 534 * The regmap must remain in cache-only until the chip has 535 * booted, so use a bypassed read. 536 */ 537 val = 0; 538 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 539 (val > 0) && (val < 0xffffffff), 540 CS35L56_HALO_STATE_POLL_US, 541 CS35L56_HALO_STATE_TIMEOUT_US, 542 false, 543 cs35l56_base->regmap, 544 CS35L56_DSP_VIRTUAL1_MBOX_2, 545 &val); 546 if (ret) { 547 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 548 read_ret, val); 549 } 550 } 551 552 static const struct reg_sequence cs35l56_system_reset_seq[] = { 553 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 554 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 555 }; 556 557 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 558 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 559 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 560 }; 561 562 static const struct reg_sequence cs35l63_system_reset_seq[] = { 563 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 564 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 565 }; 566 567 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 568 { 569 /* 570 * Must enter cache-only first so there can't be any more register 571 * accesses other than the controlled system reset sequence below. 572 */ 573 regcache_cache_only(cs35l56_base->regmap, true); 574 575 if (cs35l56_is_spi(cs35l56_base)) { 576 cs35l56_spi_system_reset(cs35l56_base); 577 return; 578 } 579 580 switch (cs35l56_base->type) { 581 case 0x54: 582 case 0x56: 583 case 0x57: 584 switch (cs35l56_base->rev) { 585 case 0xb0: 586 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 587 cs35l56_system_reset_seq, 588 ARRAY_SIZE(cs35l56_system_reset_seq)); 589 break; 590 default: 591 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 592 cs35l56_b2_system_reset_seq, 593 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 594 break; 595 } 596 break; 597 case 0x63: 598 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 599 cs35l63_system_reset_seq, 600 ARRAY_SIZE(cs35l63_system_reset_seq)); 601 break; 602 default: 603 break; 604 } 605 606 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 607 if (is_soundwire) 608 return; 609 610 cs35l56_wait_control_port_ready(); 611 612 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 613 } 614 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 615 616 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 617 { 618 int ret; 619 620 if (irq < 1) 621 return 0; 622 623 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 624 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 625 "cs35l56", cs35l56_base); 626 if (!ret) 627 cs35l56_base->irq = irq; 628 else 629 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 630 631 return ret; 632 } 633 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 634 635 irqreturn_t cs35l56_irq(int irq, void *data) 636 { 637 struct cs35l56_base *cs35l56_base = data; 638 unsigned int status1 = 0, status8 = 0, status20 = 0; 639 unsigned int mask1, mask8, mask20; 640 unsigned int val; 641 int rv; 642 643 irqreturn_t ret = IRQ_NONE; 644 645 if (!cs35l56_base->init_done) 646 return IRQ_NONE; 647 648 mutex_lock(&cs35l56_base->irq_lock); 649 650 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 651 if (rv < 0) { 652 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 653 goto err_unlock; 654 } 655 656 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 657 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 658 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 659 goto err; 660 } 661 662 /* Ack interrupts */ 663 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 664 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 665 status1 &= ~mask1; 666 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 667 668 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 669 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 670 status8 &= ~mask8; 671 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 672 673 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 674 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 675 status20 &= ~mask20; 676 /* We don't want EINT20 but they default to unmasked: force mask */ 677 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 678 679 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 680 681 /* Check to see if unmasked bits are active */ 682 if (!status1 && !status8 && !status20) 683 goto err; 684 685 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 686 dev_crit(cs35l56_base->dev, "Amp short error\n"); 687 688 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 689 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 690 691 ret = IRQ_HANDLED; 692 693 err: 694 pm_runtime_put(cs35l56_base->dev); 695 err_unlock: 696 mutex_unlock(&cs35l56_base->irq_lock); 697 698 return ret; 699 } 700 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 701 702 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 703 { 704 unsigned int val; 705 int ret; 706 707 /* 708 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 709 * can't be used here to test for memory retention. 710 * Assume that tuning must be re-loaded. 711 */ 712 if (cs35l56_base->secured) 713 return true; 714 715 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 716 if (ret) { 717 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 718 return ret; 719 } 720 721 ret = regmap_read(cs35l56_base->regmap, 722 cs35l56_base->fw_reg->prot_sts, 723 &val); 724 if (ret) 725 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 726 else 727 ret = !!(val & CS35L56_FIRMWARE_MISSING); 728 729 pm_runtime_put_autosuspend(cs35l56_base->dev); 730 731 return ret; 732 } 733 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 734 735 static const struct reg_sequence cs35l56_hibernate_seq[] = { 736 /* This must be the last register access */ 737 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 738 }; 739 740 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 741 { 742 unsigned int val; 743 744 /* 745 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 746 * transactions to meet the minimum required time from the rising edge 747 * to the last falling edge of wake. 748 * 749 * It uses bypassed read because we must wake the chip before 750 * disabling regmap cache-only. 751 */ 752 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 753 754 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 755 756 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 757 758 cs35l56_wait_control_port_ready(); 759 } 760 761 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 762 { 763 unsigned int val; 764 int ret; 765 766 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 767 cs35l56_base->fw_reg->transducer_actual_ps, 768 val, (val >= CS35L56_PS3), 769 CS35L56_PS3_POLL_US, 770 CS35L56_PS3_TIMEOUT_US); 771 if (ret) 772 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 773 774 return ret; 775 } 776 777 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 778 { 779 if (!cs35l56_base->init_done) 780 return 0; 781 782 /* Firmware must have entered a power-save state */ 783 cs35l56_wait_for_ps3(cs35l56_base); 784 785 /* Clear BOOT_DONE so it can be used to detect a reboot */ 786 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 787 788 if (!cs35l56_base->can_hibernate) { 789 regcache_cache_only(cs35l56_base->regmap, true); 790 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 791 792 return 0; 793 } 794 795 /* 796 * Must enter cache-only first so there can't be any more register 797 * accesses other than the controlled hibernate sequence below. 798 */ 799 regcache_cache_only(cs35l56_base->regmap, true); 800 801 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 802 cs35l56_hibernate_seq, 803 ARRAY_SIZE(cs35l56_hibernate_seq)); 804 805 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 806 807 return 0; 808 } 809 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 810 811 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 812 { 813 unsigned int val; 814 int ret; 815 816 if (!cs35l56_base->init_done) 817 return 0; 818 819 if (!cs35l56_base->can_hibernate) 820 goto out_sync; 821 822 /* Must be done before releasing cache-only */ 823 if (!is_soundwire) 824 cs35l56_issue_wake_event(cs35l56_base); 825 826 out_sync: 827 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 828 if (ret) { 829 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 830 goto err; 831 } 832 833 regcache_cache_only(cs35l56_base->regmap, false); 834 835 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 836 if (ret) 837 goto err; 838 839 /* BOOT_DONE will be 1 if the amp reset */ 840 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 841 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 842 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 843 regcache_mark_dirty(cs35l56_base->regmap); 844 } 845 846 regcache_sync(cs35l56_base->regmap); 847 848 dev_dbg(cs35l56_base->dev, "Resumed"); 849 850 return 0; 851 852 err: 853 regcache_cache_only(cs35l56_base->regmap, true); 854 855 if (cs35l56_base->can_hibernate) { 856 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 857 cs35l56_hibernate_seq, 858 ARRAY_SIZE(cs35l56_hibernate_seq)); 859 } 860 861 return ret; 862 } 863 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 864 865 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 866 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 867 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 868 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 869 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 870 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 871 }; 872 873 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 874 { 875 cs_dsp->num = 1; 876 cs_dsp->type = WMFW_HALO; 877 cs_dsp->rev = 0; 878 cs_dsp->dev = cs35l56_base->dev; 879 cs_dsp->regmap = cs35l56_base->regmap; 880 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 881 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 882 cs_dsp->mem = cs35l56_dsp1_regions; 883 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 884 cs_dsp->no_core_startstop = true; 885 886 cs35l56_base->dsp = cs_dsp; 887 } 888 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 889 890 struct cs35l56_pte { 891 u8 x; 892 u8 wafer_id; 893 u8 pte[2]; 894 u8 lot[3]; 895 u8 y; 896 u8 unused[3]; 897 u8 dvs; 898 } __packed; 899 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 900 901 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 902 { 903 struct cs35l56_pte pte; 904 u64 unique_id; 905 int ret; 906 907 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 908 if (ret) { 909 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 910 return ret; 911 } 912 913 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 914 unique_id <<= 32; 915 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 916 ((u32)pte.dvs << 24); 917 918 cs35l56_base->silicon_uid = unique_id; 919 920 return 0; 921 } 922 923 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 924 { 925 u32 tmp[2]; 926 u64 unique_id; 927 int ret; 928 929 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 930 if (ret) { 931 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 932 return ret; 933 } 934 935 unique_id = tmp[1]; 936 unique_id <<= 32; 937 unique_id |= tmp[0]; 938 939 cs35l56_base->silicon_uid = unique_id; 940 941 return 0; 942 } 943 944 /* Firmware calibration controls */ 945 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 946 .alg_id = 0x9f210, 947 .mem_region = WMFW_ADSP2_YM, 948 .ambient = "CAL_AMBIENT", 949 .calr = "CAL_R", 950 .status = "CAL_STATUS", 951 .checksum = "CAL_CHECKSUM", 952 }; 953 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 954 955 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 956 .alg_id = 0xbf210, 957 .mem_region = WMFW_ADSP2_YM, 958 .ambient = "CAL_AMBIENT", 959 .calr = "CAL_R", 960 .status = "CAL_STATUS", 961 .checksum = "CAL_CHECKSUM", 962 }; 963 964 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 965 { 966 int ret; 967 968 /* Driver can't apply calibration to a secured part, so skip */ 969 if (cs35l56_base->secured) 970 return 0; 971 972 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 973 cs35l56_base->silicon_uid, 974 cs35l56_base->cal_index, 975 &cs35l56_base->cal_data); 976 977 /* Only return an error status if probe should be aborted */ 978 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 979 return 0; 980 981 if (ret < 0) 982 return ret; 983 984 cs35l56_base->cal_data_valid = true; 985 986 return 0; 987 } 988 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 989 990 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 991 const struct cirrus_amp_cal_data *data) 992 { 993 994 /* Ignore if it is empty */ 995 if (!data->calTime[0] && !data->calTime[1]) 996 return -ENODATA; 997 998 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 999 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 1000 return -EINVAL; 1001 } 1002 1003 cs35l56_base->cal_data = *data; 1004 cs35l56_base->cal_data_valid = true; 1005 1006 return 0; 1007 } 1008 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 1009 1010 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 1011 { 1012 const struct cirrus_amp_cal_controls *calibration_controls = 1013 cs35l56_base->calibration_controls; 1014 struct cs_dsp *dsp = cs35l56_base->dsp; 1015 struct cirrus_amp_cal_data cal_data; 1016 struct cs_dsp_coeff_ctl *ctl; 1017 bool ngate_ch1_was_enabled = false; 1018 bool ngate_ch2_was_enabled = false; 1019 int cali_norm_en_alg_id, cali_norm_en_mem; 1020 int ret; 1021 __be32 val; 1022 1023 if (cs35l56_base->silicon_uid == 0) { 1024 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1025 return -ENXIO; 1026 } 1027 1028 switch (cs35l56_base->type) { 1029 case 0x54: 1030 case 0x56: 1031 case 0x57: 1032 if (cs35l56_base->rev < 0xb2) { 1033 cali_norm_en_alg_id = 0x9f22f; 1034 cali_norm_en_mem = WMFW_ADSP2_YM; 1035 } else { 1036 cali_norm_en_alg_id = 0x9f210; 1037 cali_norm_en_mem = WMFW_ADSP2_XM; 1038 } 1039 break; 1040 default: 1041 cali_norm_en_alg_id = 0xbf210; 1042 cali_norm_en_mem = WMFW_ADSP2_XM; 1043 break; 1044 } 1045 1046 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1047 if (ret) 1048 return ret; 1049 1050 ret = cs35l56_wait_for_ps3(cs35l56_base); 1051 if (ret) { 1052 ret = -EBUSY; 1053 goto err_pm_put; 1054 } 1055 1056 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1057 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1058 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1059 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1060 1061 scoped_guard(mutex, &dsp->pwr_lock) { 1062 ctl = cs_dsp_get_ctl(dsp, 1063 calibration_controls->status, 1064 calibration_controls->mem_region, 1065 calibration_controls->alg_id); 1066 if (!ctl) { 1067 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1068 calibration_controls->status); 1069 ret = -EIO; 1070 goto err; 1071 } 1072 1073 val = cpu_to_be32(0); 1074 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1075 "CALI_NORM_EN", 1076 cali_norm_en_mem, 1077 cali_norm_en_alg_id), 1078 0, &val, sizeof(val)); 1079 if (ret < 0) { 1080 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1081 ret = -EIO; 1082 goto err; 1083 } 1084 1085 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1086 if (ret) { 1087 ret = -EIO; 1088 goto err; 1089 } 1090 1091 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1092 (val == cpu_to_be32(1)), 1093 CS35L56_CALIBRATION_POLL_US, 1094 CS35L56_CALIBRATION_TIMEOUT_US, 1095 true, 1096 ctl, 0, &val, sizeof(val))) { 1097 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1098 be32_to_cpu(val)); 1099 switch (be32_to_cpu(val)) { 1100 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1101 ret = -ERANGE; 1102 goto err; 1103 default: 1104 ret = -ETIMEDOUT; 1105 goto err; 1106 } 1107 } 1108 } 1109 1110 cs35l56_base->cal_data_valid = false; 1111 memset(&cal_data, 0, sizeof(cal_data)); 1112 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1113 if (ret) { 1114 ret = -EIO; 1115 goto err; 1116 } 1117 1118 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1119 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1120 1121 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1122 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1123 cs35l56_base->cal_data = cal_data; 1124 cs35l56_base->cal_data_valid = true; 1125 1126 ret = 0; 1127 1128 err: 1129 if (ngate_ch1_was_enabled) { 1130 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1131 CS35L56_AUX_NGATE_CHn_EN); 1132 } 1133 if (ngate_ch2_was_enabled) { 1134 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1135 CS35L56_AUX_NGATE_CHn_EN); 1136 } 1137 err_pm_put: 1138 pm_runtime_put(cs35l56_base->dev); 1139 1140 return ret; 1141 } 1142 1143 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1144 const char __user *from, size_t count, 1145 loff_t *ppos) 1146 { 1147 static const char * const options[] = { "factory", "store_uefi" }; 1148 char buf[11] = { 0 }; 1149 int num_amps, ret; 1150 1151 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1152 return -ENXIO; 1153 1154 if (*ppos) 1155 return -EINVAL; 1156 1157 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1158 if (ret < 0) 1159 return ret; 1160 1161 switch (sysfs_match_string(options, buf)) { 1162 case 0: 1163 ret = cs35l56_perform_calibration(cs35l56_base); 1164 if (ret < 0) 1165 return ret; 1166 break; 1167 case 1: 1168 if (!cs35l56_base->cal_data_valid) 1169 return -ENODATA; 1170 1171 num_amps = cs35l56_base->num_amps; 1172 if (num_amps == 0) 1173 num_amps = -1; 1174 1175 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1176 cs35l56_base->cal_index, 1177 num_amps, 1178 &cs35l56_base->cal_data); 1179 if (ret < 0) 1180 return ret; 1181 break; 1182 default: 1183 return -EOPNOTSUPP; 1184 } 1185 1186 return count; 1187 } 1188 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1189 1190 int cs35l56_factory_calibrate(struct cs35l56_base *cs35l56_base) 1191 { 1192 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL)) 1193 return -ENXIO; 1194 1195 return cs35l56_perform_calibration(cs35l56_base); 1196 } 1197 EXPORT_SYMBOL_NS_GPL(cs35l56_factory_calibrate, "SND_SOC_CS35L56_SHARED"); 1198 1199 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1200 const char __user *from, size_t count, 1201 loff_t *ppos) 1202 { 1203 unsigned long val; 1204 int ret; 1205 1206 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1207 return -ENXIO; 1208 1209 if (*ppos) 1210 return -EINVAL; 1211 1212 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1213 if (ret) 1214 return ret; 1215 1216 ret = kstrtoul_from_user(from, count, 10, &val); 1217 if (ret < 0) 1218 goto out; 1219 1220 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1221 if (ret) 1222 ret = -EIO; 1223 out: 1224 pm_runtime_put(cs35l56_base->dev); 1225 1226 if (ret < 0) 1227 return ret; 1228 1229 return count; 1230 } 1231 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1232 1233 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1234 char __user *to, size_t count, 1235 loff_t *ppos) 1236 { 1237 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1238 return -ENXIO; 1239 1240 if (!cs35l56_base->cal_data_valid) 1241 return 0; 1242 1243 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1244 sizeof(cs35l56_base->cal_data)); 1245 } 1246 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1247 1248 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1249 const char __user *from, size_t count, 1250 loff_t *ppos) 1251 { 1252 struct cirrus_amp_cal_data cal_data; 1253 int ret; 1254 1255 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1256 return -ENXIO; 1257 1258 /* Only allow a full blob to be written */ 1259 if (*ppos || (count != sizeof(cal_data))) 1260 return -EMSGSIZE; 1261 1262 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1263 if (ret < 0) 1264 return ret; 1265 1266 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1267 if (ret) 1268 return ret; 1269 1270 return count; 1271 } 1272 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1273 1274 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1275 const struct cs35l56_cal_debugfs_fops *fops) 1276 { 1277 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1278 return; 1279 1280 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1281 1282 debugfs_create_file("calibrate", 1283 0200, cs35l56_base->debugfs, cs35l56_base, 1284 &fops->calibrate); 1285 debugfs_create_file("cal_temperature", 1286 0200, cs35l56_base->debugfs, cs35l56_base, 1287 &fops->cal_temperature); 1288 debugfs_create_file("cal_data", 1289 0644, cs35l56_base->debugfs, cs35l56_base, 1290 &fops->cal_data); 1291 } 1292 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1293 1294 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1295 { 1296 debugfs_remove_recursive(cs35l56_base->debugfs); 1297 cs35l56_base->debugfs = ERR_PTR(-ENOENT); 1298 } 1299 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1300 1301 const char * const cs35l56_cal_set_status_text[] = { 1302 "Unknown", "Default", "Set", 1303 }; 1304 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1305 1306 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1307 struct snd_ctl_elem_value *uvalue) 1308 { 1309 struct cs_dsp *dsp = cs35l56_base->dsp; 1310 __be32 cal_set_status_be; 1311 int alg_id; 1312 int ret; 1313 1314 switch (cs35l56_base->type) { 1315 case 0x54: 1316 case 0x56: 1317 case 0x57: 1318 alg_id = 0x9f210; 1319 break; 1320 default: 1321 alg_id = 0xbf210; 1322 break; 1323 } 1324 1325 scoped_guard(mutex, &dsp->pwr_lock) { 1326 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1327 "CAL_SET_STATUS", 1328 WMFW_ADSP2_YM, alg_id), 1329 0, &cal_set_status_be, 1330 sizeof(cal_set_status_be)); 1331 } 1332 if (ret) { 1333 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1334 return 0; 1335 } 1336 1337 switch (be32_to_cpu(cal_set_status_be)) { 1338 case CS35L56_CAL_SET_STATUS_DEFAULT: 1339 case CS35L56_CAL_SET_STATUS_SET: 1340 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1341 return 0; 1342 default: 1343 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1344 return 0; 1345 } 1346 } 1347 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1348 1349 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1350 bool *fw_missing, unsigned int *fw_version) 1351 { 1352 unsigned int prot_status; 1353 int ret; 1354 1355 ret = regmap_read(cs35l56_base->regmap, 1356 cs35l56_base->fw_reg->prot_sts, &prot_status); 1357 if (ret) { 1358 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1359 return ret; 1360 } 1361 1362 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1363 1364 ret = regmap_read(cs35l56_base->regmap, 1365 cs35l56_base->fw_reg->fw_ver, fw_version); 1366 if (ret) { 1367 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1368 return ret; 1369 } 1370 1371 return 0; 1372 } 1373 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1374 1375 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1376 { 1377 unsigned int firmware_version; 1378 bool firmware_missing; 1379 int ret; 1380 1381 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1382 if (ret) 1383 return; 1384 1385 if (!firmware_missing) 1386 return; 1387 1388 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1389 } 1390 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1391 1392 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1393 { 1394 __be32 pid, sid, tid; 1395 unsigned int alg_id; 1396 int ret; 1397 1398 switch (cs35l56_base->type) { 1399 case 0x54: 1400 case 0x56: 1401 case 0x57: 1402 alg_id = 0x9f212; 1403 break; 1404 default: 1405 alg_id = 0xbf212; 1406 break; 1407 } 1408 1409 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1410 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1411 WMFW_ADSP2_XM, alg_id), 1412 0, &pid, sizeof(pid)); 1413 if (!ret) 1414 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1415 WMFW_ADSP2_XM, alg_id), 1416 0, &sid, sizeof(sid)); 1417 if (!ret) 1418 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1419 WMFW_ADSP2_XM, alg_id), 1420 0, &tid, sizeof(tid)); 1421 } 1422 1423 if (ret) 1424 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1425 else 1426 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1427 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1428 } 1429 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1430 1431 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1432 { 1433 int ret; 1434 unsigned int devid, revid, otpid, secured, fw_ver; 1435 bool fw_missing; 1436 1437 /* 1438 * When the system is not using a reset_gpio ensure the device is 1439 * awake, otherwise the device has just been released from reset and 1440 * the driver must wait for the control port to become usable. 1441 */ 1442 if (!cs35l56_base->reset_gpio) 1443 cs35l56_issue_wake_event(cs35l56_base); 1444 else 1445 cs35l56_wait_control_port_ready(); 1446 1447 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1448 if (ret < 0) { 1449 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1450 return ret; 1451 } 1452 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1453 cs35l56_set_fw_reg_table(cs35l56_base); 1454 1455 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1456 if (ret) 1457 return ret; 1458 1459 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1460 if (ret < 0) { 1461 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1462 return ret; 1463 } 1464 devid &= CS35L56_DEVID_MASK; 1465 1466 switch (devid) { 1467 case 0x35A54: 1468 case 0x35A56: 1469 case 0x35A57: 1470 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1471 break; 1472 case 0x35A630: 1473 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1474 devid = devid >> 4; 1475 break; 1476 default: 1477 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1478 return -ENODEV; 1479 } 1480 1481 cs35l56_base->type = devid & 0xFF; 1482 1483 /* Silicon is now identified and booted so exit cache-only */ 1484 regcache_cache_only(cs35l56_base->regmap, false); 1485 1486 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1487 if (ret) { 1488 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1489 return ret; 1490 } 1491 1492 /* When any bus is restricted treat the device as secured */ 1493 if (secured & CS35L56_RESTRICTED_MASK) 1494 cs35l56_base->secured = true; 1495 1496 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1497 if (ret < 0) { 1498 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1499 return ret; 1500 } 1501 1502 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1503 if (ret) 1504 return ret; 1505 1506 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1507 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1508 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1509 1510 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1511 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1512 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1513 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1514 0); 1515 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1516 CS35L56_TEMP_ERR_EINT1_MASK, 1517 0); 1518 1519 switch (cs35l56_base->type) { 1520 case 0x54: 1521 case 0x56: 1522 case 0x57: 1523 ret = cs35l56_read_silicon_uid(cs35l56_base); 1524 break; 1525 default: 1526 ret = cs35l63_read_silicon_uid(cs35l56_base); 1527 break; 1528 } 1529 if (ret) 1530 return ret; 1531 1532 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1533 1534 return 0; 1535 } 1536 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1537 1538 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1539 { 1540 struct gpio_descs *descs; 1541 u32 speaker_id; 1542 int i, ret; 1543 1544 /* Check for vendor-specific speaker ID method */ 1545 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1546 if (ret >= 0) { 1547 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1548 return ret; 1549 } else if (ret != -ENOENT) { 1550 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1551 return ret; 1552 } 1553 1554 /* Attempt to read the speaker type from a device property */ 1555 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1556 if (!ret) { 1557 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1558 return speaker_id; 1559 } 1560 1561 /* Read the speaker type qualifier from the motherboard GPIOs */ 1562 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1563 if (!descs) { 1564 return -ENOENT; 1565 } else if (IS_ERR(descs)) { 1566 ret = PTR_ERR(descs); 1567 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1568 } 1569 1570 speaker_id = 0; 1571 for (i = 0; i < descs->ndescs; i++) { 1572 ret = gpiod_get_value_cansleep(descs->desc[i]); 1573 if (ret < 0) { 1574 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1575 goto err; 1576 } 1577 1578 speaker_id |= (ret << i); 1579 } 1580 1581 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1582 ret = speaker_id; 1583 err: 1584 gpiod_put_array(descs); 1585 1586 return ret; 1587 } 1588 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1589 1590 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 1591 const u32 *gpios, int num_gpios, 1592 const u32 *pulls, int num_pulls) 1593 { 1594 int max_gpio; 1595 int ret = 0; 1596 int i; 1597 1598 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) || 1599 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls))) 1600 return -EOVERFLOW; 1601 1602 switch (cs35l56_base->type) { 1603 case 0x54: 1604 case 0x56: 1605 case 0x57: 1606 max_gpio = CS35L56_MAX_GPIO; 1607 break; 1608 default: 1609 max_gpio = CS35L63_MAX_GPIO; 1610 break; 1611 } 1612 1613 for (i = 0; i < num_gpios; i++) { 1614 if (gpios[i] < 1 || gpios[i] > max_gpio) { 1615 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]); 1616 /* Keep going so we log all bad values */ 1617 ret = -EINVAL; 1618 } 1619 1620 /* Change to zero-based */ 1621 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1; 1622 } 1623 1624 for (i = 0; i < num_pulls; i++) { 1625 switch (pulls[i]) { 1626 case 0: 1627 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE; 1628 break; 1629 case 1: 1630 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP; 1631 break; 1632 case 2: 1633 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN; 1634 break; 1635 default: 1636 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]); 1637 /* Keep going so we log all bad values */ 1638 ret = -EINVAL; 1639 break; 1640 } 1641 } 1642 if (ret) 1643 return ret; 1644 1645 cs35l56_base->num_onchip_spkid_gpios = num_gpios; 1646 cs35l56_base->num_onchip_spkid_pulls = num_pulls; 1647 1648 return 0; 1649 } 1650 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED"); 1651 1652 /* Caller must pm_runtime resume before calling this function */ 1653 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base) 1654 { 1655 struct regmap *regmap = cs35l56_base->regmap; 1656 unsigned int addr_offset, val; 1657 int num_gpios, num_pulls; 1658 int i, ret; 1659 1660 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base); 1661 1662 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1663 return 0; 1664 1665 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1666 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1667 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls, 1668 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)); 1669 1670 for (i = 0; i < num_gpios; i++) { 1671 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1672 1673 /* Set unspecified pulls to NONE */ 1674 if (i < num_pulls) { 1675 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, 1676 cs35l56_base->onchip_spkid_pulls[i]); 1677 } else { 1678 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE); 1679 } 1680 1681 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset, 1682 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE, 1683 val | CS35L56_PAD_GPIO_IE); 1684 if (ret) { 1685 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n", 1686 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1687 return ret; 1688 } 1689 } 1690 1691 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES); 1692 if (ret) { 1693 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret); 1694 return ret; 1695 } 1696 1697 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2); 1698 1699 return 0; 1700 } 1701 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED"); 1702 1703 /* Caller must pm_runtime resume before calling this function */ 1704 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base) 1705 { 1706 struct regmap *regmap = cs35l56_base->regmap; 1707 unsigned int addr_offset, val; 1708 int num_gpios; 1709 int speaker_id = 0; 1710 int i, ret; 1711 1712 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base); 1713 1714 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1715 return -ENOENT; 1716 1717 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1718 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1719 1720 for (i = 0; i < num_gpios; i++) { 1721 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1722 1723 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset, 1724 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK, 1725 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO); 1726 if (ret) { 1727 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n", 1728 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1729 return ret; 1730 } 1731 } 1732 1733 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val); 1734 if (ret) { 1735 dev_err(cs35l56_base->dev, "GPIO status read failed: %d\n", ret); 1736 return ret; 1737 } 1738 1739 for (i = 0; i < num_gpios; i++) { 1740 speaker_id <<= 1; 1741 1742 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i])) 1743 speaker_id |= 1; 1744 } 1745 1746 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id); 1747 1748 return speaker_id; 1749 } 1750 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED"); 1751 1752 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1753 [0x0C] = 128000, 1754 [0x0F] = 256000, 1755 [0x11] = 384000, 1756 [0x12] = 512000, 1757 [0x15] = 768000, 1758 [0x17] = 1024000, 1759 [0x1A] = 1500000, 1760 [0x1B] = 1536000, 1761 [0x1C] = 2000000, 1762 [0x1D] = 2048000, 1763 [0x1E] = 2400000, 1764 [0x20] = 3000000, 1765 [0x21] = 3072000, 1766 [0x23] = 4000000, 1767 [0x24] = 4096000, 1768 [0x25] = 4800000, 1769 [0x27] = 6000000, 1770 [0x28] = 6144000, 1771 [0x29] = 6250000, 1772 [0x2A] = 6400000, 1773 [0x2E] = 8000000, 1774 [0x2F] = 8192000, 1775 [0x30] = 9600000, 1776 [0x32] = 12000000, 1777 [0x33] = 12288000, 1778 [0x37] = 13500000, 1779 [0x38] = 19200000, 1780 [0x39] = 22579200, 1781 [0x3B] = 24576000, 1782 }; 1783 1784 int cs35l56_get_bclk_freq_id(unsigned int freq) 1785 { 1786 int i; 1787 1788 if (freq == 0) 1789 return -EINVAL; 1790 1791 /* The BCLK frequency must be a valid PLL REFCLK */ 1792 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1793 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1794 return i; 1795 } 1796 1797 return -EINVAL; 1798 } 1799 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1800 1801 static const char * const cs35l56_supplies[/* auto-sized */] = { 1802 "VDD_P", 1803 "VDD_IO", 1804 "VDD_A", 1805 }; 1806 1807 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1808 { 1809 int i; 1810 1811 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1812 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1813 data[i].supply = cs35l56_supplies[i]; 1814 } 1815 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1816 1817 const char * const cs35l56_tx_input_texts[] = { 1818 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1819 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1820 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1821 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1822 }; 1823 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1824 1825 const unsigned int cs35l56_tx_input_values[] = { 1826 CS35L56_INPUT_SRC_NONE, 1827 CS35L56_INPUT_SRC_ASP1RX1, 1828 CS35L56_INPUT_SRC_ASP1RX2, 1829 CS35L56_INPUT_SRC_VMON, 1830 CS35L56_INPUT_SRC_IMON, 1831 CS35L56_INPUT_SRC_ERR_VOL, 1832 CS35L56_INPUT_SRC_CLASSH, 1833 CS35L56_INPUT_SRC_VDDBMON, 1834 CS35L56_INPUT_SRC_VBSTMON, 1835 CS35L56_INPUT_SRC_DSP1TX1, 1836 CS35L56_INPUT_SRC_DSP1TX2, 1837 CS35L56_INPUT_SRC_DSP1TX3, 1838 CS35L56_INPUT_SRC_DSP1TX4, 1839 CS35L56_INPUT_SRC_DSP1TX5, 1840 CS35L56_INPUT_SRC_DSP1TX6, 1841 CS35L56_INPUT_SRC_DSP1TX7, 1842 CS35L56_INPUT_SRC_DSP1TX8, 1843 CS35L56_INPUT_SRC_TEMPMON, 1844 CS35L56_INPUT_SRC_INTERPOLATOR, 1845 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1846 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1847 }; 1848 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1849 1850 const struct regmap_config cs35l56_regmap_i2c = { 1851 .reg_bits = 32, 1852 .val_bits = 32, 1853 .reg_stride = 4, 1854 .reg_format_endian = REGMAP_ENDIAN_BIG, 1855 .val_format_endian = REGMAP_ENDIAN_BIG, 1856 .max_register = CS35L56_DSP1_PMEM_5114, 1857 .reg_defaults = cs35l56_reg_defaults, 1858 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1859 .volatile_reg = cs35l56_volatile_reg, 1860 .readable_reg = cs35l56_readable_reg, 1861 .precious_reg = cs35l56_precious_reg, 1862 .cache_type = REGCACHE_MAPLE, 1863 }; 1864 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1865 1866 const struct regmap_config cs35l56_regmap_spi = { 1867 .reg_bits = 32, 1868 .val_bits = 32, 1869 .pad_bits = 16, 1870 .reg_stride = 4, 1871 .reg_format_endian = REGMAP_ENDIAN_BIG, 1872 .val_format_endian = REGMAP_ENDIAN_BIG, 1873 .max_register = CS35L56_DSP1_PMEM_5114, 1874 .reg_defaults = cs35l56_reg_defaults, 1875 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1876 .volatile_reg = cs35l56_volatile_reg, 1877 .readable_reg = cs35l56_readable_reg, 1878 .precious_reg = cs35l56_precious_reg, 1879 .cache_type = REGCACHE_MAPLE, 1880 }; 1881 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1882 1883 const struct regmap_config cs35l56_regmap_sdw = { 1884 .reg_bits = 32, 1885 .reg_base = 0x8000, 1886 .val_bits = 32, 1887 .reg_stride = 4, 1888 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1889 .val_format_endian = REGMAP_ENDIAN_BIG, 1890 .max_register = CS35L56_DSP1_PMEM_5114, 1891 .reg_defaults = cs35l56_reg_defaults, 1892 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1893 .volatile_reg = cs35l56_volatile_reg, 1894 .readable_reg = cs35l56_readable_reg, 1895 .precious_reg = cs35l56_precious_reg, 1896 .cache_type = REGCACHE_MAPLE, 1897 }; 1898 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1899 1900 const struct regmap_config cs35l63_regmap_i2c = { 1901 .reg_bits = 32, 1902 .val_bits = 32, 1903 .reg_stride = 4, 1904 .reg_base = 0x8000, 1905 .reg_format_endian = REGMAP_ENDIAN_BIG, 1906 .val_format_endian = REGMAP_ENDIAN_BIG, 1907 .max_register = CS35L56_DSP1_PMEM_5114, 1908 .reg_defaults = cs35l63_reg_defaults, 1909 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1910 .volatile_reg = cs35l63_volatile_reg, 1911 .readable_reg = cs35l56_readable_reg, 1912 .precious_reg = cs35l56_precious_reg, 1913 .cache_type = REGCACHE_MAPLE, 1914 }; 1915 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1916 1917 const struct regmap_config cs35l63_regmap_sdw = { 1918 .reg_bits = 32, 1919 .val_bits = 32, 1920 .reg_stride = 4, 1921 .reg_base = 0x8000, 1922 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1923 .val_format_endian = REGMAP_ENDIAN_BIG, 1924 .max_register = CS35L56_DSP1_PMEM_5114, 1925 .reg_defaults = cs35l63_reg_defaults, 1926 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1927 .volatile_reg = cs35l63_volatile_reg, 1928 .readable_reg = cs35l56_readable_reg, 1929 .precious_reg = cs35l56_precious_reg, 1930 .cache_type = REGCACHE_MAPLE, 1931 }; 1932 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1933 1934 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1935 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1936 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1937 MODULE_LICENSE("GPL"); 1938 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1939 MODULE_IMPORT_NS("FW_CS_DSP"); 1940