1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 /* Linux PRO/1000 Ethernet Driver main header file */
5
6 #ifndef _IGB_H_
7 #define _IGB_H_
8
9 #include "e1000_mac.h"
10 #include "e1000_82575.h"
11
12 #include <linux/timecounter.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/ptp_clock_kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/if_vlan.h>
17 #include <linux/i2c.h>
18 #include <linux/i2c-algo-bit.h>
19 #include <linux/pci.h>
20 #include <linux/mdio.h>
21 #include <linux/lockdep.h>
22
23 #include <net/xdp.h>
24 #include <net/xdp_sock_drv.h>
25
26 struct igb_adapter;
27
28 #define E1000_PCS_CFG_IGN_SD 1
29
30 /* Interrupt defines */
31 #define IGB_START_ITR 648 /* ~6000 ints/sec */
32 #define IGB_4K_ITR 980
33 #define IGB_20K_ITR 196
34 #define IGB_70K_ITR 56
35
36 /* TX/RX descriptor defines */
37 #define IGB_DEFAULT_TXD 256
38 #define IGB_DEFAULT_TX_WORK 128
39 #define IGB_MIN_TXD 64
40 #define IGB_MAX_TXD 4096
41
42 #define IGB_DEFAULT_RXD 256
43 #define IGB_MIN_RXD 64
44 #define IGB_MAX_RXD 4096
45
46 #define IGB_DEFAULT_ITR 3 /* dynamic */
47 #define IGB_MAX_ITR_USECS 10000
48 #define IGB_MIN_ITR_USECS 10
49 #define NON_Q_VECTORS 1
50 #define MAX_Q_VECTORS 8
51 #define MAX_MSIX_ENTRIES 10
52
53 /* Transmit and receive queues */
54 #define IGB_MAX_RX_QUEUES 8
55 #define IGB_MAX_RX_QUEUES_82575 4
56 #define IGB_MAX_RX_QUEUES_I211 2
57 #define IGB_MAX_TX_QUEUES 8
58 #define IGB_MAX_VF_MC_ENTRIES 30
59 #define IGB_MAX_VF_FUNCTIONS 8
60 #define IGB_MAX_VFTA_ENTRIES 128
61 #define IGB_82576_VF_DEV_ID 0x10CA
62 #define IGB_I350_VF_DEV_ID 0x1520
63
64 /* NVM version defines */
65 #define IGB_MAJOR_MASK 0xF000
66 #define IGB_MINOR_MASK 0x0FF0
67 #define IGB_BUILD_MASK 0x000F
68 #define IGB_COMB_VER_MASK 0x00FF
69 #define IGB_MAJOR_SHIFT 12
70 #define IGB_MINOR_SHIFT 4
71 #define IGB_COMB_VER_SHFT 8
72 #define IGB_NVM_VER_INVALID 0xFFFF
73 #define IGB_ETRACK_SHIFT 16
74 #define NVM_ETRACK_WORD 0x0042
75 #define NVM_COMB_VER_OFF 0x0083
76 #define NVM_COMB_VER_PTR 0x003d
77
78 /* Transmit and receive latency (for PTP timestamps) */
79 #define IGB_I210_TX_LATENCY_10 9542
80 #define IGB_I210_TX_LATENCY_100 1024
81 #define IGB_I210_TX_LATENCY_1000 178
82 #define IGB_I210_RX_LATENCY_10 20662
83 #define IGB_I210_RX_LATENCY_100 2213
84 #define IGB_I210_RX_LATENCY_1000 448
85
86 /* XDP */
87 #define IGB_XDP_PASS 0
88 #define IGB_XDP_CONSUMED BIT(0)
89 #define IGB_XDP_TX BIT(1)
90 #define IGB_XDP_REDIR BIT(2)
91 #define IGB_XDP_EXIT BIT(3)
92
93 struct vf_data_storage {
94 unsigned char vf_mac_addresses[ETH_ALEN];
95 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
96 u16 num_vf_mc_hashes;
97 u32 flags;
98 unsigned long last_nack;
99 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
100 u16 pf_qos;
101 u16 tx_rate;
102 bool spoofchk_enabled;
103 bool trusted;
104 };
105
106 /* Number of unicast MAC filters reserved for the PF in the RAR registers */
107 #define IGB_PF_MAC_FILTERS_RESERVED 3
108
109 struct vf_mac_filter {
110 struct list_head l;
111 int vf;
112 bool free;
113 u8 vf_mac[ETH_ALEN];
114 };
115
116 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
117 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
118 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
119 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
120
121 /* RX descriptor control thresholds.
122 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
123 * descriptors available in its onboard memory.
124 * Setting this to 0 disables RX descriptor prefetch.
125 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
126 * available in host memory.
127 * If PTHRESH is 0, this should also be 0.
128 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
129 * descriptors until either it has this many to write back, or the
130 * ITR timer expires.
131 */
132 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
133 #define IGB_RX_HTHRESH 8
134 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
135 #define IGB_TX_HTHRESH 1
136 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
137 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
138 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
139 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
140
141 /* this is the size past which hardware will drop packets when setting LPE=0 */
142 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
143
144 #define IGB_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
145
146 /* Supported Rx Buffer Sizes */
147 #define IGB_RXBUFFER_256 256
148 #define IGB_RXBUFFER_1536 1536
149 #define IGB_RXBUFFER_2048 2048
150 #define IGB_RXBUFFER_3072 3072
151 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256
152 #define IGB_TS_HDR_LEN 16
153
154 /* Attempt to maximize the headroom available for incoming frames. We
155 * use a 2K buffer for receives and need 1536/1534 to store the data for
156 * the frame. This leaves us with 512 bytes of room. From that we need
157 * to deduct the space needed for the shared info and the padding needed
158 * to IP align the frame.
159 *
160 * Note: For cache line sizes 256 or larger this value is going to end
161 * up negative. In these cases we should fall back to the 3K
162 * buffers.
163 */
164 #if (PAGE_SIZE < 8192)
165 #define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_1536 - NET_IP_ALIGN)
166 #define IGB_2K_TOO_SMALL_WITH_PADDING \
167 ((NET_SKB_PAD + IGB_TS_HDR_LEN + IGB_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048))
168
igb_compute_pad(int rx_buf_len)169 static inline int igb_compute_pad(int rx_buf_len)
170 {
171 int page_size, pad_size;
172
173 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
174 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
175
176 return pad_size;
177 }
178
igb_skb_pad(void)179 static inline int igb_skb_pad(void)
180 {
181 int rx_buf_len;
182
183 /* If a 2K buffer cannot handle a standard Ethernet frame then
184 * optimize padding for a 3K buffer instead of a 1.5K buffer.
185 *
186 * For a 3K buffer we need to add enough padding to allow for
187 * tailroom due to NET_IP_ALIGN possibly shifting us out of
188 * cache-line alignment.
189 */
190 if (IGB_2K_TOO_SMALL_WITH_PADDING)
191 rx_buf_len = IGB_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
192 else
193 rx_buf_len = IGB_RXBUFFER_1536;
194
195 /* if needed make room for NET_IP_ALIGN */
196 rx_buf_len -= NET_IP_ALIGN;
197
198 return igb_compute_pad(rx_buf_len);
199 }
200
201 #define IGB_SKB_PAD igb_skb_pad()
202 #else
203 #define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
204 #endif
205
206 /* How many Rx Buffers do we bundle into one write to the hardware ? */
207 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
208
209 #define IGB_RX_DMA_ATTR \
210 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
211
212 #define AUTO_ALL_MODES 0
213 #define IGB_EEPROM_APME 0x0400
214
215 #ifndef IGB_MASTER_SLAVE
216 /* Switch to override PHY master/slave setting */
217 #define IGB_MASTER_SLAVE e1000_ms_hw_default
218 #endif
219
220 #define IGB_MNG_VLAN_NONE 0xFFFF
221
222 enum igb_tx_flags {
223 /* cmd_type flags */
224 IGB_TX_FLAGS_VLAN = 0x01,
225 IGB_TX_FLAGS_TSO = 0x02,
226 IGB_TX_FLAGS_TSTAMP = 0x04,
227
228 /* olinfo flags */
229 IGB_TX_FLAGS_IPV4 = 0x10,
230 IGB_TX_FLAGS_CSUM = 0x20,
231 };
232
233 /* VLAN info */
234 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
235 #define IGB_TX_FLAGS_VLAN_SHIFT 16
236
237 /* The largest size we can write to the descriptor is 65535. In order to
238 * maintain a power of two alignment we have to limit ourselves to 32K.
239 */
240 #define IGB_MAX_TXD_PWR 15
241 #define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
242
243 /* Tx Descriptors needed, worst case */
244 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
245 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
246
247 /* EEPROM byte offsets */
248 #define IGB_SFF_8472_SWAP 0x5C
249 #define IGB_SFF_8472_COMP 0x5E
250
251 /* Bitmasks */
252 #define IGB_SFF_ADDRESSING_MODE 0x4
253 #define IGB_SFF_8472_UNSUP 0x00
254
255 /* TX resources are shared between XDP and netstack
256 * and we need to tag the buffer type to distinguish them
257 */
258 enum igb_tx_buf_type {
259 IGB_TYPE_SKB = 0,
260 IGB_TYPE_XDP,
261 IGB_TYPE_XSK
262 };
263
264 /* wrapper around a pointer to a socket buffer,
265 * so a DMA handle can be stored along with the buffer
266 */
267 struct igb_tx_buffer {
268 union e1000_adv_tx_desc *next_to_watch;
269 unsigned long time_stamp;
270 enum igb_tx_buf_type type;
271 union {
272 struct sk_buff *skb;
273 struct xdp_frame *xdpf;
274 };
275 unsigned int bytecount;
276 u16 gso_segs;
277 __be16 protocol;
278
279 DEFINE_DMA_UNMAP_ADDR(dma);
280 DEFINE_DMA_UNMAP_LEN(len);
281 u32 tx_flags;
282 };
283
284 struct igb_rx_buffer {
285 dma_addr_t dma;
286 struct page *page;
287 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
288 __u32 page_offset;
289 #else
290 __u16 page_offset;
291 #endif
292 __u16 pagecnt_bias;
293 };
294
295 struct igb_tx_queue_stats {
296 u64 packets;
297 u64 bytes;
298 u64 restart_queue;
299 u64 restart_queue2;
300 };
301
302 struct igb_rx_queue_stats {
303 u64 packets;
304 u64 bytes;
305 u64 drops;
306 u64 csum_err;
307 u64 alloc_failed;
308 };
309
310 struct igb_ring_container {
311 struct igb_ring *ring; /* pointer to linked list of rings */
312 unsigned int total_bytes; /* total bytes processed this int */
313 unsigned int total_packets; /* total packets processed this int */
314 u16 work_limit; /* total work allowed per interrupt */
315 u8 count; /* total number of rings in vector */
316 u8 itr; /* current ITR setting for ring */
317 };
318
319 struct igb_ring {
320 struct igb_q_vector *q_vector; /* backlink to q_vector */
321 struct net_device *netdev; /* back pointer to net_device */
322 struct bpf_prog *xdp_prog;
323 struct device *dev; /* device pointer for dma mapping */
324 union { /* array of buffer info structs */
325 struct igb_tx_buffer *tx_buffer_info;
326 struct igb_rx_buffer *rx_buffer_info;
327 struct xdp_buff **rx_buffer_info_zc;
328 };
329 void *desc; /* descriptor ring memory */
330 unsigned long flags; /* ring specific flags */
331 void __iomem *tail; /* pointer to ring tail register */
332 dma_addr_t dma; /* phys address of the ring */
333 unsigned int size; /* length of desc. ring in bytes */
334
335 u16 count; /* number of desc. in the ring */
336 u8 queue_index; /* logical index of the ring*/
337 u8 reg_idx; /* physical index of the ring */
338 bool launchtime_enable; /* true if LaunchTime is enabled */
339 bool cbs_enable; /* indicates if CBS is enabled */
340 s32 idleslope; /* idleSlope in kbps */
341 s32 sendslope; /* sendSlope in kbps */
342 s32 hicredit; /* hiCredit in bytes */
343 s32 locredit; /* loCredit in bytes */
344
345 /* everything past this point are written often */
346 u16 next_to_clean;
347 u16 next_to_use;
348 u16 next_to_alloc;
349
350 union {
351 /* TX */
352 struct {
353 struct igb_tx_queue_stats tx_stats;
354 struct u64_stats_sync tx_syncp;
355 struct u64_stats_sync tx_syncp2;
356 };
357 /* RX */
358 struct {
359 struct sk_buff *skb;
360 struct igb_rx_queue_stats rx_stats;
361 struct u64_stats_sync rx_syncp;
362 };
363 };
364 struct xdp_rxq_info xdp_rxq;
365 struct xsk_buff_pool *xsk_pool;
366 } ____cacheline_internodealigned_in_smp;
367
368 struct igb_q_vector {
369 struct igb_adapter *adapter; /* backlink */
370 int cpu; /* CPU for DCA */
371 u32 eims_value; /* EIMS mask value */
372
373 u16 itr_val;
374 u8 set_itr;
375 void __iomem *itr_register;
376
377 struct igb_ring_container rx, tx;
378
379 struct napi_struct napi;
380 struct rcu_head rcu; /* to avoid race with update stats on free */
381 char name[IFNAMSIZ + 9];
382
383 /* for dynamic allocation of rings associated with this q_vector */
384 struct igb_ring ring[] ____cacheline_internodealigned_in_smp;
385 };
386
387 enum e1000_ring_flags_t {
388 IGB_RING_FLAG_RX_3K_BUFFER,
389 IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
390 IGB_RING_FLAG_RX_SCTP_CSUM,
391 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
392 IGB_RING_FLAG_TX_CTX_IDX,
393 IGB_RING_FLAG_TX_DETECT_HANG,
394 IGB_RING_FLAG_TX_DISABLED,
395 IGB_RING_FLAG_RX_ALLOC_FAILED,
396 };
397
398 #define ring_uses_large_buffer(ring) \
399 test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
400 #define set_ring_uses_large_buffer(ring) \
401 set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
402 #define clear_ring_uses_large_buffer(ring) \
403 clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
404
405 #define ring_uses_build_skb(ring) \
406 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
407 #define set_ring_build_skb_enabled(ring) \
408 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
409 #define clear_ring_build_skb_enabled(ring) \
410 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
411
igb_rx_bufsz(struct igb_ring * ring)412 static inline unsigned int igb_rx_bufsz(struct igb_ring *ring)
413 {
414 #if (PAGE_SIZE < 8192)
415 if (ring_uses_large_buffer(ring))
416 return IGB_RXBUFFER_3072;
417
418 if (ring_uses_build_skb(ring))
419 return IGB_MAX_FRAME_BUILD_SKB;
420 #endif
421 return IGB_RXBUFFER_2048;
422 }
423
igb_rx_pg_order(struct igb_ring * ring)424 static inline unsigned int igb_rx_pg_order(struct igb_ring *ring)
425 {
426 #if (PAGE_SIZE < 8192)
427 if (ring_uses_large_buffer(ring))
428 return 1;
429 #endif
430 return 0;
431 }
432
433 #define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring))
434
435 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
436
437 #define IGB_RX_DESC(R, i) \
438 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
439 #define IGB_TX_DESC(R, i) \
440 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
441 #define IGB_TX_CTXTDESC(R, i) \
442 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
443
444 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
igb_test_staterr(union e1000_adv_rx_desc * rx_desc,const u32 stat_err_bits)445 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
446 const u32 stat_err_bits)
447 {
448 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
449 }
450
451 /* igb_desc_unused - calculate if we have unused descriptors */
igb_desc_unused(struct igb_ring * ring)452 static inline int igb_desc_unused(struct igb_ring *ring)
453 {
454 if (ring->next_to_clean > ring->next_to_use)
455 return ring->next_to_clean - ring->next_to_use - 1;
456
457 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
458 }
459
460 #ifdef CONFIG_IGB_HWMON
461
462 #define IGB_HWMON_TYPE_LOC 0
463 #define IGB_HWMON_TYPE_TEMP 1
464 #define IGB_HWMON_TYPE_CAUTION 2
465 #define IGB_HWMON_TYPE_MAX 3
466
467 struct hwmon_attr {
468 struct device_attribute dev_attr;
469 struct e1000_hw *hw;
470 struct e1000_thermal_diode_data *sensor;
471 char name[12];
472 };
473
474 struct hwmon_buff {
475 struct attribute_group group;
476 const struct attribute_group *groups[2];
477 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
478 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
479 unsigned int n_hwmon;
480 };
481 #endif
482
483 /* The number of L2 ether-type filter registers, Index 3 is reserved
484 * for PTP 1588 timestamp
485 */
486 #define MAX_ETYPE_FILTER (4 - 1)
487 /* ETQF filter list: one static filter per filter consumer. This is
488 * to avoid filter collisions later. Add new filters here!!
489 *
490 * Current filters: Filter 3
491 */
492 #define IGB_ETQF_FILTER_1588 3
493
494 #define IGB_N_EXTTS 2
495 #define IGB_N_PEROUT 2
496 #define IGB_N_SDP 4
497 #define IGB_RETA_SIZE 128
498 #define IGB_RSS_KEY_SIZE 40
499
500 enum igb_filter_match_flags {
501 IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
502 IGB_FILTER_FLAG_VLAN_TCI = 0x2,
503 IGB_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
504 IGB_FILTER_FLAG_DST_MAC_ADDR = 0x8,
505 };
506
507 #define IGB_MAX_RXNFC_FILTERS 16
508
509 /* RX network flow classification data structure */
510 struct igb_nfc_input {
511 /* Byte layout in order, all values with MSB first:
512 * match_flags - 1 byte
513 * etype - 2 bytes
514 * vlan_tci - 2 bytes
515 */
516 u8 match_flags;
517 __be16 etype;
518 __be16 vlan_tci;
519 u8 src_addr[ETH_ALEN];
520 u8 dst_addr[ETH_ALEN];
521 };
522
523 struct igb_nfc_filter {
524 struct hlist_node nfc_node;
525 struct igb_nfc_input filter;
526 unsigned long cookie;
527 u16 etype_reg_index;
528 u16 sw_idx;
529 u16 action;
530 };
531
532 struct igb_mac_addr {
533 u8 addr[ETH_ALEN];
534 u8 queue;
535 u8 state; /* bitmask */
536 };
537
538 #define IGB_MAC_STATE_DEFAULT 0x1
539 #define IGB_MAC_STATE_IN_USE 0x2
540 #define IGB_MAC_STATE_SRC_ADDR 0x4
541 #define IGB_MAC_STATE_QUEUE_STEERING 0x8
542
543 /* board specific private data structure */
544 struct igb_adapter {
545 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
546
547 struct net_device *netdev;
548 struct bpf_prog *xdp_prog;
549
550 unsigned long state;
551 unsigned int flags;
552
553 unsigned int num_q_vectors;
554 struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
555
556 /* Interrupt Throttle Rate */
557 u32 rx_itr_setting;
558 u32 tx_itr_setting;
559 u16 tx_itr;
560 u16 rx_itr;
561
562 /* TX */
563 u16 tx_work_limit;
564 u32 tx_timeout_count;
565 int num_tx_queues;
566 struct igb_ring *tx_ring[16];
567
568 /* RX */
569 int num_rx_queues;
570 struct igb_ring *rx_ring[16];
571
572 u32 max_frame_size;
573 u32 min_frame_size;
574
575 struct timer_list watchdog_timer;
576 struct timer_list phy_info_timer;
577
578 u16 mng_vlan_id;
579 u32 bd_number;
580 u32 wol;
581 u32 en_mng_pt;
582 u16 link_speed;
583 u16 link_duplex;
584
585 u8 __iomem *io_addr; /* Mainly for iounmap use */
586
587 struct work_struct reset_task;
588 struct work_struct watchdog_task;
589 bool fc_autoneg;
590 u8 tx_timeout_factor;
591 struct timer_list blink_timer;
592 unsigned long led_status;
593
594 /* OS defined structs */
595 struct pci_dev *pdev;
596
597 spinlock_t stats64_lock;
598 struct rtnl_link_stats64 stats64;
599
600 /* structs defined in e1000_hw.h */
601 struct e1000_hw hw;
602 struct e1000_hw_stats stats;
603 struct e1000_phy_info phy_info;
604
605 u32 test_icr;
606 struct igb_ring test_tx_ring;
607 struct igb_ring test_rx_ring;
608
609 int msg_enable;
610
611 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
612 u32 eims_enable_mask;
613 u32 eims_other;
614
615 /* to not mess up cache alignment, always add to the bottom */
616 u16 tx_ring_count;
617 u16 rx_ring_count;
618 unsigned int vfs_allocated_count;
619 struct vf_data_storage *vf_data;
620 int vf_rate_link_speed;
621 u32 rss_queues;
622 u32 wvbr;
623 u32 *shadow_vfta;
624
625 struct ptp_clock *ptp_clock;
626 struct ptp_clock_info ptp_caps;
627 struct delayed_work ptp_overflow_work;
628 struct work_struct ptp_tx_work;
629 struct sk_buff *ptp_tx_skb;
630 struct kernel_hwtstamp_config tstamp_config;
631 unsigned long ptp_tx_start;
632 unsigned long last_rx_ptp_check;
633 unsigned long last_rx_timestamp;
634 unsigned int ptp_flags;
635 spinlock_t tmreg_lock;
636 struct cyclecounter cc;
637 struct timecounter tc;
638 u32 tx_hwtstamp_timeouts;
639 u32 tx_hwtstamp_skipped;
640 u32 rx_hwtstamp_cleared;
641 bool pps_sys_wrap_on;
642
643 struct ptp_pin_desc sdp_config[IGB_N_SDP];
644 struct {
645 struct timespec64 start;
646 struct timespec64 period;
647 } perout[IGB_N_PEROUT];
648
649 char fw_version[48];
650 #ifdef CONFIG_IGB_HWMON
651 struct hwmon_buff *igb_hwmon_buff;
652 bool ets;
653 #endif
654 struct i2c_algo_bit_data i2c_algo;
655 struct i2c_adapter i2c_adap;
656 struct i2c_client *i2c_client;
657 u32 rss_indir_tbl_init;
658 u8 rss_indir_tbl[IGB_RETA_SIZE];
659 u8 rss_key[IGB_RSS_KEY_SIZE];
660
661 unsigned long link_check_timeout;
662 int copper_tries;
663 struct e1000_info ei;
664 u16 eee_advert;
665
666 /* RX network flow classification support */
667 struct hlist_head nfc_filter_list;
668 struct hlist_head cls_flower_list;
669 unsigned int nfc_filter_count;
670 /* lock for RX network flow classification filter */
671 spinlock_t nfc_lock;
672 bool etype_bitmap[MAX_ETYPE_FILTER];
673
674 struct igb_mac_addr *mac_table;
675 struct vf_mac_filter vf_macs;
676 struct vf_mac_filter *vf_mac_list;
677 /* lock for VF resources */
678 spinlock_t vfs_lock;
679 };
680
681 /* flags controlling PTP/1588 function */
682 #define IGB_PTP_ENABLED BIT(0)
683 #define IGB_PTP_OVERFLOW_CHECK BIT(1)
684
685 #define IGB_FLAG_HAS_MSI BIT(0)
686 #define IGB_FLAG_DCA_ENABLED BIT(1)
687 #define IGB_FLAG_QUAD_PORT_A BIT(2)
688 #define IGB_FLAG_QUEUE_PAIRS BIT(3)
689 #define IGB_FLAG_DMAC BIT(4)
690 #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
691 #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
692 #define IGB_FLAG_WOL_SUPPORTED BIT(8)
693 #define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
694 #define IGB_FLAG_MEDIA_RESET BIT(10)
695 #define IGB_FLAG_MAS_CAPABLE BIT(11)
696 #define IGB_FLAG_MAS_ENABLE BIT(12)
697 #define IGB_FLAG_HAS_MSIX BIT(13)
698 #define IGB_FLAG_EEE BIT(14)
699 #define IGB_FLAG_VLAN_PROMISC BIT(15)
700 #define IGB_FLAG_RX_LEGACY BIT(16)
701 #define IGB_FLAG_FQTSS BIT(17)
702
703 /* Media Auto Sense */
704 #define IGB_MAS_ENABLE_0 0X0001
705 #define IGB_MAS_ENABLE_1 0X0002
706 #define IGB_MAS_ENABLE_2 0X0004
707 #define IGB_MAS_ENABLE_3 0X0008
708
709 /* DMA Coalescing defines */
710 #define IGB_MIN_TXPBSIZE 20408
711 #define IGB_TX_BUF_4096 4096
712 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
713
714 #define IGB_82576_TSYNC_SHIFT 19
715 enum e1000_state_t {
716 __IGB_TESTING,
717 __IGB_RESETTING,
718 __IGB_DOWN,
719 __IGB_PTP_TX_IN_PROGRESS,
720 };
721
722 enum igb_boards {
723 board_82575,
724 };
725
726 extern char igb_driver_name[];
727
728 void igb_set_queue_napi(struct igb_adapter *adapter, int q_idx,
729 struct napi_struct *napi);
730 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
731 struct igb_ring *ring,
732 struct xdp_frame *xdpf);
733 int igb_open(struct net_device *netdev);
734 int igb_close(struct net_device *netdev);
735 int igb_up(struct igb_adapter *);
736 void igb_down(struct igb_adapter *);
737 void igb_reinit_locked(struct igb_adapter *);
738 void igb_reset(struct igb_adapter *);
739 int igb_reinit_queues(struct igb_adapter *);
740 void igb_write_rss_key(struct igb_adapter *adapter);
741 void igb_write_rss_indir_tbl(struct igb_adapter *);
742 int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
743 int igb_setup_tx_resources(struct igb_ring *);
744 int igb_setup_rx_resources(struct igb_ring *);
745 void igb_free_tx_resources(struct igb_ring *);
746 void igb_free_rx_resources(struct igb_ring *);
747 void igb_clean_tx_ring(struct igb_ring *tx_ring);
748 void igb_clean_rx_ring(struct igb_ring *rx_ring);
749 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
750 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
751 void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status);
752 void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets,
753 unsigned int bytes);
754 void igb_setup_tctl(struct igb_adapter *);
755 void igb_setup_rctl(struct igb_adapter *);
756 void igb_setup_srrctl(struct igb_adapter *, struct igb_ring *);
757 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
758 int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp);
759 void igb_process_skb_fields(struct igb_ring *rx_ring,
760 union e1000_adv_rx_desc *rx_desc,
761 struct sk_buff *skb);
762 void igb_alloc_rx_buffers(struct igb_ring *, u16);
763 void igb_update_stats(struct igb_adapter *);
764 bool igb_has_link(struct igb_adapter *adapter);
765 void igb_set_ethtool_ops(struct net_device *);
766 void igb_power_up_link(struct igb_adapter *);
767 void igb_set_fw_version(struct igb_adapter *);
768 void igb_ptp_init(struct igb_adapter *adapter);
769 void igb_ptp_stop(struct igb_adapter *adapter);
770 void igb_ptp_reset(struct igb_adapter *adapter);
771 void igb_ptp_suspend(struct igb_adapter *adapter);
772 void igb_ptp_rx_hang(struct igb_adapter *adapter);
773 void igb_ptp_tx_hang(struct igb_adapter *adapter);
774 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
775 int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
776 ktime_t *timestamp);
777 int igb_ptp_hwtstamp_get(struct net_device *netdev,
778 struct kernel_hwtstamp_config *config);
779 int igb_ptp_hwtstamp_set(struct net_device *netdev,
780 struct kernel_hwtstamp_config *config,
781 struct netlink_ext_ack *extack);
782 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
783 unsigned int igb_get_max_rss_queues(struct igb_adapter *);
784 #ifdef CONFIG_IGB_HWMON
785 void igb_sysfs_exit(struct igb_adapter *adapter);
786 int igb_sysfs_init(struct igb_adapter *adapter);
787 #endif
igb_reset_phy(struct e1000_hw * hw)788 static inline s32 igb_reset_phy(struct e1000_hw *hw)
789 {
790 if (hw->phy.ops.reset)
791 return hw->phy.ops.reset(hw);
792
793 return 0;
794 }
795
igb_read_phy_reg(struct e1000_hw * hw,u32 offset,u16 * data)796 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
797 {
798 if (hw->phy.ops.read_reg)
799 return hw->phy.ops.read_reg(hw, offset, data);
800
801 return 0;
802 }
803
igb_write_phy_reg(struct e1000_hw * hw,u32 offset,u16 data)804 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
805 {
806 if (hw->phy.ops.write_reg)
807 return hw->phy.ops.write_reg(hw, offset, data);
808
809 return 0;
810 }
811
igb_get_phy_info(struct e1000_hw * hw)812 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
813 {
814 if (hw->phy.ops.get_phy_info)
815 return hw->phy.ops.get_phy_info(hw);
816
817 return 0;
818 }
819
txring_txq(const struct igb_ring * tx_ring)820 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
821 {
822 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
823 }
824
825 /* This function assumes __netif_tx_lock is held by the caller. */
igb_xdp_ring_update_tail(struct igb_ring * ring)826 static inline void igb_xdp_ring_update_tail(struct igb_ring *ring)
827 {
828 lockdep_assert_held(&txring_txq(ring)->_xmit_lock);
829
830 /* Force memory writes to complete before letting h/w know there
831 * are new descriptors to fetch.
832 */
833 wmb();
834 writel(ring->next_to_use, ring->tail);
835 }
836
igb_xdp_tx_queue_mapping(struct igb_adapter * adapter)837 static inline struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
838 {
839 unsigned int r_idx = smp_processor_id();
840
841 if (r_idx >= adapter->num_tx_queues)
842 r_idx = r_idx % adapter->num_tx_queues;
843
844 return adapter->tx_ring[r_idx];
845 }
846
igb_xdp_is_enabled(struct igb_adapter * adapter)847 static inline bool igb_xdp_is_enabled(struct igb_adapter *adapter)
848 {
849 return !!READ_ONCE(adapter->xdp_prog);
850 }
851
852 int igb_add_filter(struct igb_adapter *adapter,
853 struct igb_nfc_filter *input);
854 int igb_erase_filter(struct igb_adapter *adapter,
855 struct igb_nfc_filter *input);
856
857 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
858 const u8 *addr, u8 queue, u8 flags);
859 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
860 const u8 *addr, u8 queue, u8 flags);
861
862 struct xsk_buff_pool *igb_xsk_pool(struct igb_adapter *adapter,
863 struct igb_ring *ring);
864 int igb_xsk_pool_setup(struct igb_adapter *adapter,
865 struct xsk_buff_pool *pool,
866 u16 qid);
867 bool igb_alloc_rx_buffers_zc(struct igb_ring *rx_ring,
868 struct xsk_buff_pool *xsk_pool, u16 count);
869 void igb_clean_rx_ring_zc(struct igb_ring *rx_ring);
870 int igb_clean_rx_irq_zc(struct igb_q_vector *q_vector,
871 struct xsk_buff_pool *xsk_pool, const int budget);
872 bool igb_xmit_zc(struct igb_ring *tx_ring, struct xsk_buff_pool *xsk_pool);
873 int igb_xsk_wakeup(struct net_device *dev, u32 qid, u32 flags);
874
875 #endif /* _IGB_H_ */
876