1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/pci.h> 14 #include <linux/platform_device.h> 15 #include <linux/if_vlan.h> 16 #include <linux/crash_dump.h> 17 18 #include <net/rtnetlink.h> 19 #include "hclge_cmd.h" 20 #include "hclge_dcb.h" 21 #include "hclge_fd.h" 22 #include "hclge_main.h" 23 #include "hclge_mbx.h" 24 #include "hclge_mdio.h" 25 #include "hclge_regs.h" 26 #include "hclge_tm.h" 27 #include "hclge_err.h" 28 #include "hnae3.h" 29 #include "hclge_devlink.h" 30 #include "hclge_comm_cmd.h" 31 32 #include "hclge_trace.h" 33 34 #define HCLGE_NAME "hclge" 35 36 #define HCLGE_BUF_SIZE_UNIT 256U 37 #define HCLGE_BUF_MUL_BY 2 38 #define HCLGE_BUF_DIV_BY 2 39 #define NEED_RESERVE_TC_NUM 2 40 #define BUF_MAX_PERCENT 100 41 #define BUF_RESERVE_PERCENT 90 42 43 #define HCLGE_RESET_MAX_FAIL_CNT 5 44 #define HCLGE_RESET_SYNC_TIME 100 45 #define HCLGE_PF_RESET_SYNC_TIME 20 46 #define HCLGE_PF_RESET_SYNC_CNT 1500 47 48 #define HCLGE_LINK_STATUS_MS 10 49 50 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 51 static int hclge_init_vlan_config(struct hclge_dev *hdev); 52 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 53 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 54 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 55 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 56 unsigned long *addr); 57 static int hclge_set_default_loopback(struct hclge_dev *hdev); 58 59 static void hclge_sync_mac_table(struct hclge_dev *hdev); 60 static void hclge_restore_hw_table(struct hclge_dev *hdev); 61 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 62 static void hclge_update_fec_stats(struct hclge_dev *hdev); 63 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 64 int wait_cnt); 65 static int hclge_update_port_info(struct hclge_dev *hdev); 66 67 static struct hnae3_ae_algo ae_algo; 68 69 static struct workqueue_struct *hclge_wq; 70 71 static const struct pci_device_id ae_algo_pci_tbl[] = { 72 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE) }, 73 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE) }, 74 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA) }, 75 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC) }, 76 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA) }, 77 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC) }, 78 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC) }, 79 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA) }, 80 /* required last entry */ 81 { } 82 }; 83 84 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 85 86 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 87 "External Loopback test", 88 "App Loopback test", 89 "Serdes serial Loopback test", 90 "Serdes parallel Loopback test", 91 "Phy Loopback test" 92 }; 93 94 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 95 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 97 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 98 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 99 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 101 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 102 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 103 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 105 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 106 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 107 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 109 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 111 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 113 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 115 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 117 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 119 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 121 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 123 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 125 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 127 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 129 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 131 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 133 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 135 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 137 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 139 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 141 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 142 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 143 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 144 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 145 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 147 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 149 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 151 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 153 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 155 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 157 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 159 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 161 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 163 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 165 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 167 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 169 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 171 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 173 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 175 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 176 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 177 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 178 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 179 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 180 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 181 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 182 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 183 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 184 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 185 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 186 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 187 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 188 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 189 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 190 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 191 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 192 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 193 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 194 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 195 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 197 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 199 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 201 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 203 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 205 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 206 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 207 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 208 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 209 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 210 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 211 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 212 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 213 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 214 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 215 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 216 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 217 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 218 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 219 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 220 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 221 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 222 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 223 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 224 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 225 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 226 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 227 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 229 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 230 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 231 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 233 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 235 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 236 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 237 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 238 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 239 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 240 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 241 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 242 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 243 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 244 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 245 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 247 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 249 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 251 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 253 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 255 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 257 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 259 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 261 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 263 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 265 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 267 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 268 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 269 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 270 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 271 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 272 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 273 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 274 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 275 276 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 278 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 280 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 282 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 284 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 286 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 288 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 290 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 292 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 294 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 296 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 298 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 300 }; 301 302 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 303 { 304 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 305 .ethter_type = cpu_to_le16(ETH_P_LLDP), 306 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 307 .i_port_bitmap = 0x1, 308 }, 309 }; 310 311 /** 312 * hclge_cmd_send - send command to command queue 313 * @hw: pointer to the hw struct 314 * @desc: prefilled descriptor for describing the command 315 * @num : the number of descriptors to be sent 316 * 317 * This is the main send command for command queue, it 318 * sends the queue, cleans the queue, etc 319 **/ 320 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 321 { 322 return hclge_comm_cmd_send(&hw->hw, desc, num); 323 } 324 325 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 326 int num, bool is_special) 327 { 328 int i; 329 330 trace_hclge_pf_cmd_send(hw, desc, 0, num); 331 332 if (!is_special) { 333 for (i = 1; i < num; i++) 334 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 335 } else { 336 for (i = 1; i < num; i++) 337 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 338 i, num); 339 } 340 } 341 342 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 343 int num, bool is_special) 344 { 345 int i; 346 347 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 348 return; 349 350 trace_hclge_pf_cmd_get(hw, desc, 0, num); 351 352 if (!is_special) { 353 for (i = 1; i < num; i++) 354 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 355 } else { 356 for (i = 1; i < num; i++) 357 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 358 i, num); 359 } 360 } 361 362 static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 363 .trace_cmd_send = hclge_trace_cmd_send, 364 .trace_cmd_get = hclge_trace_cmd_get, 365 }; 366 367 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 368 { 369 #define HCLGE_MAC_CMD_NUM 21 370 371 u64 *data = (u64 *)(&hdev->mac_stats); 372 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 373 __le64 *desc_data; 374 u32 data_size; 375 int ret; 376 u32 i; 377 378 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 379 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 380 if (ret) { 381 dev_err(&hdev->pdev->dev, 382 "Get MAC pkt stats fail, status = %d.\n", ret); 383 384 return ret; 385 } 386 387 /* The first desc has a 64-bit header, so data size need to minus 1 */ 388 data_size = sizeof(desc) / (sizeof(u64)) - 1; 389 390 desc_data = (__le64 *)(&desc[0].data[0]); 391 for (i = 0; i < data_size; i++) { 392 /* data memory is continuous becase only the first desc has a 393 * header in this command 394 */ 395 *data += le64_to_cpu(*desc_data); 396 data++; 397 desc_data++; 398 } 399 400 return 0; 401 } 402 403 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 404 { 405 #define HCLGE_REG_NUM_PER_DESC 4 406 407 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 408 u64 *data = (u64 *)(&hdev->mac_stats); 409 struct hclge_desc *desc; 410 __le64 *desc_data; 411 u32 data_size; 412 u32 desc_num; 413 int ret; 414 u32 i; 415 416 /* The first desc has a 64-bit header, so need to consider it */ 417 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 418 419 /* This may be called inside atomic sections, 420 * so GFP_ATOMIC is more suitable here 421 */ 422 desc = kzalloc_objs(struct hclge_desc, desc_num, GFP_ATOMIC); 423 if (!desc) 424 return -ENOMEM; 425 426 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 427 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 428 if (ret) { 429 kfree(desc); 430 return ret; 431 } 432 433 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 434 435 desc_data = (__le64 *)(&desc[0].data[0]); 436 for (i = 0; i < data_size; i++) { 437 /* data memory is continuous becase only the first desc has a 438 * header in this command 439 */ 440 *data += le64_to_cpu(*desc_data); 441 data++; 442 desc_data++; 443 } 444 445 kfree(desc); 446 447 return 0; 448 } 449 450 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 451 { 452 struct hclge_desc desc; 453 int ret; 454 455 /* Driver needs total register number of both valid registers and 456 * reserved registers, but the old firmware only returns number 457 * of valid registers in device V2. To be compatible with these 458 * devices, driver uses a fixed value. 459 */ 460 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 461 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 462 return 0; 463 } 464 465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 466 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 467 if (ret) { 468 dev_err(&hdev->pdev->dev, 469 "failed to query mac statistic reg number, ret = %d\n", 470 ret); 471 return ret; 472 } 473 474 *reg_num = le32_to_cpu(desc.data[0]); 475 if (*reg_num == 0) { 476 dev_err(&hdev->pdev->dev, 477 "mac statistic reg number is invalid!\n"); 478 return -ENODATA; 479 } 480 481 return 0; 482 } 483 484 int hclge_mac_update_stats(struct hclge_dev *hdev) 485 { 486 /* The firmware supports the new statistics acquisition method */ 487 if (hdev->ae_dev->dev_specs.mac_stats_num) 488 return hclge_mac_update_stats_complete(hdev); 489 else 490 return hclge_mac_update_stats_defective(hdev); 491 } 492 493 static int hclge_comm_get_count(struct hclge_dev *hdev, 494 const struct hclge_comm_stats_str strs[], 495 u32 size) 496 { 497 int count = 0; 498 u32 i; 499 500 for (i = 0; i < size; i++) 501 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 502 count++; 503 504 return count; 505 } 506 507 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 508 const struct hclge_comm_stats_str strs[], 509 int size, u64 *data) 510 { 511 u64 *buf = data; 512 int i; 513 514 for (i = 0; i < size; i++) { 515 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 516 continue; 517 518 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 519 buf++; 520 } 521 522 return buf; 523 } 524 525 static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 526 const struct hclge_comm_stats_str strs[], 527 int size, u8 **data) 528 { 529 int i; 530 531 if (stringset != ETH_SS_STATS) 532 return; 533 534 for (i = 0; i < size; i++) { 535 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 536 continue; 537 538 ethtool_puts(data, strs[i].desc); 539 } 540 } 541 542 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 543 { 544 struct hnae3_handle *handle; 545 int status; 546 547 handle = &hdev->vport[0].nic; 548 if (handle->client) { 549 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 550 if (status) { 551 dev_err(&hdev->pdev->dev, 552 "Update TQPS stats fail, status = %d.\n", 553 status); 554 } 555 } 556 557 hclge_update_fec_stats(hdev); 558 559 status = hclge_mac_update_stats(hdev); 560 if (status) 561 dev_err(&hdev->pdev->dev, 562 "Update MAC stats fail, status = %d.\n", status); 563 } 564 565 static void hclge_update_stats(struct hnae3_handle *handle) 566 { 567 struct hclge_vport *vport = hclge_get_vport(handle); 568 struct hclge_dev *hdev = vport->back; 569 int status; 570 571 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 572 return; 573 574 status = hclge_mac_update_stats(hdev); 575 if (status) 576 dev_err(&hdev->pdev->dev, 577 "Update MAC stats fail, status = %d.\n", 578 status); 579 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 586 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 587 } 588 589 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 590 { 591 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 592 HNAE3_SUPPORT_PHY_LOOPBACK | \ 593 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 594 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 595 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 596 597 struct hclge_vport *vport = hclge_get_vport(handle); 598 struct hclge_dev *hdev = vport->back; 599 int count = 0; 600 601 /* Loopback test support rules: 602 * mac: only GE mode support 603 * serdes: all mac mode will support include GE/XGE/LGE/CGE 604 * phy: only support when phy device exist on board 605 */ 606 if (stringset == ETH_SS_TEST) { 607 /* clear loopback bit flags at first */ 608 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 609 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 610 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 611 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 612 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 613 count += 1; 614 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 615 } 616 617 if (hdev->ae_dev->dev_specs.hilink_version != 618 HCLGE_HILINK_H60) { 619 count += 1; 620 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 621 } 622 623 count += 1; 624 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 625 count += 1; 626 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 627 628 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 629 hdev->hw.mac.phydev->drv->set_loopback) || 630 hnae3_dev_phy_imp_supported(hdev)) { 631 count += 1; 632 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 633 } 634 } else if (stringset == ETH_SS_STATS) { 635 count = hclge_comm_get_count(hdev, g_mac_stats_string, 636 ARRAY_SIZE(g_mac_stats_string)) + 637 hclge_comm_tqps_get_sset_count(handle); 638 } 639 640 return count; 641 } 642 643 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 644 u8 **data) 645 { 646 struct hclge_vport *vport = hclge_get_vport(handle); 647 struct hclge_dev *hdev = vport->back; 648 const char *str; 649 int size; 650 651 if (stringset == ETH_SS_STATS) { 652 size = ARRAY_SIZE(g_mac_stats_string); 653 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 654 size, data); 655 hclge_comm_tqps_get_strings(handle, data); 656 } else if (stringset == ETH_SS_TEST) { 657 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 658 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; 659 ethtool_puts(data, str); 660 } 661 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 662 str = hns3_nic_test_strs[HNAE3_LOOP_APP]; 663 ethtool_puts(data, str); 664 } 665 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 666 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; 667 ethtool_puts(data, str); 668 } 669 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 670 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; 671 ethtool_puts(data, str); 672 } 673 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 674 str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; 675 ethtool_puts(data, str); 676 } 677 } 678 } 679 680 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 681 { 682 struct hclge_vport *vport = hclge_get_vport(handle); 683 struct hclge_dev *hdev = vport->back; 684 u64 *p; 685 686 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 687 ARRAY_SIZE(g_mac_stats_string), data); 688 p = hclge_comm_tqps_get_stats(handle, p); 689 } 690 691 static void hclge_get_mac_stat(struct hnae3_handle *handle, 692 struct hns3_mac_stats *mac_stats) 693 { 694 struct hclge_vport *vport = hclge_get_vport(handle); 695 struct hclge_dev *hdev = vport->back; 696 697 hclge_update_stats(handle); 698 699 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 700 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 701 } 702 703 static int hclge_parse_func_status(struct hclge_dev *hdev, 704 struct hclge_func_status_cmd *status) 705 { 706 #define HCLGE_MAC_ID_MASK 0xF 707 708 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 709 return -EINVAL; 710 711 /* Set the pf to main pf */ 712 if (status->pf_state & HCLGE_PF_STATE_MAIN) 713 hdev->flag |= HCLGE_FLAG_MAIN; 714 else 715 hdev->flag &= ~HCLGE_FLAG_MAIN; 716 717 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 718 return 0; 719 } 720 721 static int hclge_query_function_status(struct hclge_dev *hdev) 722 { 723 #define HCLGE_QUERY_MAX_CNT 5 724 725 struct hclge_func_status_cmd *req; 726 struct hclge_desc desc; 727 int timeout = 0; 728 int ret; 729 730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 731 req = (struct hclge_func_status_cmd *)desc.data; 732 733 do { 734 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 735 if (ret) { 736 dev_err(&hdev->pdev->dev, 737 "query function status failed %d.\n", ret); 738 return ret; 739 } 740 741 /* Check pf reset is done */ 742 if (req->pf_state) 743 break; 744 usleep_range(1000, 2000); 745 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 746 747 return hclge_parse_func_status(hdev, req); 748 } 749 750 static int hclge_query_pf_resource(struct hclge_dev *hdev) 751 { 752 struct hclge_pf_res_cmd *req; 753 struct hclge_desc desc; 754 int ret; 755 756 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 757 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 758 if (ret) { 759 dev_err(&hdev->pdev->dev, 760 "query pf resource failed %d.\n", ret); 761 return ret; 762 } 763 764 req = (struct hclge_pf_res_cmd *)desc.data; 765 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 766 le16_to_cpu(req->ext_tqp_num); 767 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 768 769 if (req->tx_buf_size) 770 hdev->tx_buf_size = 771 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 772 else 773 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 774 775 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 776 777 if (req->dv_buf_size) 778 hdev->dv_buf_size = 779 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 780 else 781 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 782 783 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 784 785 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 786 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 787 dev_err(&hdev->pdev->dev, 788 "only %u msi resources available, not enough for pf(min:2).\n", 789 hdev->num_nic_msi); 790 return -EINVAL; 791 } 792 793 if (hnae3_dev_roce_supported(hdev)) { 794 hdev->num_roce_msi = 795 le16_to_cpu(req->pf_intr_vector_number_roce); 796 797 /* PF should have NIC vectors and Roce vectors, 798 * NIC vectors are queued before Roce vectors. 799 */ 800 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 801 } else { 802 hdev->num_msi = hdev->num_nic_msi; 803 } 804 805 return 0; 806 } 807 808 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 809 { 810 switch (speed_cmd) { 811 case HCLGE_FW_MAC_SPEED_10M: 812 *speed = HCLGE_MAC_SPEED_10M; 813 break; 814 case HCLGE_FW_MAC_SPEED_100M: 815 *speed = HCLGE_MAC_SPEED_100M; 816 break; 817 case HCLGE_FW_MAC_SPEED_1G: 818 *speed = HCLGE_MAC_SPEED_1G; 819 break; 820 case HCLGE_FW_MAC_SPEED_10G: 821 *speed = HCLGE_MAC_SPEED_10G; 822 break; 823 case HCLGE_FW_MAC_SPEED_25G: 824 *speed = HCLGE_MAC_SPEED_25G; 825 break; 826 case HCLGE_FW_MAC_SPEED_40G: 827 *speed = HCLGE_MAC_SPEED_40G; 828 break; 829 case HCLGE_FW_MAC_SPEED_50G: 830 *speed = HCLGE_MAC_SPEED_50G; 831 break; 832 case HCLGE_FW_MAC_SPEED_100G: 833 *speed = HCLGE_MAC_SPEED_100G; 834 break; 835 case HCLGE_FW_MAC_SPEED_200G: 836 *speed = HCLGE_MAC_SPEED_200G; 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 return 0; 843 } 844 845 static const struct hclge_speed_bit_map speed_bit_map[] = { 846 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 847 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 848 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 849 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 850 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 851 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 852 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 853 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 854 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 855 }; 856 857 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 858 { 859 u16 i; 860 861 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 862 if (speed == speed_bit_map[i].speed) { 863 *speed_bit = speed_bit_map[i].speed_bit; 864 return 0; 865 } 866 } 867 868 return -EINVAL; 869 } 870 871 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 872 { 873 struct hclge_vport *vport = hclge_get_vport(handle); 874 struct hclge_dev *hdev = vport->back; 875 u32 speed_ability = hdev->hw.mac.speed_ability; 876 u32 speed_bit = 0; 877 int ret; 878 879 ret = hclge_get_speed_bit(speed, &speed_bit); 880 if (ret) 881 return ret; 882 883 if (speed_bit & speed_ability) 884 return 0; 885 886 return -EINVAL; 887 } 888 889 static void hclge_update_fec_support(struct hclge_mac *mac) 890 { 891 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 892 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 893 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 894 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 895 896 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 897 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 898 mac->supported); 899 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 900 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 901 mac->supported); 902 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 903 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 904 mac->supported); 905 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 906 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 907 mac->supported); 908 } 909 910 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 911 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 912 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 913 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 914 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 915 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 916 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 917 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 918 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 919 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 920 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 921 }; 922 923 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 924 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 925 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 926 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 927 {HCLGE_SUPPORT_100G_R4_BIT, 928 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 929 {HCLGE_SUPPORT_100G_R2_BIT, 930 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 931 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 932 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 933 {HCLGE_SUPPORT_200G_R4_BIT, 934 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 935 }; 936 937 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 938 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 939 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 940 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 941 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 942 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 943 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 944 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 945 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 946 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 947 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 948 }; 949 950 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 951 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 952 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 953 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 954 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 955 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 956 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 957 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 958 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 959 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 960 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 961 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 962 }; 963 964 static void hclge_convert_setting_sr(u16 speed_ability, 965 unsigned long *link_mode) 966 { 967 int i; 968 969 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 970 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 971 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 972 link_mode); 973 } 974 } 975 976 static void hclge_convert_setting_lr(u16 speed_ability, 977 unsigned long *link_mode) 978 { 979 int i; 980 981 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 982 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 983 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 984 link_mode); 985 } 986 } 987 988 static void hclge_convert_setting_cr(u16 speed_ability, 989 unsigned long *link_mode) 990 { 991 int i; 992 993 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 994 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 995 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 996 link_mode); 997 } 998 } 999 1000 static void hclge_convert_setting_kr(u16 speed_ability, 1001 unsigned long *link_mode) 1002 { 1003 int i; 1004 1005 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1006 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1007 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1008 link_mode); 1009 } 1010 } 1011 1012 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1013 { 1014 /* If firmware has reported fec_ability, don't need to convert by speed */ 1015 if (mac->fec_ability) 1016 goto out; 1017 1018 switch (mac->speed) { 1019 case HCLGE_MAC_SPEED_10G: 1020 case HCLGE_MAC_SPEED_40G: 1021 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1022 BIT(HNAE3_FEC_NONE); 1023 break; 1024 case HCLGE_MAC_SPEED_25G: 1025 case HCLGE_MAC_SPEED_50G: 1026 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1027 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1028 break; 1029 case HCLGE_MAC_SPEED_100G: 1030 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1031 BIT(HNAE3_FEC_NONE); 1032 break; 1033 case HCLGE_MAC_SPEED_200G: 1034 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1035 BIT(HNAE3_FEC_LLRS); 1036 break; 1037 default: 1038 mac->fec_ability = 0; 1039 break; 1040 } 1041 1042 out: 1043 hclge_update_fec_support(mac); 1044 } 1045 1046 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1047 u16 speed_ability) 1048 { 1049 struct hclge_mac *mac = &hdev->hw.mac; 1050 1051 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1052 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1053 mac->supported); 1054 1055 hclge_convert_setting_sr(speed_ability, mac->supported); 1056 hclge_convert_setting_lr(speed_ability, mac->supported); 1057 hclge_convert_setting_cr(speed_ability, mac->supported); 1058 if (hnae3_dev_fec_supported(hdev)) 1059 hclge_convert_setting_fec(mac); 1060 1061 if (hnae3_dev_pause_supported(hdev)) 1062 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1063 1064 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1065 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1066 } 1067 1068 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1069 u16 speed_ability) 1070 { 1071 struct hclge_mac *mac = &hdev->hw.mac; 1072 1073 hclge_convert_setting_kr(speed_ability, mac->supported); 1074 if (hnae3_dev_fec_supported(hdev)) 1075 hclge_convert_setting_fec(mac); 1076 1077 if (hnae3_dev_pause_supported(hdev)) 1078 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1079 1080 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1081 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1082 } 1083 1084 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1085 u16 speed_ability) 1086 { 1087 unsigned long *supported = hdev->hw.mac.supported; 1088 1089 /* default to support all speed for GE port */ 1090 if (!speed_ability) 1091 speed_ability = HCLGE_SUPPORT_GE; 1092 1093 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1095 supported); 1096 1097 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1099 supported); 1100 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1101 supported); 1102 } 1103 1104 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1106 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1107 } 1108 1109 if (hnae3_dev_pause_supported(hdev)) { 1110 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1111 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1112 } 1113 1114 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1115 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1116 } 1117 1118 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1119 { 1120 u8 media_type = hdev->hw.mac.media_type; 1121 1122 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1123 hclge_parse_fiber_link_mode(hdev, speed_ability); 1124 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1125 hclge_parse_copper_link_mode(hdev, speed_ability); 1126 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1127 hclge_parse_backplane_link_mode(hdev, speed_ability); 1128 } 1129 1130 static u32 hclge_get_max_speed(u16 speed_ability) 1131 { 1132 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1133 return HCLGE_MAC_SPEED_200G; 1134 1135 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1136 return HCLGE_MAC_SPEED_100G; 1137 1138 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1139 return HCLGE_MAC_SPEED_50G; 1140 1141 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1142 return HCLGE_MAC_SPEED_40G; 1143 1144 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1145 return HCLGE_MAC_SPEED_25G; 1146 1147 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1148 return HCLGE_MAC_SPEED_10G; 1149 1150 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1151 return HCLGE_MAC_SPEED_1G; 1152 1153 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1154 return HCLGE_MAC_SPEED_100M; 1155 1156 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1157 return HCLGE_MAC_SPEED_10M; 1158 1159 return HCLGE_MAC_SPEED_1G; 1160 } 1161 1162 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1163 { 1164 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1165 #define SPEED_ABILITY_EXT_SHIFT 8 1166 1167 struct hclge_cfg_param_cmd *req; 1168 u64 mac_addr_tmp_high; 1169 u16 speed_ability_ext; 1170 u64 mac_addr_tmp; 1171 unsigned int i; 1172 1173 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1174 1175 /* get the configuration */ 1176 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1177 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1178 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1179 HCLGE_CFG_TQP_DESC_N_M, 1180 HCLGE_CFG_TQP_DESC_N_S); 1181 1182 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1183 HCLGE_CFG_PHY_ADDR_M, 1184 HCLGE_CFG_PHY_ADDR_S); 1185 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1186 HCLGE_CFG_MEDIA_TP_M, 1187 HCLGE_CFG_MEDIA_TP_S); 1188 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1189 HCLGE_CFG_RX_BUF_LEN_M, 1190 HCLGE_CFG_RX_BUF_LEN_S); 1191 /* get mac_address */ 1192 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1193 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1194 HCLGE_CFG_MAC_ADDR_H_M, 1195 HCLGE_CFG_MAC_ADDR_H_S); 1196 1197 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1198 1199 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1200 HCLGE_CFG_DEFAULT_SPEED_M, 1201 HCLGE_CFG_DEFAULT_SPEED_S); 1202 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1203 HCLGE_CFG_RSS_SIZE_M, 1204 HCLGE_CFG_RSS_SIZE_S); 1205 1206 for (i = 0; i < ETH_ALEN; i++) 1207 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1208 1209 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1210 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1211 1212 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_SPEED_ABILITY_M, 1214 HCLGE_CFG_SPEED_ABILITY_S); 1215 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1217 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1218 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1219 1220 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1221 HCLGE_CFG_VLAN_FLTR_CAP_M, 1222 HCLGE_CFG_VLAN_FLTR_CAP_S); 1223 1224 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1225 HCLGE_CFG_UMV_TBL_SPACE_M, 1226 HCLGE_CFG_UMV_TBL_SPACE_S); 1227 1228 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1229 HCLGE_CFG_PF_RSS_SIZE_M, 1230 HCLGE_CFG_PF_RSS_SIZE_S); 1231 1232 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1233 * power of 2, instead of reading out directly. This would 1234 * be more flexible for future changes and expansions. 1235 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1236 * it does not make sense if PF's field is 0. In this case, PF and VF 1237 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1238 */ 1239 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1240 1U << cfg->pf_rss_size_max : 1241 cfg->vf_rss_size_max; 1242 1243 /* The unit of the tx spare buffer size queried from configuration 1244 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1245 * needed here. 1246 */ 1247 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1248 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1249 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1250 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1251 } 1252 1253 /* hclge_get_cfg: query the static parameter from flash 1254 * @hdev: pointer to struct hclge_dev 1255 * @hcfg: the config structure to be getted 1256 */ 1257 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1258 { 1259 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1260 struct hclge_cfg_param_cmd *req; 1261 unsigned int i; 1262 int ret; 1263 1264 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1265 u32 offset = 0; 1266 1267 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1268 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1269 true); 1270 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1271 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1272 /* Len should be united by 4 bytes when send to hardware */ 1273 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1274 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1275 req->offset = cpu_to_le32(offset); 1276 } 1277 1278 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1279 if (ret) { 1280 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1281 return ret; 1282 } 1283 1284 hclge_parse_cfg(hcfg, desc); 1285 1286 return 0; 1287 } 1288 1289 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1290 { 1291 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1292 1293 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1294 1295 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1296 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1297 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1298 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1299 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1300 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1301 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1302 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1303 ae_dev->dev_specs.tnl_num = 0; 1304 } 1305 1306 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1307 struct hclge_desc *desc) 1308 { 1309 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1310 struct hclge_dev_specs_0_cmd *req0; 1311 struct hclge_dev_specs_1_cmd *req1; 1312 1313 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1314 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1315 1316 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1317 ae_dev->dev_specs.rss_ind_tbl_size = 1318 le16_to_cpu(req0->rss_ind_tbl_size); 1319 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1320 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1321 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1322 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1323 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1324 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1325 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1326 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1327 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1328 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1329 } 1330 1331 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1332 { 1333 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1334 1335 if (!dev_specs->max_non_tso_bd_num) 1336 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1337 if (!dev_specs->rss_ind_tbl_size) 1338 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1339 if (!dev_specs->rss_key_size) 1340 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1341 if (!dev_specs->max_tm_rate) 1342 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1343 if (!dev_specs->max_qset_num) 1344 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1345 if (!dev_specs->max_int_gl) 1346 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1347 if (!dev_specs->max_frm_size) 1348 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1349 if (!dev_specs->umv_size) 1350 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1351 } 1352 1353 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1354 { 1355 u32 reg_num = 0; 1356 int ret; 1357 1358 ret = hclge_mac_query_reg_num(hdev, ®_num); 1359 if (ret && ret != -EOPNOTSUPP) 1360 return ret; 1361 1362 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1363 return 0; 1364 } 1365 1366 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1367 { 1368 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1369 int ret; 1370 int i; 1371 1372 ret = hclge_query_mac_stats_num(hdev); 1373 if (ret) 1374 return ret; 1375 1376 /* set default specifications as devices lower than version V3 do not 1377 * support querying specifications from firmware. 1378 */ 1379 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1380 hclge_set_default_dev_specs(hdev); 1381 return 0; 1382 } 1383 1384 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1385 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1386 true); 1387 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1388 } 1389 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1390 1391 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1392 if (ret) 1393 return ret; 1394 1395 hclge_parse_dev_specs(hdev, desc); 1396 hclge_check_dev_specs(hdev); 1397 1398 return 0; 1399 } 1400 1401 static int hclge_get_cap(struct hclge_dev *hdev) 1402 { 1403 int ret; 1404 1405 ret = hclge_query_function_status(hdev); 1406 if (ret) { 1407 dev_err(&hdev->pdev->dev, 1408 "query function status error %d.\n", ret); 1409 return ret; 1410 } 1411 1412 /* get pf resource */ 1413 return hclge_query_pf_resource(hdev); 1414 } 1415 1416 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1417 { 1418 #define HCLGE_MIN_TX_DESC 64 1419 #define HCLGE_MIN_RX_DESC 64 1420 1421 if (!is_kdump_kernel()) 1422 return; 1423 1424 dev_info(&hdev->pdev->dev, 1425 "Running kdump kernel. Using minimal resources\n"); 1426 1427 /* minimal queue pairs equals to the number of vports */ 1428 hdev->num_tqps = hdev->num_req_vfs + 1; 1429 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1430 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1431 } 1432 1433 static void hclge_init_tc_config(struct hclge_dev *hdev) 1434 { 1435 unsigned int i; 1436 1437 if (hdev->tc_max > HNAE3_MAX_TC || 1438 hdev->tc_max < 1) { 1439 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1440 hdev->tc_max); 1441 hdev->tc_max = 1; 1442 } 1443 1444 /* Dev does not support DCB */ 1445 if (!hnae3_dev_dcb_supported(hdev)) { 1446 hdev->tc_max = 1; 1447 hdev->pfc_max = 0; 1448 } else { 1449 hdev->pfc_max = hdev->tc_max; 1450 } 1451 1452 hdev->tm_info.num_tc = 1; 1453 1454 /* Currently not support uncontiuous tc */ 1455 for (i = 0; i < hdev->tm_info.num_tc; i++) 1456 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1457 1458 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1459 } 1460 1461 static int hclge_configure(struct hclge_dev *hdev) 1462 { 1463 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1464 struct hclge_cfg cfg; 1465 int ret; 1466 1467 ret = hclge_get_cfg(hdev, &cfg); 1468 if (ret) 1469 return ret; 1470 1471 hdev->base_tqp_pid = 0; 1472 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1473 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1474 hdev->rx_buf_len = cfg.rx_buf_len; 1475 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1476 hdev->hw.mac.media_type = cfg.media_type; 1477 hdev->hw.mac.phy_addr = cfg.phy_addr; 1478 hdev->num_tx_desc = cfg.tqp_desc_num; 1479 hdev->num_rx_desc = cfg.tqp_desc_num; 1480 hdev->tm_info.num_pg = 1; 1481 hdev->tc_max = cfg.tc_num; 1482 hdev->tm_info.hw_pfc_map = 0; 1483 if (cfg.umv_space) 1484 hdev->wanted_umv_size = cfg.umv_space; 1485 else 1486 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1487 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1488 hdev->gro_en = true; 1489 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1490 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1491 1492 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1493 hdev->fd_en = true; 1494 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1495 } 1496 1497 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1498 if (ret) { 1499 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1500 cfg.default_speed, ret); 1501 return ret; 1502 } 1503 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1504 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1505 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1506 1507 hclge_parse_link_mode(hdev, cfg.speed_ability); 1508 1509 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1510 1511 hclge_init_tc_config(hdev); 1512 hclge_init_kdump_kernel_config(hdev); 1513 1514 return ret; 1515 } 1516 1517 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1518 u16 tso_mss_max) 1519 { 1520 struct hclge_cfg_tso_status_cmd *req; 1521 struct hclge_desc desc; 1522 1523 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1524 1525 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1526 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1527 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1528 1529 return hclge_cmd_send(&hdev->hw, &desc, 1); 1530 } 1531 1532 static int hclge_config_gro(struct hclge_dev *hdev) 1533 { 1534 struct hclge_cfg_gro_status_cmd *req; 1535 struct hclge_desc desc; 1536 int ret; 1537 1538 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1539 return 0; 1540 1541 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1542 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1543 1544 req->gro_en = hdev->gro_en ? 1 : 0; 1545 1546 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1547 if (ret) 1548 dev_err(&hdev->pdev->dev, 1549 "GRO hardware config cmd failed, ret = %d\n", ret); 1550 1551 return ret; 1552 } 1553 1554 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1555 { 1556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1557 struct hclge_comm_tqp *tqp; 1558 int i; 1559 1560 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1561 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1562 if (!hdev->htqp) 1563 return -ENOMEM; 1564 1565 tqp = hdev->htqp; 1566 1567 for (i = 0; i < hdev->num_tqps; i++) { 1568 tqp->dev = &hdev->pdev->dev; 1569 tqp->index = i; 1570 1571 tqp->q.ae_algo = &ae_algo; 1572 tqp->q.buf_size = hdev->rx_buf_len; 1573 tqp->q.tx_desc_num = hdev->num_tx_desc; 1574 tqp->q.rx_desc_num = hdev->num_rx_desc; 1575 1576 /* need an extended offset to configure queues >= 1577 * HCLGE_TQP_MAX_SIZE_DEV_V2 1578 */ 1579 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1580 tqp->q.io_base = hdev->hw.hw.io_base + 1581 HCLGE_TQP_REG_OFFSET + 1582 i * HCLGE_TQP_REG_SIZE; 1583 else 1584 tqp->q.io_base = hdev->hw.hw.io_base + 1585 HCLGE_TQP_REG_OFFSET + 1586 HCLGE_TQP_EXT_REG_OFFSET + 1587 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1588 HCLGE_TQP_REG_SIZE; 1589 1590 /* when device supports tx push and has device memory, 1591 * the queue can execute push mode or doorbell mode on 1592 * device memory. 1593 */ 1594 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1595 tqp->q.mem_base = hdev->hw.hw.mem_base + 1596 HCLGE_TQP_MEM_OFFSET(hdev, i); 1597 1598 tqp++; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1605 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1606 { 1607 struct hclge_tqp_map_cmd *req; 1608 struct hclge_desc desc; 1609 int ret; 1610 1611 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1612 1613 req = (struct hclge_tqp_map_cmd *)desc.data; 1614 req->tqp_id = cpu_to_le16(tqp_pid); 1615 req->tqp_vf = func_id; 1616 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1617 if (!is_pf) 1618 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1619 req->tqp_vid = cpu_to_le16(tqp_vid); 1620 1621 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1622 if (ret) 1623 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1624 1625 return ret; 1626 } 1627 1628 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1629 { 1630 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1631 struct hclge_dev *hdev = vport->back; 1632 int i, alloced; 1633 1634 for (i = 0, alloced = 0; i < hdev->num_tqps && 1635 alloced < num_tqps; i++) { 1636 if (!hdev->htqp[i].alloced) { 1637 hdev->htqp[i].q.handle = &vport->nic; 1638 hdev->htqp[i].q.tqp_index = alloced; 1639 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1640 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1641 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1642 hdev->htqp[i].alloced = true; 1643 alloced++; 1644 } 1645 } 1646 vport->alloc_tqps = alloced; 1647 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1648 vport->alloc_tqps / hdev->tm_info.num_tc); 1649 1650 /* ensure one to one mapping between irq and queue at default */ 1651 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1652 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1653 1654 return 0; 1655 } 1656 1657 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1658 u16 num_tx_desc, u16 num_rx_desc) 1659 1660 { 1661 struct hnae3_handle *nic = &vport->nic; 1662 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1663 struct hclge_dev *hdev = vport->back; 1664 int ret; 1665 1666 kinfo->num_tx_desc = num_tx_desc; 1667 kinfo->num_rx_desc = num_rx_desc; 1668 1669 kinfo->rx_buf_len = hdev->rx_buf_len; 1670 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1671 1672 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1673 sizeof(struct hnae3_queue *), GFP_KERNEL); 1674 if (!kinfo->tqp) 1675 return -ENOMEM; 1676 1677 ret = hclge_assign_tqp(vport, num_tqps); 1678 if (ret) 1679 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1680 1681 return ret; 1682 } 1683 1684 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1685 struct hclge_vport *vport) 1686 { 1687 struct hnae3_handle *nic = &vport->nic; 1688 struct hnae3_knic_private_info *kinfo; 1689 u16 i; 1690 1691 kinfo = &nic->kinfo; 1692 for (i = 0; i < vport->alloc_tqps; i++) { 1693 struct hclge_comm_tqp *q = 1694 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1695 bool is_pf; 1696 int ret; 1697 1698 is_pf = !(vport->vport_id); 1699 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1700 i, is_pf); 1701 if (ret) 1702 return ret; 1703 } 1704 1705 return 0; 1706 } 1707 1708 static int hclge_map_tqp(struct hclge_dev *hdev) 1709 { 1710 struct hclge_vport *vport = hdev->vport; 1711 u16 i, num_vport; 1712 1713 num_vport = hdev->num_req_vfs + 1; 1714 for (i = 0; i < num_vport; i++) { 1715 int ret; 1716 1717 ret = hclge_map_tqp_to_vport(hdev, vport); 1718 if (ret) 1719 return ret; 1720 1721 vport++; 1722 } 1723 1724 return 0; 1725 } 1726 1727 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1728 { 1729 struct hnae3_handle *nic = &vport->nic; 1730 struct hclge_dev *hdev = vport->back; 1731 int ret; 1732 1733 nic->pdev = hdev->pdev; 1734 nic->ae_algo = &ae_algo; 1735 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1736 MAX_NUMNODES); 1737 nic->kinfo.io_base = hdev->hw.hw.io_base; 1738 1739 ret = hclge_knic_setup(vport, num_tqps, 1740 hdev->num_tx_desc, hdev->num_rx_desc); 1741 if (ret) 1742 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1743 1744 return ret; 1745 } 1746 1747 static int hclge_alloc_vport(struct hclge_dev *hdev) 1748 { 1749 struct pci_dev *pdev = hdev->pdev; 1750 struct hclge_vport *vport; 1751 u32 tqp_main_vport; 1752 u32 tqp_per_vport; 1753 int num_vport, i; 1754 int ret; 1755 1756 /* We need to alloc a vport for main NIC of PF */ 1757 num_vport = hdev->num_req_vfs + 1; 1758 1759 if (hdev->num_tqps < num_vport) { 1760 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1761 hdev->num_tqps, num_vport); 1762 return -EINVAL; 1763 } 1764 1765 /* Alloc the same number of TQPs for every vport */ 1766 tqp_per_vport = hdev->num_tqps / num_vport; 1767 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1768 1769 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1770 GFP_KERNEL); 1771 if (!vport) 1772 return -ENOMEM; 1773 1774 hdev->vport = vport; 1775 hdev->num_alloc_vport = num_vport; 1776 1777 if (IS_ENABLED(CONFIG_PCI_IOV)) 1778 hdev->num_alloc_vfs = hdev->num_req_vfs; 1779 1780 for (i = 0; i < num_vport; i++) { 1781 vport->back = hdev; 1782 vport->vport_id = i; 1783 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1784 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1785 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1786 vport->port_base_vlan_cfg.tbl_sta = true; 1787 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1788 vport->req_vlan_fltr_en = true; 1789 INIT_LIST_HEAD(&vport->vlan_list); 1790 INIT_LIST_HEAD(&vport->uc_mac_list); 1791 INIT_LIST_HEAD(&vport->mc_mac_list); 1792 spin_lock_init(&vport->mac_list_lock); 1793 1794 if (i == 0) 1795 ret = hclge_vport_setup(vport, tqp_main_vport); 1796 else 1797 ret = hclge_vport_setup(vport, tqp_per_vport); 1798 if (ret) { 1799 dev_err(&pdev->dev, 1800 "vport setup failed for vport %d, %d\n", 1801 i, ret); 1802 return ret; 1803 } 1804 1805 vport++; 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1812 struct hclge_pkt_buf_alloc *buf_alloc) 1813 { 1814 /* TX buffer size is unit by 128 byte */ 1815 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1816 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1817 struct hclge_tx_buff_alloc_cmd *req; 1818 struct hclge_desc desc; 1819 int ret; 1820 u8 i; 1821 1822 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1823 1824 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1825 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1826 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1827 1828 req->tx_pkt_buff[i] = 1829 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1830 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1831 } 1832 1833 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1834 if (ret) 1835 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1836 ret); 1837 1838 return ret; 1839 } 1840 1841 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1842 struct hclge_pkt_buf_alloc *buf_alloc) 1843 { 1844 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1845 1846 if (ret) 1847 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1848 1849 return ret; 1850 } 1851 1852 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1853 { 1854 unsigned int i; 1855 u32 cnt = 0; 1856 1857 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1858 if (hdev->hw_tc_map & BIT(i)) 1859 cnt++; 1860 return cnt; 1861 } 1862 1863 /* Get the number of pfc enabled TCs, which have private buffer */ 1864 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1865 struct hclge_pkt_buf_alloc *buf_alloc) 1866 { 1867 struct hclge_priv_buf *priv; 1868 unsigned int i; 1869 int cnt = 0; 1870 1871 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1872 priv = &buf_alloc->priv_buf[i]; 1873 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1874 priv->enable) 1875 cnt++; 1876 } 1877 1878 return cnt; 1879 } 1880 1881 /* Get the number of pfc disabled TCs, which have private buffer */ 1882 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1883 struct hclge_pkt_buf_alloc *buf_alloc) 1884 { 1885 struct hclge_priv_buf *priv; 1886 unsigned int i; 1887 int cnt = 0; 1888 1889 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1890 priv = &buf_alloc->priv_buf[i]; 1891 if (hdev->hw_tc_map & BIT(i) && 1892 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1893 priv->enable) 1894 cnt++; 1895 } 1896 1897 return cnt; 1898 } 1899 1900 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1901 { 1902 struct hclge_priv_buf *priv; 1903 u32 rx_priv = 0; 1904 int i; 1905 1906 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1907 priv = &buf_alloc->priv_buf[i]; 1908 if (priv->enable) 1909 rx_priv += priv->buf_size; 1910 } 1911 return rx_priv; 1912 } 1913 1914 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1915 { 1916 u32 i, total_tx_size = 0; 1917 1918 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1919 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1920 1921 return total_tx_size; 1922 } 1923 1924 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1925 struct hclge_pkt_buf_alloc *buf_alloc, 1926 u32 rx_all) 1927 { 1928 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1929 u32 tc_num = hclge_get_tc_num(hdev); 1930 u32 shared_buf, aligned_mps; 1931 u32 rx_priv; 1932 int i; 1933 1934 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1935 1936 if (hnae3_dev_dcb_supported(hdev)) 1937 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1938 hdev->dv_buf_size; 1939 else 1940 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1941 + hdev->dv_buf_size; 1942 1943 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1944 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1945 HCLGE_BUF_SIZE_UNIT); 1946 1947 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1948 if (rx_all < rx_priv + shared_std) 1949 return false; 1950 1951 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1952 buf_alloc->s_buf.buf_size = shared_buf; 1953 if (hnae3_dev_dcb_supported(hdev)) { 1954 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1955 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1956 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1957 HCLGE_BUF_SIZE_UNIT); 1958 } else { 1959 buf_alloc->s_buf.self.high = aligned_mps + 1960 HCLGE_NON_DCB_ADDITIONAL_BUF; 1961 buf_alloc->s_buf.self.low = aligned_mps; 1962 } 1963 1964 if (hnae3_dev_dcb_supported(hdev)) { 1965 hi_thrd = shared_buf - hdev->dv_buf_size; 1966 1967 if (tc_num <= NEED_RESERVE_TC_NUM) 1968 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1969 / BUF_MAX_PERCENT; 1970 1971 if (tc_num) 1972 hi_thrd = hi_thrd / tc_num; 1973 1974 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 1975 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 1976 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 1977 } else { 1978 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 1979 lo_thrd = aligned_mps; 1980 } 1981 1982 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1983 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 1984 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 1985 } 1986 1987 return true; 1988 } 1989 1990 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1991 struct hclge_pkt_buf_alloc *buf_alloc) 1992 { 1993 u32 i, total_size; 1994 1995 total_size = hdev->pkt_buf_size; 1996 1997 /* alloc tx buffer for all enabled tc */ 1998 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1999 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2000 2001 if (hdev->hw_tc_map & BIT(i)) { 2002 if (total_size < hdev->tx_buf_size) 2003 return -ENOMEM; 2004 2005 priv->tx_buf_size = hdev->tx_buf_size; 2006 } else { 2007 priv->tx_buf_size = 0; 2008 } 2009 2010 total_size -= priv->tx_buf_size; 2011 } 2012 2013 return 0; 2014 } 2015 2016 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2017 struct hclge_pkt_buf_alloc *buf_alloc) 2018 { 2019 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2020 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2021 unsigned int i; 2022 2023 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2024 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2025 2026 priv->enable = 0; 2027 priv->wl.low = 0; 2028 priv->wl.high = 0; 2029 priv->buf_size = 0; 2030 2031 if (!(hdev->hw_tc_map & BIT(i))) 2032 continue; 2033 2034 priv->enable = 1; 2035 2036 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2037 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2038 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2039 HCLGE_BUF_SIZE_UNIT); 2040 } else { 2041 priv->wl.low = 0; 2042 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2043 aligned_mps; 2044 } 2045 2046 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2047 } 2048 2049 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2050 } 2051 2052 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2053 struct hclge_pkt_buf_alloc *buf_alloc) 2054 { 2055 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2056 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2057 int i; 2058 2059 /* let the last to be cleared first */ 2060 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2061 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2062 unsigned int mask = BIT((unsigned int)i); 2063 2064 if (hdev->hw_tc_map & mask && 2065 !(hdev->tm_info.hw_pfc_map & mask)) { 2066 /* Clear the no pfc TC private buffer */ 2067 priv->wl.low = 0; 2068 priv->wl.high = 0; 2069 priv->buf_size = 0; 2070 priv->enable = 0; 2071 no_pfc_priv_num--; 2072 } 2073 2074 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2075 no_pfc_priv_num == 0) 2076 break; 2077 } 2078 2079 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2080 } 2081 2082 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2083 struct hclge_pkt_buf_alloc *buf_alloc) 2084 { 2085 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2086 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2087 int i; 2088 2089 /* let the last to be cleared first */ 2090 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2091 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2092 unsigned int mask = BIT((unsigned int)i); 2093 2094 if (hdev->hw_tc_map & mask && 2095 hdev->tm_info.hw_pfc_map & mask) { 2096 /* Reduce the number of pfc TC with private buffer */ 2097 priv->wl.low = 0; 2098 priv->enable = 0; 2099 priv->wl.high = 0; 2100 priv->buf_size = 0; 2101 pfc_priv_num--; 2102 } 2103 2104 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2105 pfc_priv_num == 0) 2106 break; 2107 } 2108 2109 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2110 } 2111 2112 static bool hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2113 struct hclge_pkt_buf_alloc *buf_alloc) 2114 { 2115 #define COMPENSATE_BUFFER 0x3C00 2116 #define COMPENSATE_HALF_MPS_NUM 5 2117 #define PRIV_WL_GAP 0x1800 2118 2119 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2120 u32 tc_num = hclge_get_tc_num(hdev); 2121 u32 half_mps = hdev->mps >> 1; 2122 u32 min_rx_priv; 2123 unsigned int i; 2124 2125 if (tc_num) 2126 rx_priv = rx_priv / tc_num; 2127 2128 if (tc_num <= NEED_RESERVE_TC_NUM) 2129 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2130 2131 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2132 COMPENSATE_HALF_MPS_NUM * half_mps; 2133 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2134 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2135 if (rx_priv < min_rx_priv) 2136 return false; 2137 2138 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2139 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2140 2141 priv->enable = 0; 2142 priv->wl.low = 0; 2143 priv->wl.high = 0; 2144 priv->buf_size = 0; 2145 2146 if (!(hdev->hw_tc_map & BIT(i))) 2147 continue; 2148 2149 priv->enable = 1; 2150 priv->buf_size = rx_priv; 2151 priv->wl.high = rx_priv - hdev->dv_buf_size; 2152 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2153 } 2154 2155 buf_alloc->s_buf.buf_size = 0; 2156 2157 return true; 2158 } 2159 2160 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2161 * @hdev: pointer to struct hclge_dev 2162 * @buf_alloc: pointer to buffer calculation data 2163 * @return: 0: calculate successful, negative: fail 2164 */ 2165 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2166 struct hclge_pkt_buf_alloc *buf_alloc) 2167 { 2168 /* When DCB is not supported, rx private buffer is not allocated. */ 2169 if (!hnae3_dev_dcb_supported(hdev)) { 2170 u32 rx_all = hdev->pkt_buf_size; 2171 2172 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2173 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2174 return -ENOMEM; 2175 2176 return 0; 2177 } 2178 2179 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2180 return 0; 2181 2182 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2183 return 0; 2184 2185 /* try to decrease the buffer size */ 2186 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2187 return 0; 2188 2189 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2190 return 0; 2191 2192 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2193 return 0; 2194 2195 return -ENOMEM; 2196 } 2197 2198 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2199 struct hclge_pkt_buf_alloc *buf_alloc) 2200 { 2201 struct hclge_rx_priv_buff_cmd *req; 2202 struct hclge_desc desc; 2203 int ret; 2204 int i; 2205 2206 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2207 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2208 2209 /* Alloc private buffer TCs */ 2210 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2211 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2212 2213 req->buf_num[i] = 2214 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2215 req->buf_num[i] |= 2216 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2217 } 2218 2219 req->shared_buf = 2220 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2221 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2222 2223 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2224 if (ret) 2225 dev_err(&hdev->pdev->dev, 2226 "rx private buffer alloc cmd failed %d\n", ret); 2227 2228 return ret; 2229 } 2230 2231 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2232 struct hclge_pkt_buf_alloc *buf_alloc) 2233 { 2234 struct hclge_rx_priv_wl_buf *req; 2235 struct hclge_priv_buf *priv; 2236 struct hclge_desc desc[2]; 2237 int i, j; 2238 int ret; 2239 2240 for (i = 0; i < 2; i++) { 2241 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2242 false); 2243 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2244 2245 /* The first descriptor set the NEXT bit to 1 */ 2246 if (i == 0) 2247 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2248 else 2249 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2250 2251 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2252 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2253 2254 priv = &buf_alloc->priv_buf[idx]; 2255 req->tc_wl[j].high = 2256 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2257 req->tc_wl[j].high |= 2258 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2259 req->tc_wl[j].low = 2260 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2261 req->tc_wl[j].low |= 2262 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2263 } 2264 } 2265 2266 /* Send 2 descriptor at one time */ 2267 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2268 if (ret) 2269 dev_err(&hdev->pdev->dev, 2270 "rx private waterline config cmd failed %d\n", 2271 ret); 2272 return ret; 2273 } 2274 2275 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2276 struct hclge_pkt_buf_alloc *buf_alloc) 2277 { 2278 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2279 struct hclge_rx_com_thrd *req; 2280 struct hclge_desc desc[2]; 2281 struct hclge_tc_thrd *tc; 2282 int i, j; 2283 int ret; 2284 2285 for (i = 0; i < 2; i++) { 2286 hclge_cmd_setup_basic_desc(&desc[i], 2287 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2288 req = (struct hclge_rx_com_thrd *)desc[i].data; 2289 2290 /* The first descriptor set the NEXT bit to 1 */ 2291 if (i == 0) 2292 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2293 else 2294 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2295 2296 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2297 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2298 2299 req->com_thrd[j].high = 2300 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2301 req->com_thrd[j].high |= 2302 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2303 req->com_thrd[j].low = 2304 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2305 req->com_thrd[j].low |= 2306 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2307 } 2308 } 2309 2310 /* Send 2 descriptors at one time */ 2311 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2312 if (ret) 2313 dev_err(&hdev->pdev->dev, 2314 "common threshold config cmd failed %d\n", ret); 2315 return ret; 2316 } 2317 2318 static int hclge_common_wl_config(struct hclge_dev *hdev, 2319 struct hclge_pkt_buf_alloc *buf_alloc) 2320 { 2321 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2322 struct hclge_rx_com_wl *req; 2323 struct hclge_desc desc; 2324 int ret; 2325 2326 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2327 2328 req = (struct hclge_rx_com_wl *)desc.data; 2329 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2330 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2331 2332 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2333 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2334 2335 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2336 if (ret) 2337 dev_err(&hdev->pdev->dev, 2338 "common waterline config cmd failed %d\n", ret); 2339 2340 return ret; 2341 } 2342 2343 int hclge_buffer_alloc(struct hclge_dev *hdev) 2344 { 2345 struct hclge_pkt_buf_alloc *pkt_buf; 2346 int ret; 2347 2348 pkt_buf = kzalloc_obj(*pkt_buf); 2349 if (!pkt_buf) 2350 return -ENOMEM; 2351 2352 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2353 if (ret) { 2354 dev_err(&hdev->pdev->dev, 2355 "could not calc tx buffer size for all TCs %d\n", ret); 2356 goto out; 2357 } 2358 2359 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2360 if (ret) { 2361 dev_err(&hdev->pdev->dev, 2362 "could not alloc tx buffers %d\n", ret); 2363 goto out; 2364 } 2365 2366 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2367 if (ret) { 2368 dev_err(&hdev->pdev->dev, 2369 "could not calc rx priv buffer size for all TCs %d\n", 2370 ret); 2371 goto out; 2372 } 2373 2374 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2375 if (ret) { 2376 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2377 ret); 2378 goto out; 2379 } 2380 2381 if (hnae3_dev_dcb_supported(hdev)) { 2382 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2383 if (ret) { 2384 dev_err(&hdev->pdev->dev, 2385 "could not configure rx private waterline %d\n", 2386 ret); 2387 goto out; 2388 } 2389 2390 ret = hclge_common_thrd_config(hdev, pkt_buf); 2391 if (ret) { 2392 dev_err(&hdev->pdev->dev, 2393 "could not configure common threshold %d\n", 2394 ret); 2395 goto out; 2396 } 2397 } 2398 2399 ret = hclge_common_wl_config(hdev, pkt_buf); 2400 if (ret) 2401 dev_err(&hdev->pdev->dev, 2402 "could not configure common waterline %d\n", ret); 2403 2404 out: 2405 kfree(pkt_buf); 2406 return ret; 2407 } 2408 2409 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2410 { 2411 struct hnae3_handle *roce = &vport->roce; 2412 struct hnae3_handle *nic = &vport->nic; 2413 struct hclge_dev *hdev = vport->back; 2414 2415 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2416 2417 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2418 return -EINVAL; 2419 2420 roce->rinfo.base_vector = hdev->num_nic_msi; 2421 2422 roce->rinfo.netdev = nic->kinfo.netdev; 2423 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2424 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2425 2426 roce->pdev = nic->pdev; 2427 roce->ae_algo = nic->ae_algo; 2428 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2429 MAX_NUMNODES); 2430 2431 return 0; 2432 } 2433 2434 static int hclge_init_msi(struct hclge_dev *hdev) 2435 { 2436 struct pci_dev *pdev = hdev->pdev; 2437 int vectors; 2438 int i; 2439 2440 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2441 hdev->num_msi, 2442 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2443 if (vectors < 0) { 2444 dev_err(&pdev->dev, 2445 "failed(%d) to allocate MSI/MSI-X vectors\n", 2446 vectors); 2447 return vectors; 2448 } 2449 if (vectors < hdev->num_msi) 2450 dev_warn(&hdev->pdev->dev, 2451 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2452 hdev->num_msi, vectors); 2453 2454 hdev->num_msi = vectors; 2455 hdev->num_msi_left = vectors; 2456 2457 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2458 sizeof(u16), GFP_KERNEL); 2459 if (!hdev->vector_status) { 2460 pci_free_irq_vectors(pdev); 2461 return -ENOMEM; 2462 } 2463 2464 for (i = 0; i < hdev->num_msi; i++) 2465 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2466 2467 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2468 sizeof(int), GFP_KERNEL); 2469 if (!hdev->vector_irq) { 2470 pci_free_irq_vectors(pdev); 2471 return -ENOMEM; 2472 } 2473 2474 return 0; 2475 } 2476 2477 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2478 { 2479 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2480 duplex = HCLGE_MAC_FULL; 2481 2482 return duplex; 2483 } 2484 2485 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2486 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2487 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2488 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2489 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2490 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2491 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2492 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2493 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2494 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2495 }; 2496 2497 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2498 { 2499 u16 i; 2500 2501 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2502 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2503 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2504 return 0; 2505 } 2506 } 2507 2508 return -EINVAL; 2509 } 2510 2511 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2512 u8 duplex, u8 lane_num) 2513 { 2514 struct hclge_config_mac_speed_dup_cmd *req; 2515 struct hclge_desc desc; 2516 u32 speed_fw; 2517 int ret; 2518 2519 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2520 2521 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2522 2523 if (duplex) 2524 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2525 2526 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2527 if (ret) { 2528 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2529 return ret; 2530 } 2531 2532 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2533 speed_fw); 2534 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2535 1); 2536 req->lane_num = lane_num; 2537 2538 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2539 if (ret) { 2540 dev_err(&hdev->pdev->dev, 2541 "mac speed/duplex config cmd failed %d.\n", ret); 2542 return ret; 2543 } 2544 2545 return 0; 2546 } 2547 2548 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2549 { 2550 struct hclge_mac *mac = &hdev->hw.mac; 2551 int ret; 2552 2553 duplex = hclge_check_speed_dup(duplex, speed); 2554 if (!mac->support_autoneg && mac->speed == (u32)speed && 2555 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2556 return 0; 2557 2558 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2559 if (ret) 2560 return ret; 2561 2562 hdev->hw.mac.speed = speed; 2563 hdev->hw.mac.duplex = duplex; 2564 if (!lane_num) 2565 hdev->hw.mac.lane_num = lane_num; 2566 2567 return 0; 2568 } 2569 2570 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2571 u8 duplex, u8 lane_num) 2572 { 2573 struct hclge_vport *vport = hclge_get_vport(handle); 2574 struct hclge_dev *hdev = vport->back; 2575 int ret; 2576 2577 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2578 2579 if (ret) 2580 return ret; 2581 2582 hdev->hw.mac.req_speed = (u32)speed; 2583 hdev->hw.mac.req_duplex = duplex; 2584 2585 return 0; 2586 } 2587 2588 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2589 { 2590 struct hclge_config_auto_neg_cmd *req; 2591 struct hclge_desc desc; 2592 u32 flag = 0; 2593 int ret; 2594 2595 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2596 2597 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2598 if (enable) 2599 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2600 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2601 2602 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2603 if (ret) 2604 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2605 ret); 2606 2607 return ret; 2608 } 2609 2610 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2611 { 2612 struct hclge_vport *vport = hclge_get_vport(handle); 2613 struct hclge_dev *hdev = vport->back; 2614 2615 if (!hdev->hw.mac.support_autoneg) { 2616 if (enable) { 2617 dev_err(&hdev->pdev->dev, 2618 "autoneg is not supported by current port\n"); 2619 return -EOPNOTSUPP; 2620 } else { 2621 return 0; 2622 } 2623 } 2624 2625 return hclge_set_autoneg_en(hdev, enable); 2626 } 2627 2628 static int hclge_get_autoneg(struct hnae3_handle *handle) 2629 { 2630 struct hclge_vport *vport = hclge_get_vport(handle); 2631 struct hclge_dev *hdev = vport->back; 2632 struct phy_device *phydev = hdev->hw.mac.phydev; 2633 2634 if (phydev) 2635 return phydev->autoneg; 2636 2637 return hdev->hw.mac.autoneg; 2638 } 2639 2640 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2641 { 2642 struct hclge_vport *vport = hclge_get_vport(handle); 2643 struct hclge_dev *hdev = vport->back; 2644 int ret; 2645 2646 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2647 2648 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2649 if (ret) 2650 return ret; 2651 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2652 } 2653 2654 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2655 { 2656 struct hclge_vport *vport = hclge_get_vport(handle); 2657 struct hclge_dev *hdev = vport->back; 2658 2659 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2660 return hclge_set_autoneg_en(hdev, !halt); 2661 2662 return 0; 2663 } 2664 2665 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2666 struct hclge_desc *desc, u32 desc_len) 2667 { 2668 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2669 u32 desc_index = 0; 2670 u32 data_index = 0; 2671 u32 i; 2672 2673 for (i = 0; i < lane_size; i++) { 2674 if (data_index >= HCLGE_DESC_DATA_LEN) { 2675 desc_index++; 2676 data_index = 0; 2677 } 2678 2679 if (desc_index >= desc_len) 2680 return; 2681 2682 hdev->fec_stats.per_lanes[i] += 2683 le32_to_cpu(desc[desc_index].data[data_index]); 2684 data_index++; 2685 } 2686 } 2687 2688 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2689 struct hclge_desc *desc, u32 desc_len) 2690 { 2691 struct hclge_query_fec_stats_cmd *req; 2692 2693 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2694 2695 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2696 hdev->fec_stats.rs_corr_blocks += 2697 le32_to_cpu(req->rs_fec_corr_blocks); 2698 hdev->fec_stats.rs_uncorr_blocks += 2699 le32_to_cpu(req->rs_fec_uncorr_blocks); 2700 hdev->fec_stats.rs_error_blocks += 2701 le32_to_cpu(req->rs_fec_error_blocks); 2702 hdev->fec_stats.base_r_corr_blocks += 2703 le32_to_cpu(req->base_r_fec_corr_blocks); 2704 hdev->fec_stats.base_r_uncorr_blocks += 2705 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2706 2707 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2708 } 2709 2710 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2711 { 2712 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2713 int ret; 2714 u32 i; 2715 2716 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2717 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2718 true); 2719 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2720 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2721 } 2722 2723 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2724 if (ret) 2725 return ret; 2726 2727 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2728 2729 return 0; 2730 } 2731 2732 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2733 { 2734 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2735 int ret; 2736 2737 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2738 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2739 return; 2740 2741 ret = hclge_update_fec_stats_hw(hdev); 2742 if (ret) 2743 dev_err(&hdev->pdev->dev, 2744 "failed to update fec stats, ret = %d\n", ret); 2745 2746 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2747 } 2748 2749 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2750 struct ethtool_fec_stats *fec_stats) 2751 { 2752 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2753 fec_stats->uncorrectable_blocks.total = 2754 hdev->fec_stats.rs_uncorr_blocks; 2755 } 2756 2757 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2758 struct ethtool_fec_stats *fec_stats) 2759 { 2760 u32 i; 2761 2762 if (hdev->fec_stats.base_r_lane_num == 0 || 2763 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2764 dev_err(&hdev->pdev->dev, 2765 "fec stats lane number(%llu) is invalid\n", 2766 hdev->fec_stats.base_r_lane_num); 2767 return; 2768 } 2769 2770 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2771 fec_stats->corrected_blocks.lanes[i] = 2772 hdev->fec_stats.base_r_corr_per_lanes[i]; 2773 fec_stats->uncorrectable_blocks.lanes[i] = 2774 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2775 } 2776 } 2777 2778 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2779 struct ethtool_fec_stats *fec_stats) 2780 { 2781 u32 fec_mode = hdev->hw.mac.fec_mode; 2782 2783 switch (fec_mode) { 2784 case BIT(HNAE3_FEC_RS): 2785 case BIT(HNAE3_FEC_LLRS): 2786 hclge_get_fec_stats_total(hdev, fec_stats); 2787 break; 2788 case BIT(HNAE3_FEC_BASER): 2789 hclge_get_fec_stats_lanes(hdev, fec_stats); 2790 break; 2791 default: 2792 dev_err(&hdev->pdev->dev, 2793 "fec stats is not supported by current fec mode(0x%x)\n", 2794 fec_mode); 2795 break; 2796 } 2797 } 2798 2799 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2800 struct ethtool_fec_stats *fec_stats) 2801 { 2802 struct hclge_vport *vport = hclge_get_vport(handle); 2803 struct hclge_dev *hdev = vport->back; 2804 u32 fec_mode = hdev->hw.mac.fec_mode; 2805 2806 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2807 fec_mode == BIT(HNAE3_FEC_AUTO) || 2808 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2809 return; 2810 2811 hclge_update_fec_stats(hdev); 2812 2813 hclge_comm_get_fec_stats(hdev, fec_stats); 2814 } 2815 2816 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2817 { 2818 struct hclge_config_fec_cmd *req; 2819 struct hclge_desc desc; 2820 int ret; 2821 2822 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2823 2824 req = (struct hclge_config_fec_cmd *)desc.data; 2825 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2826 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2827 if (fec_mode & BIT(HNAE3_FEC_RS)) 2828 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2829 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2830 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2831 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2832 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2833 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2834 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2835 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2836 2837 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2838 if (ret) 2839 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2840 2841 return ret; 2842 } 2843 2844 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2845 { 2846 struct hclge_vport *vport = hclge_get_vport(handle); 2847 struct hclge_dev *hdev = vport->back; 2848 struct hclge_mac *mac = &hdev->hw.mac; 2849 int ret; 2850 2851 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2852 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2853 return -EINVAL; 2854 } 2855 2856 ret = hclge_set_fec_hw(hdev, fec_mode); 2857 if (ret) 2858 return ret; 2859 2860 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2861 return 0; 2862 } 2863 2864 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2865 u8 *fec_mode) 2866 { 2867 struct hclge_vport *vport = hclge_get_vport(handle); 2868 struct hclge_dev *hdev = vport->back; 2869 struct hclge_mac *mac = &hdev->hw.mac; 2870 2871 if (fec_ability) 2872 *fec_ability = mac->fec_ability; 2873 if (fec_mode) 2874 *fec_mode = mac->fec_mode; 2875 } 2876 2877 static int hclge_mac_init(struct hclge_dev *hdev) 2878 { 2879 struct hclge_mac *mac = &hdev->hw.mac; 2880 int ret; 2881 2882 hdev->support_sfp_query = true; 2883 2884 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2885 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2886 2887 if (hdev->hw.mac.support_autoneg) { 2888 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2889 if (ret) 2890 return ret; 2891 } 2892 2893 if (!hdev->hw.mac.autoneg) { 2894 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 2895 hdev->hw.mac.req_duplex, 2896 hdev->hw.mac.lane_num); 2897 if (ret) 2898 return ret; 2899 } 2900 2901 mac->link = 0; 2902 2903 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2904 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2905 if (ret) 2906 return ret; 2907 } 2908 2909 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2910 if (ret) { 2911 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2912 return ret; 2913 } 2914 2915 ret = hclge_set_default_loopback(hdev); 2916 if (ret) 2917 return ret; 2918 2919 ret = hclge_buffer_alloc(hdev); 2920 if (ret) 2921 dev_err(&hdev->pdev->dev, 2922 "allocate buffer fail, ret=%d\n", ret); 2923 2924 return ret; 2925 } 2926 2927 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2928 { 2929 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2930 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2931 hdev->last_mbx_scheduled = jiffies; 2932 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2933 } 2934 } 2935 2936 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2937 { 2938 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2939 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2940 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2941 hdev->last_rst_scheduled = jiffies; 2942 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2943 } 2944 } 2945 2946 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2947 { 2948 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2949 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2950 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2951 } 2952 2953 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2954 { 2955 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2956 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2957 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2958 } 2959 2960 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2961 { 2962 struct hclge_link_status_cmd *req; 2963 struct hclge_desc desc; 2964 int ret; 2965 2966 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2967 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2968 if (ret) { 2969 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2970 ret); 2971 return ret; 2972 } 2973 2974 req = (struct hclge_link_status_cmd *)desc.data; 2975 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2976 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2977 2978 return 0; 2979 } 2980 2981 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2982 { 2983 struct phy_device *phydev = hdev->hw.mac.phydev; 2984 2985 *link_status = HCLGE_LINK_STATUS_DOWN; 2986 2987 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2988 return 0; 2989 2990 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 2991 return 0; 2992 2993 return hclge_get_mac_link_status(hdev, link_status); 2994 } 2995 2996 static void hclge_push_link_status(struct hclge_dev *hdev) 2997 { 2998 struct hclge_vport *vport; 2999 int ret; 3000 u16 i; 3001 3002 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3003 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3004 3005 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3006 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3007 continue; 3008 3009 ret = hclge_push_vf_link_status(vport); 3010 if (ret) { 3011 dev_err(&hdev->pdev->dev, 3012 "failed to push link status to vf%u, ret = %d\n", 3013 i, ret); 3014 } 3015 } 3016 } 3017 3018 static void hclge_update_link_status(struct hclge_dev *hdev) 3019 { 3020 struct hnae3_handle *handle = &hdev->vport[0].nic; 3021 struct hnae3_client *client = hdev->nic_client; 3022 int state; 3023 int ret; 3024 3025 if (!client) 3026 return; 3027 3028 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3029 return; 3030 3031 ret = hclge_get_mac_phy_link(hdev, &state); 3032 if (ret) { 3033 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3034 return; 3035 } 3036 3037 if (state != hdev->hw.mac.link) { 3038 hdev->hw.mac.link = state; 3039 if (state == HCLGE_LINK_STATUS_UP) 3040 hclge_update_port_info(hdev); 3041 3042 client->ops->link_status_change(handle, state); 3043 hclge_config_mac_tnl_int(hdev, state); 3044 3045 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3046 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3047 struct hnae3_client *rclient = hdev->roce_client; 3048 3049 if (rclient && rclient->ops->link_status_change) 3050 rclient->ops->link_status_change(rhandle, 3051 state); 3052 } 3053 3054 hclge_push_link_status(hdev); 3055 } 3056 3057 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3058 } 3059 3060 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3061 { 3062 u32 speed_ability; 3063 3064 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3065 return; 3066 3067 switch (mac->module_type) { 3068 case HNAE3_MODULE_TYPE_FIBRE_LR: 3069 hclge_convert_setting_lr(speed_ability, mac->advertising); 3070 break; 3071 case HNAE3_MODULE_TYPE_FIBRE_SR: 3072 case HNAE3_MODULE_TYPE_AOC: 3073 hclge_convert_setting_sr(speed_ability, mac->advertising); 3074 break; 3075 case HNAE3_MODULE_TYPE_CR: 3076 hclge_convert_setting_cr(speed_ability, mac->advertising); 3077 break; 3078 case HNAE3_MODULE_TYPE_KR: 3079 hclge_convert_setting_kr(speed_ability, mac->advertising); 3080 break; 3081 default: 3082 break; 3083 } 3084 } 3085 3086 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3087 { 3088 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3089 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3090 mac->advertising); 3091 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3092 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3093 mac->advertising); 3094 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3095 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3096 mac->advertising); 3097 else 3098 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3099 mac->advertising); 3100 } 3101 3102 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3103 { 3104 struct hclge_mac *mac = &hdev->hw.mac; 3105 bool rx_en, tx_en; 3106 3107 switch (hdev->fc_mode_last_time) { 3108 case HCLGE_FC_RX_PAUSE: 3109 rx_en = true; 3110 tx_en = false; 3111 break; 3112 case HCLGE_FC_TX_PAUSE: 3113 rx_en = false; 3114 tx_en = true; 3115 break; 3116 case HCLGE_FC_FULL: 3117 rx_en = true; 3118 tx_en = true; 3119 break; 3120 default: 3121 rx_en = false; 3122 tx_en = false; 3123 break; 3124 } 3125 3126 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3127 } 3128 3129 static void hclge_update_advertising(struct hclge_dev *hdev) 3130 { 3131 struct hclge_mac *mac = &hdev->hw.mac; 3132 3133 linkmode_zero(mac->advertising); 3134 hclge_update_speed_advertising(mac); 3135 hclge_update_fec_advertising(mac); 3136 hclge_update_pause_advertising(hdev); 3137 } 3138 3139 static void hclge_update_port_capability(struct hclge_dev *hdev, 3140 struct hclge_mac *mac) 3141 { 3142 if (hnae3_dev_fec_supported(hdev)) 3143 hclge_convert_setting_fec(mac); 3144 3145 /* firmware can not identify back plane type, the media type 3146 * read from configuration can help deal it 3147 */ 3148 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3149 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3150 mac->module_type = HNAE3_MODULE_TYPE_KR; 3151 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3152 mac->module_type = HNAE3_MODULE_TYPE_TP; 3153 3154 if (mac->support_autoneg) { 3155 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3156 linkmode_copy(mac->advertising, mac->supported); 3157 } else { 3158 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3159 mac->supported); 3160 hclge_update_advertising(hdev); 3161 } 3162 } 3163 3164 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3165 { 3166 struct hclge_sfp_info_cmd *resp; 3167 struct hclge_desc desc; 3168 int ret; 3169 3170 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3171 resp = (struct hclge_sfp_info_cmd *)desc.data; 3172 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3173 if (ret == -EOPNOTSUPP) { 3174 dev_warn(&hdev->pdev->dev, 3175 "IMP do not support get SFP speed %d\n", ret); 3176 return ret; 3177 } else if (ret) { 3178 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3179 return ret; 3180 } 3181 3182 *speed = le32_to_cpu(resp->speed); 3183 3184 return 0; 3185 } 3186 3187 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3188 { 3189 struct hclge_sfp_info_cmd *resp; 3190 struct hclge_desc desc; 3191 int ret; 3192 3193 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3194 resp = (struct hclge_sfp_info_cmd *)desc.data; 3195 3196 resp->query_type = QUERY_ACTIVE_SPEED; 3197 3198 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3199 if (ret == -EOPNOTSUPP) { 3200 dev_warn(&hdev->pdev->dev, 3201 "IMP does not support get SFP info %d\n", ret); 3202 return ret; 3203 } else if (ret) { 3204 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3205 return ret; 3206 } 3207 3208 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3209 * set to mac->speed. 3210 */ 3211 if (!le32_to_cpu(resp->speed)) 3212 return 0; 3213 3214 mac->speed = le32_to_cpu(resp->speed); 3215 /* if resp->speed_ability is 0, it means it's an old version 3216 * firmware, do not update these params 3217 */ 3218 if (resp->speed_ability) { 3219 mac->module_type = le32_to_cpu(resp->module_type); 3220 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3221 mac->autoneg = resp->autoneg; 3222 mac->support_autoneg = resp->autoneg_ability; 3223 mac->speed_type = QUERY_ACTIVE_SPEED; 3224 mac->lane_num = resp->lane_num; 3225 if (!resp->active_fec) 3226 mac->fec_mode = 0; 3227 else 3228 mac->fec_mode = BIT(resp->active_fec); 3229 mac->fec_ability = resp->fec_ability; 3230 } else { 3231 mac->speed_type = QUERY_SFP_SPEED; 3232 } 3233 3234 return 0; 3235 } 3236 3237 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3238 struct ethtool_link_ksettings *cmd) 3239 { 3240 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3241 struct hclge_vport *vport = hclge_get_vport(handle); 3242 struct hclge_phy_link_ksetting_0_cmd *req0; 3243 struct hclge_phy_link_ksetting_1_cmd *req1; 3244 u32 supported, advertising, lp_advertising; 3245 struct hclge_dev *hdev = vport->back; 3246 int ret; 3247 3248 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3249 true); 3250 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3251 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3252 true); 3253 3254 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3255 if (ret) { 3256 dev_err(&hdev->pdev->dev, 3257 "failed to get phy link ksetting, ret = %d.\n", ret); 3258 return ret; 3259 } 3260 3261 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3262 cmd->base.autoneg = req0->autoneg; 3263 cmd->base.speed = le32_to_cpu(req0->speed); 3264 cmd->base.duplex = req0->duplex; 3265 cmd->base.port = req0->port; 3266 cmd->base.transceiver = req0->transceiver; 3267 cmd->base.phy_address = req0->phy_address; 3268 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3269 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3270 supported = le32_to_cpu(req0->supported); 3271 advertising = le32_to_cpu(req0->advertising); 3272 lp_advertising = le32_to_cpu(req0->lp_advertising); 3273 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3274 supported); 3275 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3276 advertising); 3277 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3278 lp_advertising); 3279 3280 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3281 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3282 cmd->base.master_slave_state = req1->master_slave_state; 3283 3284 return 0; 3285 } 3286 3287 static int 3288 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3289 const struct ethtool_link_ksettings *cmd) 3290 { 3291 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3292 struct hclge_vport *vport = hclge_get_vport(handle); 3293 struct hclge_phy_link_ksetting_0_cmd *req0; 3294 struct hclge_phy_link_ksetting_1_cmd *req1; 3295 struct hclge_dev *hdev = vport->back; 3296 u32 advertising; 3297 int ret; 3298 3299 if (cmd->base.autoneg == AUTONEG_DISABLE && 3300 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3301 (cmd->base.duplex != DUPLEX_HALF && 3302 cmd->base.duplex != DUPLEX_FULL))) 3303 return -EINVAL; 3304 3305 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3306 false); 3307 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3308 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3309 false); 3310 3311 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3312 req0->autoneg = cmd->base.autoneg; 3313 req0->speed = cpu_to_le32(cmd->base.speed); 3314 req0->duplex = cmd->base.duplex; 3315 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3316 cmd->link_modes.advertising); 3317 req0->advertising = cpu_to_le32(advertising); 3318 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3319 3320 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3321 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3322 3323 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3324 if (ret) { 3325 dev_err(&hdev->pdev->dev, 3326 "failed to set phy link ksettings, ret = %d.\n", ret); 3327 return ret; 3328 } 3329 3330 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3331 hdev->hw.mac.req_speed = cmd->base.speed; 3332 hdev->hw.mac.req_duplex = cmd->base.duplex; 3333 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3334 3335 return 0; 3336 } 3337 3338 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3339 { 3340 struct ethtool_link_ksettings cmd; 3341 int ret; 3342 3343 if (!hnae3_dev_phy_imp_supported(hdev)) 3344 return 0; 3345 3346 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3347 if (ret) 3348 return ret; 3349 3350 hdev->hw.mac.autoneg = cmd.base.autoneg; 3351 hdev->hw.mac.speed = cmd.base.speed; 3352 hdev->hw.mac.duplex = cmd.base.duplex; 3353 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3354 3355 return 0; 3356 } 3357 3358 static int hclge_tp_port_init(struct hclge_dev *hdev) 3359 { 3360 struct ethtool_link_ksettings cmd; 3361 3362 if (!hnae3_dev_phy_imp_supported(hdev)) 3363 return 0; 3364 3365 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3366 cmd.base.speed = hdev->hw.mac.req_speed; 3367 cmd.base.duplex = hdev->hw.mac.req_duplex; 3368 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3369 3370 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3371 } 3372 3373 static int hclge_update_port_info(struct hclge_dev *hdev) 3374 { 3375 struct hclge_mac *mac = &hdev->hw.mac; 3376 u32 speed; 3377 int ret; 3378 3379 /* get the port info from SFP cmd if not copper port */ 3380 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3381 return hclge_update_tp_port_info(hdev); 3382 3383 /* if IMP does not support get SFP/qSFP info, return directly */ 3384 if (!hdev->support_sfp_query) 3385 return 0; 3386 3387 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3388 speed = mac->speed; 3389 ret = hclge_get_sfp_info(hdev, mac); 3390 } else { 3391 speed = HCLGE_MAC_SPEED_UNKNOWN; 3392 ret = hclge_get_sfp_speed(hdev, &speed); 3393 } 3394 3395 if (ret == -EOPNOTSUPP) { 3396 hdev->support_sfp_query = false; 3397 return ret; 3398 } else if (ret) { 3399 return ret; 3400 } 3401 3402 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3403 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3404 hclge_update_port_capability(hdev, mac); 3405 if (mac->speed != speed) 3406 (void)hclge_tm_port_shaper_cfg(hdev); 3407 return 0; 3408 } 3409 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3410 HCLGE_MAC_FULL, mac->lane_num); 3411 } else { 3412 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3413 return 0; /* do nothing if no SFP */ 3414 3415 /* must config full duplex for SFP */ 3416 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3417 } 3418 } 3419 3420 static int hclge_get_status(struct hnae3_handle *handle) 3421 { 3422 struct hclge_vport *vport = hclge_get_vport(handle); 3423 struct hclge_dev *hdev = vport->back; 3424 3425 hclge_update_link_status(hdev); 3426 3427 return hdev->hw.mac.link; 3428 } 3429 3430 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3431 { 3432 if (!pci_num_vf(hdev->pdev)) { 3433 dev_err(&hdev->pdev->dev, 3434 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3435 return NULL; 3436 } 3437 3438 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3439 dev_err(&hdev->pdev->dev, 3440 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3441 vf, pci_num_vf(hdev->pdev)); 3442 return NULL; 3443 } 3444 3445 /* VF start from 1 in vport */ 3446 vf += HCLGE_VF_VPORT_START_NUM; 3447 return &hdev->vport[vf]; 3448 } 3449 3450 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3451 struct ifla_vf_info *ivf) 3452 { 3453 struct hclge_vport *vport = hclge_get_vport(handle); 3454 struct hclge_dev *hdev = vport->back; 3455 3456 vport = hclge_get_vf_vport(hdev, vf); 3457 if (!vport) 3458 return -EINVAL; 3459 3460 ivf->vf = vf; 3461 ivf->linkstate = vport->vf_info.link_state; 3462 ivf->spoofchk = vport->vf_info.spoofchk; 3463 ivf->trusted = vport->vf_info.trusted; 3464 ivf->min_tx_rate = 0; 3465 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3466 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3467 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3468 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3469 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3470 3471 return 0; 3472 } 3473 3474 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3475 int link_state) 3476 { 3477 struct hclge_vport *vport = hclge_get_vport(handle); 3478 struct hclge_dev *hdev = vport->back; 3479 int link_state_old; 3480 int ret; 3481 3482 vport = hclge_get_vf_vport(hdev, vf); 3483 if (!vport) 3484 return -EINVAL; 3485 3486 link_state_old = vport->vf_info.link_state; 3487 vport->vf_info.link_state = link_state; 3488 3489 /* return success directly if the VF is unalive, VF will 3490 * query link state itself when it starts work. 3491 */ 3492 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3493 return 0; 3494 3495 ret = hclge_push_vf_link_status(vport); 3496 if (ret) { 3497 vport->vf_info.link_state = link_state_old; 3498 dev_err(&hdev->pdev->dev, 3499 "failed to push vf%d link status, ret = %d\n", vf, ret); 3500 } 3501 3502 return ret; 3503 } 3504 3505 static void hclge_set_reset_pending(struct hclge_dev *hdev, 3506 enum hnae3_reset_type reset_type) 3507 { 3508 /* When an incorrect reset type is executed, the get_reset_level 3509 * function generates the HNAE3_NONE_RESET flag. As a result, this 3510 * type do not need to pending. 3511 */ 3512 if (reset_type != HNAE3_NONE_RESET) 3513 set_bit(reset_type, &hdev->reset_pending); 3514 } 3515 3516 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3517 { 3518 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3519 3520 /* fetch the events from their corresponding regs */ 3521 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3522 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3523 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3524 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3525 3526 /* Assumption: If by any chance reset and mailbox events are reported 3527 * together then we will only process reset event in this go and will 3528 * defer the processing of the mailbox events. Since, we would have not 3529 * cleared RX CMDQ event this time we would receive again another 3530 * interrupt from H/W just for the mailbox. 3531 * 3532 * check for vector0 reset event sources 3533 */ 3534 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3535 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3536 hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); 3537 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3538 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3539 hdev->rst_stats.imp_rst_cnt++; 3540 return HCLGE_VECTOR0_EVENT_RST; 3541 } 3542 3543 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3544 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3545 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3546 hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); 3547 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3548 hdev->rst_stats.global_rst_cnt++; 3549 return HCLGE_VECTOR0_EVENT_RST; 3550 } 3551 3552 /* check for vector0 msix event and hardware error event source */ 3553 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3554 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3555 return HCLGE_VECTOR0_EVENT_ERR; 3556 3557 /* check for vector0 ptp event source */ 3558 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3559 *clearval = msix_src_reg; 3560 return HCLGE_VECTOR0_EVENT_PTP; 3561 } 3562 3563 /* check for vector0 mailbox(=CMDQ RX) event source */ 3564 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3565 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3566 *clearval = cmdq_src_reg; 3567 return HCLGE_VECTOR0_EVENT_MBX; 3568 } 3569 3570 /* print other vector0 event source */ 3571 dev_info(&hdev->pdev->dev, 3572 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3573 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3574 3575 return HCLGE_VECTOR0_EVENT_OTHER; 3576 } 3577 3578 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3579 u32 regclr) 3580 { 3581 #define HCLGE_IMP_RESET_DELAY 5 3582 3583 switch (event_type) { 3584 case HCLGE_VECTOR0_EVENT_PTP: 3585 case HCLGE_VECTOR0_EVENT_RST: 3586 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3587 mdelay(HCLGE_IMP_RESET_DELAY); 3588 3589 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3590 break; 3591 case HCLGE_VECTOR0_EVENT_MBX: 3592 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3593 break; 3594 default: 3595 break; 3596 } 3597 } 3598 3599 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3600 { 3601 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3602 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3603 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3604 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3605 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3606 } 3607 3608 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3609 { 3610 writel(enable ? 1 : 0, vector->addr); 3611 } 3612 3613 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3614 { 3615 struct hclge_dev *hdev = data; 3616 unsigned long flags; 3617 u32 clearval = 0; 3618 u32 event_cause; 3619 3620 hclge_enable_vector(&hdev->misc_vector, false); 3621 event_cause = hclge_check_event_cause(hdev, &clearval); 3622 3623 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3624 switch (event_cause) { 3625 case HCLGE_VECTOR0_EVENT_ERR: 3626 hclge_errhand_task_schedule(hdev); 3627 break; 3628 case HCLGE_VECTOR0_EVENT_RST: 3629 hclge_reset_task_schedule(hdev); 3630 break; 3631 case HCLGE_VECTOR0_EVENT_PTP: 3632 spin_lock_irqsave(&hdev->ptp->lock, flags); 3633 hclge_ptp_clean_tx_hwts(hdev); 3634 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3635 break; 3636 case HCLGE_VECTOR0_EVENT_MBX: 3637 /* If we are here then, 3638 * 1. Either we are not handling any mbx task and we are not 3639 * scheduled as well 3640 * OR 3641 * 2. We could be handling a mbx task but nothing more is 3642 * scheduled. 3643 * In both cases, we should schedule mbx task as there are more 3644 * mbx messages reported by this interrupt. 3645 */ 3646 hclge_mbx_task_schedule(hdev); 3647 break; 3648 default: 3649 dev_warn(&hdev->pdev->dev, 3650 "received unknown or unhandled event of vector0\n"); 3651 break; 3652 } 3653 3654 hclge_clear_event_cause(hdev, event_cause, clearval); 3655 3656 /* Enable interrupt if it is not caused by reset event or error event */ 3657 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3658 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3659 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3660 hclge_enable_vector(&hdev->misc_vector, true); 3661 3662 return IRQ_HANDLED; 3663 } 3664 3665 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3666 { 3667 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3668 dev_warn(&hdev->pdev->dev, 3669 "vector(vector_id %d) has been freed.\n", vector_id); 3670 return; 3671 } 3672 3673 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3674 hdev->num_msi_left += 1; 3675 hdev->num_msi_used -= 1; 3676 } 3677 3678 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3679 { 3680 struct hclge_misc_vector *vector = &hdev->misc_vector; 3681 3682 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3683 3684 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3685 hdev->vector_status[0] = 0; 3686 3687 hdev->num_msi_left -= 1; 3688 hdev->num_msi_used += 1; 3689 } 3690 3691 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3692 { 3693 int ret; 3694 3695 hclge_get_misc_vector(hdev); 3696 3697 /* this would be explicitly freed in the end */ 3698 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3699 HCLGE_NAME, pci_name(hdev->pdev)); 3700 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3701 IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); 3702 if (ret) { 3703 hclge_free_vector(hdev, 0); 3704 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3705 hdev->misc_vector.vector_irq); 3706 } 3707 3708 return ret; 3709 } 3710 3711 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3712 { 3713 free_irq(hdev->misc_vector.vector_irq, hdev); 3714 hclge_free_vector(hdev, 0); 3715 } 3716 3717 int hclge_notify_client(struct hclge_dev *hdev, 3718 enum hnae3_reset_notify_type type) 3719 { 3720 struct hnae3_handle *handle = &hdev->vport[0].nic; 3721 struct hnae3_client *client = hdev->nic_client; 3722 int ret; 3723 3724 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3725 return 0; 3726 3727 if (!client->ops->reset_notify) 3728 return -EOPNOTSUPP; 3729 3730 ret = client->ops->reset_notify(handle, type); 3731 if (ret) 3732 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3733 type, ret); 3734 3735 return ret; 3736 } 3737 3738 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3739 enum hnae3_reset_notify_type type) 3740 { 3741 struct hnae3_handle *handle = &hdev->vport[0].roce; 3742 struct hnae3_client *client = hdev->roce_client; 3743 int ret; 3744 3745 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3746 return 0; 3747 3748 if (!client->ops->reset_notify) 3749 return -EOPNOTSUPP; 3750 3751 ret = client->ops->reset_notify(handle, type); 3752 if (ret) 3753 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3754 type, ret); 3755 3756 return ret; 3757 } 3758 3759 static int hclge_reset_wait(struct hclge_dev *hdev) 3760 { 3761 #define HCLGE_RESET_WATI_MS 100 3762 #define HCLGE_RESET_WAIT_CNT 350 3763 3764 u32 val, reg, reg_bit; 3765 u32 cnt = 0; 3766 3767 switch (hdev->reset_type) { 3768 case HNAE3_IMP_RESET: 3769 reg = HCLGE_GLOBAL_RESET_REG; 3770 reg_bit = HCLGE_IMP_RESET_BIT; 3771 break; 3772 case HNAE3_GLOBAL_RESET: 3773 reg = HCLGE_GLOBAL_RESET_REG; 3774 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3775 break; 3776 case HNAE3_FUNC_RESET: 3777 reg = HCLGE_FUN_RST_ING; 3778 reg_bit = HCLGE_FUN_RST_ING_B; 3779 break; 3780 default: 3781 dev_err(&hdev->pdev->dev, 3782 "Wait for unsupported reset type: %d\n", 3783 hdev->reset_type); 3784 return -EINVAL; 3785 } 3786 3787 val = hclge_read_dev(&hdev->hw, reg); 3788 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3789 msleep(HCLGE_RESET_WATI_MS); 3790 val = hclge_read_dev(&hdev->hw, reg); 3791 cnt++; 3792 } 3793 3794 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3795 dev_warn(&hdev->pdev->dev, 3796 "Wait for reset timeout: %d\n", hdev->reset_type); 3797 return -EBUSY; 3798 } 3799 3800 return 0; 3801 } 3802 3803 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3804 { 3805 struct hclge_vf_rst_cmd *req; 3806 struct hclge_desc desc; 3807 3808 req = (struct hclge_vf_rst_cmd *)desc.data; 3809 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3810 req->dest_vfid = func_id; 3811 3812 if (reset) 3813 req->vf_rst = 0x1; 3814 3815 return hclge_cmd_send(&hdev->hw, &desc, 1); 3816 } 3817 3818 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3819 { 3820 int i; 3821 3822 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3823 struct hclge_vport *vport = &hdev->vport[i]; 3824 int ret; 3825 3826 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3827 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3828 if (ret) { 3829 dev_err(&hdev->pdev->dev, 3830 "set vf(%u) rst failed %d!\n", 3831 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3832 ret); 3833 return ret; 3834 } 3835 3836 if (!reset || 3837 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3838 continue; 3839 3840 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3841 hdev->reset_type == HNAE3_FUNC_RESET) { 3842 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3843 &vport->need_notify); 3844 continue; 3845 } 3846 3847 /* Inform VF to process the reset. 3848 * hclge_inform_reset_assert_to_vf may fail if VF 3849 * driver is not loaded. 3850 */ 3851 ret = hclge_inform_reset_assert_to_vf(vport); 3852 if (ret) 3853 dev_warn(&hdev->pdev->dev, 3854 "inform reset to vf(%u) failed %d!\n", 3855 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3856 ret); 3857 } 3858 3859 return 0; 3860 } 3861 3862 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3863 { 3864 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3865 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3866 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3867 return; 3868 3869 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3870 HCLGE_MBX_SCHED_TIMEOUT)) 3871 dev_warn(&hdev->pdev->dev, 3872 "mbx service task is scheduled after %ums on cpu%u!\n", 3873 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3874 smp_processor_id()); 3875 3876 hclge_mbx_handler(hdev); 3877 3878 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3879 } 3880 3881 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3882 { 3883 struct hclge_pf_rst_sync_cmd *req; 3884 struct hclge_desc desc; 3885 int cnt = 0; 3886 int ret; 3887 3888 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3889 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3890 3891 do { 3892 /* vf need to down netdev by mbx during PF or FLR reset */ 3893 hclge_mailbox_service_task(hdev); 3894 3895 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3896 /* for compatible with old firmware, wait 3897 * 100 ms for VF to stop IO 3898 */ 3899 if (ret == -EOPNOTSUPP) { 3900 msleep(HCLGE_RESET_SYNC_TIME); 3901 return; 3902 } else if (ret) { 3903 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3904 ret); 3905 return; 3906 } else if (req->all_vf_ready) { 3907 return; 3908 } 3909 msleep(HCLGE_PF_RESET_SYNC_TIME); 3910 hclge_comm_cmd_reuse_desc(&desc, true); 3911 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3912 3913 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3914 } 3915 3916 void hclge_report_hw_error(struct hclge_dev *hdev, 3917 enum hnae3_hw_error_type type) 3918 { 3919 struct hnae3_client *client = hdev->nic_client; 3920 3921 if (!client || !client->ops->process_hw_error || 3922 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3923 return; 3924 3925 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3926 } 3927 3928 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3929 { 3930 u32 reg_val; 3931 3932 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3933 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3934 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3935 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3936 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3937 } 3938 3939 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3940 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3941 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3942 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3943 } 3944 } 3945 3946 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3947 { 3948 struct hclge_desc desc; 3949 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3950 int ret; 3951 3952 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3953 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3954 req->fun_reset_vfid = func_id; 3955 3956 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3957 if (ret) 3958 dev_err(&hdev->pdev->dev, 3959 "send function reset cmd fail, status =%d\n", ret); 3960 3961 return ret; 3962 } 3963 3964 static void hclge_do_reset(struct hclge_dev *hdev) 3965 { 3966 struct hnae3_handle *handle = &hdev->vport[0].nic; 3967 struct pci_dev *pdev = hdev->pdev; 3968 u32 val; 3969 3970 if (hclge_get_hw_reset_stat(handle)) { 3971 dev_info(&pdev->dev, "hardware reset not finish\n"); 3972 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3973 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3974 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3975 return; 3976 } 3977 3978 switch (hdev->reset_type) { 3979 case HNAE3_IMP_RESET: 3980 dev_info(&pdev->dev, "IMP reset requested\n"); 3981 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3982 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3983 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3984 break; 3985 case HNAE3_GLOBAL_RESET: 3986 dev_info(&pdev->dev, "global reset requested\n"); 3987 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 3988 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 3989 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 3990 break; 3991 case HNAE3_FUNC_RESET: 3992 dev_info(&pdev->dev, "PF reset requested\n"); 3993 /* schedule again to check later */ 3994 hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); 3995 hclge_reset_task_schedule(hdev); 3996 break; 3997 default: 3998 dev_warn(&pdev->dev, 3999 "unsupported reset type: %d\n", hdev->reset_type); 4000 break; 4001 } 4002 } 4003 4004 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4005 unsigned long *addr) 4006 { 4007 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4008 struct hclge_dev *hdev = ae_dev->priv; 4009 4010 /* return the highest priority reset level amongst all */ 4011 if (test_bit(HNAE3_IMP_RESET, addr)) { 4012 rst_level = HNAE3_IMP_RESET; 4013 clear_bit(HNAE3_IMP_RESET, addr); 4014 clear_bit(HNAE3_GLOBAL_RESET, addr); 4015 clear_bit(HNAE3_FUNC_RESET, addr); 4016 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4017 rst_level = HNAE3_GLOBAL_RESET; 4018 clear_bit(HNAE3_GLOBAL_RESET, addr); 4019 clear_bit(HNAE3_FUNC_RESET, addr); 4020 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4021 rst_level = HNAE3_FUNC_RESET; 4022 clear_bit(HNAE3_FUNC_RESET, addr); 4023 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4024 rst_level = HNAE3_FLR_RESET; 4025 clear_bit(HNAE3_FLR_RESET, addr); 4026 } 4027 4028 clear_bit(HNAE3_NONE_RESET, addr); 4029 4030 if (hdev->reset_type != HNAE3_NONE_RESET && 4031 rst_level < hdev->reset_type) 4032 return HNAE3_NONE_RESET; 4033 4034 return rst_level; 4035 } 4036 4037 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4038 { 4039 u32 clearval = 0; 4040 4041 switch (hdev->reset_type) { 4042 case HNAE3_IMP_RESET: 4043 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4044 break; 4045 case HNAE3_GLOBAL_RESET: 4046 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4047 break; 4048 default: 4049 break; 4050 } 4051 4052 if (!clearval) 4053 return; 4054 4055 /* For revision 0x20, the reset interrupt source 4056 * can only be cleared after hardware reset done 4057 */ 4058 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4059 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4060 clearval); 4061 4062 hclge_enable_vector(&hdev->misc_vector, true); 4063 } 4064 4065 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4066 { 4067 u32 reg_val; 4068 4069 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4070 if (enable) 4071 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4072 else 4073 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4074 4075 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4076 } 4077 4078 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4079 { 4080 int ret; 4081 4082 ret = hclge_set_all_vf_rst(hdev, true); 4083 if (ret) 4084 return ret; 4085 4086 hclge_func_reset_sync_vf(hdev); 4087 4088 return 0; 4089 } 4090 4091 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4092 { 4093 u32 reg_val; 4094 int ret = 0; 4095 4096 switch (hdev->reset_type) { 4097 case HNAE3_FUNC_RESET: 4098 ret = hclge_func_reset_notify_vf(hdev); 4099 if (ret) 4100 return ret; 4101 4102 ret = hclge_func_reset_cmd(hdev, 0); 4103 if (ret) { 4104 dev_err(&hdev->pdev->dev, 4105 "asserting function reset fail %d!\n", ret); 4106 return ret; 4107 } 4108 4109 /* After performaning pf reset, it is not necessary to do the 4110 * mailbox handling or send any command to firmware, because 4111 * any mailbox handling or command to firmware is only valid 4112 * after hclge_comm_cmd_init is called. 4113 */ 4114 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4115 hdev->rst_stats.pf_rst_cnt++; 4116 break; 4117 case HNAE3_FLR_RESET: 4118 ret = hclge_func_reset_notify_vf(hdev); 4119 if (ret) 4120 return ret; 4121 break; 4122 case HNAE3_IMP_RESET: 4123 hclge_handle_imp_error(hdev); 4124 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4125 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4126 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4127 break; 4128 default: 4129 break; 4130 } 4131 4132 /* inform hardware that preparatory work is done */ 4133 msleep(HCLGE_RESET_SYNC_TIME); 4134 hclge_reset_handshake(hdev, true); 4135 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4136 4137 return ret; 4138 } 4139 4140 static void hclge_show_rst_info(struct hclge_dev *hdev) 4141 { 4142 char *buf; 4143 4144 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4145 if (!buf) 4146 return; 4147 4148 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4149 4150 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4151 4152 kfree(buf); 4153 } 4154 4155 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4156 { 4157 #define MAX_RESET_FAIL_CNT 5 4158 4159 if (hdev->reset_pending) { 4160 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4161 hdev->reset_pending); 4162 return true; 4163 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4164 HCLGE_RESET_INT_M) { 4165 dev_info(&hdev->pdev->dev, 4166 "reset failed because new reset interrupt\n"); 4167 hclge_clear_reset_cause(hdev); 4168 return false; 4169 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4170 hdev->rst_stats.reset_fail_cnt++; 4171 hclge_set_reset_pending(hdev, hdev->reset_type); 4172 dev_info(&hdev->pdev->dev, 4173 "re-schedule reset task(%u)\n", 4174 hdev->rst_stats.reset_fail_cnt); 4175 return true; 4176 } 4177 4178 hclge_clear_reset_cause(hdev); 4179 4180 /* recover the handshake status when reset fail */ 4181 hclge_reset_handshake(hdev, true); 4182 4183 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4184 4185 hclge_show_rst_info(hdev); 4186 4187 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4188 4189 return false; 4190 } 4191 4192 static void hclge_update_reset_level(struct hclge_dev *hdev) 4193 { 4194 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4195 enum hnae3_reset_type reset_level; 4196 4197 /* reset request will not be set during reset, so clear 4198 * pending reset request to avoid unnecessary reset 4199 * caused by the same reason. 4200 */ 4201 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4202 4203 /* if default_reset_request has a higher level reset request, 4204 * it should be handled as soon as possible. since some errors 4205 * need this kind of reset to fix. 4206 */ 4207 reset_level = hclge_get_reset_level(ae_dev, 4208 &hdev->default_reset_request); 4209 if (reset_level != HNAE3_NONE_RESET) 4210 set_bit(reset_level, &hdev->reset_request); 4211 } 4212 4213 static int hclge_set_rst_done(struct hclge_dev *hdev) 4214 { 4215 struct hclge_pf_rst_done_cmd *req; 4216 struct hclge_desc desc; 4217 int ret; 4218 4219 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4220 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4221 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4222 4223 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4224 /* To be compatible with the old firmware, which does not support 4225 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4226 * return success 4227 */ 4228 if (ret == -EOPNOTSUPP) { 4229 dev_warn(&hdev->pdev->dev, 4230 "current firmware does not support command(0x%x)!\n", 4231 HCLGE_OPC_PF_RST_DONE); 4232 return 0; 4233 } else if (ret) { 4234 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4235 ret); 4236 } 4237 4238 return ret; 4239 } 4240 4241 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4242 { 4243 int ret = 0; 4244 4245 switch (hdev->reset_type) { 4246 case HNAE3_FUNC_RESET: 4247 case HNAE3_FLR_RESET: 4248 ret = hclge_set_all_vf_rst(hdev, false); 4249 break; 4250 case HNAE3_GLOBAL_RESET: 4251 case HNAE3_IMP_RESET: 4252 ret = hclge_set_rst_done(hdev); 4253 break; 4254 default: 4255 break; 4256 } 4257 4258 /* clear up the handshake status after re-initialize done */ 4259 hclge_reset_handshake(hdev, false); 4260 4261 return ret; 4262 } 4263 4264 static int hclge_reset_stack(struct hclge_dev *hdev) 4265 { 4266 int ret; 4267 4268 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4269 if (ret) 4270 return ret; 4271 4272 ret = hclge_reset_ae_dev(hdev->ae_dev); 4273 if (ret) 4274 return ret; 4275 4276 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4277 } 4278 4279 static int hclge_reset_prepare(struct hclge_dev *hdev) 4280 { 4281 int ret; 4282 4283 hdev->rst_stats.reset_cnt++; 4284 /* perform reset of the stack & ae device for a client */ 4285 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4286 if (ret) 4287 return ret; 4288 4289 rtnl_lock(); 4290 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4291 rtnl_unlock(); 4292 if (ret) 4293 return ret; 4294 4295 return hclge_reset_prepare_wait(hdev); 4296 } 4297 4298 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4299 { 4300 int ret; 4301 4302 hdev->rst_stats.hw_reset_done_cnt++; 4303 4304 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4305 if (ret) 4306 return ret; 4307 4308 rtnl_lock(); 4309 ret = hclge_reset_stack(hdev); 4310 rtnl_unlock(); 4311 if (ret) 4312 return ret; 4313 4314 hclge_clear_reset_cause(hdev); 4315 4316 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4317 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4318 * times 4319 */ 4320 if (ret && 4321 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4322 return ret; 4323 4324 ret = hclge_reset_prepare_up(hdev); 4325 if (ret) 4326 return ret; 4327 4328 rtnl_lock(); 4329 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4330 rtnl_unlock(); 4331 if (ret) 4332 return ret; 4333 4334 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4335 if (ret) 4336 return ret; 4337 4338 hdev->last_reset_time = jiffies; 4339 hdev->rst_stats.reset_fail_cnt = 0; 4340 hdev->rst_stats.reset_done_cnt++; 4341 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4342 4343 hclge_update_reset_level(hdev); 4344 4345 return 0; 4346 } 4347 4348 static void hclge_reset(struct hclge_dev *hdev) 4349 { 4350 if (hclge_reset_prepare(hdev)) 4351 goto err_reset; 4352 4353 if (hclge_reset_wait(hdev)) 4354 goto err_reset; 4355 4356 if (hclge_reset_rebuild(hdev)) 4357 goto err_reset; 4358 4359 return; 4360 4361 err_reset: 4362 if (hclge_reset_err_handle(hdev)) 4363 hclge_reset_task_schedule(hdev); 4364 } 4365 4366 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4367 { 4368 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4369 struct hclge_dev *hdev = ae_dev->priv; 4370 4371 /* We might end up getting called broadly because of 2 below cases: 4372 * 1. Recoverable error was conveyed through APEI and only way to bring 4373 * normalcy is to reset. 4374 * 2. A new reset request from the stack due to timeout 4375 * 4376 * check if this is a new reset request and we are not here just because 4377 * last reset attempt did not succeed and watchdog hit us again. We will 4378 * know this if last reset request did not occur very recently (watchdog 4379 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4380 * In case of new request we reset the "reset level" to PF reset. 4381 * And if it is a repeat reset request of the most recent one then we 4382 * want to make sure we throttle the reset request. Therefore, we will 4383 * not allow it again before 3*HZ times. 4384 */ 4385 4386 if (time_before(jiffies, (hdev->last_reset_time + 4387 HCLGE_RESET_INTERVAL))) { 4388 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4389 return; 4390 } 4391 4392 if (hdev->default_reset_request) { 4393 hdev->reset_level = 4394 hclge_get_reset_level(ae_dev, 4395 &hdev->default_reset_request); 4396 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4397 hdev->reset_level = HNAE3_FUNC_RESET; 4398 } 4399 4400 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4401 hdev->reset_level); 4402 4403 /* request reset & schedule reset task */ 4404 set_bit(hdev->reset_level, &hdev->reset_request); 4405 hclge_reset_task_schedule(hdev); 4406 4407 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4408 hdev->reset_level++; 4409 } 4410 4411 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4412 enum hnae3_reset_type rst_type) 4413 { 4414 #define HCLGE_SUPPORT_RESET_TYPE \ 4415 (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ 4416 BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) 4417 4418 struct hclge_dev *hdev = ae_dev->priv; 4419 4420 if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { 4421 /* To prevent reset triggered by hclge_reset_event */ 4422 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 4423 dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", 4424 rst_type); 4425 return; 4426 } 4427 4428 set_bit(rst_type, &hdev->default_reset_request); 4429 } 4430 4431 static void hclge_reset_timer(struct timer_list *t) 4432 { 4433 struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer); 4434 4435 /* if default_reset_request has no value, it means that this reset 4436 * request has already be handled, so just return here 4437 */ 4438 if (!hdev->default_reset_request) 4439 return; 4440 4441 dev_info(&hdev->pdev->dev, 4442 "triggering reset in reset timer\n"); 4443 hclge_reset_event(hdev->pdev, NULL); 4444 } 4445 4446 static void hclge_reset_subtask(struct hclge_dev *hdev) 4447 { 4448 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4449 4450 /* check if there is any ongoing reset in the hardware. This status can 4451 * be checked from reset_pending. If there is then, we need to wait for 4452 * hardware to complete reset. 4453 * a. If we are able to figure out in reasonable time that hardware 4454 * has fully resetted then, we can proceed with driver, client 4455 * reset. 4456 * b. else, we can come back later to check this status so re-sched 4457 * now. 4458 */ 4459 hdev->last_reset_time = jiffies; 4460 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4461 if (hdev->reset_type != HNAE3_NONE_RESET) 4462 hclge_reset(hdev); 4463 4464 /* check if we got any *new* reset requests to be honored */ 4465 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4466 if (hdev->reset_type != HNAE3_NONE_RESET) 4467 hclge_do_reset(hdev); 4468 4469 hdev->reset_type = HNAE3_NONE_RESET; 4470 } 4471 4472 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4473 { 4474 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4475 enum hnae3_reset_type reset_type; 4476 4477 if (ae_dev->hw_err_reset_req) { 4478 reset_type = hclge_get_reset_level(ae_dev, 4479 &ae_dev->hw_err_reset_req); 4480 hclge_set_def_reset_request(ae_dev, reset_type); 4481 } 4482 4483 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4484 ae_dev->ops->reset_event(hdev->pdev, NULL); 4485 4486 /* enable interrupt after error handling complete */ 4487 hclge_enable_vector(&hdev->misc_vector, true); 4488 } 4489 4490 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4491 { 4492 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4493 4494 ae_dev->hw_err_reset_req = 0; 4495 4496 if (hclge_find_error_source(hdev)) { 4497 hclge_handle_error_info_log(ae_dev); 4498 hclge_handle_mac_tnl(hdev); 4499 hclge_handle_vf_queue_err_ras(hdev); 4500 } 4501 4502 hclge_handle_err_reset_request(hdev); 4503 } 4504 4505 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4506 { 4507 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4508 struct device *dev = &hdev->pdev->dev; 4509 u32 msix_sts_reg; 4510 4511 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4512 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4513 if (hclge_handle_hw_msix_error 4514 (hdev, &hdev->default_reset_request)) 4515 dev_info(dev, "received msix interrupt 0x%x\n", 4516 msix_sts_reg); 4517 } 4518 4519 hclge_handle_hw_ras_error(ae_dev); 4520 4521 hclge_handle_err_reset_request(hdev); 4522 } 4523 4524 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4525 { 4526 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4527 return; 4528 4529 if (hnae3_dev_ras_imp_supported(hdev)) 4530 hclge_handle_err_recovery(hdev); 4531 else 4532 hclge_misc_err_recovery(hdev); 4533 } 4534 4535 static void hclge_reset_service_task(struct hclge_dev *hdev) 4536 { 4537 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4538 return; 4539 4540 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4541 HCLGE_RESET_SCHED_TIMEOUT)) 4542 dev_warn(&hdev->pdev->dev, 4543 "reset service task is scheduled after %ums on cpu%u!\n", 4544 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4545 smp_processor_id()); 4546 4547 down(&hdev->reset_sem); 4548 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4549 4550 hclge_reset_subtask(hdev); 4551 4552 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4553 up(&hdev->reset_sem); 4554 } 4555 4556 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4557 { 4558 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4559 4560 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4561 int i; 4562 4563 /* start from vport 1 for PF is always alive */ 4564 for (i = 1; i < hdev->num_alloc_vport; i++) { 4565 struct hclge_vport *vport = &hdev->vport[i]; 4566 4567 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4568 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4569 continue; 4570 if (time_after(jiffies, vport->last_active_jiffies + 4571 alive_time)) { 4572 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4573 dev_warn(&hdev->pdev->dev, 4574 "VF %u heartbeat timeout\n", 4575 i - HCLGE_VF_VPORT_START_NUM); 4576 } 4577 } 4578 } 4579 4580 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4581 { 4582 unsigned long delta = round_jiffies_relative(HZ); 4583 4584 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4585 return; 4586 4587 /* Always handle the link updating to make sure link state is 4588 * updated when it is triggered by mbx. 4589 */ 4590 hclge_update_link_status(hdev); 4591 hclge_sync_mac_table(hdev); 4592 hclge_sync_promisc_mode(hdev); 4593 hclge_sync_fd_table(hdev); 4594 4595 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4596 delta = jiffies - hdev->last_serv_processed; 4597 4598 if (delta < round_jiffies_relative(HZ)) { 4599 delta = round_jiffies_relative(HZ) - delta; 4600 goto out; 4601 } 4602 } 4603 4604 hdev->serv_processed_cnt++; 4605 hclge_update_vport_alive(hdev); 4606 4607 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4608 hdev->last_serv_processed = jiffies; 4609 goto out; 4610 } 4611 4612 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4613 hclge_update_stats_for_all(hdev); 4614 4615 hclge_update_port_info(hdev); 4616 hclge_sync_vlan_filter(hdev); 4617 4618 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4619 hclge_rfs_filter_expire(hdev); 4620 4621 hdev->last_serv_processed = jiffies; 4622 4623 out: 4624 hclge_task_schedule(hdev, delta); 4625 } 4626 4627 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4628 { 4629 unsigned long flags; 4630 4631 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4632 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4633 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4634 return; 4635 4636 /* to prevent concurrence with the irq handler */ 4637 spin_lock_irqsave(&hdev->ptp->lock, flags); 4638 4639 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4640 * handler may handle it just before spin_lock_irqsave(). 4641 */ 4642 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4643 hclge_ptp_clean_tx_hwts(hdev); 4644 4645 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4646 } 4647 4648 static void hclge_service_task(struct work_struct *work) 4649 { 4650 struct hclge_dev *hdev = 4651 container_of(work, struct hclge_dev, service_task.work); 4652 4653 hclge_errhand_service_task(hdev); 4654 hclge_reset_service_task(hdev); 4655 hclge_ptp_service_task(hdev); 4656 hclge_mailbox_service_task(hdev); 4657 hclge_periodic_service_task(hdev); 4658 4659 /* Handle error recovery, reset and mbx again in case periodical task 4660 * delays the handling by calling hclge_task_schedule() in 4661 * hclge_periodic_service_task(). 4662 */ 4663 hclge_errhand_service_task(hdev); 4664 hclge_reset_service_task(hdev); 4665 hclge_mailbox_service_task(hdev); 4666 } 4667 4668 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4669 { 4670 /* VF handle has no client */ 4671 if (!handle->client) 4672 return container_of(handle, struct hclge_vport, nic); 4673 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4674 return container_of(handle, struct hclge_vport, roce); 4675 else 4676 return container_of(handle, struct hclge_vport, nic); 4677 } 4678 4679 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4680 struct hnae3_vector_info *vector_info) 4681 { 4682 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4683 4684 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4685 4686 /* need an extend offset to config vector >= 64 */ 4687 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4688 vector_info->io_addr = hdev->hw.hw.io_base + 4689 HCLGE_VECTOR_REG_BASE + 4690 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4691 else 4692 vector_info->io_addr = hdev->hw.hw.io_base + 4693 HCLGE_VECTOR_EXT_REG_BASE + 4694 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4695 HCLGE_VECTOR_REG_OFFSET_H + 4696 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4697 HCLGE_VECTOR_REG_OFFSET; 4698 4699 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4700 hdev->vector_irq[idx] = vector_info->vector; 4701 } 4702 4703 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4704 struct hnae3_vector_info *vector_info) 4705 { 4706 struct hclge_vport *vport = hclge_get_vport(handle); 4707 struct hnae3_vector_info *vector = vector_info; 4708 struct hclge_dev *hdev = vport->back; 4709 int alloc = 0; 4710 u16 i = 0; 4711 u16 j; 4712 4713 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4714 vector_num = min(hdev->num_msi_left, vector_num); 4715 4716 for (j = 0; j < vector_num; j++) { 4717 while (++i < hdev->num_nic_msi) { 4718 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4719 hclge_get_vector_info(hdev, i, vector); 4720 vector++; 4721 alloc++; 4722 4723 break; 4724 } 4725 } 4726 } 4727 hdev->num_msi_left -= alloc; 4728 hdev->num_msi_used += alloc; 4729 4730 return alloc; 4731 } 4732 4733 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4734 { 4735 int i; 4736 4737 for (i = 0; i < hdev->num_msi; i++) 4738 if (vector == hdev->vector_irq[i]) 4739 return i; 4740 4741 return -EINVAL; 4742 } 4743 4744 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4745 { 4746 struct hclge_vport *vport = hclge_get_vport(handle); 4747 struct hclge_dev *hdev = vport->back; 4748 int vector_id; 4749 4750 vector_id = hclge_get_vector_index(hdev, vector); 4751 if (vector_id < 0) { 4752 dev_err(&hdev->pdev->dev, 4753 "Get vector index fail. vector = %d\n", vector); 4754 return vector_id; 4755 } 4756 4757 hclge_free_vector(hdev, vector_id); 4758 4759 return 0; 4760 } 4761 4762 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4763 u8 *key, u8 *hfunc) 4764 { 4765 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4766 struct hclge_vport *vport = hclge_get_vport(handle); 4767 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4768 4769 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4770 4771 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4772 ae_dev->dev_specs.rss_ind_tbl_size); 4773 4774 return 0; 4775 } 4776 4777 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4778 const u8 *key, const u8 hfunc) 4779 { 4780 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4781 struct hclge_vport *vport = hclge_get_vport(handle); 4782 struct hclge_dev *hdev = vport->back; 4783 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4784 int ret, i; 4785 4786 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4787 if (ret) { 4788 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4789 return ret; 4790 } 4791 4792 /* Update the shadow RSS table with user specified qids */ 4793 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4794 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4795 4796 /* Update the hardware */ 4797 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4798 rss_cfg->rss_indirection_tbl); 4799 } 4800 4801 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4802 const struct ethtool_rxfh_fields *nfc) 4803 { 4804 struct hclge_vport *vport = hclge_get_vport(handle); 4805 struct hclge_dev *hdev = vport->back; 4806 int ret; 4807 4808 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4809 &hdev->rss_cfg, nfc); 4810 if (ret) { 4811 dev_err(&hdev->pdev->dev, 4812 "failed to set rss tuple, ret = %d.\n", ret); 4813 return ret; 4814 } 4815 4816 return 0; 4817 } 4818 4819 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4820 struct ethtool_rxfh_fields *nfc) 4821 { 4822 struct hclge_vport *vport = hclge_get_vport(handle); 4823 u8 tuple_sets; 4824 int ret; 4825 4826 nfc->data = 0; 4827 4828 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4829 &tuple_sets); 4830 if (ret || !tuple_sets) 4831 return ret; 4832 4833 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4834 4835 return 0; 4836 } 4837 4838 static int hclge_get_tc_size(struct hnae3_handle *handle) 4839 { 4840 struct hclge_vport *vport = hclge_get_vport(handle); 4841 struct hclge_dev *hdev = vport->back; 4842 4843 return hdev->pf_rss_size_max; 4844 } 4845 4846 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4847 { 4848 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4849 struct hclge_vport *vport = hdev->vport; 4850 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4851 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4852 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4853 struct hnae3_tc_info *tc_info; 4854 u16 roundup_size; 4855 u16 rss_size; 4856 int i; 4857 4858 tc_info = &vport->nic.kinfo.tc_info; 4859 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4860 rss_size = tc_info->tqp_count[i]; 4861 tc_valid[i] = 0; 4862 4863 if (!(hdev->hw_tc_map & BIT(i))) 4864 continue; 4865 4866 /* tc_size set to hardware is the log2 of roundup power of two 4867 * of rss_size, the acutal queue size is limited by indirection 4868 * table. 4869 */ 4870 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4871 rss_size == 0) { 4872 dev_err(&hdev->pdev->dev, 4873 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4874 rss_size); 4875 return -EINVAL; 4876 } 4877 4878 roundup_size = roundup_pow_of_two(rss_size); 4879 roundup_size = ilog2(roundup_size); 4880 4881 tc_valid[i] = 1; 4882 tc_size[i] = roundup_size; 4883 tc_offset[i] = tc_info->tqp_offset[i]; 4884 } 4885 4886 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4887 tc_size); 4888 } 4889 4890 int hclge_rss_init_hw(struct hclge_dev *hdev) 4891 { 4892 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4893 u8 *key = hdev->rss_cfg.rss_hash_key; 4894 u8 hfunc = hdev->rss_cfg.rss_algo; 4895 int ret; 4896 4897 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4898 rss_indir); 4899 if (ret) 4900 return ret; 4901 4902 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4903 if (ret) 4904 return ret; 4905 4906 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4907 if (ret) 4908 return ret; 4909 4910 return hclge_init_rss_tc_mode(hdev); 4911 } 4912 4913 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4914 int vector_id, bool en, 4915 struct hnae3_ring_chain_node *ring_chain) 4916 { 4917 struct hclge_dev *hdev = vport->back; 4918 struct hnae3_ring_chain_node *node; 4919 struct hclge_desc desc; 4920 struct hclge_ctrl_vector_chain_cmd *req = 4921 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4922 enum hclge_comm_cmd_status status; 4923 enum hclge_opcode_type op; 4924 u16 tqp_type_and_id; 4925 int i; 4926 4927 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4928 hclge_cmd_setup_basic_desc(&desc, op, false); 4929 req->int_vector_id_l = hnae3_get_field(vector_id, 4930 HCLGE_VECTOR_ID_L_M, 4931 HCLGE_VECTOR_ID_L_S); 4932 req->int_vector_id_h = hnae3_get_field(vector_id, 4933 HCLGE_VECTOR_ID_H_M, 4934 HCLGE_VECTOR_ID_H_S); 4935 4936 i = 0; 4937 for (node = ring_chain; node; node = node->next) { 4938 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4939 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4940 HCLGE_INT_TYPE_S, 4941 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4942 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4943 HCLGE_TQP_ID_S, node->tqp_index); 4944 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4945 HCLGE_INT_GL_IDX_S, 4946 hnae3_get_field(node->int_gl_idx, 4947 HNAE3_RING_GL_IDX_M, 4948 HNAE3_RING_GL_IDX_S)); 4949 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4950 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4951 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4952 req->vfid = vport->vport_id; 4953 4954 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4955 if (status) { 4956 dev_err(&hdev->pdev->dev, 4957 "Map TQP fail, status is %d.\n", 4958 status); 4959 return -EIO; 4960 } 4961 i = 0; 4962 4963 hclge_cmd_setup_basic_desc(&desc, 4964 op, 4965 false); 4966 req->int_vector_id_l = 4967 hnae3_get_field(vector_id, 4968 HCLGE_VECTOR_ID_L_M, 4969 HCLGE_VECTOR_ID_L_S); 4970 req->int_vector_id_h = 4971 hnae3_get_field(vector_id, 4972 HCLGE_VECTOR_ID_H_M, 4973 HCLGE_VECTOR_ID_H_S); 4974 } 4975 } 4976 4977 if (i > 0) { 4978 req->int_cause_num = i; 4979 req->vfid = vport->vport_id; 4980 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4981 if (status) { 4982 dev_err(&hdev->pdev->dev, 4983 "Map TQP fail, status is %d.\n", status); 4984 return -EIO; 4985 } 4986 } 4987 4988 return 0; 4989 } 4990 4991 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4992 struct hnae3_ring_chain_node *ring_chain) 4993 { 4994 struct hclge_vport *vport = hclge_get_vport(handle); 4995 struct hclge_dev *hdev = vport->back; 4996 int vector_id; 4997 4998 vector_id = hclge_get_vector_index(hdev, vector); 4999 if (vector_id < 0) { 5000 dev_err(&hdev->pdev->dev, 5001 "failed to get vector index. vector=%d\n", vector); 5002 return vector_id; 5003 } 5004 5005 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5006 } 5007 5008 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5009 struct hnae3_ring_chain_node *ring_chain) 5010 { 5011 struct hclge_vport *vport = hclge_get_vport(handle); 5012 struct hclge_dev *hdev = vport->back; 5013 int vector_id, ret; 5014 5015 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5016 return 0; 5017 5018 vector_id = hclge_get_vector_index(hdev, vector); 5019 if (vector_id < 0) { 5020 dev_err(&handle->pdev->dev, 5021 "Get vector index fail. ret =%d\n", vector_id); 5022 return vector_id; 5023 } 5024 5025 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5026 if (ret) 5027 dev_err(&handle->pdev->dev, 5028 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5029 vector_id, ret); 5030 5031 return ret; 5032 } 5033 5034 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5035 bool en_uc, bool en_mc, bool en_bc) 5036 { 5037 struct hclge_vport *vport = &hdev->vport[vf_id]; 5038 struct hnae3_handle *handle = &vport->nic; 5039 struct hclge_promisc_cfg_cmd *req; 5040 struct hclge_desc desc; 5041 bool uc_tx_en = en_uc; 5042 u8 promisc_cfg = 0; 5043 int ret; 5044 5045 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5046 5047 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5048 req->vf_id = vf_id; 5049 5050 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5051 uc_tx_en = false; 5052 5053 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5054 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5055 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5056 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5057 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5058 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5059 req->extend_promisc = promisc_cfg; 5060 5061 /* to be compatible with DEVICE_VERSION_V1/2 */ 5062 promisc_cfg = 0; 5063 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5064 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5065 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5066 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5067 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5068 req->promisc = promisc_cfg; 5069 5070 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5071 if (ret) 5072 dev_err(&hdev->pdev->dev, 5073 "failed to set vport %u promisc mode, ret = %d.\n", 5074 vf_id, ret); 5075 5076 return ret; 5077 } 5078 5079 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5080 bool en_mc_pmc, bool en_bc_pmc) 5081 { 5082 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5083 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5084 } 5085 5086 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5087 bool en_mc_pmc) 5088 { 5089 struct hclge_vport *vport = hclge_get_vport(handle); 5090 struct hclge_dev *hdev = vport->back; 5091 bool en_bc_pmc = true; 5092 5093 /* For device whose version below V2, if broadcast promisc enabled, 5094 * vlan filter is always bypassed. So broadcast promisc should be 5095 * disabled until user enable promisc mode 5096 */ 5097 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5098 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5099 5100 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5101 en_bc_pmc); 5102 } 5103 5104 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5105 { 5106 struct hclge_vport *vport = hclge_get_vport(handle); 5107 5108 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5109 } 5110 5111 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 5112 { 5113 struct hclge_vport *vport = hclge_get_vport(handle); 5114 struct hclge_dev *hdev = vport->back; 5115 5116 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 5117 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 5118 } 5119 5120 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 5121 { 5122 struct hclge_vport *vport = hclge_get_vport(handle); 5123 struct hclge_dev *hdev = vport->back; 5124 5125 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 5126 } 5127 5128 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 5129 { 5130 struct hclge_vport *vport = hclge_get_vport(handle); 5131 struct hclge_dev *hdev = vport->back; 5132 5133 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5134 } 5135 5136 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 5137 { 5138 struct hclge_vport *vport = hclge_get_vport(handle); 5139 struct hclge_dev *hdev = vport->back; 5140 5141 return hdev->rst_stats.hw_reset_done_cnt; 5142 } 5143 5144 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 5145 { 5146 #define HCLGE_LINK_STATUS_WAIT_CNT 3 5147 5148 struct hclge_desc desc; 5149 struct hclge_config_mac_mode_cmd *req = 5150 (struct hclge_config_mac_mode_cmd *)desc.data; 5151 u32 loop_en = 0; 5152 int ret; 5153 5154 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 5155 5156 if (enable) { 5157 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 5158 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 5159 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 5160 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 5161 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 5162 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 5163 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 5164 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 5165 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 5166 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 5167 } 5168 5169 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 5170 5171 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5172 if (ret) { 5173 dev_err(&hdev->pdev->dev, 5174 "mac enable fail, ret =%d.\n", ret); 5175 return; 5176 } 5177 5178 if (!enable) 5179 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 5180 HCLGE_LINK_STATUS_WAIT_CNT); 5181 } 5182 5183 u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5184 u8 vf_id, u8 network_port_id) 5185 { 5186 u32 port_number = 0; 5187 5188 if (port_type == HOST_PORT) { 5189 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5190 pf_id); 5191 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5192 vf_id); 5193 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5194 } else { 5195 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5196 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5197 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5198 } 5199 5200 return port_number; 5201 } 5202 5203 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 5204 u8 switch_param, u8 param_mask) 5205 { 5206 struct hclge_mac_vlan_switch_cmd *req; 5207 struct hclge_desc desc; 5208 u32 func_id; 5209 int ret; 5210 5211 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 5212 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 5213 5214 /* read current config parameter */ 5215 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 5216 true); 5217 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 5218 req->func_id = cpu_to_le32(func_id); 5219 5220 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5221 if (ret) { 5222 dev_err(&hdev->pdev->dev, 5223 "read mac vlan switch parameter fail, ret = %d\n", ret); 5224 return ret; 5225 } 5226 5227 /* modify and write new config parameter */ 5228 hclge_comm_cmd_reuse_desc(&desc, false); 5229 req->switch_param = (req->switch_param & param_mask) | switch_param; 5230 req->param_mask = param_mask; 5231 5232 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5233 if (ret) 5234 dev_err(&hdev->pdev->dev, 5235 "set mac vlan switch parameter fail, ret = %d\n", ret); 5236 return ret; 5237 } 5238 5239 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 5240 int link_ret) 5241 { 5242 #define HCLGE_PHY_LINK_STATUS_NUM 200 5243 5244 struct phy_device *phydev = hdev->hw.mac.phydev; 5245 int i = 0; 5246 int ret; 5247 5248 do { 5249 ret = phy_read_status(phydev); 5250 if (ret) { 5251 dev_err(&hdev->pdev->dev, 5252 "phy update link status fail, ret = %d\n", ret); 5253 return; 5254 } 5255 5256 if (phydev->link == link_ret) 5257 break; 5258 5259 msleep(HCLGE_LINK_STATUS_MS); 5260 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 5261 } 5262 5263 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 5264 int wait_cnt) 5265 { 5266 int link_status; 5267 int i = 0; 5268 int ret; 5269 5270 do { 5271 ret = hclge_get_mac_link_status(hdev, &link_status); 5272 if (ret) 5273 return ret; 5274 if (link_status == link_ret) 5275 return 0; 5276 5277 msleep(HCLGE_LINK_STATUS_MS); 5278 } while (++i < wait_cnt); 5279 return -EBUSY; 5280 } 5281 5282 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 5283 bool is_phy) 5284 { 5285 #define HCLGE_MAC_LINK_STATUS_NUM 100 5286 5287 int link_ret; 5288 5289 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 5290 5291 if (is_phy) 5292 hclge_phy_link_status_wait(hdev, link_ret); 5293 5294 return hclge_mac_link_status_wait(hdev, link_ret, 5295 HCLGE_MAC_LINK_STATUS_NUM); 5296 } 5297 5298 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 5299 { 5300 struct hclge_config_mac_mode_cmd *req; 5301 struct hclge_desc desc; 5302 u32 loop_en; 5303 int ret; 5304 5305 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 5306 /* 1 Read out the MAC mode config at first */ 5307 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 5308 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5309 if (ret) { 5310 dev_err(&hdev->pdev->dev, 5311 "mac loopback get fail, ret =%d.\n", ret); 5312 return ret; 5313 } 5314 5315 /* 2 Then setup the loopback flag */ 5316 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 5317 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 5318 5319 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 5320 5321 /* 3 Config mac work mode with loopback flag 5322 * and its original configure parameters 5323 */ 5324 hclge_comm_cmd_reuse_desc(&desc, false); 5325 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5326 if (ret) 5327 dev_err(&hdev->pdev->dev, 5328 "mac loopback set fail, ret =%d.\n", ret); 5329 return ret; 5330 } 5331 5332 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 5333 enum hnae3_loop loop_mode) 5334 { 5335 struct hclge_common_lb_cmd *req; 5336 struct hclge_desc desc; 5337 u8 loop_mode_b; 5338 int ret; 5339 5340 req = (struct hclge_common_lb_cmd *)desc.data; 5341 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 5342 5343 switch (loop_mode) { 5344 case HNAE3_LOOP_SERIAL_SERDES: 5345 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 5346 break; 5347 case HNAE3_LOOP_PARALLEL_SERDES: 5348 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 5349 break; 5350 case HNAE3_LOOP_PHY: 5351 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 5352 break; 5353 default: 5354 dev_err(&hdev->pdev->dev, 5355 "unsupported loopback mode %d\n", loop_mode); 5356 return -ENOTSUPP; 5357 } 5358 5359 req->mask = loop_mode_b; 5360 if (en) 5361 req->enable = loop_mode_b; 5362 5363 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5364 if (ret) 5365 dev_err(&hdev->pdev->dev, 5366 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 5367 loop_mode, ret); 5368 5369 return ret; 5370 } 5371 5372 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 5373 { 5374 #define HCLGE_COMMON_LB_RETRY_MS 10 5375 #define HCLGE_COMMON_LB_RETRY_NUM 100 5376 5377 struct hclge_common_lb_cmd *req; 5378 struct hclge_desc desc; 5379 u32 i = 0; 5380 int ret; 5381 5382 req = (struct hclge_common_lb_cmd *)desc.data; 5383 5384 do { 5385 msleep(HCLGE_COMMON_LB_RETRY_MS); 5386 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 5387 true); 5388 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5389 if (ret) { 5390 dev_err(&hdev->pdev->dev, 5391 "failed to get loopback done status, ret = %d\n", 5392 ret); 5393 return ret; 5394 } 5395 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 5396 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 5397 5398 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 5399 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 5400 return -EBUSY; 5401 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 5402 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 5403 return -EIO; 5404 } 5405 5406 return 0; 5407 } 5408 5409 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 5410 enum hnae3_loop loop_mode) 5411 { 5412 int ret; 5413 5414 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 5415 if (ret) 5416 return ret; 5417 5418 return hclge_cfg_common_loopback_wait(hdev); 5419 } 5420 5421 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 5422 enum hnae3_loop loop_mode) 5423 { 5424 int ret; 5425 5426 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 5427 if (ret) 5428 return ret; 5429 5430 hclge_cfg_mac_mode(hdev, en); 5431 5432 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 5433 if (ret) 5434 dev_err(&hdev->pdev->dev, 5435 "serdes loopback config mac mode timeout\n"); 5436 5437 return ret; 5438 } 5439 5440 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 5441 struct phy_device *phydev) 5442 { 5443 int ret; 5444 5445 if (!phydev->suspended) { 5446 ret = phy_suspend(phydev); 5447 if (ret) 5448 return ret; 5449 } 5450 5451 ret = phy_resume(phydev); 5452 if (ret) 5453 return ret; 5454 5455 return phy_loopback(phydev, true, 0); 5456 } 5457 5458 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 5459 struct phy_device *phydev) 5460 { 5461 int ret; 5462 5463 ret = phy_loopback(phydev, false, 0); 5464 if (ret) 5465 return ret; 5466 5467 return phy_suspend(phydev); 5468 } 5469 5470 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 5471 { 5472 struct phy_device *phydev = hdev->hw.mac.phydev; 5473 int ret; 5474 5475 if (!phydev) { 5476 if (hnae3_dev_phy_imp_supported(hdev)) 5477 return hclge_set_common_loopback(hdev, en, 5478 HNAE3_LOOP_PHY); 5479 return -ENOTSUPP; 5480 } 5481 5482 if (en) 5483 ret = hclge_enable_phy_loopback(hdev, phydev); 5484 else 5485 ret = hclge_disable_phy_loopback(hdev, phydev); 5486 if (ret) { 5487 dev_err(&hdev->pdev->dev, 5488 "set phy loopback fail, ret = %d\n", ret); 5489 return ret; 5490 } 5491 5492 hclge_cfg_mac_mode(hdev, en); 5493 5494 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 5495 if (ret) 5496 dev_err(&hdev->pdev->dev, 5497 "phy loopback config mac mode timeout\n"); 5498 5499 return ret; 5500 } 5501 5502 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 5503 u16 stream_id, bool enable) 5504 { 5505 struct hclge_desc desc; 5506 struct hclge_cfg_com_tqp_queue_cmd *req = 5507 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 5508 5509 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 5510 req->tqp_id = cpu_to_le16(tqp_id); 5511 req->stream_id = cpu_to_le16(stream_id); 5512 if (enable) 5513 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 5514 5515 return hclge_cmd_send(&hdev->hw, &desc, 1); 5516 } 5517 5518 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 5519 { 5520 struct hclge_vport *vport = hclge_get_vport(handle); 5521 struct hclge_dev *hdev = vport->back; 5522 int ret; 5523 u16 i; 5524 5525 for (i = 0; i < handle->kinfo.num_tqps; i++) { 5526 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 5527 if (ret) 5528 return ret; 5529 } 5530 return 0; 5531 } 5532 5533 static int hclge_set_loopback(struct hnae3_handle *handle, 5534 enum hnae3_loop loop_mode, bool en) 5535 { 5536 struct hclge_vport *vport = hclge_get_vport(handle); 5537 struct hclge_dev *hdev = vport->back; 5538 int ret = 0; 5539 5540 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 5541 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 5542 * the same, the packets are looped back in the SSU. If SSU loopback 5543 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 5544 */ 5545 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 5546 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 5547 5548 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 5549 HCLGE_SWITCH_ALW_LPBK_MASK); 5550 if (ret) 5551 return ret; 5552 } 5553 5554 switch (loop_mode) { 5555 case HNAE3_LOOP_APP: 5556 ret = hclge_set_app_loopback(hdev, en); 5557 break; 5558 case HNAE3_LOOP_SERIAL_SERDES: 5559 case HNAE3_LOOP_PARALLEL_SERDES: 5560 ret = hclge_set_common_loopback(hdev, en, loop_mode); 5561 break; 5562 case HNAE3_LOOP_PHY: 5563 ret = hclge_set_phy_loopback(hdev, en); 5564 break; 5565 case HNAE3_LOOP_EXTERNAL: 5566 break; 5567 default: 5568 ret = -ENOTSUPP; 5569 dev_err(&hdev->pdev->dev, 5570 "loop_mode %d is not supported\n", loop_mode); 5571 break; 5572 } 5573 5574 if (ret) 5575 return ret; 5576 5577 ret = hclge_tqp_enable(handle, en); 5578 if (ret) 5579 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 5580 str_enable_disable(en), ret); 5581 5582 return ret; 5583 } 5584 5585 static int hclge_set_default_loopback(struct hclge_dev *hdev) 5586 { 5587 int ret; 5588 5589 ret = hclge_set_app_loopback(hdev, false); 5590 if (ret) 5591 return ret; 5592 5593 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 5594 if (ret) 5595 return ret; 5596 5597 return hclge_cfg_common_loopback(hdev, false, 5598 HNAE3_LOOP_PARALLEL_SERDES); 5599 } 5600 5601 static void hclge_flush_link_update(struct hclge_dev *hdev) 5602 { 5603 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 5604 5605 unsigned long last = hdev->serv_processed_cnt; 5606 int i = 0; 5607 5608 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 5609 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 5610 last == hdev->serv_processed_cnt) 5611 usleep_range(1, 1); 5612 } 5613 5614 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 5615 { 5616 struct hclge_vport *vport = hclge_get_vport(handle); 5617 struct hclge_dev *hdev = vport->back; 5618 5619 if (enable) { 5620 hclge_task_schedule(hdev, 0); 5621 } else { 5622 /* Set the DOWN flag here to disable link updating */ 5623 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5624 5625 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 5626 hclge_flush_link_update(hdev); 5627 } 5628 } 5629 5630 static int hclge_ae_start(struct hnae3_handle *handle) 5631 { 5632 struct hclge_vport *vport = hclge_get_vport(handle); 5633 struct hclge_dev *hdev = vport->back; 5634 5635 /* mac enable */ 5636 hclge_cfg_mac_mode(hdev, true); 5637 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 5638 hdev->hw.mac.link = 0; 5639 5640 /* reset tqp stats */ 5641 hclge_comm_reset_tqp_stats(handle); 5642 5643 hclge_mac_start_phy(hdev); 5644 5645 return 0; 5646 } 5647 5648 static void hclge_ae_stop(struct hnae3_handle *handle) 5649 { 5650 struct hclge_vport *vport = hclge_get_vport(handle); 5651 struct hclge_dev *hdev = vport->back; 5652 5653 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5654 spin_lock_bh(&hdev->fd_rule_lock); 5655 hclge_clear_arfs_rules(hdev); 5656 spin_unlock_bh(&hdev->fd_rule_lock); 5657 5658 /* If it is not PF reset or FLR, the firmware will disable the MAC, 5659 * so it only need to stop phy here. 5660 */ 5661 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 5662 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 5663 HCLGE_PFC_DISABLE); 5664 if (hdev->reset_type != HNAE3_FUNC_RESET && 5665 hdev->reset_type != HNAE3_FLR_RESET) { 5666 hclge_mac_stop_phy(hdev); 5667 hclge_update_link_status(hdev); 5668 return; 5669 } 5670 } 5671 5672 hclge_reset_tqp(handle); 5673 5674 hclge_config_mac_tnl_int(hdev, false); 5675 5676 /* Mac disable */ 5677 hclge_cfg_mac_mode(hdev, false); 5678 5679 hclge_mac_stop_phy(hdev); 5680 5681 /* reset tqp stats */ 5682 hclge_comm_reset_tqp_stats(handle); 5683 hclge_update_link_status(hdev); 5684 } 5685 5686 int hclge_vport_start(struct hclge_vport *vport) 5687 { 5688 struct hclge_dev *hdev = vport->back; 5689 5690 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 5691 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 5692 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5693 vport->last_active_jiffies = jiffies; 5694 vport->need_notify = 0; 5695 5696 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 5697 if (vport->vport_id) { 5698 hclge_restore_mac_table_common(vport); 5699 hclge_restore_vport_vlan_table(vport); 5700 } else { 5701 hclge_restore_hw_table(hdev); 5702 } 5703 } 5704 5705 clear_bit(vport->vport_id, hdev->vport_config_block); 5706 5707 return 0; 5708 } 5709 5710 void hclge_vport_stop(struct hclge_vport *vport) 5711 { 5712 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 5713 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 5714 vport->need_notify = 0; 5715 } 5716 5717 static int hclge_client_start(struct hnae3_handle *handle) 5718 { 5719 struct hclge_vport *vport = hclge_get_vport(handle); 5720 5721 return hclge_vport_start(vport); 5722 } 5723 5724 static void hclge_client_stop(struct hnae3_handle *handle) 5725 { 5726 struct hclge_vport *vport = hclge_get_vport(handle); 5727 5728 hclge_vport_stop(vport); 5729 } 5730 5731 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 5732 u16 cmdq_resp, u8 resp_code, 5733 enum hclge_mac_vlan_tbl_opcode op) 5734 { 5735 struct hclge_dev *hdev = vport->back; 5736 5737 if (cmdq_resp) { 5738 dev_err(&hdev->pdev->dev, 5739 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 5740 cmdq_resp); 5741 return -EIO; 5742 } 5743 5744 if (op == HCLGE_MAC_VLAN_ADD) { 5745 if (!resp_code || resp_code == 1) 5746 return 0; 5747 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 5748 resp_code == HCLGE_ADD_MC_OVERFLOW) 5749 return -ENOSPC; 5750 5751 dev_err(&hdev->pdev->dev, 5752 "add mac addr failed for undefined, code=%u.\n", 5753 resp_code); 5754 return -EIO; 5755 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 5756 if (!resp_code) { 5757 return 0; 5758 } else if (resp_code == 1) { 5759 dev_dbg(&hdev->pdev->dev, 5760 "remove mac addr failed for miss.\n"); 5761 return -ENOENT; 5762 } 5763 5764 dev_err(&hdev->pdev->dev, 5765 "remove mac addr failed for undefined, code=%u.\n", 5766 resp_code); 5767 return -EIO; 5768 } else if (op == HCLGE_MAC_VLAN_LKUP) { 5769 if (!resp_code) { 5770 return 0; 5771 } else if (resp_code == 1) { 5772 dev_dbg(&hdev->pdev->dev, 5773 "lookup mac addr failed for miss.\n"); 5774 return -ENOENT; 5775 } 5776 5777 dev_err(&hdev->pdev->dev, 5778 "lookup mac addr failed for undefined, code=%u.\n", 5779 resp_code); 5780 return -EIO; 5781 } 5782 5783 dev_err(&hdev->pdev->dev, 5784 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 5785 5786 return -EINVAL; 5787 } 5788 5789 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 5790 { 5791 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 5792 5793 unsigned int word_num; 5794 unsigned int bit_num; 5795 5796 if (vfid > 255 || vfid < 0) 5797 return -EIO; 5798 5799 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 5800 word_num = vfid / 32; 5801 bit_num = vfid % 32; 5802 if (clr) 5803 desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 5804 else 5805 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 5806 } else { 5807 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 5808 bit_num = vfid % 32; 5809 if (clr) 5810 desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 5811 else 5812 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 5813 } 5814 5815 return 0; 5816 } 5817 5818 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 5819 { 5820 #define HCLGE_DESC_NUMBER 3 5821 #define HCLGE_FUNC_NUMBER_PER_DESC 6 5822 int i, j; 5823 5824 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 5825 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 5826 if (desc[i].data[j]) 5827 return false; 5828 5829 return true; 5830 } 5831 5832 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 5833 const u8 *addr, bool is_mc) 5834 { 5835 const unsigned char *mac_addr = addr; 5836 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 5837 (mac_addr[0]) | (mac_addr[1] << 8); 5838 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 5839 5840 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5841 if (is_mc) { 5842 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 5843 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5844 } 5845 5846 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 5847 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 5848 } 5849 5850 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 5851 struct hclge_mac_vlan_tbl_entry_cmd *req) 5852 { 5853 struct hclge_dev *hdev = vport->back; 5854 struct hclge_desc desc; 5855 u8 resp_code; 5856 u16 retval; 5857 int ret; 5858 5859 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 5860 5861 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5862 5863 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5864 if (ret) { 5865 dev_err(&hdev->pdev->dev, 5866 "del mac addr failed for cmd_send, ret =%d.\n", 5867 ret); 5868 return ret; 5869 } 5870 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 5871 retval = le16_to_cpu(desc.retval); 5872 5873 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 5874 HCLGE_MAC_VLAN_REMOVE); 5875 } 5876 5877 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 5878 struct hclge_mac_vlan_tbl_entry_cmd *req, 5879 struct hclge_desc *desc, 5880 bool is_mc) 5881 { 5882 struct hclge_dev *hdev = vport->back; 5883 u8 resp_code; 5884 u16 retval; 5885 int ret; 5886 5887 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 5888 if (is_mc) { 5889 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5890 memcpy(desc[0].data, 5891 req, 5892 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5893 hclge_cmd_setup_basic_desc(&desc[1], 5894 HCLGE_OPC_MAC_VLAN_ADD, 5895 true); 5896 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5897 hclge_cmd_setup_basic_desc(&desc[2], 5898 HCLGE_OPC_MAC_VLAN_ADD, 5899 true); 5900 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5901 } else { 5902 memcpy(desc[0].data, 5903 req, 5904 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5905 ret = hclge_cmd_send(&hdev->hw, desc, 1); 5906 } 5907 if (ret) { 5908 dev_err(&hdev->pdev->dev, 5909 "lookup mac addr failed for cmd_send, ret =%d.\n", 5910 ret); 5911 return ret; 5912 } 5913 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 5914 retval = le16_to_cpu(desc[0].retval); 5915 5916 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 5917 HCLGE_MAC_VLAN_LKUP); 5918 } 5919 5920 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 5921 struct hclge_mac_vlan_tbl_entry_cmd *req, 5922 struct hclge_desc *mc_desc) 5923 { 5924 struct hclge_dev *hdev = vport->back; 5925 int cfg_status; 5926 u8 resp_code; 5927 u16 retval; 5928 int ret; 5929 5930 if (!mc_desc) { 5931 struct hclge_desc desc; 5932 5933 hclge_cmd_setup_basic_desc(&desc, 5934 HCLGE_OPC_MAC_VLAN_ADD, 5935 false); 5936 memcpy(desc.data, req, 5937 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5938 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5939 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 5940 retval = le16_to_cpu(desc.retval); 5941 5942 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 5943 resp_code, 5944 HCLGE_MAC_VLAN_ADD); 5945 } else { 5946 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 5947 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5948 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 5949 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5950 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 5951 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 5952 memcpy(mc_desc[0].data, req, 5953 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5954 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 5955 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 5956 retval = le16_to_cpu(mc_desc[0].retval); 5957 5958 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 5959 resp_code, 5960 HCLGE_MAC_VLAN_ADD); 5961 } 5962 5963 if (ret) { 5964 dev_err(&hdev->pdev->dev, 5965 "add mac addr failed for cmd_send, ret =%d.\n", 5966 ret); 5967 return ret; 5968 } 5969 5970 return cfg_status; 5971 } 5972 5973 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 5974 u16 *allocated_size) 5975 { 5976 struct hclge_umv_spc_alc_cmd *req; 5977 struct hclge_desc desc; 5978 int ret; 5979 5980 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 5981 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 5982 5983 req->space_size = cpu_to_le32(space_size); 5984 5985 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5986 if (ret) { 5987 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 5988 ret); 5989 return ret; 5990 } 5991 5992 *allocated_size = le32_to_cpu(desc.data[1]); 5993 5994 return 0; 5995 } 5996 5997 static int hclge_init_umv_space(struct hclge_dev *hdev) 5998 { 5999 u16 allocated_size = 0; 6000 int ret; 6001 6002 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 6003 if (ret) 6004 return ret; 6005 6006 if (allocated_size < hdev->wanted_umv_size) 6007 dev_warn(&hdev->pdev->dev, 6008 "failed to alloc umv space, want %u, get %u\n", 6009 hdev->wanted_umv_size, allocated_size); 6010 6011 hdev->max_umv_size = allocated_size; 6012 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 6013 hdev->share_umv_size = hdev->priv_umv_size + 6014 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 6015 6016 if (hdev->ae_dev->dev_specs.mc_mac_size) 6017 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 6018 6019 return 0; 6020 } 6021 6022 static void hclge_reset_umv_space(struct hclge_dev *hdev) 6023 { 6024 struct hclge_vport *vport; 6025 int i; 6026 6027 for (i = 0; i < hdev->num_alloc_vport; i++) { 6028 vport = &hdev->vport[i]; 6029 vport->used_umv_num = 0; 6030 } 6031 6032 mutex_lock(&hdev->vport_lock); 6033 hdev->share_umv_size = hdev->priv_umv_size + 6034 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 6035 mutex_unlock(&hdev->vport_lock); 6036 6037 hdev->used_mc_mac_num = 0; 6038 } 6039 6040 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 6041 { 6042 struct hclge_dev *hdev = vport->back; 6043 bool is_full; 6044 6045 if (need_lock) 6046 mutex_lock(&hdev->vport_lock); 6047 6048 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 6049 hdev->share_umv_size == 0); 6050 6051 if (need_lock) 6052 mutex_unlock(&hdev->vport_lock); 6053 6054 return is_full; 6055 } 6056 6057 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 6058 { 6059 struct hclge_dev *hdev = vport->back; 6060 6061 if (is_free) { 6062 if (vport->used_umv_num > hdev->priv_umv_size) 6063 hdev->share_umv_size++; 6064 6065 if (vport->used_umv_num > 0) 6066 vport->used_umv_num--; 6067 } else { 6068 if (vport->used_umv_num >= hdev->priv_umv_size && 6069 hdev->share_umv_size > 0) 6070 hdev->share_umv_size--; 6071 vport->used_umv_num++; 6072 } 6073 } 6074 6075 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 6076 const u8 *mac_addr) 6077 { 6078 struct hclge_mac_node *mac_node, *tmp; 6079 6080 list_for_each_entry_safe(mac_node, tmp, list, node) 6081 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 6082 return mac_node; 6083 6084 return NULL; 6085 } 6086 6087 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 6088 enum HCLGE_MAC_NODE_STATE state) 6089 { 6090 switch (state) { 6091 /* from set_rx_mode or tmp_add_list */ 6092 case HCLGE_MAC_TO_ADD: 6093 if (mac_node->state == HCLGE_MAC_TO_DEL) 6094 mac_node->state = HCLGE_MAC_ACTIVE; 6095 break; 6096 /* only from set_rx_mode */ 6097 case HCLGE_MAC_TO_DEL: 6098 if (mac_node->state == HCLGE_MAC_TO_ADD) { 6099 list_del(&mac_node->node); 6100 kfree(mac_node); 6101 } else { 6102 mac_node->state = HCLGE_MAC_TO_DEL; 6103 } 6104 break; 6105 /* only from tmp_add_list, the mac_node->state won't be 6106 * ACTIVE. 6107 */ 6108 case HCLGE_MAC_ACTIVE: 6109 if (mac_node->state == HCLGE_MAC_TO_ADD) 6110 mac_node->state = HCLGE_MAC_ACTIVE; 6111 6112 break; 6113 } 6114 } 6115 6116 int hclge_update_mac_list(struct hclge_vport *vport, 6117 enum HCLGE_MAC_NODE_STATE state, 6118 enum HCLGE_MAC_ADDR_TYPE mac_type, 6119 const unsigned char *addr) 6120 { 6121 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6122 struct hclge_dev *hdev = vport->back; 6123 struct hclge_mac_node *mac_node; 6124 struct list_head *list; 6125 6126 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6127 &vport->uc_mac_list : &vport->mc_mac_list; 6128 6129 spin_lock_bh(&vport->mac_list_lock); 6130 6131 /* if the mac addr is already in the mac list, no need to add a new 6132 * one into it, just check the mac addr state, convert it to a new 6133 * state, or just remove it, or do nothing. 6134 */ 6135 mac_node = hclge_find_mac_node(list, addr); 6136 if (mac_node) { 6137 hclge_update_mac_node(mac_node, state); 6138 spin_unlock_bh(&vport->mac_list_lock); 6139 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6140 return 0; 6141 } 6142 6143 /* if this address is never added, unnecessary to delete */ 6144 if (state == HCLGE_MAC_TO_DEL) { 6145 spin_unlock_bh(&vport->mac_list_lock); 6146 hnae3_format_mac_addr(format_mac_addr, addr); 6147 dev_err(&hdev->pdev->dev, 6148 "failed to delete address %s from mac list\n", 6149 format_mac_addr); 6150 return -ENOENT; 6151 } 6152 6153 mac_node = kzalloc_obj(*mac_node, GFP_ATOMIC); 6154 if (!mac_node) { 6155 spin_unlock_bh(&vport->mac_list_lock); 6156 return -ENOMEM; 6157 } 6158 6159 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6160 6161 mac_node->state = state; 6162 ether_addr_copy(mac_node->mac_addr, addr); 6163 list_add_tail(&mac_node->node, list); 6164 6165 spin_unlock_bh(&vport->mac_list_lock); 6166 6167 return 0; 6168 } 6169 6170 static int hclge_add_uc_addr(struct hnae3_handle *handle, 6171 const unsigned char *addr) 6172 { 6173 struct hclge_vport *vport = hclge_get_vport(handle); 6174 6175 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 6176 addr); 6177 } 6178 6179 int hclge_add_uc_addr_common(struct hclge_vport *vport, 6180 const unsigned char *addr) 6181 { 6182 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6183 struct hclge_dev *hdev = vport->back; 6184 struct hclge_mac_vlan_tbl_entry_cmd req; 6185 struct hclge_desc desc; 6186 u16 egress_port = 0; 6187 int ret; 6188 6189 /* mac addr check */ 6190 if (is_zero_ether_addr(addr) || 6191 is_broadcast_ether_addr(addr) || 6192 is_multicast_ether_addr(addr)) { 6193 hnae3_format_mac_addr(format_mac_addr, addr); 6194 dev_err(&hdev->pdev->dev, 6195 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 6196 format_mac_addr, is_zero_ether_addr(addr), 6197 is_broadcast_ether_addr(addr), 6198 is_multicast_ether_addr(addr)); 6199 return -EINVAL; 6200 } 6201 6202 memset(&req, 0, sizeof(req)); 6203 6204 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 6205 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 6206 6207 req.egress_port = cpu_to_le16(egress_port); 6208 6209 hclge_prepare_mac_addr(&req, addr, false); 6210 6211 /* Lookup the mac address in the mac_vlan table, and add 6212 * it if the entry is inexistent. Repeated unicast entry 6213 * is not allowed in the mac vlan table. 6214 */ 6215 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 6216 if (ret == -ENOENT) { 6217 mutex_lock(&hdev->vport_lock); 6218 if (!hclge_is_umv_space_full(vport, false)) { 6219 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 6220 if (!ret) 6221 hclge_update_umv_space(vport, false); 6222 mutex_unlock(&hdev->vport_lock); 6223 return ret; 6224 } 6225 mutex_unlock(&hdev->vport_lock); 6226 6227 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 6228 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 6229 hdev->priv_umv_size); 6230 6231 return -ENOSPC; 6232 } 6233 6234 /* check if we just hit the duplicate */ 6235 if (!ret) 6236 return -EEXIST; 6237 6238 return ret; 6239 } 6240 6241 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 6242 const unsigned char *addr) 6243 { 6244 struct hclge_vport *vport = hclge_get_vport(handle); 6245 6246 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 6247 addr); 6248 } 6249 6250 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 6251 const unsigned char *addr) 6252 { 6253 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6254 struct hclge_dev *hdev = vport->back; 6255 struct hclge_mac_vlan_tbl_entry_cmd req; 6256 int ret; 6257 6258 /* mac addr check */ 6259 if (is_zero_ether_addr(addr) || 6260 is_broadcast_ether_addr(addr) || 6261 is_multicast_ether_addr(addr)) { 6262 hnae3_format_mac_addr(format_mac_addr, addr); 6263 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 6264 format_mac_addr); 6265 return -EINVAL; 6266 } 6267 6268 memset(&req, 0, sizeof(req)); 6269 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 6270 hclge_prepare_mac_addr(&req, addr, false); 6271 ret = hclge_remove_mac_vlan_tbl(vport, &req); 6272 if (!ret || ret == -ENOENT) { 6273 mutex_lock(&hdev->vport_lock); 6274 hclge_update_umv_space(vport, true); 6275 mutex_unlock(&hdev->vport_lock); 6276 return 0; 6277 } 6278 6279 return ret; 6280 } 6281 6282 static int hclge_add_mc_addr(struct hnae3_handle *handle, 6283 const unsigned char *addr) 6284 { 6285 struct hclge_vport *vport = hclge_get_vport(handle); 6286 6287 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 6288 addr); 6289 } 6290 6291 int hclge_add_mc_addr_common(struct hclge_vport *vport, 6292 const unsigned char *addr) 6293 { 6294 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6295 struct hclge_dev *hdev = vport->back; 6296 struct hclge_mac_vlan_tbl_entry_cmd req; 6297 struct hclge_desc desc[3]; 6298 bool is_new_addr = false; 6299 int status; 6300 6301 /* mac addr check */ 6302 if (!is_multicast_ether_addr(addr)) { 6303 hnae3_format_mac_addr(format_mac_addr, addr); 6304 dev_err(&hdev->pdev->dev, 6305 "Add mc mac err! invalid mac:%s.\n", 6306 format_mac_addr); 6307 return -EINVAL; 6308 } 6309 memset(&req, 0, sizeof(req)); 6310 hclge_prepare_mac_addr(&req, addr, true); 6311 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 6312 if (status) { 6313 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 6314 hdev->used_mc_mac_num >= 6315 hdev->ae_dev->dev_specs.mc_mac_size) 6316 goto err_no_space; 6317 6318 is_new_addr = true; 6319 6320 /* This mac addr do not exist, add new entry for it */ 6321 memset(desc[0].data, 0, sizeof(desc[0].data)); 6322 memset(desc[1].data, 0, sizeof(desc[0].data)); 6323 memset(desc[2].data, 0, sizeof(desc[0].data)); 6324 } 6325 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 6326 if (status) 6327 return status; 6328 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 6329 if (status == -ENOSPC) 6330 goto err_no_space; 6331 else if (!status && is_new_addr) 6332 hdev->used_mc_mac_num++; 6333 6334 return status; 6335 6336 err_no_space: 6337 /* if already overflow, not to print each time */ 6338 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 6339 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 6340 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 6341 } 6342 6343 return -ENOSPC; 6344 } 6345 6346 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 6347 const unsigned char *addr) 6348 { 6349 struct hclge_vport *vport = hclge_get_vport(handle); 6350 6351 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 6352 addr); 6353 } 6354 6355 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 6356 const unsigned char *addr) 6357 { 6358 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6359 struct hclge_dev *hdev = vport->back; 6360 struct hclge_mac_vlan_tbl_entry_cmd req; 6361 enum hclge_comm_cmd_status status; 6362 struct hclge_desc desc[3]; 6363 6364 /* mac addr check */ 6365 if (!is_multicast_ether_addr(addr)) { 6366 hnae3_format_mac_addr(format_mac_addr, addr); 6367 dev_dbg(&hdev->pdev->dev, 6368 "Remove mc mac err! invalid mac:%s.\n", 6369 format_mac_addr); 6370 return -EINVAL; 6371 } 6372 6373 memset(&req, 0, sizeof(req)); 6374 hclge_prepare_mac_addr(&req, addr, true); 6375 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 6376 if (!status) { 6377 /* This mac addr exist, remove this handle's VFID for it */ 6378 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 6379 if (status) 6380 return status; 6381 6382 if (hclge_is_all_function_id_zero(desc)) { 6383 /* All the vfid is zero, so need to delete this entry */ 6384 status = hclge_remove_mac_vlan_tbl(vport, &req); 6385 if (!status) 6386 hdev->used_mc_mac_num--; 6387 } else { 6388 /* Not all the vfid is zero, update the vfid */ 6389 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 6390 } 6391 } else if (status == -ENOENT) { 6392 status = 0; 6393 } 6394 6395 return status; 6396 } 6397 6398 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 6399 struct list_head *list, 6400 enum HCLGE_MAC_ADDR_TYPE mac_type) 6401 { 6402 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 6403 struct hclge_mac_node *mac_node, *tmp; 6404 int ret; 6405 6406 if (mac_type == HCLGE_MAC_ADDR_UC) 6407 sync = hclge_add_uc_addr_common; 6408 else 6409 sync = hclge_add_mc_addr_common; 6410 6411 list_for_each_entry_safe(mac_node, tmp, list, node) { 6412 ret = sync(vport, mac_node->mac_addr); 6413 if (!ret) { 6414 mac_node->state = HCLGE_MAC_ACTIVE; 6415 } else { 6416 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 6417 &vport->state); 6418 6419 /* If one unicast mac address is existing in hardware, 6420 * we need to try whether other unicast mac addresses 6421 * are new addresses that can be added. 6422 * Multicast mac address can be reusable, even though 6423 * there is no space to add new multicast mac address, 6424 * we should check whether other mac addresses are 6425 * existing in hardware for reuse. 6426 */ 6427 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 6428 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 6429 break; 6430 } 6431 } 6432 } 6433 6434 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 6435 struct list_head *list, 6436 enum HCLGE_MAC_ADDR_TYPE mac_type) 6437 { 6438 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 6439 struct hclge_mac_node *mac_node, *tmp; 6440 int ret; 6441 6442 if (mac_type == HCLGE_MAC_ADDR_UC) 6443 unsync = hclge_rm_uc_addr_common; 6444 else 6445 unsync = hclge_rm_mc_addr_common; 6446 6447 list_for_each_entry_safe(mac_node, tmp, list, node) { 6448 ret = unsync(vport, mac_node->mac_addr); 6449 if (!ret || ret == -ENOENT) { 6450 list_del(&mac_node->node); 6451 kfree(mac_node); 6452 } else { 6453 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 6454 &vport->state); 6455 break; 6456 } 6457 } 6458 } 6459 6460 static bool hclge_sync_from_add_list(struct list_head *add_list, 6461 struct list_head *mac_list) 6462 { 6463 struct hclge_mac_node *mac_node, *tmp, *new_node; 6464 bool all_added = true; 6465 6466 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 6467 if (mac_node->state == HCLGE_MAC_TO_ADD) 6468 all_added = false; 6469 6470 /* if the mac address from tmp_add_list is not in the 6471 * uc/mc_mac_list, it means have received a TO_DEL request 6472 * during the time window of adding the mac address into mac 6473 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 6474 * then it will be removed at next time. else it must be TO_ADD, 6475 * this address hasn't been added into mac table, 6476 * so just remove the mac node. 6477 */ 6478 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 6479 if (new_node) { 6480 hclge_update_mac_node(new_node, mac_node->state); 6481 list_del(&mac_node->node); 6482 kfree(mac_node); 6483 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 6484 mac_node->state = HCLGE_MAC_TO_DEL; 6485 list_move_tail(&mac_node->node, mac_list); 6486 } else { 6487 list_del(&mac_node->node); 6488 kfree(mac_node); 6489 } 6490 } 6491 6492 return all_added; 6493 } 6494 6495 static void hclge_sync_from_del_list(struct list_head *del_list, 6496 struct list_head *mac_list) 6497 { 6498 struct hclge_mac_node *mac_node, *tmp, *new_node; 6499 6500 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 6501 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 6502 if (new_node) { 6503 /* If the mac addr exists in the mac list, it means 6504 * received a new TO_ADD request during the time window 6505 * of configuring the mac address. For the mac node 6506 * state is TO_ADD, and the address is already in the 6507 * in the hardware(due to delete fail), so we just need 6508 * to change the mac node state to ACTIVE. 6509 */ 6510 new_node->state = HCLGE_MAC_ACTIVE; 6511 list_del(&mac_node->node); 6512 kfree(mac_node); 6513 } else { 6514 list_move_tail(&mac_node->node, mac_list); 6515 } 6516 } 6517 } 6518 6519 static void hclge_update_overflow_flags(struct hclge_vport *vport, 6520 enum HCLGE_MAC_ADDR_TYPE mac_type, 6521 bool is_all_added) 6522 { 6523 if (mac_type == HCLGE_MAC_ADDR_UC) { 6524 if (is_all_added) 6525 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 6526 else if (hclge_is_umv_space_full(vport, true)) 6527 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 6528 } else { 6529 if (is_all_added) 6530 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 6531 else 6532 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 6533 } 6534 } 6535 6536 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 6537 enum HCLGE_MAC_ADDR_TYPE mac_type) 6538 { 6539 struct hclge_mac_node *mac_node, *tmp, *new_node; 6540 struct list_head tmp_add_list, tmp_del_list; 6541 struct list_head *list; 6542 bool all_added; 6543 6544 INIT_LIST_HEAD(&tmp_add_list); 6545 INIT_LIST_HEAD(&tmp_del_list); 6546 6547 /* move the mac addr to the tmp_add_list and tmp_del_list, then 6548 * we can add/delete these mac addr outside the spin lock 6549 */ 6550 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6551 &vport->uc_mac_list : &vport->mc_mac_list; 6552 6553 spin_lock_bh(&vport->mac_list_lock); 6554 6555 list_for_each_entry_safe(mac_node, tmp, list, node) { 6556 switch (mac_node->state) { 6557 case HCLGE_MAC_TO_DEL: 6558 list_move_tail(&mac_node->node, &tmp_del_list); 6559 break; 6560 case HCLGE_MAC_TO_ADD: 6561 new_node = kzalloc_obj(*new_node, GFP_ATOMIC); 6562 if (!new_node) 6563 goto stop_traverse; 6564 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 6565 new_node->state = mac_node->state; 6566 list_add_tail(&new_node->node, &tmp_add_list); 6567 break; 6568 default: 6569 break; 6570 } 6571 } 6572 6573 stop_traverse: 6574 spin_unlock_bh(&vport->mac_list_lock); 6575 6576 /* delete first, in order to get max mac table space for adding */ 6577 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 6578 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 6579 6580 /* if some mac addresses were added/deleted fail, move back to the 6581 * mac_list, and retry at next time. 6582 */ 6583 spin_lock_bh(&vport->mac_list_lock); 6584 6585 hclge_sync_from_del_list(&tmp_del_list, list); 6586 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 6587 6588 spin_unlock_bh(&vport->mac_list_lock); 6589 6590 hclge_update_overflow_flags(vport, mac_type, all_added); 6591 } 6592 6593 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 6594 { 6595 struct hclge_dev *hdev = vport->back; 6596 6597 if (test_bit(vport->vport_id, hdev->vport_config_block)) 6598 return false; 6599 6600 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 6601 return true; 6602 6603 return false; 6604 } 6605 6606 static void hclge_sync_mac_table(struct hclge_dev *hdev) 6607 { 6608 int i; 6609 6610 for (i = 0; i < hdev->num_alloc_vport; i++) { 6611 struct hclge_vport *vport = &hdev->vport[i]; 6612 6613 if (!hclge_need_sync_mac_table(vport)) 6614 continue; 6615 6616 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 6617 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 6618 } 6619 } 6620 6621 static void hclge_build_del_list(struct list_head *list, 6622 bool is_del_list, 6623 struct list_head *tmp_del_list) 6624 { 6625 struct hclge_mac_node *mac_cfg, *tmp; 6626 6627 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 6628 switch (mac_cfg->state) { 6629 case HCLGE_MAC_TO_DEL: 6630 case HCLGE_MAC_ACTIVE: 6631 list_move_tail(&mac_cfg->node, tmp_del_list); 6632 break; 6633 case HCLGE_MAC_TO_ADD: 6634 if (is_del_list) { 6635 list_del(&mac_cfg->node); 6636 kfree(mac_cfg); 6637 } 6638 break; 6639 } 6640 } 6641 } 6642 6643 static void hclge_unsync_del_list(struct hclge_vport *vport, 6644 int (*unsync)(struct hclge_vport *vport, 6645 const unsigned char *addr), 6646 bool is_del_list, 6647 struct list_head *tmp_del_list) 6648 { 6649 struct hclge_mac_node *mac_cfg, *tmp; 6650 int ret; 6651 6652 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 6653 ret = unsync(vport, mac_cfg->mac_addr); 6654 if (!ret || ret == -ENOENT) { 6655 /* clear all mac addr from hardware, but remain these 6656 * mac addr in the mac list, and restore them after 6657 * vf reset finished. 6658 */ 6659 if (!is_del_list && 6660 mac_cfg->state == HCLGE_MAC_ACTIVE) { 6661 mac_cfg->state = HCLGE_MAC_TO_ADD; 6662 } else { 6663 list_del(&mac_cfg->node); 6664 kfree(mac_cfg); 6665 } 6666 } else if (is_del_list) { 6667 mac_cfg->state = HCLGE_MAC_TO_DEL; 6668 } 6669 } 6670 } 6671 6672 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 6673 enum HCLGE_MAC_ADDR_TYPE mac_type) 6674 { 6675 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 6676 struct hclge_dev *hdev = vport->back; 6677 struct list_head tmp_del_list, *list; 6678 6679 if (mac_type == HCLGE_MAC_ADDR_UC) { 6680 list = &vport->uc_mac_list; 6681 unsync = hclge_rm_uc_addr_common; 6682 } else { 6683 list = &vport->mc_mac_list; 6684 unsync = hclge_rm_mc_addr_common; 6685 } 6686 6687 INIT_LIST_HEAD(&tmp_del_list); 6688 6689 if (!is_del_list) 6690 set_bit(vport->vport_id, hdev->vport_config_block); 6691 6692 spin_lock_bh(&vport->mac_list_lock); 6693 6694 hclge_build_del_list(list, is_del_list, &tmp_del_list); 6695 6696 spin_unlock_bh(&vport->mac_list_lock); 6697 6698 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 6699 6700 spin_lock_bh(&vport->mac_list_lock); 6701 6702 hclge_sync_from_del_list(&tmp_del_list, list); 6703 6704 spin_unlock_bh(&vport->mac_list_lock); 6705 } 6706 6707 /* remove all mac address when uninitailize */ 6708 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 6709 enum HCLGE_MAC_ADDR_TYPE mac_type) 6710 { 6711 struct hclge_mac_node *mac_node, *tmp; 6712 struct hclge_dev *hdev = vport->back; 6713 struct list_head tmp_del_list, *list; 6714 6715 INIT_LIST_HEAD(&tmp_del_list); 6716 6717 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6718 &vport->uc_mac_list : &vport->mc_mac_list; 6719 6720 spin_lock_bh(&vport->mac_list_lock); 6721 6722 list_for_each_entry_safe(mac_node, tmp, list, node) { 6723 switch (mac_node->state) { 6724 case HCLGE_MAC_TO_DEL: 6725 case HCLGE_MAC_ACTIVE: 6726 list_move_tail(&mac_node->node, &tmp_del_list); 6727 break; 6728 case HCLGE_MAC_TO_ADD: 6729 list_del(&mac_node->node); 6730 kfree(mac_node); 6731 break; 6732 } 6733 } 6734 6735 spin_unlock_bh(&vport->mac_list_lock); 6736 6737 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 6738 6739 if (!list_empty(&tmp_del_list)) 6740 dev_warn(&hdev->pdev->dev, 6741 "uninit %s mac list for vport %u not completely.\n", 6742 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 6743 vport->vport_id); 6744 6745 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 6746 list_del(&mac_node->node); 6747 kfree(mac_node); 6748 } 6749 } 6750 6751 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 6752 { 6753 struct hclge_vport *vport; 6754 int i; 6755 6756 for (i = 0; i < hdev->num_alloc_vport; i++) { 6757 vport = &hdev->vport[i]; 6758 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 6759 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 6760 } 6761 } 6762 6763 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 6764 u16 cmdq_resp, u8 resp_code) 6765 { 6766 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 6767 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 6768 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 6769 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 6770 6771 int return_status; 6772 6773 if (cmdq_resp) { 6774 dev_err(&hdev->pdev->dev, 6775 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 6776 cmdq_resp); 6777 return -EIO; 6778 } 6779 6780 switch (resp_code) { 6781 case HCLGE_ETHERTYPE_SUCCESS_ADD: 6782 case HCLGE_ETHERTYPE_ALREADY_ADD: 6783 return_status = 0; 6784 break; 6785 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 6786 dev_err(&hdev->pdev->dev, 6787 "add mac ethertype failed for manager table overflow.\n"); 6788 return_status = -EIO; 6789 break; 6790 case HCLGE_ETHERTYPE_KEY_CONFLICT: 6791 dev_err(&hdev->pdev->dev, 6792 "add mac ethertype failed for key conflict.\n"); 6793 return_status = -EIO; 6794 break; 6795 default: 6796 dev_err(&hdev->pdev->dev, 6797 "add mac ethertype failed for undefined, code=%u.\n", 6798 resp_code); 6799 return_status = -EIO; 6800 } 6801 6802 return return_status; 6803 } 6804 6805 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 6806 u8 *mac_addr) 6807 { 6808 struct hclge_vport *vport = hclge_get_vport(handle); 6809 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6810 struct hclge_dev *hdev = vport->back; 6811 6812 vport = hclge_get_vf_vport(hdev, vf); 6813 if (!vport) 6814 return -EINVAL; 6815 6816 hnae3_format_mac_addr(format_mac_addr, mac_addr); 6817 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 6818 dev_info(&hdev->pdev->dev, 6819 "Specified MAC(=%s) is same as before, no change committed!\n", 6820 format_mac_addr); 6821 return 0; 6822 } 6823 6824 ether_addr_copy(vport->vf_info.mac, mac_addr); 6825 6826 /* there is a timewindow for PF to know VF unalive, it may 6827 * cause send mailbox fail, but it doesn't matter, VF will 6828 * query it when reinit. 6829 */ 6830 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 6831 dev_info(&hdev->pdev->dev, 6832 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 6833 vf, format_mac_addr); 6834 (void)hclge_inform_reset_assert_to_vf(vport); 6835 return 0; 6836 } 6837 6838 dev_info(&hdev->pdev->dev, 6839 "MAC of VF %d has been set to %s, will be active after VF reset\n", 6840 vf, format_mac_addr); 6841 return 0; 6842 } 6843 6844 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 6845 const struct hclge_mac_mgr_tbl_entry_cmd *req) 6846 { 6847 struct hclge_desc desc; 6848 u8 resp_code; 6849 u16 retval; 6850 int ret; 6851 6852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 6853 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 6854 6855 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6856 if (ret) { 6857 dev_err(&hdev->pdev->dev, 6858 "add mac ethertype failed for cmd_send, ret =%d.\n", 6859 ret); 6860 return ret; 6861 } 6862 6863 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 6864 retval = le16_to_cpu(desc.retval); 6865 6866 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 6867 } 6868 6869 static int init_mgr_tbl(struct hclge_dev *hdev) 6870 { 6871 int ret; 6872 u32 i; 6873 6874 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 6875 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 6876 if (ret) { 6877 dev_err(&hdev->pdev->dev, 6878 "add mac ethertype failed, ret =%d.\n", 6879 ret); 6880 return ret; 6881 } 6882 } 6883 6884 return 0; 6885 } 6886 6887 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 6888 { 6889 struct hclge_vport *vport = hclge_get_vport(handle); 6890 struct hclge_dev *hdev = vport->back; 6891 6892 ether_addr_copy(p, hdev->hw.mac.mac_addr); 6893 } 6894 6895 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 6896 const u8 *old_addr, const u8 *new_addr) 6897 { 6898 struct list_head *list = &vport->uc_mac_list; 6899 struct hclge_mac_node *old_node, *new_node; 6900 6901 new_node = hclge_find_mac_node(list, new_addr); 6902 if (!new_node) { 6903 new_node = kzalloc_obj(*new_node, GFP_ATOMIC); 6904 if (!new_node) 6905 return -ENOMEM; 6906 6907 new_node->state = HCLGE_MAC_TO_ADD; 6908 ether_addr_copy(new_node->mac_addr, new_addr); 6909 list_add(&new_node->node, list); 6910 } else { 6911 if (new_node->state == HCLGE_MAC_TO_DEL) 6912 new_node->state = HCLGE_MAC_ACTIVE; 6913 6914 /* make sure the new addr is in the list head, avoid dev 6915 * addr may be not re-added into mac table for the umv space 6916 * limitation after global/imp reset which will clear mac 6917 * table by hardware. 6918 */ 6919 list_move(&new_node->node, list); 6920 } 6921 6922 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 6923 old_node = hclge_find_mac_node(list, old_addr); 6924 if (old_node) { 6925 if (old_node->state == HCLGE_MAC_TO_ADD) { 6926 list_del(&old_node->node); 6927 kfree(old_node); 6928 } else { 6929 old_node->state = HCLGE_MAC_TO_DEL; 6930 } 6931 } 6932 } 6933 6934 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6935 6936 return 0; 6937 } 6938 6939 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 6940 bool is_first) 6941 { 6942 const unsigned char *new_addr = (const unsigned char *)p; 6943 struct hclge_vport *vport = hclge_get_vport(handle); 6944 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6945 struct hclge_dev *hdev = vport->back; 6946 unsigned char *old_addr = NULL; 6947 int ret; 6948 6949 /* mac addr check */ 6950 if (is_zero_ether_addr(new_addr) || 6951 is_broadcast_ether_addr(new_addr) || 6952 is_multicast_ether_addr(new_addr)) { 6953 hnae3_format_mac_addr(format_mac_addr, new_addr); 6954 dev_err(&hdev->pdev->dev, 6955 "change uc mac err! invalid mac: %s.\n", 6956 format_mac_addr); 6957 return -EINVAL; 6958 } 6959 6960 ret = hclge_pause_addr_cfg(hdev, new_addr); 6961 if (ret) { 6962 dev_err(&hdev->pdev->dev, 6963 "failed to configure mac pause address, ret = %d\n", 6964 ret); 6965 return ret; 6966 } 6967 6968 if (!is_first) 6969 old_addr = hdev->hw.mac.mac_addr; 6970 6971 spin_lock_bh(&vport->mac_list_lock); 6972 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 6973 if (ret) { 6974 hnae3_format_mac_addr(format_mac_addr, new_addr); 6975 dev_err(&hdev->pdev->dev, 6976 "failed to change the mac addr:%s, ret = %d\n", 6977 format_mac_addr, ret); 6978 spin_unlock_bh(&vport->mac_list_lock); 6979 6980 if (!is_first) 6981 hclge_pause_addr_cfg(hdev, old_addr); 6982 6983 return ret; 6984 } 6985 /* we must update dev addr with spin lock protect, preventing dev addr 6986 * being removed by set_rx_mode path. 6987 */ 6988 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 6989 spin_unlock_bh(&vport->mac_list_lock); 6990 6991 hclge_task_schedule(hdev, 0); 6992 6993 return 0; 6994 } 6995 6996 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 6997 { 6998 struct mii_ioctl_data *data = if_mii(ifr); 6999 7000 if (!hnae3_dev_phy_imp_supported(hdev)) 7001 return -EOPNOTSUPP; 7002 7003 switch (cmd) { 7004 case SIOCGMIIPHY: 7005 data->phy_id = hdev->hw.mac.phy_addr; 7006 /* this command reads phy id and register at the same time */ 7007 fallthrough; 7008 case SIOCGMIIREG: 7009 return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out); 7010 7011 case SIOCSMIIREG: 7012 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 7013 default: 7014 return -EOPNOTSUPP; 7015 } 7016 } 7017 7018 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 7019 int cmd) 7020 { 7021 struct hclge_vport *vport = hclge_get_vport(handle); 7022 struct hclge_dev *hdev = vport->back; 7023 7024 if (!hdev->hw.mac.phydev) 7025 return hclge_mii_ioctl(hdev, ifr, cmd); 7026 7027 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 7028 } 7029 7030 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 7031 bool bypass_en) 7032 { 7033 struct hclge_port_vlan_filter_bypass_cmd *req; 7034 struct hclge_desc desc; 7035 int ret; 7036 7037 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 7038 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 7039 req->vf_id = vf_id; 7040 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 7041 bypass_en ? 1 : 0); 7042 7043 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7044 if (ret) 7045 dev_err(&hdev->pdev->dev, 7046 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 7047 vf_id, ret); 7048 7049 return ret; 7050 } 7051 7052 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 7053 u8 fe_type, bool filter_en, u8 vf_id) 7054 { 7055 struct hclge_vlan_filter_ctrl_cmd *req; 7056 struct hclge_desc desc; 7057 int ret; 7058 7059 /* read current vlan filter parameter */ 7060 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 7061 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 7062 req->vlan_type = vlan_type; 7063 req->vf_id = vf_id; 7064 7065 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7066 if (ret) { 7067 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 7068 vf_id, ret); 7069 return ret; 7070 } 7071 7072 /* modify and write new config parameter */ 7073 hclge_comm_cmd_reuse_desc(&desc, false); 7074 req->vlan_fe = filter_en ? 7075 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 7076 7077 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7078 if (ret) 7079 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 7080 vf_id, ret); 7081 7082 return ret; 7083 } 7084 7085 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 7086 { 7087 struct hclge_dev *hdev = vport->back; 7088 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 7089 int ret; 7090 7091 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 7092 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7093 HCLGE_FILTER_FE_EGRESS_V1_B, 7094 enable, vport->vport_id); 7095 7096 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7097 HCLGE_FILTER_FE_EGRESS, enable, 7098 vport->vport_id); 7099 if (ret) 7100 return ret; 7101 7102 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 7103 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 7104 !enable); 7105 } else if (!vport->vport_id) { 7106 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 7107 enable = false; 7108 7109 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 7110 HCLGE_FILTER_FE_INGRESS, 7111 enable, 0); 7112 } 7113 7114 return ret; 7115 } 7116 7117 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 7118 { 7119 struct hnae3_handle *handle = &vport->nic; 7120 struct hclge_vport_vlan_cfg *vlan, *tmp; 7121 struct hclge_dev *hdev = vport->back; 7122 7123 if (vport->vport_id) { 7124 if (vport->port_base_vlan_cfg.state != 7125 HNAE3_PORT_BASE_VLAN_DISABLE) 7126 return true; 7127 7128 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 7129 return false; 7130 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 7131 return false; 7132 } 7133 7134 if (!vport->req_vlan_fltr_en) 7135 return false; 7136 7137 /* compatible with former device, always enable vlan filter */ 7138 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 7139 return true; 7140 7141 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 7142 if (vlan->vlan_id != 0) 7143 return true; 7144 7145 return false; 7146 } 7147 7148 static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport, 7149 bool request_en) 7150 { 7151 bool need_en; 7152 int ret; 7153 7154 need_en = hclge_need_enable_vport_vlan_filter(vport); 7155 if (need_en == vport->cur_vlan_fltr_en) 7156 return 0; 7157 7158 ret = hclge_set_vport_vlan_filter(vport, need_en); 7159 if (ret) 7160 return ret; 7161 7162 vport->cur_vlan_fltr_en = need_en; 7163 7164 return 0; 7165 } 7166 7167 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 7168 { 7169 struct hclge_dev *hdev = vport->back; 7170 int ret; 7171 7172 mutex_lock(&hdev->vport_lock); 7173 vport->req_vlan_fltr_en = request_en; 7174 ret = __hclge_enable_vport_vlan_filter(vport, request_en); 7175 mutex_unlock(&hdev->vport_lock); 7176 7177 return ret; 7178 } 7179 7180 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 7181 { 7182 struct hclge_vport *vport = hclge_get_vport(handle); 7183 7184 return hclge_enable_vport_vlan_filter(vport, enable); 7185 } 7186 7187 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 7188 bool is_kill, u16 vlan, 7189 struct hclge_desc *desc) 7190 { 7191 struct hclge_vlan_filter_vf_cfg_cmd *req0; 7192 struct hclge_vlan_filter_vf_cfg_cmd *req1; 7193 u8 vf_byte_val; 7194 u8 vf_byte_off; 7195 int ret; 7196 7197 hclge_cmd_setup_basic_desc(&desc[0], 7198 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 7199 hclge_cmd_setup_basic_desc(&desc[1], 7200 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 7201 7202 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 7203 7204 vf_byte_off = vfid / 8; 7205 vf_byte_val = 1 << (vfid % 8); 7206 7207 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 7208 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 7209 7210 req0->vlan_id = cpu_to_le16(vlan); 7211 req0->vlan_cfg = is_kill; 7212 7213 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 7214 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 7215 else 7216 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 7217 7218 ret = hclge_cmd_send(&hdev->hw, desc, 2); 7219 if (ret) { 7220 dev_err(&hdev->pdev->dev, 7221 "Send vf vlan command fail, ret =%d.\n", 7222 ret); 7223 return ret; 7224 } 7225 7226 return 0; 7227 } 7228 7229 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 7230 bool is_kill, struct hclge_desc *desc) 7231 { 7232 struct hclge_vlan_filter_vf_cfg_cmd *req; 7233 7234 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 7235 7236 if (!is_kill) { 7237 #define HCLGE_VF_VLAN_NO_ENTRY 2 7238 if (!req->resp_code || req->resp_code == 1) 7239 return 0; 7240 7241 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 7242 set_bit(vfid, hdev->vf_vlan_full); 7243 dev_warn(&hdev->pdev->dev, 7244 "vf vlan table is full, vf vlan filter is disabled\n"); 7245 return 0; 7246 } 7247 7248 dev_err(&hdev->pdev->dev, 7249 "Add vf vlan filter fail, ret =%u.\n", 7250 req->resp_code); 7251 } else { 7252 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 7253 if (!req->resp_code) 7254 return 0; 7255 7256 /* vf vlan filter is disabled when vf vlan table is full, 7257 * then new vlan id will not be added into vf vlan table. 7258 * Just return 0 without warning, avoid massive verbose 7259 * print logs when unload. 7260 */ 7261 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 7262 return 0; 7263 7264 dev_err(&hdev->pdev->dev, 7265 "Kill vf vlan filter fail, ret =%u.\n", 7266 req->resp_code); 7267 } 7268 7269 return -EIO; 7270 } 7271 7272 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 7273 bool is_kill, u16 vlan) 7274 { 7275 struct hclge_vport *vport = &hdev->vport[vfid]; 7276 struct hclge_desc desc[2]; 7277 int ret; 7278 7279 /* if vf vlan table is full, firmware will close vf vlan filter, it 7280 * is unable and unnecessary to add new vlan id to vf vlan filter. 7281 * If spoof check is enable, and vf vlan is full, it shouldn't add 7282 * new vlan, because tx packets with these vlan id will be dropped. 7283 */ 7284 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 7285 if (vport->vf_info.spoofchk && vlan) { 7286 dev_err(&hdev->pdev->dev, 7287 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 7288 return -EPERM; 7289 } 7290 return 0; 7291 } 7292 7293 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 7294 if (ret) 7295 return ret; 7296 7297 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 7298 } 7299 7300 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 7301 u16 vlan_id, bool is_kill) 7302 { 7303 struct hclge_vlan_filter_pf_cfg_cmd *req; 7304 struct hclge_desc desc; 7305 u8 vlan_offset_byte_val; 7306 u8 vlan_offset_byte; 7307 u8 vlan_offset_160; 7308 int ret; 7309 7310 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 7311 7312 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 7313 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 7314 HCLGE_VLAN_BYTE_SIZE; 7315 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 7316 7317 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 7318 req->vlan_offset = vlan_offset_160; 7319 req->vlan_cfg = is_kill; 7320 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 7321 7322 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7323 if (ret) 7324 dev_err(&hdev->pdev->dev, 7325 "port vlan command, send fail, ret =%d.\n", ret); 7326 return ret; 7327 } 7328 7329 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 7330 u16 vlan_id, bool is_kill) 7331 { 7332 /* vlan 0 may be added twice when 8021q module is enabled */ 7333 if (!is_kill && !vlan_id && 7334 test_bit(vport_id, hdev->vlan_table[vlan_id])) 7335 return false; 7336 7337 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 7338 dev_warn(&hdev->pdev->dev, 7339 "Add port vlan failed, vport %u is already in vlan %u\n", 7340 vport_id, vlan_id); 7341 return false; 7342 } 7343 7344 if (is_kill && 7345 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 7346 dev_warn(&hdev->pdev->dev, 7347 "Delete port vlan failed, vport %u is not in vlan %u\n", 7348 vport_id, vlan_id); 7349 return false; 7350 } 7351 7352 return true; 7353 } 7354 7355 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 7356 u16 vport_id, u16 vlan_id, 7357 bool is_kill) 7358 { 7359 u16 vport_idx, vport_num = 0; 7360 int ret; 7361 7362 if (is_kill && !vlan_id) 7363 return 0; 7364 7365 if (vlan_id >= VLAN_N_VID) 7366 return -EINVAL; 7367 7368 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 7369 if (ret) { 7370 dev_err(&hdev->pdev->dev, 7371 "Set %u vport vlan filter config fail, ret =%d.\n", 7372 vport_id, ret); 7373 return ret; 7374 } 7375 7376 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 7377 return 0; 7378 7379 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 7380 vport_num++; 7381 7382 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 7383 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 7384 is_kill); 7385 7386 return ret; 7387 } 7388 7389 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 7390 { 7391 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 7392 struct hclge_vport_vtag_tx_cfg_cmd *req; 7393 struct hclge_dev *hdev = vport->back; 7394 struct hclge_desc desc; 7395 u16 bmap_index; 7396 int status; 7397 7398 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 7399 7400 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 7401 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 7402 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 7403 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 7404 vcfg->accept_tag1 ? 1 : 0); 7405 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 7406 vcfg->accept_untag1 ? 1 : 0); 7407 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 7408 vcfg->accept_tag2 ? 1 : 0); 7409 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 7410 vcfg->accept_untag2 ? 1 : 0); 7411 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 7412 vcfg->insert_tag1_en ? 1 : 0); 7413 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 7414 vcfg->insert_tag2_en ? 1 : 0); 7415 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 7416 vcfg->tag_shift_mode_en ? 1 : 0); 7417 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 7418 7419 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 7420 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 7421 HCLGE_VF_NUM_PER_BYTE; 7422 req->vf_bitmap[bmap_index] = 7423 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 7424 7425 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7426 if (status) 7427 dev_err(&hdev->pdev->dev, 7428 "Send port txvlan cfg command fail, ret =%d\n", 7429 status); 7430 7431 return status; 7432 } 7433 7434 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 7435 { 7436 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 7437 struct hclge_vport_vtag_rx_cfg_cmd *req; 7438 struct hclge_dev *hdev = vport->back; 7439 struct hclge_desc desc; 7440 u16 bmap_index; 7441 int status; 7442 7443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 7444 7445 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 7446 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 7447 vcfg->strip_tag1_en ? 1 : 0); 7448 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 7449 vcfg->strip_tag2_en ? 1 : 0); 7450 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 7451 vcfg->vlan1_vlan_prionly ? 1 : 0); 7452 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 7453 vcfg->vlan2_vlan_prionly ? 1 : 0); 7454 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 7455 vcfg->strip_tag1_discard_en ? 1 : 0); 7456 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 7457 vcfg->strip_tag2_discard_en ? 1 : 0); 7458 7459 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 7460 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 7461 HCLGE_VF_NUM_PER_BYTE; 7462 req->vf_bitmap[bmap_index] = 7463 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 7464 7465 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7466 if (status) 7467 dev_err(&hdev->pdev->dev, 7468 "Send port rxvlan cfg command fail, ret =%d\n", 7469 status); 7470 7471 return status; 7472 } 7473 7474 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 7475 u16 port_base_vlan_state, 7476 u16 vlan_tag, u8 qos) 7477 { 7478 int ret; 7479 7480 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7481 vport->txvlan_cfg.accept_tag1 = true; 7482 vport->txvlan_cfg.insert_tag1_en = false; 7483 vport->txvlan_cfg.default_tag1 = 0; 7484 } else { 7485 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 7486 7487 vport->txvlan_cfg.accept_tag1 = 7488 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 7489 vport->txvlan_cfg.insert_tag1_en = true; 7490 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 7491 vlan_tag; 7492 } 7493 7494 vport->txvlan_cfg.accept_untag1 = true; 7495 7496 /* accept_tag2 and accept_untag2 are not supported on 7497 * pdev revision(0x20), new revision support them, 7498 * this two fields can not be configured by user. 7499 */ 7500 vport->txvlan_cfg.accept_tag2 = true; 7501 vport->txvlan_cfg.accept_untag2 = true; 7502 vport->txvlan_cfg.insert_tag2_en = false; 7503 vport->txvlan_cfg.default_tag2 = 0; 7504 vport->txvlan_cfg.tag_shift_mode_en = true; 7505 7506 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7507 vport->rxvlan_cfg.strip_tag1_en = false; 7508 vport->rxvlan_cfg.strip_tag2_en = 7509 vport->rxvlan_cfg.rx_vlan_offload_en; 7510 vport->rxvlan_cfg.strip_tag2_discard_en = false; 7511 } else { 7512 vport->rxvlan_cfg.strip_tag1_en = 7513 vport->rxvlan_cfg.rx_vlan_offload_en; 7514 vport->rxvlan_cfg.strip_tag2_en = true; 7515 vport->rxvlan_cfg.strip_tag2_discard_en = true; 7516 } 7517 7518 vport->rxvlan_cfg.strip_tag1_discard_en = false; 7519 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 7520 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 7521 7522 ret = hclge_set_vlan_tx_offload_cfg(vport); 7523 if (ret) 7524 return ret; 7525 7526 return hclge_set_vlan_rx_offload_cfg(vport); 7527 } 7528 7529 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 7530 { 7531 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 7532 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 7533 struct hclge_desc desc; 7534 int status; 7535 7536 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 7537 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 7538 rx_req->ot_fst_vlan_type = 7539 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 7540 rx_req->ot_sec_vlan_type = 7541 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 7542 rx_req->in_fst_vlan_type = 7543 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 7544 rx_req->in_sec_vlan_type = 7545 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 7546 7547 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7548 if (status) { 7549 dev_err(&hdev->pdev->dev, 7550 "Send rxvlan protocol type command fail, ret =%d\n", 7551 status); 7552 return status; 7553 } 7554 7555 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 7556 7557 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 7558 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 7559 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 7560 7561 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7562 if (status) 7563 dev_err(&hdev->pdev->dev, 7564 "Send txvlan protocol type command fail, ret =%d\n", 7565 status); 7566 7567 return status; 7568 } 7569 7570 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 7571 { 7572 struct hclge_vport *vport; 7573 bool enable = true; 7574 int ret; 7575 int i; 7576 7577 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 7578 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7579 HCLGE_FILTER_FE_EGRESS_V1_B, 7580 true, 0); 7581 7582 /* for revision 0x21, vf vlan filter is per function */ 7583 for (i = 0; i < hdev->num_alloc_vport; i++) { 7584 vport = &hdev->vport[i]; 7585 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7586 HCLGE_FILTER_FE_EGRESS, true, 7587 vport->vport_id); 7588 if (ret) 7589 return ret; 7590 vport->cur_vlan_fltr_en = true; 7591 } 7592 7593 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 7594 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 7595 enable = false; 7596 7597 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 7598 HCLGE_FILTER_FE_INGRESS, enable, 0); 7599 } 7600 7601 static int hclge_init_vlan_type(struct hclge_dev *hdev) 7602 { 7603 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 7604 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 7605 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 7606 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 7607 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 7608 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 7609 7610 return hclge_set_vlan_protocol_type(hdev); 7611 } 7612 7613 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 7614 { 7615 struct hclge_port_base_vlan_config *cfg; 7616 struct hclge_vport *vport; 7617 int ret; 7618 int i; 7619 7620 for (i = 0; i < hdev->num_alloc_vport; i++) { 7621 vport = &hdev->vport[i]; 7622 cfg = &vport->port_base_vlan_cfg; 7623 7624 ret = hclge_vlan_offload_cfg(vport, cfg->state, 7625 cfg->vlan_info.vlan_tag, 7626 cfg->vlan_info.qos); 7627 if (ret) 7628 return ret; 7629 } 7630 return 0; 7631 } 7632 7633 static int hclge_init_vlan_config(struct hclge_dev *hdev) 7634 { 7635 struct hnae3_handle *handle = &hdev->vport[0].nic; 7636 int ret; 7637 7638 ret = hclge_init_vlan_filter(hdev); 7639 if (ret) 7640 return ret; 7641 7642 ret = hclge_init_vlan_type(hdev); 7643 if (ret) 7644 return ret; 7645 7646 ret = hclge_init_vport_vlan_offload(hdev); 7647 if (ret) 7648 return ret; 7649 7650 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 7651 } 7652 7653 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 7654 bool writen_to_tbl) 7655 { 7656 struct hclge_vport_vlan_cfg *vlan, *tmp; 7657 struct hclge_dev *hdev = vport->back; 7658 7659 mutex_lock(&hdev->vport_lock); 7660 7661 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7662 if (vlan->vlan_id == vlan_id) { 7663 mutex_unlock(&hdev->vport_lock); 7664 return; 7665 } 7666 } 7667 7668 vlan = kzalloc_obj(*vlan); 7669 if (!vlan) { 7670 mutex_unlock(&hdev->vport_lock); 7671 return; 7672 } 7673 7674 vlan->hd_tbl_status = writen_to_tbl; 7675 vlan->vlan_id = vlan_id; 7676 7677 list_add_tail(&vlan->node, &vport->vlan_list); 7678 mutex_unlock(&hdev->vport_lock); 7679 } 7680 7681 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 7682 { 7683 struct hclge_vport_vlan_cfg *vlan, *tmp; 7684 struct hclge_dev *hdev = vport->back; 7685 int ret; 7686 7687 mutex_lock(&hdev->vport_lock); 7688 7689 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7690 if (!vlan->hd_tbl_status) { 7691 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7692 vport->vport_id, 7693 vlan->vlan_id, false); 7694 if (ret) { 7695 dev_err(&hdev->pdev->dev, 7696 "restore vport vlan list failed, ret=%d\n", 7697 ret); 7698 7699 mutex_unlock(&hdev->vport_lock); 7700 return ret; 7701 } 7702 } 7703 vlan->hd_tbl_status = true; 7704 } 7705 7706 mutex_unlock(&hdev->vport_lock); 7707 7708 return 0; 7709 } 7710 7711 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 7712 bool is_write_tbl) 7713 { 7714 struct hclge_vport_vlan_cfg *vlan, *tmp; 7715 struct hclge_dev *hdev = vport->back; 7716 7717 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7718 if (vlan->vlan_id == vlan_id) { 7719 if (is_write_tbl && vlan->hd_tbl_status) 7720 hclge_set_vlan_filter_hw(hdev, 7721 htons(ETH_P_8021Q), 7722 vport->vport_id, 7723 vlan_id, 7724 true); 7725 7726 list_del(&vlan->node); 7727 kfree(vlan); 7728 break; 7729 } 7730 } 7731 } 7732 7733 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 7734 { 7735 struct hclge_vport_vlan_cfg *vlan, *tmp; 7736 struct hclge_dev *hdev = vport->back; 7737 7738 mutex_lock(&hdev->vport_lock); 7739 7740 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7741 if (vlan->hd_tbl_status) 7742 hclge_set_vlan_filter_hw(hdev, 7743 htons(ETH_P_8021Q), 7744 vport->vport_id, 7745 vlan->vlan_id, 7746 true); 7747 7748 vlan->hd_tbl_status = false; 7749 if (is_del_list) { 7750 list_del(&vlan->node); 7751 kfree(vlan); 7752 } 7753 } 7754 clear_bit(vport->vport_id, hdev->vf_vlan_full); 7755 mutex_unlock(&hdev->vport_lock); 7756 } 7757 7758 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 7759 { 7760 struct hclge_vport_vlan_cfg *vlan, *tmp; 7761 struct hclge_vport *vport; 7762 int i; 7763 7764 mutex_lock(&hdev->vport_lock); 7765 7766 for (i = 0; i < hdev->num_alloc_vport; i++) { 7767 vport = &hdev->vport[i]; 7768 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7769 list_del(&vlan->node); 7770 kfree(vlan); 7771 } 7772 } 7773 7774 mutex_unlock(&hdev->vport_lock); 7775 } 7776 7777 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 7778 { 7779 struct hclge_vlan_info *vlan_info; 7780 struct hclge_vport *vport; 7781 u16 vlan_proto; 7782 u16 vlan_id; 7783 u16 state; 7784 int vf_id; 7785 int ret; 7786 7787 /* PF should restore all vfs port base vlan */ 7788 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 7789 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 7790 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 7791 &vport->port_base_vlan_cfg.vlan_info : 7792 &vport->port_base_vlan_cfg.old_vlan_info; 7793 7794 vlan_id = vlan_info->vlan_tag; 7795 vlan_proto = vlan_info->vlan_proto; 7796 state = vport->port_base_vlan_cfg.state; 7797 7798 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 7799 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 7800 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 7801 vport->vport_id, 7802 vlan_id, false); 7803 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 7804 } 7805 } 7806 } 7807 7808 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 7809 { 7810 struct hclge_vport_vlan_cfg *vlan, *tmp; 7811 struct hclge_dev *hdev = vport->back; 7812 int ret; 7813 7814 mutex_lock(&hdev->vport_lock); 7815 7816 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7817 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7818 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7819 vport->vport_id, 7820 vlan->vlan_id, false); 7821 if (ret) 7822 break; 7823 vlan->hd_tbl_status = true; 7824 } 7825 } 7826 7827 mutex_unlock(&hdev->vport_lock); 7828 } 7829 7830 /* For global reset and imp reset, hardware will clear the mac table, 7831 * so we change the mac address state from ACTIVE to TO_ADD, then they 7832 * can be restored in the service task after reset complete. Furtherly, 7833 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 7834 * be restored after reset, so just remove these mac nodes from mac_list. 7835 */ 7836 static void hclge_mac_node_convert_for_reset(struct list_head *list) 7837 { 7838 struct hclge_mac_node *mac_node, *tmp; 7839 7840 list_for_each_entry_safe(mac_node, tmp, list, node) { 7841 if (mac_node->state == HCLGE_MAC_ACTIVE) { 7842 mac_node->state = HCLGE_MAC_TO_ADD; 7843 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 7844 list_del(&mac_node->node); 7845 kfree(mac_node); 7846 } 7847 } 7848 } 7849 7850 void hclge_restore_mac_table_common(struct hclge_vport *vport) 7851 { 7852 spin_lock_bh(&vport->mac_list_lock); 7853 7854 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 7855 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 7856 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 7857 7858 spin_unlock_bh(&vport->mac_list_lock); 7859 } 7860 7861 static void hclge_restore_hw_table(struct hclge_dev *hdev) 7862 { 7863 struct hclge_vport *vport = &hdev->vport[0]; 7864 struct hnae3_handle *handle = &vport->nic; 7865 7866 hclge_restore_mac_table_common(vport); 7867 hclge_restore_vport_port_base_vlan_config(hdev); 7868 hclge_restore_vport_vlan_table(vport); 7869 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 7870 hclge_restore_fd_entries(handle); 7871 } 7872 7873 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 7874 { 7875 struct hclge_vport *vport = hclge_get_vport(handle); 7876 7877 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7878 vport->rxvlan_cfg.strip_tag1_en = false; 7879 vport->rxvlan_cfg.strip_tag2_en = enable; 7880 vport->rxvlan_cfg.strip_tag2_discard_en = false; 7881 } else { 7882 vport->rxvlan_cfg.strip_tag1_en = enable; 7883 vport->rxvlan_cfg.strip_tag2_en = true; 7884 vport->rxvlan_cfg.strip_tag2_discard_en = true; 7885 } 7886 7887 vport->rxvlan_cfg.strip_tag1_discard_en = false; 7888 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 7889 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 7890 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 7891 7892 return hclge_set_vlan_rx_offload_cfg(vport); 7893 } 7894 7895 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 7896 { 7897 struct hclge_dev *hdev = vport->back; 7898 7899 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 7900 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 7901 } 7902 7903 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 7904 u16 port_base_vlan_state, 7905 struct hclge_vlan_info *new_info, 7906 struct hclge_vlan_info *old_info) 7907 { 7908 struct hclge_dev *hdev = vport->back; 7909 int ret; 7910 7911 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 7912 hclge_rm_vport_all_vlan_table(vport, false); 7913 /* force clear VLAN 0 */ 7914 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 7915 if (ret) 7916 return ret; 7917 return hclge_set_vlan_filter_hw(hdev, 7918 htons(new_info->vlan_proto), 7919 vport->vport_id, 7920 new_info->vlan_tag, 7921 false); 7922 } 7923 7924 vport->port_base_vlan_cfg.tbl_sta = false; 7925 7926 /* force add VLAN 0 */ 7927 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 7928 if (ret) 7929 return ret; 7930 7931 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 7932 vport->vport_id, old_info->vlan_tag, 7933 true); 7934 if (ret) 7935 return ret; 7936 7937 return hclge_add_vport_all_vlan_table(vport); 7938 } 7939 7940 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 7941 const struct hclge_vlan_info *old_cfg) 7942 { 7943 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 7944 return true; 7945 7946 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 7947 return true; 7948 7949 return false; 7950 } 7951 7952 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 7953 struct hclge_vlan_info *new_info, 7954 struct hclge_vlan_info *old_info) 7955 { 7956 struct hclge_dev *hdev = vport->back; 7957 int ret; 7958 7959 /* add new VLAN tag */ 7960 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 7961 vport->vport_id, new_info->vlan_tag, 7962 false); 7963 if (ret) 7964 return ret; 7965 7966 vport->port_base_vlan_cfg.tbl_sta = false; 7967 /* remove old VLAN tag */ 7968 if (old_info->vlan_tag == 0) 7969 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 7970 true, 0); 7971 else 7972 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7973 vport->vport_id, 7974 old_info->vlan_tag, true); 7975 if (ret) 7976 dev_err(&hdev->pdev->dev, 7977 "failed to clear vport%u port base vlan %u, ret = %d.\n", 7978 vport->vport_id, old_info->vlan_tag, ret); 7979 7980 return ret; 7981 } 7982 7983 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 7984 struct hclge_vlan_info *vlan_info) 7985 { 7986 struct hnae3_handle *nic = &vport->nic; 7987 struct hclge_vlan_info *old_vlan_info; 7988 int ret; 7989 7990 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 7991 7992 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 7993 vlan_info->qos); 7994 if (ret) 7995 return ret; 7996 7997 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 7998 goto out; 7999 8000 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 8001 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 8002 old_vlan_info); 8003 else 8004 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 8005 old_vlan_info); 8006 if (ret) 8007 return ret; 8008 8009 out: 8010 vport->port_base_vlan_cfg.state = state; 8011 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 8012 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 8013 else 8014 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 8015 8016 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 8017 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 8018 vport->port_base_vlan_cfg.tbl_sta = true; 8019 hclge_set_vport_vlan_fltr_change(vport); 8020 8021 return 0; 8022 } 8023 8024 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 8025 enum hnae3_port_base_vlan_state state, 8026 u16 vlan, u8 qos) 8027 { 8028 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8029 if (!vlan && !qos) 8030 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 8031 8032 return HNAE3_PORT_BASE_VLAN_ENABLE; 8033 } 8034 8035 if (!vlan && !qos) 8036 return HNAE3_PORT_BASE_VLAN_DISABLE; 8037 8038 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 8039 vport->port_base_vlan_cfg.vlan_info.qos == qos) 8040 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 8041 8042 return HNAE3_PORT_BASE_VLAN_MODIFY; 8043 } 8044 8045 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 8046 u16 vlan, u8 qos, __be16 proto) 8047 { 8048 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 8049 struct hclge_vport *vport = hclge_get_vport(handle); 8050 struct hclge_dev *hdev = vport->back; 8051 struct hclge_vlan_info vlan_info; 8052 u16 state; 8053 int ret; 8054 8055 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 8056 return -EOPNOTSUPP; 8057 8058 vport = hclge_get_vf_vport(hdev, vfid); 8059 if (!vport) 8060 return -EINVAL; 8061 8062 /* qos is a 3 bits value, so can not be bigger than 7 */ 8063 if (vlan > VLAN_N_VID - 1 || qos > 7) 8064 return -EINVAL; 8065 if (proto != htons(ETH_P_8021Q)) 8066 return -EPROTONOSUPPORT; 8067 8068 state = hclge_get_port_base_vlan_state(vport, 8069 vport->port_base_vlan_cfg.state, 8070 vlan, qos); 8071 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 8072 return 0; 8073 8074 vlan_info.vlan_tag = vlan; 8075 vlan_info.qos = qos; 8076 vlan_info.vlan_proto = ntohs(proto); 8077 8078 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 8079 if (ret) { 8080 dev_err(&hdev->pdev->dev, 8081 "failed to update port base vlan for vf %d, ret = %d\n", 8082 vfid, ret); 8083 return ret; 8084 } 8085 8086 /* there is a timewindow for PF to know VF unalive, it may 8087 * cause send mailbox fail, but it doesn't matter, VF will 8088 * query it when reinit. 8089 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 8090 * VLAN state. 8091 */ 8092 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 8093 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 8094 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 8095 vport->vport_id, 8096 state, 8097 &vlan_info); 8098 else 8099 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 8100 &vport->need_notify); 8101 } 8102 return 0; 8103 } 8104 8105 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 8106 { 8107 struct hclge_vlan_info *vlan_info; 8108 struct hclge_vport *vport; 8109 int ret; 8110 int vf; 8111 8112 /* clear port base vlan for all vf */ 8113 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 8114 vport = &hdev->vport[vf]; 8115 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 8116 8117 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8118 vport->vport_id, 8119 vlan_info->vlan_tag, true); 8120 if (ret) 8121 dev_err(&hdev->pdev->dev, 8122 "failed to clear vf vlan for vf%d, ret = %d\n", 8123 vf - HCLGE_VF_VPORT_START_NUM, ret); 8124 } 8125 } 8126 8127 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 8128 u16 vlan_id, bool is_kill) 8129 { 8130 struct hclge_vport *vport = hclge_get_vport(handle); 8131 struct hclge_dev *hdev = vport->back; 8132 bool writen_to_tbl = false; 8133 int ret = 0; 8134 8135 if (vlan_id >= VLAN_N_VID) 8136 return -EINVAL; 8137 8138 /* When device is resetting or reset failed, firmware is unable to 8139 * handle mailbox. Just record the vlan id, and remove it after 8140 * reset finished. 8141 */ 8142 mutex_lock(&hdev->vport_lock); 8143 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8144 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 8145 set_bit(vlan_id, vport->vlan_del_fail_bmap); 8146 mutex_unlock(&hdev->vport_lock); 8147 return -EBUSY; 8148 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 8149 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 8150 } 8151 mutex_unlock(&hdev->vport_lock); 8152 8153 /* when port base vlan enabled, we use port base vlan as the vlan 8154 * filter entry. In this case, we don't update vlan filter table 8155 * when user add new vlan or remove exist vlan, just update the vport 8156 * vlan list. The vlan id in vlan list will be writen in vlan filter 8157 * table until port base vlan disabled 8158 */ 8159 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8160 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 8161 vlan_id, is_kill); 8162 writen_to_tbl = true; 8163 } 8164 8165 if (!ret) { 8166 if (!is_kill) { 8167 hclge_add_vport_vlan_table(vport, vlan_id, 8168 writen_to_tbl); 8169 } else if (is_kill && vlan_id != 0) { 8170 mutex_lock(&hdev->vport_lock); 8171 hclge_rm_vport_vlan_table(vport, vlan_id, false); 8172 mutex_unlock(&hdev->vport_lock); 8173 } 8174 } else if (is_kill) { 8175 /* when remove hw vlan filter failed, record the vlan id, 8176 * and try to remove it from hw later, to be consistence 8177 * with stack 8178 */ 8179 mutex_lock(&hdev->vport_lock); 8180 set_bit(vlan_id, vport->vlan_del_fail_bmap); 8181 mutex_unlock(&hdev->vport_lock); 8182 } 8183 8184 hclge_set_vport_vlan_fltr_change(vport); 8185 8186 return ret; 8187 } 8188 8189 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 8190 { 8191 struct hclge_vport *vport; 8192 int ret; 8193 u16 i; 8194 8195 for (i = 0; i < hdev->num_alloc_vport; i++) { 8196 vport = &hdev->vport[i]; 8197 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 8198 &vport->state)) 8199 continue; 8200 8201 mutex_lock(&hdev->vport_lock); 8202 ret = __hclge_enable_vport_vlan_filter(vport, 8203 vport->req_vlan_fltr_en); 8204 if (ret) { 8205 dev_err(&hdev->pdev->dev, 8206 "failed to sync vlan filter state for vport%u, ret = %d\n", 8207 vport->vport_id, ret); 8208 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 8209 &vport->state); 8210 mutex_unlock(&hdev->vport_lock); 8211 return; 8212 } 8213 mutex_unlock(&hdev->vport_lock); 8214 } 8215 } 8216 8217 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 8218 { 8219 #define HCLGE_MAX_SYNC_COUNT 60 8220 8221 int i, ret, sync_cnt = 0; 8222 u16 vlan_id; 8223 8224 mutex_lock(&hdev->vport_lock); 8225 /* start from vport 1 for PF is always alive */ 8226 for (i = 0; i < hdev->num_alloc_vport; i++) { 8227 struct hclge_vport *vport = &hdev->vport[i]; 8228 8229 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 8230 VLAN_N_VID); 8231 while (vlan_id != VLAN_N_VID) { 8232 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8233 vport->vport_id, vlan_id, 8234 true); 8235 if (ret && ret != -EINVAL) { 8236 mutex_unlock(&hdev->vport_lock); 8237 return; 8238 } 8239 8240 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 8241 hclge_rm_vport_vlan_table(vport, vlan_id, false); 8242 hclge_set_vport_vlan_fltr_change(vport); 8243 8244 sync_cnt++; 8245 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 8246 mutex_unlock(&hdev->vport_lock); 8247 return; 8248 } 8249 8250 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 8251 VLAN_N_VID); 8252 } 8253 } 8254 mutex_unlock(&hdev->vport_lock); 8255 8256 hclge_sync_vlan_fltr_state(hdev); 8257 } 8258 8259 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 8260 { 8261 struct hclge_config_max_frm_size_cmd *req; 8262 struct hclge_desc desc; 8263 8264 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 8265 8266 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 8267 req->max_frm_size = cpu_to_le16(new_mps); 8268 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 8269 8270 return hclge_cmd_send(&hdev->hw, &desc, 1); 8271 } 8272 8273 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 8274 { 8275 struct hclge_vport *vport = hclge_get_vport(handle); 8276 8277 return hclge_set_vport_mtu(vport, new_mtu); 8278 } 8279 8280 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 8281 { 8282 struct hclge_dev *hdev = vport->back; 8283 int i, max_frm_size, ret; 8284 8285 /* HW supprt 2 layer vlan */ 8286 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 8287 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 8288 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 8289 return -EINVAL; 8290 8291 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 8292 mutex_lock(&hdev->vport_lock); 8293 /* VF's mps must fit within hdev->mps */ 8294 if (vport->vport_id && (u32)max_frm_size > hdev->mps) { 8295 mutex_unlock(&hdev->vport_lock); 8296 return -EINVAL; 8297 } else if (vport->vport_id) { 8298 vport->mps = max_frm_size; 8299 mutex_unlock(&hdev->vport_lock); 8300 return 0; 8301 } 8302 8303 /* PF's mps must be greater then VF's mps */ 8304 for (i = 1; i < hdev->num_alloc_vport; i++) 8305 if ((u32)max_frm_size < hdev->vport[i].mps) { 8306 dev_err(&hdev->pdev->dev, 8307 "failed to set pf mtu for less than vport %d, mps = %u.\n", 8308 i, hdev->vport[i].mps); 8309 mutex_unlock(&hdev->vport_lock); 8310 return -EINVAL; 8311 } 8312 8313 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 8314 8315 ret = hclge_set_mac_mtu(hdev, max_frm_size); 8316 if (ret) { 8317 dev_err(&hdev->pdev->dev, 8318 "Change mtu fail, ret =%d\n", ret); 8319 goto out; 8320 } 8321 8322 hdev->mps = max_frm_size; 8323 vport->mps = max_frm_size; 8324 8325 ret = hclge_buffer_alloc(hdev); 8326 if (ret) 8327 dev_err(&hdev->pdev->dev, 8328 "Allocate buffer fail, ret =%d\n", ret); 8329 8330 out: 8331 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 8332 mutex_unlock(&hdev->vport_lock); 8333 return ret; 8334 } 8335 8336 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 8337 bool enable) 8338 { 8339 struct hclge_reset_tqp_queue_cmd *req; 8340 struct hclge_desc desc; 8341 int ret; 8342 8343 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 8344 8345 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 8346 req->tqp_id = cpu_to_le16(queue_id); 8347 if (enable) 8348 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 8349 8350 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8351 if (ret) { 8352 dev_err(&hdev->pdev->dev, 8353 "Send tqp reset cmd error, status =%d\n", ret); 8354 return ret; 8355 } 8356 8357 return 0; 8358 } 8359 8360 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 8361 u8 *reset_status) 8362 { 8363 struct hclge_reset_tqp_queue_cmd *req; 8364 struct hclge_desc desc; 8365 int ret; 8366 8367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 8368 8369 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 8370 req->tqp_id = cpu_to_le16(queue_id); 8371 8372 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8373 if (ret) { 8374 dev_err(&hdev->pdev->dev, 8375 "Get reset status error, status =%d\n", ret); 8376 return ret; 8377 } 8378 8379 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 8380 8381 return 0; 8382 } 8383 8384 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 8385 { 8386 struct hclge_comm_tqp *tqp; 8387 struct hnae3_queue *queue; 8388 8389 queue = handle->kinfo.tqp[queue_id]; 8390 tqp = container_of(queue, struct hclge_comm_tqp, q); 8391 8392 return tqp->index; 8393 } 8394 8395 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 8396 { 8397 struct hclge_vport *vport = hclge_get_vport(handle); 8398 struct hclge_dev *hdev = vport->back; 8399 u16 reset_try_times = 0; 8400 u8 reset_status; 8401 u16 queue_gid; 8402 int ret; 8403 u16 i; 8404 8405 for (i = 0; i < handle->kinfo.num_tqps; i++) { 8406 queue_gid = hclge_covert_handle_qid_global(handle, i); 8407 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 8408 if (ret) { 8409 dev_err(&hdev->pdev->dev, 8410 "failed to send reset tqp cmd, ret = %d\n", 8411 ret); 8412 return ret; 8413 } 8414 8415 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 8416 ret = hclge_get_reset_status(hdev, queue_gid, 8417 &reset_status); 8418 if (ret) 8419 return ret; 8420 8421 if (reset_status) 8422 break; 8423 8424 /* Wait for tqp hw reset */ 8425 usleep_range(1000, 1200); 8426 } 8427 8428 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 8429 dev_err(&hdev->pdev->dev, 8430 "wait for tqp hw reset timeout\n"); 8431 return -ETIME; 8432 } 8433 8434 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 8435 if (ret) { 8436 dev_err(&hdev->pdev->dev, 8437 "failed to deassert soft reset, ret = %d\n", 8438 ret); 8439 return ret; 8440 } 8441 reset_try_times = 0; 8442 } 8443 return 0; 8444 } 8445 8446 static int hclge_reset_rcb(struct hnae3_handle *handle) 8447 { 8448 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 8449 #define HCLGE_RESET_RCB_SUCCESS 1U 8450 8451 struct hclge_vport *vport = hclge_get_vport(handle); 8452 struct hclge_dev *hdev = vport->back; 8453 struct hclge_reset_cmd *req; 8454 struct hclge_desc desc; 8455 u8 return_status; 8456 u16 queue_gid; 8457 int ret; 8458 8459 queue_gid = hclge_covert_handle_qid_global(handle, 0); 8460 8461 req = (struct hclge_reset_cmd *)desc.data; 8462 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 8463 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 8464 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 8465 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 8466 8467 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8468 if (ret) { 8469 dev_err(&hdev->pdev->dev, 8470 "failed to send rcb reset cmd, ret = %d\n", ret); 8471 return ret; 8472 } 8473 8474 return_status = req->fun_reset_rcb_return_status; 8475 if (return_status == HCLGE_RESET_RCB_SUCCESS) 8476 return 0; 8477 8478 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 8479 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 8480 return_status); 8481 return -EIO; 8482 } 8483 8484 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 8485 * again to reset all tqps 8486 */ 8487 return hclge_reset_tqp_cmd(handle); 8488 } 8489 8490 int hclge_reset_tqp(struct hnae3_handle *handle) 8491 { 8492 struct hclge_vport *vport = hclge_get_vport(handle); 8493 struct hclge_dev *hdev = vport->back; 8494 int ret; 8495 8496 /* only need to disable PF's tqp */ 8497 if (!vport->vport_id) { 8498 ret = hclge_tqp_enable(handle, false); 8499 if (ret) { 8500 dev_err(&hdev->pdev->dev, 8501 "failed to disable tqp, ret = %d\n", ret); 8502 return ret; 8503 } 8504 } 8505 8506 return hclge_reset_rcb(handle); 8507 } 8508 8509 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 8510 { 8511 struct hclge_vport *vport = hclge_get_vport(handle); 8512 struct hclge_dev *hdev = vport->back; 8513 8514 return hdev->fw_version; 8515 } 8516 8517 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 8518 { 8519 struct hclge_comm_query_scc_cmd *resp; 8520 struct hclge_desc desc; 8521 int ret; 8522 8523 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 8524 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 8525 8526 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8527 if (ret) 8528 return ret; 8529 8530 *scc_version = le32_to_cpu(resp->scc_version); 8531 8532 return 0; 8533 } 8534 8535 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 8536 { 8537 struct phy_device *phydev = hdev->hw.mac.phydev; 8538 8539 if (!phydev) 8540 return; 8541 8542 phy_set_asym_pause(phydev, rx_en, tx_en); 8543 } 8544 8545 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 8546 { 8547 int ret; 8548 8549 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 8550 return 0; 8551 8552 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 8553 if (ret) 8554 dev_err(&hdev->pdev->dev, 8555 "configure pauseparam error, ret = %d.\n", ret); 8556 8557 return ret; 8558 } 8559 8560 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 8561 { 8562 struct phy_device *phydev = hdev->hw.mac.phydev; 8563 u16 remote_advertising = 0; 8564 u16 local_advertising; 8565 u32 rx_pause, tx_pause; 8566 u8 flowctl; 8567 8568 if (!phydev->link) 8569 return 0; 8570 8571 if (!phydev->autoneg) 8572 return hclge_mac_pause_setup_hw(hdev); 8573 8574 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 8575 8576 if (phydev->pause) 8577 remote_advertising = LPA_PAUSE_CAP; 8578 8579 if (phydev->asym_pause) 8580 remote_advertising |= LPA_PAUSE_ASYM; 8581 8582 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 8583 remote_advertising); 8584 tx_pause = flowctl & FLOW_CTRL_TX; 8585 rx_pause = flowctl & FLOW_CTRL_RX; 8586 8587 if (phydev->duplex == HCLGE_MAC_HALF) { 8588 tx_pause = 0; 8589 rx_pause = 0; 8590 } 8591 8592 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 8593 } 8594 8595 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 8596 u32 *rx_en, u32 *tx_en) 8597 { 8598 struct hclge_vport *vport = hclge_get_vport(handle); 8599 struct hclge_dev *hdev = vport->back; 8600 u8 media_type = hdev->hw.mac.media_type; 8601 8602 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 8603 hclge_get_autoneg(handle) : 0; 8604 8605 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 8606 *rx_en = 0; 8607 *tx_en = 0; 8608 return; 8609 } 8610 8611 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 8612 *rx_en = 1; 8613 *tx_en = 0; 8614 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 8615 *tx_en = 1; 8616 *rx_en = 0; 8617 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 8618 *rx_en = 1; 8619 *tx_en = 1; 8620 } else { 8621 *rx_en = 0; 8622 *tx_en = 0; 8623 } 8624 } 8625 8626 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 8627 u32 rx_en, u32 tx_en) 8628 { 8629 if (rx_en && tx_en) 8630 hdev->fc_mode_last_time = HCLGE_FC_FULL; 8631 else if (rx_en && !tx_en) 8632 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 8633 else if (!rx_en && tx_en) 8634 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 8635 else 8636 hdev->fc_mode_last_time = HCLGE_FC_NONE; 8637 8638 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 8639 } 8640 8641 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 8642 u32 rx_en, u32 tx_en) 8643 { 8644 struct hclge_vport *vport = hclge_get_vport(handle); 8645 struct hclge_dev *hdev = vport->back; 8646 struct phy_device *phydev = hdev->hw.mac.phydev; 8647 u32 fc_autoneg; 8648 8649 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 8650 fc_autoneg = hclge_get_autoneg(handle); 8651 if (auto_neg != fc_autoneg) { 8652 dev_info(&hdev->pdev->dev, 8653 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 8654 return -EOPNOTSUPP; 8655 } 8656 } 8657 8658 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 8659 dev_info(&hdev->pdev->dev, 8660 "Priority flow control enabled. Cannot set link flow control.\n"); 8661 return -EOPNOTSUPP; 8662 } 8663 8664 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 8665 8666 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 8667 8668 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 8669 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 8670 8671 if (phydev) 8672 return phy_start_aneg(phydev); 8673 8674 return -EOPNOTSUPP; 8675 } 8676 8677 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 8678 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 8679 { 8680 struct hclge_vport *vport = hclge_get_vport(handle); 8681 struct hclge_dev *hdev = vport->back; 8682 8683 if (speed) 8684 *speed = hdev->hw.mac.speed; 8685 if (duplex) 8686 *duplex = hdev->hw.mac.duplex; 8687 if (auto_neg) 8688 *auto_neg = hdev->hw.mac.autoneg; 8689 if (lane_num) 8690 *lane_num = hdev->hw.mac.lane_num; 8691 } 8692 8693 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 8694 u8 *module_type) 8695 { 8696 struct hclge_vport *vport = hclge_get_vport(handle); 8697 struct hclge_dev *hdev = vport->back; 8698 8699 /* When nic is down, the service task is not running, doesn't update 8700 * the port information per second. Query the port information before 8701 * return the media type, ensure getting the correct media information. 8702 */ 8703 hclge_update_port_info(hdev); 8704 8705 if (media_type) 8706 *media_type = hdev->hw.mac.media_type; 8707 8708 if (module_type) 8709 *module_type = hdev->hw.mac.module_type; 8710 } 8711 8712 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 8713 u8 *tp_mdix_ctrl, u8 *tp_mdix) 8714 { 8715 struct hclge_vport *vport = hclge_get_vport(handle); 8716 struct hclge_dev *hdev = vport->back; 8717 struct phy_device *phydev = hdev->hw.mac.phydev; 8718 int mdix_ctrl, mdix, is_resolved; 8719 unsigned int retval; 8720 8721 if (!phydev) { 8722 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 8723 *tp_mdix = ETH_TP_MDI_INVALID; 8724 return; 8725 } 8726 8727 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 8728 8729 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 8730 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 8731 HCLGE_PHY_MDIX_CTRL_S); 8732 8733 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 8734 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 8735 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 8736 8737 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 8738 8739 switch (mdix_ctrl) { 8740 case 0x0: 8741 *tp_mdix_ctrl = ETH_TP_MDI; 8742 break; 8743 case 0x1: 8744 *tp_mdix_ctrl = ETH_TP_MDI_X; 8745 break; 8746 case 0x3: 8747 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 8748 break; 8749 default: 8750 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 8751 break; 8752 } 8753 8754 if (!is_resolved) 8755 *tp_mdix = ETH_TP_MDI_INVALID; 8756 else if (mdix) 8757 *tp_mdix = ETH_TP_MDI_X; 8758 else 8759 *tp_mdix = ETH_TP_MDI; 8760 } 8761 8762 static void hclge_info_show(struct hclge_dev *hdev) 8763 { 8764 struct hnae3_handle *handle = &hdev->vport->nic; 8765 struct device *dev = &hdev->pdev->dev; 8766 8767 dev_info(dev, "PF info begin:\n"); 8768 8769 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 8770 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 8771 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 8772 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 8773 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 8774 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 8775 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 8776 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 8777 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 8778 dev_info(dev, "This is %s PF\n", 8779 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 8780 dev_info(dev, "DCB %s\n", 8781 str_enable_disable(handle->kinfo.tc_info.dcb_ets_active)); 8782 dev_info(dev, "MQPRIO %s\n", 8783 str_enable_disable(handle->kinfo.tc_info.mqprio_active)); 8784 dev_info(dev, "Default tx spare buffer size: %u\n", 8785 hdev->tx_spare_buf_size); 8786 8787 dev_info(dev, "PF info end.\n"); 8788 } 8789 8790 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 8791 struct hclge_vport *vport) 8792 { 8793 struct hnae3_client *client = vport->nic.client; 8794 struct hclge_dev *hdev = ae_dev->priv; 8795 u32 rst_cnt = hdev->rst_stats.reset_cnt; 8796 int ret; 8797 8798 ret = client->ops->init_instance(&vport->nic); 8799 if (ret) 8800 return ret; 8801 8802 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8803 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8804 rst_cnt != hdev->rst_stats.reset_cnt) { 8805 ret = -EBUSY; 8806 goto init_nic_err; 8807 } 8808 8809 /* Enable nic hw error interrupts */ 8810 ret = hclge_config_nic_hw_error(hdev, true); 8811 if (ret) { 8812 dev_err(&ae_dev->pdev->dev, 8813 "fail(%d) to enable hw error interrupts\n", ret); 8814 goto init_nic_err; 8815 } 8816 8817 hnae3_set_client_init_flag(client, ae_dev, 1); 8818 8819 if (netif_msg_drv(&hdev->vport->nic)) 8820 hclge_info_show(hdev); 8821 8822 return ret; 8823 8824 init_nic_err: 8825 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8826 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8827 msleep(HCLGE_WAIT_RESET_DONE); 8828 8829 client->ops->uninit_instance(&vport->nic, 0); 8830 8831 return ret; 8832 } 8833 8834 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 8835 struct hclge_vport *vport) 8836 { 8837 struct hclge_dev *hdev = ae_dev->priv; 8838 struct hnae3_client *client; 8839 u32 rst_cnt; 8840 int ret; 8841 8842 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 8843 !hdev->nic_client) 8844 return 0; 8845 8846 client = hdev->roce_client; 8847 ret = hclge_init_roce_base_info(vport); 8848 if (ret) 8849 return ret; 8850 8851 rst_cnt = hdev->rst_stats.reset_cnt; 8852 ret = client->ops->init_instance(&vport->roce); 8853 if (ret) 8854 return ret; 8855 8856 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8857 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8858 rst_cnt != hdev->rst_stats.reset_cnt) { 8859 ret = -EBUSY; 8860 goto init_roce_err; 8861 } 8862 8863 /* Enable roce ras interrupts */ 8864 ret = hclge_config_rocee_ras_interrupt(hdev, true); 8865 if (ret) { 8866 dev_err(&ae_dev->pdev->dev, 8867 "fail(%d) to enable roce ras interrupts\n", ret); 8868 goto init_roce_err; 8869 } 8870 8871 hnae3_set_client_init_flag(client, ae_dev, 1); 8872 8873 return 0; 8874 8875 init_roce_err: 8876 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8877 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8878 msleep(HCLGE_WAIT_RESET_DONE); 8879 8880 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 8881 8882 return ret; 8883 } 8884 8885 static int hclge_init_client_instance(struct hnae3_client *client, 8886 struct hnae3_ae_dev *ae_dev) 8887 { 8888 struct hclge_dev *hdev = ae_dev->priv; 8889 struct hclge_vport *vport = &hdev->vport[0]; 8890 int ret; 8891 8892 switch (client->type) { 8893 case HNAE3_CLIENT_KNIC: 8894 hdev->nic_client = client; 8895 vport->nic.client = client; 8896 ret = hclge_init_nic_client_instance(ae_dev, vport); 8897 if (ret) 8898 goto clear_nic; 8899 8900 ret = hclge_init_roce_client_instance(ae_dev, vport); 8901 if (ret) 8902 goto clear_roce; 8903 8904 break; 8905 case HNAE3_CLIENT_ROCE: 8906 if (hnae3_dev_roce_supported(hdev)) { 8907 hdev->roce_client = client; 8908 vport->roce.client = client; 8909 } 8910 8911 ret = hclge_init_roce_client_instance(ae_dev, vport); 8912 if (ret) 8913 goto clear_roce; 8914 8915 break; 8916 default: 8917 return -EINVAL; 8918 } 8919 8920 return 0; 8921 8922 clear_nic: 8923 hdev->nic_client = NULL; 8924 vport->nic.client = NULL; 8925 return ret; 8926 clear_roce: 8927 hdev->roce_client = NULL; 8928 vport->roce.client = NULL; 8929 return ret; 8930 } 8931 8932 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 8933 { 8934 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8935 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 8936 } 8937 8938 static void hclge_uninit_client_instance(struct hnae3_client *client, 8939 struct hnae3_ae_dev *ae_dev) 8940 { 8941 struct hclge_dev *hdev = ae_dev->priv; 8942 struct hclge_vport *vport = &hdev->vport[0]; 8943 8944 if (hdev->roce_client) { 8945 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8946 while (hclge_uninit_need_wait(hdev)) 8947 msleep(HCLGE_WAIT_RESET_DONE); 8948 8949 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 8950 hdev->roce_client = NULL; 8951 vport->roce.client = NULL; 8952 } 8953 if (client->type == HNAE3_CLIENT_ROCE) 8954 return; 8955 if (hdev->nic_client && client->ops->uninit_instance) { 8956 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8957 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8958 msleep(HCLGE_WAIT_RESET_DONE); 8959 8960 client->ops->uninit_instance(&vport->nic, 0); 8961 hdev->nic_client = NULL; 8962 vport->nic.client = NULL; 8963 } 8964 } 8965 8966 static int hclge_dev_mem_map(struct hclge_dev *hdev) 8967 { 8968 struct pci_dev *pdev = hdev->pdev; 8969 struct hclge_hw *hw = &hdev->hw; 8970 8971 /* for device does not have device memory, return directly */ 8972 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 8973 return 0; 8974 8975 hw->hw.mem_base = 8976 devm_ioremap_wc(&pdev->dev, 8977 pci_resource_start(pdev, HCLGE_MEM_BAR), 8978 pci_resource_len(pdev, HCLGE_MEM_BAR)); 8979 if (!hw->hw.mem_base) { 8980 dev_err(&pdev->dev, "failed to map device memory\n"); 8981 return -EFAULT; 8982 } 8983 8984 return 0; 8985 } 8986 8987 static int hclge_pci_init(struct hclge_dev *hdev) 8988 { 8989 struct pci_dev *pdev = hdev->pdev; 8990 struct hclge_hw *hw; 8991 int ret; 8992 8993 ret = pci_enable_device(pdev); 8994 if (ret) { 8995 dev_err(&pdev->dev, "failed to enable PCI device\n"); 8996 return ret; 8997 } 8998 8999 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 9000 if (ret) { 9001 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 9002 if (ret) { 9003 dev_err(&pdev->dev, 9004 "can't set consistent PCI DMA\n"); 9005 goto err_disable_device; 9006 } 9007 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 9008 } 9009 9010 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 9011 if (ret) { 9012 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 9013 goto err_disable_device; 9014 } 9015 9016 pci_set_master(pdev); 9017 hw = &hdev->hw; 9018 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 9019 if (!hw->hw.io_base) { 9020 dev_err(&pdev->dev, "Can't map configuration register space\n"); 9021 ret = -ENOMEM; 9022 goto err_release_regions; 9023 } 9024 9025 ret = hclge_dev_mem_map(hdev); 9026 if (ret) 9027 goto err_unmap_io_base; 9028 9029 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 9030 9031 return 0; 9032 9033 err_unmap_io_base: 9034 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9035 err_release_regions: 9036 pci_release_regions(pdev); 9037 err_disable_device: 9038 pci_disable_device(pdev); 9039 9040 return ret; 9041 } 9042 9043 static void hclge_pci_uninit(struct hclge_dev *hdev) 9044 { 9045 struct pci_dev *pdev = hdev->pdev; 9046 9047 if (hdev->hw.hw.mem_base) 9048 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 9049 9050 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9051 pci_free_irq_vectors(pdev); 9052 pci_release_regions(pdev); 9053 pci_disable_device(pdev); 9054 } 9055 9056 static void hclge_state_init(struct hclge_dev *hdev) 9057 { 9058 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 9059 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9060 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 9061 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9062 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 9063 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 9064 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 9065 } 9066 9067 static void hclge_state_uninit(struct hclge_dev *hdev) 9068 { 9069 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9070 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 9071 9072 if (hdev->reset_timer.function) 9073 timer_delete_sync(&hdev->reset_timer); 9074 if (hdev->service_task.work.func) 9075 cancel_delayed_work_sync(&hdev->service_task); 9076 } 9077 9078 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 9079 enum hnae3_reset_type rst_type) 9080 { 9081 #define HCLGE_RESET_RETRY_WAIT_MS 500 9082 #define HCLGE_RESET_RETRY_CNT 5 9083 9084 struct hclge_dev *hdev = ae_dev->priv; 9085 int retry_cnt = 0; 9086 int ret; 9087 9088 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 9089 down(&hdev->reset_sem); 9090 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9091 hdev->reset_type = rst_type; 9092 ret = hclge_reset_prepare(hdev); 9093 if (!ret && !hdev->reset_pending) 9094 break; 9095 9096 dev_err(&hdev->pdev->dev, 9097 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 9098 ret, hdev->reset_pending, retry_cnt); 9099 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9100 up(&hdev->reset_sem); 9101 msleep(HCLGE_RESET_RETRY_WAIT_MS); 9102 } 9103 9104 /* disable misc vector before reset done */ 9105 hclge_enable_vector(&hdev->misc_vector, false); 9106 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 9107 9108 if (hdev->reset_type == HNAE3_FLR_RESET) 9109 hdev->rst_stats.flr_rst_cnt++; 9110 } 9111 9112 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 9113 { 9114 struct hclge_dev *hdev = ae_dev->priv; 9115 int ret; 9116 9117 hclge_enable_vector(&hdev->misc_vector, true); 9118 9119 ret = hclge_reset_rebuild(hdev); 9120 if (ret) 9121 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 9122 9123 hdev->reset_type = HNAE3_NONE_RESET; 9124 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 9125 up(&hdev->reset_sem); 9126 } 9127 9128 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 9129 { 9130 u16 i; 9131 9132 for (i = 0; i < hdev->num_alloc_vport; i++) { 9133 struct hclge_vport *vport = &hdev->vport[i]; 9134 int ret; 9135 9136 /* Send cmd to clear vport's FUNC_RST_ING */ 9137 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 9138 if (ret) 9139 dev_warn(&hdev->pdev->dev, 9140 "clear vport(%u) rst failed %d!\n", 9141 vport->vport_id, ret); 9142 } 9143 } 9144 9145 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 9146 { 9147 struct hclge_desc desc; 9148 int ret; 9149 9150 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 9151 9152 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9153 /* This new command is only supported by new firmware, it will 9154 * fail with older firmware. Error value -EOPNOSUPP can only be 9155 * returned by older firmware running this command, to keep code 9156 * backward compatible we will override this value and return 9157 * success. 9158 */ 9159 if (ret && ret != -EOPNOTSUPP) { 9160 dev_err(&hdev->pdev->dev, 9161 "failed to clear hw resource, ret = %d\n", ret); 9162 return ret; 9163 } 9164 return 0; 9165 } 9166 9167 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 9168 { 9169 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 9170 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 9171 } 9172 9173 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 9174 { 9175 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 9176 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 9177 } 9178 9179 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 9180 { 9181 struct hclge_vport *vport = hclge_get_vport(handle); 9182 9183 return &vport->back->hw.mac.wol; 9184 } 9185 9186 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 9187 u32 *wol_supported) 9188 { 9189 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 9190 struct hclge_desc desc; 9191 int ret; 9192 9193 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 9194 true); 9195 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 9196 9197 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9198 if (ret) { 9199 dev_err(&hdev->pdev->dev, 9200 "failed to query wol supported, ret = %d\n", ret); 9201 return ret; 9202 } 9203 9204 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 9205 9206 return 0; 9207 } 9208 9209 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 9210 struct hclge_wol_info *wol_info) 9211 { 9212 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 9213 struct hclge_desc desc; 9214 int ret; 9215 9216 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 9217 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 9218 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 9219 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 9220 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 9221 9222 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9223 if (ret) 9224 dev_err(&hdev->pdev->dev, 9225 "failed to set wol config, ret = %d\n", ret); 9226 9227 return ret; 9228 } 9229 9230 static int hclge_update_wol(struct hclge_dev *hdev) 9231 { 9232 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 9233 9234 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 9235 return 0; 9236 9237 return hclge_set_wol_cfg(hdev, wol_info); 9238 } 9239 9240 static int hclge_init_wol(struct hclge_dev *hdev) 9241 { 9242 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 9243 int ret; 9244 9245 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 9246 return 0; 9247 9248 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 9249 ret = hclge_get_wol_supported_mode(hdev, 9250 &wol_info->wol_support_mode); 9251 if (ret) { 9252 wol_info->wol_support_mode = 0; 9253 return ret; 9254 } 9255 9256 return hclge_update_wol(hdev); 9257 } 9258 9259 static void hclge_get_wol(struct hnae3_handle *handle, 9260 struct ethtool_wolinfo *wol) 9261 { 9262 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 9263 9264 wol->supported = wol_info->wol_support_mode; 9265 wol->wolopts = wol_info->wol_current_mode; 9266 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 9267 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 9268 } 9269 9270 static int hclge_set_wol(struct hnae3_handle *handle, 9271 struct ethtool_wolinfo *wol) 9272 { 9273 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 9274 struct hclge_vport *vport = hclge_get_vport(handle); 9275 u32 wol_mode; 9276 int ret; 9277 9278 wol_mode = wol->wolopts; 9279 if (wol_mode & ~wol_info->wol_support_mode) 9280 return -EINVAL; 9281 9282 wol_info->wol_current_mode = wol_mode; 9283 if (wol_mode & WAKE_MAGICSECURE) { 9284 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 9285 wol_info->wol_sopass_size = SOPASS_MAX; 9286 } else { 9287 wol_info->wol_sopass_size = 0; 9288 } 9289 9290 ret = hclge_set_wol_cfg(vport->back, wol_info); 9291 if (ret) 9292 wol_info->wol_current_mode = 0; 9293 9294 return ret; 9295 } 9296 9297 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 9298 { 9299 struct pci_dev *pdev = ae_dev->pdev; 9300 struct hclge_dev *hdev; 9301 int ret; 9302 9303 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 9304 if (!hdev) 9305 return -ENOMEM; 9306 9307 hdev->pdev = pdev; 9308 hdev->ae_dev = ae_dev; 9309 hdev->reset_type = HNAE3_NONE_RESET; 9310 hdev->reset_level = HNAE3_FUNC_RESET; 9311 ae_dev->priv = hdev; 9312 9313 /* HW supprt 2 layer vlan */ 9314 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 9315 9316 mutex_init(&hdev->vport_lock); 9317 spin_lock_init(&hdev->fd_rule_lock); 9318 sema_init(&hdev->reset_sem, 1); 9319 9320 ret = hclge_pci_init(hdev); 9321 if (ret) 9322 goto out; 9323 9324 /* Firmware command queue initialize */ 9325 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 9326 if (ret) 9327 goto err_pci_uninit; 9328 9329 /* Firmware command initialize */ 9330 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 9331 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 9332 true, hdev->reset_pending); 9333 if (ret) 9334 goto err_cmd_uninit; 9335 9336 ret = hclge_clear_hw_resource(hdev); 9337 if (ret) 9338 goto err_cmd_uninit; 9339 9340 ret = hclge_get_cap(hdev); 9341 if (ret) 9342 goto err_cmd_uninit; 9343 9344 ret = hclge_query_dev_specs(hdev); 9345 if (ret) { 9346 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 9347 ret); 9348 goto err_cmd_uninit; 9349 } 9350 9351 ret = hclge_configure(hdev); 9352 if (ret) { 9353 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 9354 goto err_cmd_uninit; 9355 } 9356 9357 ret = hclge_init_msi(hdev); 9358 if (ret) { 9359 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 9360 goto err_cmd_uninit; 9361 } 9362 9363 ret = hclge_misc_irq_init(hdev); 9364 if (ret) 9365 goto err_msi_uninit; 9366 9367 ret = hclge_alloc_tqps(hdev); 9368 if (ret) { 9369 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 9370 goto err_msi_irq_uninit; 9371 } 9372 9373 ret = hclge_alloc_vport(hdev); 9374 if (ret) 9375 goto err_msi_irq_uninit; 9376 9377 ret = hclge_map_tqp(hdev); 9378 if (ret) 9379 goto err_msi_irq_uninit; 9380 9381 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 9382 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 9383 if (hnae3_dev_phy_imp_supported(hdev)) 9384 ret = hclge_update_tp_port_info(hdev); 9385 else 9386 ret = hclge_mac_mdio_config(hdev); 9387 9388 if (ret) 9389 goto err_msi_irq_uninit; 9390 } 9391 9392 ret = hclge_init_umv_space(hdev); 9393 if (ret) 9394 goto err_mdiobus_unreg; 9395 9396 ret = hclge_mac_init(hdev); 9397 if (ret) { 9398 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 9399 goto err_mdiobus_unreg; 9400 } 9401 9402 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 9403 if (ret) { 9404 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 9405 goto err_mdiobus_unreg; 9406 } 9407 9408 ret = hclge_config_gro(hdev); 9409 if (ret) 9410 goto err_mdiobus_unreg; 9411 9412 ret = hclge_init_vlan_config(hdev); 9413 if (ret) { 9414 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 9415 goto err_mdiobus_unreg; 9416 } 9417 9418 ret = hclge_tm_schd_init(hdev); 9419 if (ret) { 9420 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 9421 goto err_mdiobus_unreg; 9422 } 9423 9424 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 9425 &hdev->rss_cfg); 9426 if (ret) { 9427 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 9428 goto err_mdiobus_unreg; 9429 } 9430 9431 ret = hclge_rss_init_hw(hdev); 9432 if (ret) { 9433 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 9434 goto err_mdiobus_unreg; 9435 } 9436 9437 ret = init_mgr_tbl(hdev); 9438 if (ret) { 9439 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 9440 goto err_mdiobus_unreg; 9441 } 9442 9443 ret = hclge_init_fd_config(hdev); 9444 if (ret) { 9445 dev_err(&pdev->dev, 9446 "fd table init fail, ret=%d\n", ret); 9447 goto err_mdiobus_unreg; 9448 } 9449 9450 ret = hclge_ptp_init(hdev); 9451 if (ret) 9452 goto err_mdiobus_unreg; 9453 9454 ret = hclge_update_port_info(hdev); 9455 if (ret) 9456 goto err_ptp_uninit; 9457 9458 INIT_KFIFO(hdev->mac_tnl_log); 9459 9460 hclge_dcb_ops_set(hdev); 9461 9462 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 9463 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 9464 9465 hclge_clear_all_event_cause(hdev); 9466 hclge_clear_resetting_state(hdev); 9467 9468 /* Log and clear the hw errors those already occurred */ 9469 if (hnae3_dev_ras_imp_supported(hdev)) 9470 hclge_handle_occurred_error(hdev); 9471 else 9472 hclge_handle_all_hns_hw_errors(ae_dev); 9473 9474 /* request delayed reset for the error recovery because an immediate 9475 * global reset on a PF affecting pending initialization of other PFs 9476 */ 9477 if (ae_dev->hw_err_reset_req) { 9478 enum hnae3_reset_type reset_level; 9479 9480 reset_level = hclge_get_reset_level(ae_dev, 9481 &ae_dev->hw_err_reset_req); 9482 hclge_set_def_reset_request(ae_dev, reset_level); 9483 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 9484 } 9485 9486 hclge_init_rxd_adv_layout(hdev); 9487 9488 ret = hclge_init_wol(hdev); 9489 if (ret) 9490 dev_warn(&pdev->dev, 9491 "failed to wake on lan init, ret = %d\n", ret); 9492 9493 ret = hclge_devlink_init(hdev); 9494 if (ret) 9495 goto err_ptp_uninit; 9496 9497 hclge_state_init(hdev); 9498 hdev->last_reset_time = jiffies; 9499 9500 /* Enable MISC vector(vector0) */ 9501 enable_irq(hdev->misc_vector.vector_irq); 9502 hclge_enable_vector(&hdev->misc_vector, true); 9503 9504 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 9505 HCLGE_DRIVER_NAME); 9506 9507 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 9508 return 0; 9509 9510 err_ptp_uninit: 9511 hclge_ptp_uninit(hdev); 9512 err_mdiobus_unreg: 9513 if (hdev->hw.mac.phydev) 9514 mdiobus_unregister(hdev->hw.mac.mdio_bus); 9515 err_msi_irq_uninit: 9516 hclge_misc_irq_uninit(hdev); 9517 err_msi_uninit: 9518 pci_free_irq_vectors(pdev); 9519 err_cmd_uninit: 9520 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 9521 err_pci_uninit: 9522 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9523 pci_release_regions(pdev); 9524 pci_disable_device(pdev); 9525 out: 9526 mutex_destroy(&hdev->vport_lock); 9527 return ret; 9528 } 9529 9530 static void hclge_stats_clear(struct hclge_dev *hdev) 9531 { 9532 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 9533 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 9534 } 9535 9536 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 9537 { 9538 return hclge_config_switch_param(hdev, vf, enable, 9539 HCLGE_SWITCH_ANTI_SPOOF_MASK); 9540 } 9541 9542 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 9543 { 9544 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9545 HCLGE_FILTER_FE_NIC_INGRESS_B, 9546 enable, vf); 9547 } 9548 9549 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 9550 { 9551 int ret; 9552 9553 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 9554 if (ret) { 9555 dev_err(&hdev->pdev->dev, 9556 "Set vf %d mac spoof check %s failed, ret=%d\n", 9557 vf, str_on_off(enable), ret); 9558 return ret; 9559 } 9560 9561 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 9562 if (ret) 9563 dev_err(&hdev->pdev->dev, 9564 "Set vf %d vlan spoof check %s failed, ret=%d\n", 9565 vf, str_on_off(enable), ret); 9566 9567 return ret; 9568 } 9569 9570 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 9571 bool enable) 9572 { 9573 struct hclge_vport *vport = hclge_get_vport(handle); 9574 struct hclge_dev *hdev = vport->back; 9575 u32 new_spoofchk = enable ? 1 : 0; 9576 int ret; 9577 9578 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9579 return -EOPNOTSUPP; 9580 9581 vport = hclge_get_vf_vport(hdev, vf); 9582 if (!vport) 9583 return -EINVAL; 9584 9585 if (vport->vf_info.spoofchk == new_spoofchk) 9586 return 0; 9587 9588 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 9589 dev_warn(&hdev->pdev->dev, 9590 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 9591 vf); 9592 else if (enable && hclge_is_umv_space_full(vport, true)) 9593 dev_warn(&hdev->pdev->dev, 9594 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 9595 vf); 9596 9597 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 9598 if (ret) 9599 return ret; 9600 9601 vport->vf_info.spoofchk = new_spoofchk; 9602 return 0; 9603 } 9604 9605 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 9606 { 9607 struct hclge_vport *vport = hdev->vport; 9608 int ret; 9609 int i; 9610 9611 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9612 return 0; 9613 9614 /* resume the vf spoof check state after reset */ 9615 for (i = 0; i < hdev->num_alloc_vport; i++) { 9616 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 9617 vport->vf_info.spoofchk); 9618 if (ret) 9619 return ret; 9620 9621 vport++; 9622 } 9623 9624 return 0; 9625 } 9626 9627 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 9628 { 9629 struct hclge_vport *vport = hclge_get_vport(handle); 9630 struct hclge_dev *hdev = vport->back; 9631 u32 new_trusted = enable ? 1 : 0; 9632 9633 vport = hclge_get_vf_vport(hdev, vf); 9634 if (!vport) 9635 return -EINVAL; 9636 9637 if (vport->vf_info.trusted == new_trusted) 9638 return 0; 9639 9640 vport->vf_info.trusted = new_trusted; 9641 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 9642 hclge_task_schedule(hdev, 0); 9643 9644 return 0; 9645 } 9646 9647 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 9648 { 9649 int ret; 9650 int vf; 9651 9652 /* reset vf rate to default value */ 9653 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 9654 struct hclge_vport *vport = &hdev->vport[vf]; 9655 9656 vport->vf_info.max_tx_rate = 0; 9657 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 9658 if (ret) 9659 dev_err(&hdev->pdev->dev, 9660 "vf%d failed to reset to default, ret=%d\n", 9661 vf - HCLGE_VF_VPORT_START_NUM, ret); 9662 } 9663 } 9664 9665 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 9666 int min_tx_rate, int max_tx_rate) 9667 { 9668 if (min_tx_rate != 0 || 9669 max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) { 9670 dev_err(&hdev->pdev->dev, 9671 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 9672 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 9673 return -EINVAL; 9674 } 9675 9676 return 0; 9677 } 9678 9679 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 9680 int min_tx_rate, int max_tx_rate, bool force) 9681 { 9682 struct hclge_vport *vport = hclge_get_vport(handle); 9683 struct hclge_dev *hdev = vport->back; 9684 int ret; 9685 9686 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 9687 if (ret) 9688 return ret; 9689 9690 vport = hclge_get_vf_vport(hdev, vf); 9691 if (!vport) 9692 return -EINVAL; 9693 9694 if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate) 9695 return 0; 9696 9697 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 9698 if (ret) 9699 return ret; 9700 9701 vport->vf_info.max_tx_rate = max_tx_rate; 9702 9703 return 0; 9704 } 9705 9706 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 9707 { 9708 struct hnae3_handle *handle = &hdev->vport->nic; 9709 struct hclge_vport *vport; 9710 int ret; 9711 int vf; 9712 9713 /* resume the vf max_tx_rate after reset */ 9714 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 9715 vport = hclge_get_vf_vport(hdev, vf); 9716 if (!vport) 9717 return -EINVAL; 9718 9719 /* zero means max rate, after reset, firmware already set it to 9720 * max rate, so just continue. 9721 */ 9722 if (!vport->vf_info.max_tx_rate) 9723 continue; 9724 9725 ret = hclge_set_vf_rate(handle, vf, 0, 9726 vport->vf_info.max_tx_rate, true); 9727 if (ret) { 9728 dev_err(&hdev->pdev->dev, 9729 "vf%d failed to resume tx_rate:%u, ret=%d\n", 9730 vf, vport->vf_info.max_tx_rate, ret); 9731 return ret; 9732 } 9733 } 9734 9735 return 0; 9736 } 9737 9738 static void hclge_reset_vport_state(struct hclge_dev *hdev) 9739 { 9740 struct hclge_vport *vport = hdev->vport; 9741 int i; 9742 9743 for (i = 0; i < hdev->num_alloc_vport; i++) { 9744 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 9745 vport++; 9746 } 9747 } 9748 9749 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 9750 { 9751 struct hclge_dev *hdev = ae_dev->priv; 9752 struct pci_dev *pdev = ae_dev->pdev; 9753 int ret; 9754 9755 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9756 9757 hclge_stats_clear(hdev); 9758 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 9759 * so here should not clean table in memory. 9760 */ 9761 if (hdev->reset_type == HNAE3_IMP_RESET || 9762 hdev->reset_type == HNAE3_GLOBAL_RESET) { 9763 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 9764 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 9765 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 9766 hclge_reset_umv_space(hdev); 9767 } 9768 9769 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 9770 true, hdev->reset_pending); 9771 if (ret) { 9772 dev_err(&pdev->dev, "Cmd queue init failed\n"); 9773 return ret; 9774 } 9775 9776 ret = hclge_map_tqp(hdev); 9777 if (ret) { 9778 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 9779 return ret; 9780 } 9781 9782 ret = hclge_mac_init(hdev); 9783 if (ret) { 9784 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 9785 return ret; 9786 } 9787 9788 ret = hclge_tp_port_init(hdev); 9789 if (ret) { 9790 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 9791 ret); 9792 return ret; 9793 } 9794 9795 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 9796 if (ret) { 9797 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 9798 return ret; 9799 } 9800 9801 ret = hclge_config_gro(hdev); 9802 if (ret) 9803 return ret; 9804 9805 ret = hclge_init_vlan_config(hdev); 9806 if (ret) { 9807 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 9808 return ret; 9809 } 9810 9811 hclge_reset_tc_config(hdev); 9812 9813 ret = hclge_tm_init_hw(hdev, true); 9814 if (ret) { 9815 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 9816 return ret; 9817 } 9818 9819 ret = hclge_rss_init_hw(hdev); 9820 if (ret) { 9821 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 9822 return ret; 9823 } 9824 9825 ret = init_mgr_tbl(hdev); 9826 if (ret) { 9827 dev_err(&pdev->dev, 9828 "failed to reinit manager table, ret = %d\n", ret); 9829 return ret; 9830 } 9831 9832 ret = hclge_init_fd_config(hdev); 9833 if (ret) { 9834 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 9835 return ret; 9836 } 9837 9838 ret = hclge_ptp_init(hdev); 9839 if (ret) 9840 return ret; 9841 9842 /* Log and clear the hw errors those already occurred */ 9843 if (hnae3_dev_ras_imp_supported(hdev)) 9844 hclge_handle_occurred_error(hdev); 9845 else 9846 hclge_handle_all_hns_hw_errors(ae_dev); 9847 9848 /* Re-enable the hw error interrupts because 9849 * the interrupts get disabled on global reset. 9850 */ 9851 ret = hclge_config_nic_hw_error(hdev, true); 9852 if (ret) { 9853 dev_err(&pdev->dev, 9854 "fail(%d) to re-enable NIC hw error interrupts\n", 9855 ret); 9856 return ret; 9857 } 9858 9859 if (hdev->roce_client) { 9860 ret = hclge_config_rocee_ras_interrupt(hdev, true); 9861 if (ret) { 9862 dev_err(&pdev->dev, 9863 "fail(%d) to re-enable roce ras interrupts\n", 9864 ret); 9865 return ret; 9866 } 9867 } 9868 9869 hclge_reset_vport_state(hdev); 9870 ret = hclge_reset_vport_spoofchk(hdev); 9871 if (ret) 9872 return ret; 9873 9874 ret = hclge_resume_vf_rate(hdev); 9875 if (ret) 9876 return ret; 9877 9878 hclge_init_rxd_adv_layout(hdev); 9879 9880 ret = hclge_update_wol(hdev); 9881 if (ret) 9882 dev_warn(&pdev->dev, 9883 "failed to update wol config, ret = %d\n", ret); 9884 9885 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 9886 HCLGE_DRIVER_NAME); 9887 9888 return 0; 9889 } 9890 9891 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 9892 { 9893 struct hclge_dev *hdev = ae_dev->priv; 9894 struct hclge_mac *mac = &hdev->hw.mac; 9895 9896 hclge_reset_vf_rate(hdev); 9897 hclge_clear_vf_vlan(hdev); 9898 hclge_state_uninit(hdev); 9899 hclge_ptp_uninit(hdev); 9900 hclge_uninit_rxd_adv_layout(hdev); 9901 hclge_uninit_mac_table(hdev); 9902 hclge_del_all_fd_entries(hdev); 9903 9904 if (mac->phydev) 9905 mdiobus_unregister(mac->mdio_bus); 9906 9907 /* Disable MISC vector(vector0) */ 9908 hclge_enable_vector(&hdev->misc_vector, false); 9909 disable_irq(hdev->misc_vector.vector_irq); 9910 9911 /* Disable all hw interrupts */ 9912 hclge_config_mac_tnl_int(hdev, false); 9913 hclge_config_nic_hw_error(hdev, false); 9914 hclge_config_rocee_ras_interrupt(hdev, false); 9915 9916 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 9917 hclge_misc_irq_uninit(hdev); 9918 hclge_devlink_uninit(hdev); 9919 hclge_pci_uninit(hdev); 9920 hclge_uninit_vport_vlan_table(hdev); 9921 mutex_destroy(&hdev->vport_lock); 9922 ae_dev->priv = NULL; 9923 } 9924 9925 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 9926 { 9927 struct hclge_vport *vport = hclge_get_vport(handle); 9928 struct hclge_dev *hdev = vport->back; 9929 9930 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 9931 } 9932 9933 static void hclge_get_channels(struct hnae3_handle *handle, 9934 struct ethtool_channels *ch) 9935 { 9936 ch->max_combined = hclge_get_max_channels(handle); 9937 ch->other_count = 1; 9938 ch->max_other = 1; 9939 ch->combined_count = handle->kinfo.rss_size; 9940 } 9941 9942 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 9943 u16 *alloc_tqps, u16 *max_rss_size) 9944 { 9945 struct hclge_vport *vport = hclge_get_vport(handle); 9946 struct hclge_dev *hdev = vport->back; 9947 9948 *alloc_tqps = vport->alloc_tqps; 9949 *max_rss_size = hdev->pf_rss_size_max; 9950 } 9951 9952 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 9953 { 9954 struct hclge_vport *vport = hclge_get_vport(handle); 9955 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 9956 struct hclge_dev *hdev = vport->back; 9957 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 9958 u16 tc_valid[HCLGE_MAX_TC_NUM]; 9959 u16 roundup_size; 9960 unsigned int i; 9961 9962 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 9963 roundup_size = ilog2(roundup_size); 9964 /* Set the RSS TC mode according to the new RSS size */ 9965 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 9966 tc_valid[i] = 0; 9967 9968 if (!(hdev->hw_tc_map & BIT(i))) 9969 continue; 9970 9971 tc_valid[i] = 1; 9972 tc_size[i] = roundup_size; 9973 tc_offset[i] = vport->nic.kinfo.rss_size * i; 9974 } 9975 9976 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 9977 tc_size); 9978 } 9979 9980 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 9981 bool rxfh_configured) 9982 { 9983 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 9984 struct hclge_vport *vport = hclge_get_vport(handle); 9985 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 9986 struct hclge_dev *hdev = vport->back; 9987 u16 cur_rss_size = kinfo->rss_size; 9988 u16 cur_tqps = kinfo->num_tqps; 9989 u32 *rss_indir; 9990 unsigned int i; 9991 int ret; 9992 9993 kinfo->req_rss_size = new_tqps_num; 9994 9995 ret = hclge_tm_vport_map_update(hdev); 9996 if (ret) { 9997 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 9998 return ret; 9999 } 10000 10001 ret = hclge_set_rss_tc_mode_cfg(handle); 10002 if (ret) 10003 return ret; 10004 10005 /* RSS indirection table has been configured by user */ 10006 if (rxfh_configured) 10007 goto out; 10008 10009 /* Reinitializes the rss indirect table according to the new RSS size */ 10010 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 10011 GFP_KERNEL); 10012 if (!rss_indir) 10013 return -ENOMEM; 10014 10015 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 10016 rss_indir[i] = i % kinfo->rss_size; 10017 10018 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 10019 if (ret) 10020 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 10021 ret); 10022 10023 kfree(rss_indir); 10024 10025 out: 10026 if (!ret) 10027 dev_info(&hdev->pdev->dev, 10028 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 10029 cur_rss_size, kinfo->rss_size, 10030 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 10031 10032 return ret; 10033 } 10034 10035 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 10036 { 10037 struct hclge_set_led_state_cmd *req; 10038 struct hclge_desc desc; 10039 int ret; 10040 10041 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 10042 10043 req = (struct hclge_set_led_state_cmd *)desc.data; 10044 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 10045 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 10046 10047 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10048 if (ret) 10049 dev_err(&hdev->pdev->dev, 10050 "Send set led state cmd error, ret =%d\n", ret); 10051 10052 return ret; 10053 } 10054 10055 enum hclge_led_status { 10056 HCLGE_LED_OFF, 10057 HCLGE_LED_ON, 10058 HCLGE_LED_NO_CHANGE = 0xFF, 10059 }; 10060 10061 static int hclge_set_led_id(struct hnae3_handle *handle, 10062 enum ethtool_phys_id_state status) 10063 { 10064 struct hclge_vport *vport = hclge_get_vport(handle); 10065 struct hclge_dev *hdev = vport->back; 10066 10067 switch (status) { 10068 case ETHTOOL_ID_ACTIVE: 10069 return hclge_set_led_status(hdev, HCLGE_LED_ON); 10070 case ETHTOOL_ID_INACTIVE: 10071 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 10072 default: 10073 return -EINVAL; 10074 } 10075 } 10076 10077 static void hclge_get_link_mode(struct hnae3_handle *handle, 10078 unsigned long *supported, 10079 unsigned long *advertising) 10080 { 10081 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 10082 struct hclge_vport *vport = hclge_get_vport(handle); 10083 struct hclge_dev *hdev = vport->back; 10084 unsigned int idx = 0; 10085 10086 for (; idx < size; idx++) { 10087 supported[idx] = hdev->hw.mac.supported[idx]; 10088 advertising[idx] = hdev->hw.mac.advertising[idx]; 10089 } 10090 } 10091 10092 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 10093 { 10094 struct hclge_vport *vport = hclge_get_vport(handle); 10095 struct hclge_dev *hdev = vport->back; 10096 bool gro_en_old = hdev->gro_en; 10097 int ret; 10098 10099 hdev->gro_en = enable; 10100 ret = hclge_config_gro(hdev); 10101 if (ret) 10102 hdev->gro_en = gro_en_old; 10103 10104 return ret; 10105 } 10106 10107 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 10108 { 10109 struct hnae3_handle *handle = &vport->nic; 10110 struct hclge_dev *hdev = vport->back; 10111 bool uc_en = false; 10112 bool mc_en = false; 10113 u8 tmp_flags; 10114 bool bc_en; 10115 int ret; 10116 10117 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 10118 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 10119 vport->last_promisc_flags = vport->overflow_promisc_flags; 10120 } 10121 10122 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 10123 &vport->state)) 10124 return 0; 10125 10126 /* for PF */ 10127 if (!vport->vport_id) { 10128 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 10129 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 10130 tmp_flags & HNAE3_MPE); 10131 if (!ret) 10132 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10133 &vport->state); 10134 else 10135 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 10136 &vport->state); 10137 return ret; 10138 } 10139 10140 /* for VF */ 10141 if (vport->vf_info.trusted) { 10142 uc_en = vport->vf_info.request_uc_en > 0 || 10143 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 10144 mc_en = vport->vf_info.request_mc_en > 0 || 10145 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 10146 } 10147 bc_en = vport->vf_info.request_bc_en > 0; 10148 10149 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 10150 mc_en, bc_en); 10151 if (ret) { 10152 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 10153 return ret; 10154 } 10155 hclge_set_vport_vlan_fltr_change(vport); 10156 10157 return 0; 10158 } 10159 10160 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 10161 { 10162 struct hclge_vport *vport; 10163 int ret; 10164 u16 i; 10165 10166 for (i = 0; i < hdev->num_alloc_vport; i++) { 10167 vport = &hdev->vport[i]; 10168 10169 ret = hclge_sync_vport_promisc_mode(vport); 10170 if (ret) 10171 return; 10172 } 10173 } 10174 10175 static bool hclge_module_existed(struct hclge_dev *hdev) 10176 { 10177 struct hclge_desc desc; 10178 u32 existed; 10179 int ret; 10180 10181 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 10182 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10183 if (ret) { 10184 dev_err(&hdev->pdev->dev, 10185 "failed to get SFP exist state, ret = %d\n", ret); 10186 return false; 10187 } 10188 10189 existed = le32_to_cpu(desc.data[0]); 10190 10191 return existed != 0; 10192 } 10193 10194 /* need 6 bds(total 140 bytes) in one reading 10195 * return the number of bytes actually read, 0 means read failed. 10196 */ 10197 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 10198 u32 len, u8 *data) 10199 { 10200 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 10201 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 10202 u16 read_len; 10203 u16 copy_len; 10204 int ret; 10205 int i; 10206 10207 /* setup all 6 bds to read module eeprom info. */ 10208 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 10209 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 10210 true); 10211 10212 /* bd0~bd4 need next flag */ 10213 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 10214 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 10215 } 10216 10217 /* setup bd0, this bd contains offset and read length. */ 10218 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 10219 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 10220 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 10221 sfp_info_bd0->read_len = cpu_to_le16(read_len); 10222 10223 ret = hclge_cmd_send(&hdev->hw, desc, i); 10224 if (ret) { 10225 dev_err(&hdev->pdev->dev, 10226 "failed to get SFP eeprom info, ret = %d\n", ret); 10227 return 0; 10228 } 10229 10230 /* copy sfp info from bd0 to out buffer. */ 10231 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 10232 memcpy(data, sfp_info_bd0->data, copy_len); 10233 read_len = copy_len; 10234 10235 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 10236 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 10237 if (read_len >= len) 10238 return read_len; 10239 10240 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 10241 memcpy(data + read_len, desc[i].data, copy_len); 10242 read_len += copy_len; 10243 } 10244 10245 return read_len; 10246 } 10247 10248 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 10249 u32 len, u8 *data) 10250 { 10251 struct hclge_vport *vport = hclge_get_vport(handle); 10252 struct hclge_dev *hdev = vport->back; 10253 u32 read_len = 0; 10254 u16 data_len; 10255 10256 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 10257 return -EOPNOTSUPP; 10258 10259 if (!hclge_module_existed(hdev)) 10260 return -ENXIO; 10261 10262 while (read_len < len) { 10263 data_len = hclge_get_sfp_eeprom_info(hdev, 10264 offset + read_len, 10265 len - read_len, 10266 data + read_len); 10267 if (!data_len) 10268 return -EIO; 10269 10270 read_len += data_len; 10271 } 10272 10273 return 0; 10274 } 10275 10276 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 10277 u32 *status_code) 10278 { 10279 struct hclge_vport *vport = hclge_get_vport(handle); 10280 struct hclge_dev *hdev = vport->back; 10281 struct hclge_desc desc; 10282 int ret; 10283 10284 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 10285 return -EOPNOTSUPP; 10286 10287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 10288 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10289 if (ret) { 10290 dev_err(&hdev->pdev->dev, 10291 "failed to query link diagnosis info, ret = %d\n", ret); 10292 return ret; 10293 } 10294 10295 *status_code = le32_to_cpu(desc.data[0]); 10296 return 0; 10297 } 10298 10299 /* After disable sriov, VF still has some config and info need clean, 10300 * which configed by PF. 10301 */ 10302 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 10303 { 10304 struct hclge_dev *hdev = vport->back; 10305 struct hclge_vlan_info vlan_info; 10306 int ret; 10307 10308 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 10309 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 10310 vport->need_notify = 0; 10311 vport->mps = 0; 10312 10313 /* after disable sriov, clean VF rate configured by PF */ 10314 ret = hclge_tm_qs_shaper_cfg(vport, 0); 10315 if (ret) 10316 dev_err(&hdev->pdev->dev, 10317 "failed to clean vf%d rate config, ret = %d\n", 10318 vfid, ret); 10319 10320 vlan_info.vlan_tag = 0; 10321 vlan_info.qos = 0; 10322 vlan_info.vlan_proto = ETH_P_8021Q; 10323 ret = hclge_update_port_base_vlan_cfg(vport, 10324 HNAE3_PORT_BASE_VLAN_DISABLE, 10325 &vlan_info); 10326 if (ret) 10327 dev_err(&hdev->pdev->dev, 10328 "failed to clean vf%d port base vlan, ret = %d\n", 10329 vfid, ret); 10330 10331 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 10332 if (ret) 10333 dev_err(&hdev->pdev->dev, 10334 "failed to clean vf%d spoof config, ret = %d\n", 10335 vfid, ret); 10336 10337 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 10338 } 10339 10340 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 10341 { 10342 struct hclge_dev *hdev = ae_dev->priv; 10343 struct hclge_vport *vport; 10344 int i; 10345 10346 for (i = 0; i < num_vfs; i++) { 10347 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 10348 10349 hclge_clear_vport_vf_info(vport, i); 10350 } 10351 } 10352 10353 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 10354 u8 *priority) 10355 { 10356 struct hclge_vport *vport = hclge_get_vport(h); 10357 10358 if (dscp >= HNAE3_MAX_DSCP) 10359 return -EINVAL; 10360 10361 if (tc_mode) 10362 *tc_mode = vport->nic.kinfo.tc_map_mode; 10363 if (priority) 10364 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 10365 vport->nic.kinfo.dscp_prio[dscp]; 10366 10367 return 0; 10368 } 10369 10370 static const struct hnae3_ae_ops hclge_ops = { 10371 .init_ae_dev = hclge_init_ae_dev, 10372 .uninit_ae_dev = hclge_uninit_ae_dev, 10373 .reset_prepare = hclge_reset_prepare_general, 10374 .reset_done = hclge_reset_done, 10375 .init_client_instance = hclge_init_client_instance, 10376 .uninit_client_instance = hclge_uninit_client_instance, 10377 .map_ring_to_vector = hclge_map_ring_to_vector, 10378 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 10379 .get_vector = hclge_get_vector, 10380 .put_vector = hclge_put_vector, 10381 .set_promisc_mode = hclge_set_promisc_mode, 10382 .request_update_promisc_mode = hclge_request_update_promisc_mode, 10383 .set_loopback = hclge_set_loopback, 10384 .start = hclge_ae_start, 10385 .stop = hclge_ae_stop, 10386 .client_start = hclge_client_start, 10387 .client_stop = hclge_client_stop, 10388 .get_status = hclge_get_status, 10389 .get_ksettings_an_result = hclge_get_ksettings_an_result, 10390 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 10391 .get_media_type = hclge_get_media_type, 10392 .check_port_speed = hclge_check_port_speed, 10393 .get_fec_stats = hclge_get_fec_stats, 10394 .get_fec = hclge_get_fec, 10395 .set_fec = hclge_set_fec, 10396 .get_rss_key_size = hclge_comm_get_rss_key_size, 10397 .get_rss = hclge_get_rss, 10398 .set_rss = hclge_set_rss, 10399 .set_rss_tuple = hclge_set_rss_tuple, 10400 .get_rss_tuple = hclge_get_rss_tuple, 10401 .get_tc_size = hclge_get_tc_size, 10402 .get_mac_addr = hclge_get_mac_addr, 10403 .set_mac_addr = hclge_set_mac_addr, 10404 .do_ioctl = hclge_do_ioctl, 10405 .add_uc_addr = hclge_add_uc_addr, 10406 .rm_uc_addr = hclge_rm_uc_addr, 10407 .add_mc_addr = hclge_add_mc_addr, 10408 .rm_mc_addr = hclge_rm_mc_addr, 10409 .set_autoneg = hclge_set_autoneg, 10410 .get_autoneg = hclge_get_autoneg, 10411 .restart_autoneg = hclge_restart_autoneg, 10412 .halt_autoneg = hclge_halt_autoneg, 10413 .get_pauseparam = hclge_get_pauseparam, 10414 .set_pauseparam = hclge_set_pauseparam, 10415 .set_mtu = hclge_set_mtu, 10416 .reset_queue = hclge_reset_tqp, 10417 .get_stats = hclge_get_stats, 10418 .get_mac_stats = hclge_get_mac_stat, 10419 .update_stats = hclge_update_stats, 10420 .get_strings = hclge_get_strings, 10421 .get_sset_count = hclge_get_sset_count, 10422 .get_fw_version = hclge_get_fw_version, 10423 .get_mdix_mode = hclge_get_mdix_mode, 10424 .enable_vlan_filter = hclge_enable_vlan_filter, 10425 .set_vlan_filter = hclge_set_vlan_filter, 10426 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 10427 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 10428 .reset_event = hclge_reset_event, 10429 .get_reset_level = hclge_get_reset_level, 10430 .set_default_reset_request = hclge_set_def_reset_request, 10431 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 10432 .set_channels = hclge_set_channels, 10433 .get_channels = hclge_get_channels, 10434 .get_regs_len = hclge_get_regs_len, 10435 .get_regs = hclge_get_regs, 10436 .set_led_id = hclge_set_led_id, 10437 .get_link_mode = hclge_get_link_mode, 10438 .add_fd_entry = hclge_add_fd_entry, 10439 .del_fd_entry = hclge_del_fd_entry, 10440 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 10441 .get_fd_rule_info = hclge_get_fd_rule_info, 10442 .get_fd_all_rules = hclge_get_all_rules, 10443 .enable_fd = hclge_enable_fd, 10444 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 10445 .dbg_get_read_func = hclge_dbg_get_read_func, 10446 .handle_hw_ras_error = hclge_handle_hw_ras_error, 10447 .get_hw_reset_stat = hclge_get_hw_reset_stat, 10448 .ae_dev_resetting = hclge_ae_dev_resetting, 10449 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 10450 .set_gro_en = hclge_gro_en, 10451 .get_global_queue_id = hclge_covert_handle_qid_global, 10452 .set_timer_task = hclge_set_timer_task, 10453 .mac_connect_phy = hclge_mac_connect_phy, 10454 .mac_disconnect_phy = hclge_mac_disconnect_phy, 10455 .get_vf_config = hclge_get_vf_config, 10456 .set_vf_link_state = hclge_set_vf_link_state, 10457 .set_vf_spoofchk = hclge_set_vf_spoofchk, 10458 .set_vf_trust = hclge_set_vf_trust, 10459 .set_vf_rate = hclge_set_vf_rate, 10460 .set_vf_mac = hclge_set_vf_mac, 10461 .get_module_eeprom = hclge_get_module_eeprom, 10462 .get_cmdq_stat = hclge_get_cmdq_stat, 10463 .add_cls_flower = hclge_add_cls_flower, 10464 .del_cls_flower = hclge_del_cls_flower, 10465 .cls_flower_active = hclge_is_cls_flower_active, 10466 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 10467 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 10468 .set_tx_hwts_info = hclge_ptp_set_tx_info, 10469 .get_rx_hwts = hclge_ptp_get_rx_hwts, 10470 .get_ts_info = hclge_ptp_get_ts_info, 10471 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 10472 .clean_vf_config = hclge_clean_vport_config, 10473 .get_dscp_prio = hclge_get_dscp_prio, 10474 .get_wol = hclge_get_wol, 10475 .set_wol = hclge_set_wol, 10476 .hwtstamp_get = hclge_ptp_get_cfg, 10477 .hwtstamp_set = hclge_ptp_set_cfg, 10478 }; 10479 10480 static struct hnae3_ae_algo ae_algo = { 10481 .ops = &hclge_ops, 10482 .pdev_id_table = ae_algo_pci_tbl, 10483 }; 10484 10485 static int __init hclge_init(void) 10486 { 10487 pr_debug("%s is initializing\n", HCLGE_NAME); 10488 10489 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, 10490 HCLGE_NAME); 10491 if (!hclge_wq) { 10492 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 10493 return -ENOMEM; 10494 } 10495 10496 hnae3_register_ae_algo(&ae_algo); 10497 10498 return 0; 10499 } 10500 10501 static void __exit hclge_exit(void) 10502 { 10503 hnae3_acquire_unload_lock(); 10504 hnae3_unregister_ae_algo_prepare(&ae_algo); 10505 hnae3_unregister_ae_algo(&ae_algo); 10506 destroy_workqueue(hclge_wq); 10507 hnae3_release_unload_lock(); 10508 } 10509 module_init(hclge_init); 10510 module_exit(hclge_exit); 10511 10512 MODULE_LICENSE("GPL"); 10513 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 10514 MODULE_DESCRIPTION("HCLGE Driver"); 10515 MODULE_VERSION(HCLGE_MOD_VERSION); 10516