1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/types.h>
10 #include <linux/cpu.h>
11 #include <asm/cpu.h>
12 #include <asm/cputype.h>
13 #include <asm/cpufeature.h>
14 #include <asm/fpsimd.h>
15 #include <asm/kvm_asm.h>
16 #include <asm/smp_plat.h>
17
18 static u64 target_impl_cpu_num;
19 static struct target_impl_cpu *target_impl_cpus;
20
cpu_errata_set_target_impl(u64 num,void * impl_cpus)21 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus)
22 {
23 if (target_impl_cpu_num || !num || !impl_cpus)
24 return false;
25
26 target_impl_cpu_num = num;
27 target_impl_cpus = impl_cpus;
28 return true;
29 }
30
is_midr_in_range(struct midr_range const * range)31 static inline bool is_midr_in_range(struct midr_range const *range)
32 {
33 int i;
34
35 if (!target_impl_cpu_num)
36 return midr_is_cpu_model_range(read_cpuid_id(), range->model,
37 range->rv_min, range->rv_max);
38
39 for (i = 0; i < target_impl_cpu_num; i++) {
40 if (midr_is_cpu_model_range(target_impl_cpus[i].midr,
41 range->model,
42 range->rv_min, range->rv_max))
43 return true;
44 }
45 return false;
46 }
47
is_midr_in_range_list(struct midr_range const * ranges)48 bool is_midr_in_range_list(struct midr_range const *ranges)
49 {
50 while (ranges->model)
51 if (is_midr_in_range(ranges++))
52 return true;
53 return false;
54 }
55 EXPORT_SYMBOL_GPL(is_midr_in_range_list);
56
57 static bool __maybe_unused
__is_affected_midr_range(const struct arm64_cpu_capabilities * entry,u32 midr,u32 revidr)58 __is_affected_midr_range(const struct arm64_cpu_capabilities *entry,
59 u32 midr, u32 revidr)
60 {
61 const struct arm64_midr_revidr *fix;
62 if (!is_midr_in_range(&entry->midr_range))
63 return false;
64
65 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
66 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
67 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
68 return false;
69 return true;
70 }
71
72 static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities * entry,int scope)73 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
74 {
75 int i;
76
77 if (!target_impl_cpu_num) {
78 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
79 return __is_affected_midr_range(entry, read_cpuid_id(),
80 read_cpuid(REVIDR_EL1));
81 }
82
83 for (i = 0; i < target_impl_cpu_num; i++) {
84 if (__is_affected_midr_range(entry, target_impl_cpus[i].midr,
85 target_impl_cpus[i].revidr))
86 return true;
87 }
88 return false;
89 }
90
91 static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities * entry,int scope)92 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
93 int scope)
94 {
95 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
96 return is_midr_in_range_list(entry->midr_range_list);
97 }
98
99 static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities * entry,int scope)100 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
101 {
102 u32 model;
103
104 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
105
106 model = read_cpuid_id();
107 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
108 MIDR_ARCHITECTURE_MASK;
109
110 return model == entry->midr_range.model;
111 }
112
113 static bool
has_mismatched_cache_type(const struct arm64_cpu_capabilities * entry,int scope)114 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
115 int scope)
116 {
117 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
118 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
119 u64 ctr_raw, ctr_real;
120
121 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
122
123 /*
124 * We want to make sure that all the CPUs in the system expose
125 * a consistent CTR_EL0 to make sure that applications behaves
126 * correctly with migration.
127 *
128 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
129 *
130 * 1) It is safe if the system doesn't support IDC, as CPU anyway
131 * reports IDC = 0, consistent with the rest.
132 *
133 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
134 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
135 *
136 * So, we need to make sure either the raw CTR_EL0 or the effective
137 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
138 */
139 ctr_raw = read_cpuid_cachetype() & mask;
140 ctr_real = read_cpuid_effective_cachetype() & mask;
141
142 return (ctr_real != sys) && (ctr_raw != sys);
143 }
144
145 #ifdef CONFIG_ARM64_ERRATUM_4311569
146 static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569);
early_arm_si_l1_workaround_4311569_cfg(char * arg)147 static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg)
148 {
149 static_branch_enable(&arm_si_l1_workaround_4311569);
150 pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n");
151
152 return 0;
153 }
154 early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg);
155
156 /*
157 * We have some earlier use cases to call cache maintenance operation functions, for example,
158 * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this
159 * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its
160 * safe to have the workaround off by default.
161 */
162 static bool
need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities * entry,int scope)163 need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope)
164 {
165 return static_branch_unlikely(&arm_si_l1_workaround_4311569);
166 }
167 #endif
168
169 static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities * cap)170 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
171 {
172 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
173 bool enable_uct_trap = false;
174
175 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
176 if ((read_cpuid_cachetype() & mask) !=
177 (arm64_ftr_reg_ctrel0.sys_val & mask))
178 enable_uct_trap = true;
179
180 /* ... or if the system is affected by an erratum */
181 if (cap->capability == ARM64_WORKAROUND_1542419)
182 enable_uct_trap = true;
183
184 if (enable_uct_trap)
185 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
186 }
187
188 #ifdef CONFIG_ARM64_ERRATUM_1463225
189 static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities * entry,int scope)190 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
191 int scope)
192 {
193 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
194 }
195 #endif
196
197 static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities * __unused)198 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
199 {
200 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
201 }
202
203 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
204 .matches = is_affected_midr_range, \
205 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
206
207 #define CAP_MIDR_ALL_VERSIONS(model) \
208 .matches = is_affected_midr_range, \
209 .midr_range = MIDR_ALL_VERSIONS(model)
210
211 #define MIDR_FIXED(rev, revidr_mask) \
212 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
213
214 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
215 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
216 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
217
218 #define CAP_MIDR_RANGE_LIST(list) \
219 .matches = is_affected_midr_range_list, \
220 .midr_range_list = list
221
222 /* Errata affecting a range of revisions of given model variant */
223 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
224 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
225
226 /* Errata affecting a single variant/revision of a model */
227 #define ERRATA_MIDR_REV(model, var, rev) \
228 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
229
230 /* Errata affecting all variants/revisions of a given a model */
231 #define ERRATA_MIDR_ALL_VERSIONS(model) \
232 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
233 CAP_MIDR_ALL_VERSIONS(model)
234
235 /* Errata affecting a list of midr ranges, with same work around */
236 #define ERRATA_MIDR_RANGE_LIST(midr_list) \
237 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
238 CAP_MIDR_RANGE_LIST(midr_list)
239
240 static const __maybe_unused struct midr_range tx2_family_cpus[] = {
241 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
242 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
243 {},
244 };
245
246 static bool __maybe_unused
needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities * entry,int scope)247 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
248 int scope)
249 {
250 int i;
251
252 if (!is_affected_midr_range_list(entry, scope) ||
253 !is_hyp_mode_available())
254 return false;
255
256 for_each_possible_cpu(i) {
257 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
258 return true;
259 }
260
261 return false;
262 }
263
264 static bool __maybe_unused
has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities * entry,int scope)265 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
266 int scope)
267 {
268 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
269 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
270
271 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
272 return is_midr_in_range(&range) && has_dic;
273 }
274
275 static const struct midr_range apple_cpus[] = {
276 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
277 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
278 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
279 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
280 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
281 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
282 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
283 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
284 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
285 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
286 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
287 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
288 {},
289 };
290
has_impdef_pmuv3(const struct arm64_cpu_capabilities * entry,int scope)291 static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope)
292 {
293 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
294 unsigned int pmuver;
295
296 if (!is_kernel_in_hyp_mode())
297 return false;
298
299 pmuver = cpuid_feature_extract_unsigned_field(dfr0,
300 ID_AA64DFR0_EL1_PMUVer_SHIFT);
301 if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
302 return false;
303
304 return is_midr_in_range_list(apple_cpus);
305 }
306
has_broken_gic_v3_seis(const struct arm64_cpu_capabilities * entry,int scope)307 static bool has_broken_gic_v3_seis(const struct arm64_cpu_capabilities *entry, int scope)
308 {
309 return (is_kernel_in_hyp_mode() &&
310 is_midr_in_range_list(apple_cpus) &&
311 (read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS));
312 }
313
cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities * __unused)314 static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused)
315 {
316 sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56));
317 }
318
319 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC
320 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
321 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
322 {
323 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
324 },
325 {
326 .midr_range.model = MIDR_QCOM_KRYO,
327 .matches = is_kryo_midr,
328 },
329 #endif
330 #ifdef CONFIG_ARM64_ERRATUM_1286807
331 {
332 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
333 },
334 {
335 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
336 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
337 },
338 #endif
339 #ifdef CONFIG_ARM64_ERRATUM_2441007
340 {
341 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
342 },
343 #endif
344 #ifdef CONFIG_ARM64_ERRATUM_2441009
345 {
346 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
347 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
348 },
349 #endif
350 #ifdef CONFIG_ARM64_ERRATUM_4118414
351 {
352 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) {
353 MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM),
354 MIDR_ALL_VERSIONS(MIDR_C1_ULTRA),
355 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
356 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
357 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
358 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
359 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
360 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
361 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
362 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
363 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
364 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
365 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
366 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
367 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
368 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
369 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
370 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
371 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
372 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
373 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
374 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
375 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
376 {}
377 })),
378 },
379 #endif
380 {}
381 };
382 #endif
383
384 #ifdef CONFIG_CAVIUM_ERRATUM_23154
385 static const struct midr_range cavium_erratum_23154_cpus[] = {
386 MIDR_ALL_VERSIONS(MIDR_THUNDERX),
387 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX),
388 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX),
389 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX),
390 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX),
391 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX),
392 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),
393 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),
394 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),
395 {},
396 };
397 #endif
398
399 #ifdef CONFIG_CAVIUM_ERRATUM_27456
400 static const struct midr_range cavium_erratum_27456_cpus[] = {
401 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
402 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
403 /* Cavium ThunderX, T81 pass 1.0 */
404 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
405 {},
406 };
407 #endif
408
409 #ifdef CONFIG_CAVIUM_ERRATUM_30115
410 static const struct midr_range cavium_erratum_30115_cpus[] = {
411 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
412 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
413 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
414 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
415 /* Cavium ThunderX, T83 pass 1.0 */
416 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
417 {},
418 };
419 #endif
420
421 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
422 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
423 {
424 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
425 },
426 {
427 .midr_range.model = MIDR_QCOM_KRYO,
428 .matches = is_kryo_midr,
429 },
430 {},
431 };
432 #endif
433
434 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
435 static const struct midr_range workaround_clean_cache[] = {
436 #if defined(CONFIG_ARM64_ERRATUM_826319) || \
437 defined(CONFIG_ARM64_ERRATUM_827319) || \
438 defined(CONFIG_ARM64_ERRATUM_824069)
439 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
440 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
441 #endif
442 #ifdef CONFIG_ARM64_ERRATUM_819472
443 /* Cortex-A53 r0p[01] : ARM errata 819472 */
444 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
445 #endif
446 {},
447 };
448 #endif
449
450 #ifdef CONFIG_ARM64_ERRATUM_1418040
451 /*
452 * - 1188873 affects r0p0 to r2p0
453 * - 1418040 affects r0p0 to r3p1
454 */
455 static const struct midr_range erratum_1418040_list[] = {
456 /* Cortex-A76 r0p0 to r3p1 */
457 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
458 /* Neoverse-N1 r0p0 to r3p1 */
459 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
460 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
461 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
462 {},
463 };
464 #endif
465
466 #ifdef CONFIG_ARM64_ERRATUM_845719
467 static const struct midr_range erratum_845719_list[] = {
468 /* Cortex-A53 r0p[01234] */
469 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
470 /* Brahma-B53 r0p[0] */
471 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
472 /* Kryo2XX Silver rAp4 */
473 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
474 {},
475 };
476 #endif
477
478 #ifdef CONFIG_ARM64_ERRATUM_843419
479 static const struct arm64_cpu_capabilities erratum_843419_list[] = {
480 {
481 /* Cortex-A53 r0p[01234] */
482 .matches = is_affected_midr_range,
483 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
484 MIDR_FIXED(0x4, BIT(8)),
485 },
486 {
487 /* Brahma-B53 r0p[0] */
488 .matches = is_affected_midr_range,
489 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
490 },
491 {},
492 };
493 #endif
494
495 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
496 static const struct midr_range erratum_speculative_at_list[] = {
497 #ifdef CONFIG_ARM64_ERRATUM_1165522
498 /* Cortex A76 r0p0 to r2p0 */
499 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
500 #endif
501 #ifdef CONFIG_ARM64_ERRATUM_1319367
502 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
503 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
504 #endif
505 #ifdef CONFIG_ARM64_ERRATUM_1530923
506 /* Cortex A55 r0p0 to r2p0 */
507 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
508 /* Kryo4xx Silver (rdpe => r1p0) */
509 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
510 #endif
511 {},
512 };
513 #endif
514
515 #ifdef CONFIG_ARM64_ERRATUM_1463225
516 static const struct midr_range erratum_1463225[] = {
517 /* Cortex-A76 r0p0 - r3p1 */
518 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
519 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
520 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
521 {},
522 };
523 #endif
524
525 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
526 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
527 #ifdef CONFIG_ARM64_ERRATUM_2139208
528 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
529 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
530 #endif
531 #ifdef CONFIG_ARM64_ERRATUM_2119858
532 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
533 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
534 #endif
535 {},
536 };
537 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
538
539 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
540 static const struct midr_range tsb_flush_fail_cpus[] = {
541 #ifdef CONFIG_ARM64_ERRATUM_2067961
542 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
543 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
544 #endif
545 #ifdef CONFIG_ARM64_ERRATUM_2054223
546 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
547 #endif
548 {},
549 };
550 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
551
552 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
553 static struct midr_range trbe_write_out_of_range_cpus[] = {
554 #ifdef CONFIG_ARM64_ERRATUM_2253138
555 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
556 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
557 #endif
558 #ifdef CONFIG_ARM64_ERRATUM_2224489
559 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
560 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
561 #endif
562 {},
563 };
564 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
565
566 #ifdef CONFIG_ARM64_ERRATUM_1742098
567 static struct midr_range broken_aarch32_aes[] = {
568 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
569 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
570 {},
571 };
572 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
573
574 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
575 static const struct midr_range erratum_spec_unpriv_load_list[] = {
576 #ifdef CONFIG_ARM64_ERRATUM_3117295
577 MIDR_ALL_VERSIONS(MIDR_CORTEX_A510),
578 #endif
579 #ifdef CONFIG_ARM64_ERRATUM_2966298
580 /* Cortex-A520 r0p0 to r0p1 */
581 MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),
582 #endif
583 {},
584 };
585 #endif
586
587 #ifdef CONFIG_ARM64_ERRATUM_3194386
588 static const struct midr_range erratum_spec_ssbs_list[] = {
589 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
590 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
591 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
592 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
593 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
594 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
595 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
596 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
597 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
598 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
599 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
600 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
601 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
602 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
603 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
604 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
605 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
606 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
607 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
608 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
609 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
610 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
611 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
612 {}
613 };
614 #endif
615
616 #ifdef CONFIG_ARM64_ERRATUM_4193714
has_sme_dvmsync_erratum(const struct arm64_cpu_capabilities * entry,int scope)617 static bool has_sme_dvmsync_erratum(const struct arm64_cpu_capabilities *entry,
618 int scope)
619 {
620 if (!id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1)))
621 return false;
622
623 return is_affected_midr_range(entry, scope);
624 }
625
cpu_enable_sme_dvmsync(const struct arm64_cpu_capabilities * __unused)626 static void cpu_enable_sme_dvmsync(const struct arm64_cpu_capabilities *__unused)
627 {
628 if (this_cpu_has_cap(ARM64_WORKAROUND_4193714))
629 sme_enable_dvmsync();
630 }
631 #endif
632
633 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
634 static const struct midr_range erratum_ac03_cpu_38_list[] = {
635 MIDR_ALL_VERSIONS(MIDR_AMPERE1),
636 MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
637 {},
638 };
639 #endif
640
641 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23
642 static const struct midr_range erratum_ac04_cpu_23_list[] = {
643 MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
644 {},
645 };
646 #endif
647
648 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP
649 static const struct midr_range cnp_erratum_cpus[] = {
650 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
651 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
652 #endif
653 #ifdef CONFIG_HISILICON_ERRATUM_162100125
654 MIDR_ALL_VERSIONS(MIDR_HISI_HIP09),
655 #endif
656 {},
657 };
658 #endif
659
660 const struct arm64_cpu_capabilities arm64_errata[] = {
661 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
662 {
663 .desc = "ARM errata 826319, 827319, 824069, or 819472",
664 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
665 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
666 .cpu_enable = cpu_enable_cache_maint_trap,
667 },
668 #endif
669 #ifdef CONFIG_ARM64_ERRATUM_832075
670 {
671 /* Cortex-A57 r0p0 - r1p2 */
672 .desc = "ARM erratum 832075",
673 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
674 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
675 0, 0,
676 1, 2),
677 },
678 #endif
679 #ifdef CONFIG_ARM64_ERRATUM_834220
680 {
681 /* Cortex-A57 r0p0 - r1p2 */
682 .desc = "ARM erratum 834220",
683 .capability = ARM64_WORKAROUND_834220,
684 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
685 0, 0,
686 1, 2),
687 },
688 #endif
689 #ifdef CONFIG_ARM64_ERRATUM_843419
690 {
691 .desc = "ARM erratum 843419",
692 .capability = ARM64_WORKAROUND_843419,
693 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
694 .matches = cpucap_multi_entry_cap_matches,
695 .match_list = erratum_843419_list,
696 },
697 #endif
698 #ifdef CONFIG_ARM64_ERRATUM_845719
699 {
700 .desc = "ARM erratum 845719",
701 .capability = ARM64_WORKAROUND_845719,
702 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
703 },
704 #endif
705 #ifdef CONFIG_CAVIUM_ERRATUM_23154
706 {
707 .desc = "Cavium errata 23154 and 38545",
708 .capability = ARM64_WORKAROUND_CAVIUM_23154,
709 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
710 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus),
711 },
712 #endif
713 #ifdef CONFIG_CAVIUM_ERRATUM_27456
714 {
715 .desc = "Cavium erratum 27456",
716 .capability = ARM64_WORKAROUND_CAVIUM_27456,
717 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
718 },
719 #endif
720 #ifdef CONFIG_CAVIUM_ERRATUM_30115
721 {
722 .desc = "Cavium erratum 30115",
723 .capability = ARM64_WORKAROUND_CAVIUM_30115,
724 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
725 },
726 #endif
727 {
728 .desc = "Mismatched cache type (CTR_EL0)",
729 .capability = ARM64_MISMATCHED_CACHE_TYPE,
730 .matches = has_mismatched_cache_type,
731 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
732 .cpu_enable = cpu_enable_trap_ctr_access,
733 },
734 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
735 {
736 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
737 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
738 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
739 .matches = cpucap_multi_entry_cap_matches,
740 .match_list = qcom_erratum_1003_list,
741 },
742 #endif
743 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC
744 {
745 .desc = "Broken broadcast TLBI completion",
746 .capability = ARM64_WORKAROUND_REPEAT_TLBI_SYNC,
747 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
748 .matches = cpucap_multi_entry_cap_matches,
749 .match_list = arm64_repeat_tlbi_list,
750 },
751 #endif
752 #ifdef CONFIG_ARM64_ERRATUM_858921
753 {
754 /* Cortex-A73 all versions */
755 .desc = "ARM erratum 858921",
756 .capability = ARM64_WORKAROUND_858921,
757 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
758 },
759 #endif
760 {
761 .desc = "Spectre-v2",
762 .capability = ARM64_SPECTRE_V2,
763 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
764 .matches = has_spectre_v2,
765 .cpu_enable = spectre_v2_enable_mitigation,
766 },
767 #ifdef CONFIG_RANDOMIZE_BASE
768 {
769 /* Must come after the Spectre-v2 entry */
770 .desc = "Spectre-v3a",
771 .capability = ARM64_SPECTRE_V3A,
772 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
773 .matches = has_spectre_v3a,
774 .cpu_enable = spectre_v3a_enable_mitigation,
775 },
776 #endif
777 {
778 .desc = "Spectre-v4",
779 .capability = ARM64_SPECTRE_V4,
780 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
781 .matches = has_spectre_v4,
782 .cpu_enable = spectre_v4_enable_mitigation,
783 },
784 {
785 .desc = "Spectre-BHB",
786 .capability = ARM64_SPECTRE_BHB,
787 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
788 .matches = is_spectre_bhb_affected,
789 .cpu_enable = spectre_bhb_enable_mitigation,
790 },
791 #ifdef CONFIG_ARM64_ERRATUM_1418040
792 {
793 .desc = "ARM erratum 1418040",
794 .capability = ARM64_WORKAROUND_1418040,
795 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
796 /*
797 * We need to allow affected CPUs to come in late, but
798 * also need the non-affected CPUs to be able to come
799 * in at any point in time. Wonderful.
800 */
801 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
802 },
803 #endif
804 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
805 {
806 .desc = "ARM errata 1165522, 1319367, or 1530923",
807 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
808 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
809 },
810 #endif
811 #ifdef CONFIG_ARM64_ERRATUM_1463225
812 {
813 .desc = "ARM erratum 1463225",
814 .capability = ARM64_WORKAROUND_1463225,
815 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
816 .matches = has_cortex_a76_erratum_1463225,
817 .midr_range_list = erratum_1463225,
818 },
819 #endif
820 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
821 {
822 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
823 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
824 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
825 .matches = needs_tx2_tvm_workaround,
826 },
827 {
828 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
829 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
830 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
831 },
832 #endif
833 #ifdef CONFIG_ARM64_ERRATUM_1542419
834 {
835 /* we depend on the firmware portion for correctness */
836 .desc = "ARM erratum 1542419 (kernel portion)",
837 .capability = ARM64_WORKAROUND_1542419,
838 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
839 .matches = has_neoverse_n1_erratum_1542419,
840 .cpu_enable = cpu_enable_trap_ctr_access,
841 },
842 #endif
843 #ifdef CONFIG_ARM64_ERRATUM_1508412
844 {
845 /* we depend on the firmware portion for correctness */
846 .desc = "ARM erratum 1508412 (kernel portion)",
847 .capability = ARM64_WORKAROUND_1508412,
848 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
849 0, 0,
850 1, 0),
851 },
852 #endif
853 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP
854 {
855 .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125",
856 .capability = ARM64_WORKAROUND_DISABLE_CNP,
857 ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus),
858 },
859 #endif
860 #ifdef CONFIG_NVIDIA_OLYMPUS_1027_ERRATUM
861 {
862 /* NVIDIA Olympus core */
863 .desc = "NVIDIA Olympus device store/load ordering erratum",
864 .capability = ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027,
865 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
866 },
867 #endif
868 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
869 {
870 /*
871 * The erratum work around is handled within the TRBE
872 * driver and can be applied per-cpu. So, we can allow
873 * a late CPU to come online with this erratum.
874 */
875 .desc = "ARM erratum 2119858 or 2139208",
876 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
877 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
878 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
879 },
880 #endif
881 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
882 {
883 .desc = "ARM erratum 2067961 or 2054223",
884 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
885 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
886 },
887 #endif
888 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
889 {
890 .desc = "ARM erratum 2253138 or 2224489",
891 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
892 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
893 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
894 },
895 #endif
896 #ifdef CONFIG_ARM64_ERRATUM_2645198
897 {
898 .desc = "ARM erratum 2645198",
899 .capability = ARM64_WORKAROUND_2645198,
900 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715)
901 },
902 #endif
903 #ifdef CONFIG_ARM64_ERRATUM_2077057
904 {
905 .desc = "ARM erratum 2077057",
906 .capability = ARM64_WORKAROUND_2077057,
907 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
908 },
909 #endif
910 #ifdef CONFIG_ARM64_ERRATUM_2064142
911 {
912 .desc = "ARM erratum 2064142",
913 .capability = ARM64_WORKAROUND_2064142,
914
915 /* Cortex-A510 r0p0 - r0p2 */
916 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
917 },
918 #endif
919 #ifdef CONFIG_ARM64_ERRATUM_2457168
920 {
921 .desc = "ARM erratum 2457168",
922 .capability = ARM64_WORKAROUND_2457168,
923 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
924
925 /* Cortex-A510 r0p0-r1p1 */
926 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
927 },
928 #endif
929 #ifdef CONFIG_ARM64_ERRATUM_2038923
930 {
931 .desc = "ARM erratum 2038923",
932 .capability = ARM64_WORKAROUND_2038923,
933
934 /* Cortex-A510 r0p0 - r0p2 */
935 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
936 },
937 #endif
938 #ifdef CONFIG_ARM64_ERRATUM_1902691
939 {
940 .desc = "ARM erratum 1902691",
941 .capability = ARM64_WORKAROUND_1902691,
942
943 /* Cortex-A510 r0p0 - r0p1 */
944 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
945 },
946 #endif
947 #ifdef CONFIG_ARM64_ERRATUM_1742098
948 {
949 .desc = "ARM erratum 1742098",
950 .capability = ARM64_WORKAROUND_1742098,
951 CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
952 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
953 },
954 #endif
955 #ifdef CONFIG_ARM64_ERRATUM_2658417
956 {
957 .desc = "ARM erratum 2658417",
958 .capability = ARM64_WORKAROUND_2658417,
959 /* Cortex-A510 r0p0 - r1p1 */
960 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
961 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
962 },
963 #endif
964 #ifdef CONFIG_ARM64_ERRATUM_3194386
965 {
966 .desc = "SSBS not fully self-synchronizing",
967 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
968 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
969 },
970 #endif
971 #ifdef CONFIG_ARM64_ERRATUM_4311569
972 {
973 .capability = ARM64_WORKAROUND_4311569,
974 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
975 .matches = need_arm_si_l1_workaround_4311569,
976 },
977 #endif
978 #ifdef CONFIG_ARM64_ERRATUM_4193714
979 {
980 .desc = "C1-Pro SME DVMSync early acknowledgement",
981 .capability = ARM64_WORKAROUND_4193714,
982 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
983 .matches = has_sme_dvmsync_erratum,
984 .cpu_enable = cpu_enable_sme_dvmsync,
985 /* C1-Pro r0p0 - r1p2 (the latter only when REVIDR_EL1[0]==0) */
986 .midr_range = MIDR_RANGE(MIDR_C1_PRO, 0, 0, 1, 2),
987 MIDR_FIXED(MIDR_CPU_VAR_REV(1, 2), BIT(0)),
988 },
989 #endif
990 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
991 {
992 .desc = "ARM errata 2966298, 3117295",
993 .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD,
994 /* Cortex-A520 r0p0 - r0p1 */
995 ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list),
996 },
997 #endif
998 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
999 {
1000 .desc = "AmpereOne erratum AC03_CPU_38",
1001 .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38,
1002 ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list),
1003 },
1004 #endif
1005 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23
1006 {
1007 .desc = "AmpereOne erratum AC04_CPU_23",
1008 .capability = ARM64_WORKAROUND_AMPERE_AC04_CPU_23,
1009 ERRATA_MIDR_RANGE_LIST(erratum_ac04_cpu_23_list),
1010 },
1011 #endif
1012 {
1013 .desc = "Broken CNTVOFF_EL2",
1014 .capability = ARM64_WORKAROUND_QCOM_ORYON_CNTVOFF,
1015 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) {
1016 MIDR_ALL_VERSIONS(MIDR_QCOM_ORYON_X1),
1017 {}
1018 })),
1019 },
1020 {
1021 .desc = "Apple IMPDEF PMUv3 Traps",
1022 .capability = ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS,
1023 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1024 .matches = has_impdef_pmuv3,
1025 .cpu_enable = cpu_enable_impdef_pmuv3_traps,
1026 },
1027 {
1028 .desc = "Known broken GICv3 SEIS implementation",
1029 .capability = ARM64_WORKAROUND_GICv3_BROKEN_SEIS,
1030 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1031 .matches = has_broken_gic_v3_seis,
1032 },
1033 {
1034 }
1035 };
1036