1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/vmalloc.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/display/drm_dp_mst_helper.h>
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_fixed.h>
32 #include <drm/drm_edid.h>
33 #include "dm_services.h"
34 #include "amdgpu.h"
35 #include "amdgpu_dm.h"
36 #include "amdgpu_dm_mst_types.h"
37 #include "amdgpu_dm_hdcp.h"
38
39 #include "dc.h"
40 #include "dm_helpers.h"
41
42 #include "ddc_service_types.h"
43 #include "dpcd_defs.h"
44
45 #include "dmub_cmd.h"
46 #if defined(CONFIG_DEBUG_FS)
47 #include "amdgpu_dm_debugfs.h"
48 #endif
49
50 #include "dc/resource/dcn20/dcn20_resource.h"
51
52 #define PEAK_FACTOR_X1000 1006
53
54 /*
55 * This function handles both native AUX and I2C-Over-AUX transactions.
56 */
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)57 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
58 struct drm_dp_aux_msg *msg)
59 {
60 ssize_t result = 0;
61 struct aux_payload payload;
62 enum aux_return_code_type operation_result;
63 struct amdgpu_device *adev;
64 struct ddc_service *ddc;
65 uint8_t copy[16];
66
67 if (WARN_ON(msg->size > 16))
68 return -E2BIG;
69
70 payload.address = msg->address;
71 payload.data = msg->buffer;
72 payload.length = msg->size;
73 payload.reply = &msg->reply;
74 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
75 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
76 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
77 payload.write_status_update =
78 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
79 payload.defer_delay = 0;
80
81 if (payload.write) {
82 memcpy(copy, msg->buffer, msg->size);
83 payload.data = copy;
84 }
85
86 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
87 &operation_result);
88
89 /*
90 * w/a on certain intel platform where hpd is unexpected to pull low during
91 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
92 * aux transaction is succuess in such case, therefore bypass the error
93 */
94 ddc = TO_DM_AUX(aux)->ddc_service;
95 adev = ddc->ctx->driver_context;
96 if (adev->dm.aux_hpd_discon_quirk) {
97 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
98 operation_result == AUX_RET_ERROR_HPD_DISCON) {
99 result = msg->size;
100 operation_result = AUX_RET_SUCCESS;
101 }
102 }
103
104 /*
105 * result equals to 0 includes the cases of AUX_DEFER/I2C_DEFER
106 */
107 if (payload.write && result >= 0) {
108 if (result) {
109 /*one byte indicating partially written bytes*/
110 drm_dbg_dp(adev_to_drm(adev), "amdgpu: AUX partially written\n");
111 result = payload.data[0];
112 } else if (!payload.reply[0])
113 /*I2C_ACK|AUX_ACK*/
114 result = msg->size;
115 }
116
117 if (result < 0) {
118 switch (operation_result) {
119 case AUX_RET_SUCCESS:
120 break;
121 case AUX_RET_ERROR_HPD_DISCON:
122 case AUX_RET_ERROR_UNKNOWN:
123 case AUX_RET_ERROR_INVALID_OPERATION:
124 case AUX_RET_ERROR_PROTOCOL_ERROR:
125 result = -EIO;
126 break;
127 case AUX_RET_ERROR_INVALID_REPLY:
128 case AUX_RET_ERROR_ENGINE_ACQUIRE:
129 result = -EBUSY;
130 break;
131 case AUX_RET_ERROR_TIMEOUT:
132 result = -ETIMEDOUT;
133 break;
134 }
135
136 drm_dbg_dp(adev_to_drm(adev), "amdgpu: DP AUX transfer fail:%d\n", operation_result);
137 }
138
139 if (payload.reply[0])
140 drm_dbg_dp(adev_to_drm(adev), "amdgpu: AUX reply command not ACK: 0x%02x.",
141 payload.reply[0]);
142
143 return result;
144 }
145
146 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)147 dm_dp_mst_connector_destroy(struct drm_connector *connector)
148 {
149 struct amdgpu_dm_connector *aconnector =
150 to_amdgpu_dm_connector(connector);
151
152 if (aconnector->dc_sink) {
153 dc_link_remove_remote_sink(aconnector->dc_link,
154 aconnector->dc_sink);
155 dc_sink_release(aconnector->dc_sink);
156 }
157
158 drm_edid_free(aconnector->drm_edid);
159
160 drm_connector_cleanup(connector);
161 drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
162 kfree(aconnector);
163 }
164
165 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)166 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
167 {
168 struct amdgpu_dm_connector *amdgpu_dm_connector =
169 to_amdgpu_dm_connector(connector);
170 int r;
171
172 r = drm_dp_mst_connector_late_register(connector,
173 amdgpu_dm_connector->mst_output_port);
174 if (r < 0)
175 return r;
176
177 #if defined(CONFIG_DEBUG_FS)
178 connector_debugfs_init(amdgpu_dm_connector);
179 #endif
180
181 return 0;
182 }
183
184
185 static inline void
amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector * aconnector)186 amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector)
187 {
188 aconnector->drm_edid = NULL;
189 aconnector->dsc_aux = NULL;
190 aconnector->mst_output_port->passthrough_aux = NULL;
191 aconnector->mst_local_bw = 0;
192 aconnector->vc_full_pbn = 0;
193 }
194
195 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)196 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
197 {
198 struct amdgpu_dm_connector *aconnector =
199 to_amdgpu_dm_connector(connector);
200 struct drm_dp_mst_port *port = aconnector->mst_output_port;
201 struct amdgpu_dm_connector *root = aconnector->mst_root;
202 struct dc_link *dc_link = aconnector->dc_link;
203 struct dc_sink *dc_sink = aconnector->dc_sink;
204
205 drm_dp_mst_connector_early_unregister(connector, port);
206
207 /*
208 * Release dc_sink for connector which its attached port is
209 * no longer in the mst topology
210 */
211 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
212 if (dc_sink) {
213 if (dc_link->sink_count)
214 dc_link_remove_remote_sink(dc_link, dc_sink);
215
216 drm_dbg_dp(connector->dev,
217 "DM_MST: remove remote sink 0x%p, %d remaining\n",
218 dc_sink, dc_link->sink_count);
219
220 dc_sink_release(dc_sink);
221 aconnector->dc_sink = NULL;
222 amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
223 }
224
225 aconnector->mst_status = MST_STATUS_DEFAULT;
226 drm_modeset_unlock(&root->mst_mgr.base.lock);
227 }
228
229 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
230 .fill_modes = drm_helper_probe_single_connector_modes,
231 .destroy = dm_dp_mst_connector_destroy,
232 .reset = amdgpu_dm_connector_funcs_reset,
233 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
234 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
235 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
236 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
237 .late_register = amdgpu_dm_mst_connector_late_register,
238 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
239 };
240
needs_dsc_aux_workaround(struct dc_link * link)241 bool needs_dsc_aux_workaround(struct dc_link *link)
242 {
243 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
244 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
245 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
246 return true;
247
248 return false;
249 }
250
251 #if defined(CONFIG_DRM_AMD_DC_FP)
is_synaptics_cascaded_panamera(struct dc_link * link,struct drm_dp_mst_port * port)252 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
253 {
254 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
255
256 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
257 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
258 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
259 DRM_INFO("Synaptics Cascaded MST hub\n");
260 return true;
261 }
262 }
263
264 return false;
265 }
266
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)267 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
268 {
269 struct dc_sink *dc_sink = aconnector->dc_sink;
270 struct drm_dp_mst_port *port = aconnector->mst_output_port;
271 u8 dsc_caps[16] = { 0 };
272 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
273 u8 *dsc_branch_dec_caps = NULL;
274
275 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
276
277 /*
278 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
279 * because it only check the dsc/fec caps of the "port variable" and not the dock
280 *
281 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
282 *
283 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
284 *
285 */
286 if (!aconnector->dsc_aux && !port->parent->port_parent &&
287 needs_dsc_aux_workaround(aconnector->dc_link))
288 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
289
290 /* synaptics cascaded MST hub case */
291 if (is_synaptics_cascaded_panamera(aconnector->dc_link, port))
292 aconnector->dsc_aux = port->mgr->aux;
293
294 if (!aconnector->dsc_aux)
295 return false;
296
297 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
298 return false;
299
300 if (drm_dp_dpcd_read(aconnector->dsc_aux,
301 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
302 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
303
304 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
305 dsc_caps, dsc_branch_dec_caps,
306 &dc_sink->dsc_caps.dsc_dec_caps))
307 return false;
308
309 return true;
310 }
311 #endif
312
retrieve_downstream_port_device(struct amdgpu_dm_connector * aconnector)313 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
314 {
315 union dp_downstream_port_present ds_port_present;
316
317 if (!aconnector->dsc_aux)
318 return false;
319
320 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
321 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
322 return false;
323 }
324
325 aconnector->mst_downstream_port_present = ds_port_present;
326 DRM_INFO("Downstream port present %d, type %d\n",
327 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
328
329 return true;
330 }
331
dm_dp_mst_get_modes(struct drm_connector * connector)332 static int dm_dp_mst_get_modes(struct drm_connector *connector)
333 {
334 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
335 int ret = 0;
336
337 if (!aconnector)
338 return drm_add_edid_modes(connector, NULL);
339
340 if (!aconnector->drm_edid) {
341 const struct drm_edid *drm_edid;
342
343 drm_edid = drm_dp_mst_edid_read(connector,
344 &aconnector->mst_root->mst_mgr,
345 aconnector->mst_output_port);
346
347 if (!drm_edid) {
348 amdgpu_dm_set_mst_status(&aconnector->mst_status,
349 MST_REMOTE_EDID, false);
350
351 drm_edid_connector_update(
352 &aconnector->base,
353 NULL);
354
355 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
356 if (!aconnector->dc_sink) {
357 struct dc_sink *dc_sink;
358 struct dc_sink_init_data init_params = {
359 .link = aconnector->dc_link,
360 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
361
362 dc_sink = dc_link_add_remote_sink(
363 aconnector->dc_link,
364 NULL,
365 0,
366 &init_params);
367
368 if (!dc_sink) {
369 DRM_ERROR("Unable to add a remote sink\n");
370 return 0;
371 }
372
373 drm_dbg_dp(connector->dev,
374 "DM_MST: add remote sink 0x%p, %d remaining\n",
375 dc_sink,
376 aconnector->dc_link->sink_count);
377
378 dc_sink->priv = aconnector;
379 aconnector->dc_sink = dc_sink;
380 }
381
382 return ret;
383 }
384
385 aconnector->drm_edid = drm_edid;
386 amdgpu_dm_set_mst_status(&aconnector->mst_status,
387 MST_REMOTE_EDID, true);
388 }
389
390 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
391 dc_sink_release(aconnector->dc_sink);
392 aconnector->dc_sink = NULL;
393 }
394
395 if (!aconnector->dc_sink) {
396 struct dc_sink *dc_sink;
397 struct dc_sink_init_data init_params = {
398 .link = aconnector->dc_link,
399 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
400 const struct edid *edid;
401
402 edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw()
403 dc_sink = dc_link_add_remote_sink(
404 aconnector->dc_link,
405 (uint8_t *)edid,
406 (edid->extensions + 1) * EDID_LENGTH,
407 &init_params);
408
409 if (!dc_sink) {
410 DRM_ERROR("Unable to add a remote sink\n");
411 return 0;
412 }
413
414 drm_dbg_dp(connector->dev,
415 "DM_MST: add remote sink 0x%p, %d remaining\n",
416 dc_sink, aconnector->dc_link->sink_count);
417
418 dc_sink->priv = aconnector;
419 /* dc_link_add_remote_sink returns a new reference */
420 aconnector->dc_sink = dc_sink;
421
422 /* when display is unplugged from mst hub, connctor will be
423 * destroyed within dm_dp_mst_connector_destroy. connector
424 * hdcp perperties, like type, undesired, desired, enabled,
425 * will be lost. So, save hdcp properties into hdcp_work within
426 * amdgpu_dm_atomic_commit_tail. if the same display is
427 * plugged back with same display index, its hdcp properties
428 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
429 */
430 if (aconnector->dc_sink && connector->state) {
431 struct drm_device *dev = connector->dev;
432 struct amdgpu_device *adev = drm_to_adev(dev);
433
434 if (adev->dm.hdcp_workqueue) {
435 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
436 struct hdcp_workqueue *hdcp_w =
437 &hdcp_work[aconnector->dc_link->link_index];
438
439 connector->state->hdcp_content_type =
440 hdcp_w->hdcp_content_type[connector->index];
441 connector->state->content_protection =
442 hdcp_w->content_protection[connector->index];
443 }
444 }
445
446 if (aconnector->dc_sink) {
447 amdgpu_dm_update_freesync_caps(
448 connector, aconnector->drm_edid);
449
450 #if defined(CONFIG_DRM_AMD_DC_FP)
451 if (!validate_dsc_caps_on_connector(aconnector))
452 memset(&aconnector->dc_sink->dsc_caps,
453 0, sizeof(aconnector->dc_sink->dsc_caps));
454 #endif
455
456 if (!retrieve_downstream_port_device(aconnector))
457 memset(&aconnector->mst_downstream_port_present,
458 0, sizeof(aconnector->mst_downstream_port_present));
459 }
460 }
461
462 drm_edid_connector_update(&aconnector->base, aconnector->drm_edid);
463
464 ret = drm_edid_connector_add_modes(connector);
465
466 return ret;
467 }
468
469 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)470 dm_mst_atomic_best_encoder(struct drm_connector *connector,
471 struct drm_atomic_state *state)
472 {
473 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
474 connector);
475 struct amdgpu_device *adev = drm_to_adev(connector->dev);
476 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
477
478 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
479 }
480
481 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)482 dm_dp_mst_detect(struct drm_connector *connector,
483 struct drm_modeset_acquire_ctx *ctx, bool force)
484 {
485 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
486 struct amdgpu_dm_connector *master = aconnector->mst_root;
487 struct drm_dp_mst_port *port = aconnector->mst_output_port;
488 int connection_status;
489
490 if (drm_connector_is_unregistered(connector))
491 return connector_status_disconnected;
492
493 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
494 aconnector->mst_output_port);
495
496 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
497 uint8_t dpcd_rev;
498 int ret;
499
500 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
501
502 if (ret == 1) {
503 port->dpcd_rev = dpcd_rev;
504
505 /* Could be DP1.2 DP Rx case*/
506 if (!dpcd_rev) {
507 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
508
509 if (ret == 1)
510 port->dpcd_rev = dpcd_rev;
511 }
512
513 if (!dpcd_rev)
514 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
515 }
516
517 /*
518 * Could be legacy sink, logical port etc on DP1.2.
519 * Will get Nack under these cases when issue remote
520 * DPCD read.
521 */
522 if (ret != 1)
523 DRM_DEBUG_KMS("Can't access DPCD");
524 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
525 port->dpcd_rev = 0;
526 }
527
528 /*
529 * Release dc_sink for connector which unplug event is notified by CSN msg
530 */
531 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
532 if (aconnector->dc_link->sink_count)
533 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
534
535 drm_dbg_dp(connector->dev,
536 "DM_MST: remove remote sink 0x%p, %d remaining\n",
537 aconnector->dc_link,
538 aconnector->dc_link->sink_count);
539
540 dc_sink_release(aconnector->dc_sink);
541 aconnector->dc_sink = NULL;
542 amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
543
544 amdgpu_dm_set_mst_status(&aconnector->mst_status,
545 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
546 false);
547 }
548
549 return connection_status;
550 }
551
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)552 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
553 struct drm_atomic_state *state)
554 {
555 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
556 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr;
557 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port;
558
559 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
560 }
561
562 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
563 .get_modes = dm_dp_mst_get_modes,
564 .mode_valid = amdgpu_dm_connector_mode_valid,
565 .atomic_best_encoder = dm_mst_atomic_best_encoder,
566 .detect_ctx = dm_dp_mst_detect,
567 .atomic_check = dm_dp_mst_atomic_check,
568 };
569
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)570 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
571 {
572 drm_encoder_cleanup(encoder);
573 }
574
575 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
576 .destroy = amdgpu_dm_encoder_destroy,
577 };
578
579 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)580 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
581 {
582 struct drm_device *dev = adev_to_drm(adev);
583 int i;
584
585 for (i = 0; i < adev->dm.display_indexes_num; i++) {
586 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
587 struct drm_encoder *encoder = &amdgpu_encoder->base;
588
589 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
590
591 drm_encoder_init(
592 dev,
593 &amdgpu_encoder->base,
594 &amdgpu_dm_encoder_funcs,
595 DRM_MODE_ENCODER_DPMST,
596 NULL);
597
598 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
599 }
600 }
601
602 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)603 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
604 struct drm_dp_mst_port *port,
605 const char *pathprop)
606 {
607 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
608 struct drm_device *dev = master->base.dev;
609 struct amdgpu_device *adev = drm_to_adev(dev);
610 struct amdgpu_dm_connector *aconnector;
611 struct drm_connector *connector;
612 int i;
613
614 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
615 if (!aconnector)
616 return NULL;
617
618 DRM_DEBUG_DRIVER("%s: Create aconnector 0x%p for port 0x%p\n", __func__, aconnector, port);
619
620 connector = &aconnector->base;
621 aconnector->mst_output_port = port;
622 aconnector->mst_root = master;
623 amdgpu_dm_set_mst_status(&aconnector->mst_status,
624 MST_PROBE, true);
625
626 if (drm_connector_dynamic_init(
627 dev,
628 connector,
629 &dm_dp_mst_connector_funcs,
630 DRM_MODE_CONNECTOR_DisplayPort,
631 NULL)) {
632 kfree(aconnector);
633 return NULL;
634 }
635 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
636
637 amdgpu_dm_connector_init_helper(
638 &adev->dm,
639 aconnector,
640 DRM_MODE_CONNECTOR_DisplayPort,
641 master->dc_link,
642 master->connector_id);
643
644 for (i = 0; i < adev->dm.display_indexes_num; i++) {
645 drm_connector_attach_encoder(&aconnector->base,
646 &adev->dm.mst_encoders[i].base);
647 }
648
649 connector->max_bpc_property = master->base.max_bpc_property;
650 if (connector->max_bpc_property)
651 drm_connector_attach_max_bpc_property(connector, 8, 16);
652
653 connector->vrr_capable_property = master->base.vrr_capable_property;
654 if (connector->vrr_capable_property)
655 drm_connector_attach_vrr_capable_property(connector);
656
657 drm_object_attach_property(
658 &connector->base,
659 dev->mode_config.path_property,
660 0);
661 drm_object_attach_property(
662 &connector->base,
663 dev->mode_config.tile_property,
664 0);
665 connector->colorspace_property = master->base.colorspace_property;
666 if (connector->colorspace_property)
667 drm_connector_attach_colorspace_property(connector);
668
669 drm_connector_set_path_property(connector, pathprop);
670
671 /*
672 * Initialize connector state before adding the connectror to drm and
673 * framebuffer lists
674 */
675 amdgpu_dm_connector_funcs_reset(connector);
676
677 drm_dp_mst_get_port_malloc(port);
678
679 return connector;
680 }
681
dm_handle_mst_sideband_msg_ready_event(struct drm_dp_mst_topology_mgr * mgr,enum mst_msg_ready_type msg_rdy_type)682 void dm_handle_mst_sideband_msg_ready_event(
683 struct drm_dp_mst_topology_mgr *mgr,
684 enum mst_msg_ready_type msg_rdy_type)
685 {
686 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
687 uint8_t dret;
688 bool new_irq_handled = false;
689 int dpcd_addr;
690 uint8_t dpcd_bytes_to_read;
691 const uint8_t max_process_count = 30;
692 uint8_t process_count = 0;
693 u8 retry;
694 struct amdgpu_dm_connector *aconnector =
695 container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
696
697
698 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
699
700 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
701 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
702 /* DPCD 0x200 - 0x201 for downstream IRQ */
703 dpcd_addr = DP_SINK_COUNT;
704 } else {
705 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
706 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
707 dpcd_addr = DP_SINK_COUNT_ESI;
708 }
709
710 mutex_lock(&aconnector->handle_mst_msg_ready);
711
712 while (process_count < max_process_count) {
713 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
714
715 process_count++;
716
717 dret = drm_dp_dpcd_read(
718 &aconnector->dm_dp_aux.aux,
719 dpcd_addr,
720 esi,
721 dpcd_bytes_to_read);
722
723 if (dret != dpcd_bytes_to_read) {
724 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!");
725 break;
726 }
727
728 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
729
730 switch (msg_rdy_type) {
731 case DOWN_REP_MSG_RDY_EVENT:
732 /* Only handle DOWN_REP_MSG_RDY case*/
733 esi[1] &= DP_DOWN_REP_MSG_RDY;
734 break;
735 case UP_REQ_MSG_RDY_EVENT:
736 /* Only handle UP_REQ_MSG_RDY case*/
737 esi[1] &= DP_UP_REQ_MSG_RDY;
738 break;
739 default:
740 /* Handle both cases*/
741 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
742 break;
743 }
744
745 if (!esi[1])
746 break;
747
748 /* handle MST irq */
749 if (aconnector->mst_mgr.mst_state)
750 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
751 esi,
752 ack,
753 &new_irq_handled);
754
755 if (new_irq_handled) {
756 /* ACK at DPCD to notify down stream */
757 for (retry = 0; retry < 3; retry++) {
758 ssize_t wret;
759
760 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
761 dpcd_addr + 1,
762 ack[1]);
763 if (wret == 1)
764 break;
765 }
766
767 if (retry == 3) {
768 DRM_ERROR("Failed to ack MST event.\n");
769 break;
770 }
771
772 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
773
774 new_irq_handled = false;
775 } else {
776 break;
777 }
778 }
779
780 mutex_unlock(&aconnector->handle_mst_msg_ready);
781
782 if (process_count == max_process_count)
783 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
784 }
785
dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr * mgr)786 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
787 {
788 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
789 }
790
791 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
792 .add_connector = dm_dp_add_mst_connector,
793 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
794 };
795
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)796 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
797 struct amdgpu_dm_connector *aconnector,
798 int link_index)
799 {
800 struct dc_link_settings max_link_enc_cap = {0};
801
802 aconnector->dm_dp_aux.aux.name =
803 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
804 link_index);
805 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
806 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
807 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
808
809 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
810 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
811 &aconnector->base);
812
813 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
814 return;
815
816 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
817 aconnector->mst_mgr.cbs = &dm_mst_cbs;
818 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
819 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
820
821 drm_connector_attach_dp_subconnector_property(&aconnector->base);
822 }
823
dm_mst_get_pbn_divider(struct dc_link * link)824 int dm_mst_get_pbn_divider(struct dc_link *link)
825 {
826 if (!link)
827 return 0;
828
829 return dc_link_bandwidth_kbps(link,
830 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
831 }
832
833 struct dsc_mst_fairness_params {
834 struct dc_crtc_timing *timing;
835 struct dc_sink *sink;
836 struct dc_dsc_bw_range bw_range;
837 bool compression_possible;
838 struct drm_dp_mst_port *port;
839 enum dsc_clock_force_state clock_force_enable;
840 uint32_t num_slices_h;
841 uint32_t num_slices_v;
842 uint32_t bpp_overwrite;
843 struct amdgpu_dm_connector *aconnector;
844 };
845
846 #if defined(CONFIG_DRM_AMD_DC_FP)
get_fec_overhead_multiplier(struct dc_link * dc_link)847 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
848 {
849 u8 link_coding_cap;
850 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
851
852 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
853 if (link_coding_cap == DP_128b_132b_ENCODING)
854 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
855
856 return fec_overhead_multiplier_x1000;
857 }
858
kbps_to_peak_pbn(int kbps,uint16_t fec_overhead_multiplier_x1000)859 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
860 {
861 u64 peak_kbps = kbps;
862
863 peak_kbps *= 1006;
864 peak_kbps *= fec_overhead_multiplier_x1000;
865 peak_kbps = div_u64(peak_kbps, 1000 * 1000);
866 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
867 }
868
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)869 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
870 struct dsc_mst_fairness_vars *vars,
871 int count,
872 int k)
873 {
874 struct drm_connector *drm_connector;
875 int i;
876 struct dc_dsc_config_options dsc_options = {0};
877
878 for (i = 0; i < count; i++) {
879 drm_connector = ¶ms[i].aconnector->base;
880
881 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
882 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
883
884 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
885 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
886 params[i].sink->ctx->dc->res_pool->dscs[0],
887 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
888 &dsc_options,
889 0,
890 params[i].timing,
891 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
892 ¶ms[i].timing->dsc_cfg)) {
893 params[i].timing->flags.DSC = 1;
894
895 if (params[i].bpp_overwrite)
896 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
897 else
898 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
899
900 if (params[i].num_slices_h)
901 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
902
903 if (params[i].num_slices_v)
904 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
905 } else {
906 params[i].timing->flags.DSC = 0;
907 }
908 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
909 }
910
911 for (i = 0; i < count; i++) {
912 if (params[i].sink) {
913 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
914 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
915 DRM_DEBUG_DRIVER("MST_DSC %s i=%d dispname=%s\n", __func__, i,
916 params[i].sink->edid_caps.display_name);
917 }
918
919 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n",
920 params[i].timing->flags.DSC,
921 params[i].timing->dsc_cfg.bits_per_pixel,
922 vars[i + k].pbn);
923 }
924 }
925
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)926 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
927 {
928 struct dc_dsc_config dsc_config;
929 u64 kbps;
930
931 struct drm_connector *drm_connector = ¶m.aconnector->base;
932 struct dc_dsc_config_options dsc_options = {0};
933
934 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);
935 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
936
937 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
938 dc_dsc_compute_config(
939 param.sink->ctx->dc->res_pool->dscs[0],
940 ¶m.sink->dsc_caps.dsc_dec_caps,
941 &dsc_options,
942 (int) kbps, param.timing,
943 dc_link_get_highest_encoding_format(param.aconnector->dc_link),
944 &dsc_config);
945
946 return dsc_config.bits_per_pixel;
947 }
948
increase_dsc_bpp(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)949 static int increase_dsc_bpp(struct drm_atomic_state *state,
950 struct drm_dp_mst_topology_state *mst_state,
951 struct dc_link *dc_link,
952 struct dsc_mst_fairness_params *params,
953 struct dsc_mst_fairness_vars *vars,
954 int count,
955 int k)
956 {
957 int i;
958 bool bpp_increased[MAX_PIPES];
959 int initial_slack[MAX_PIPES];
960 int min_initial_slack;
961 int next_index;
962 int remaining_to_increase = 0;
963 int link_timeslots_used;
964 int fair_pbn_alloc;
965 int ret = 0;
966 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
967
968 for (i = 0; i < count; i++) {
969 if (vars[i + k].dsc_enabled) {
970 initial_slack[i] =
971 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
972 bpp_increased[i] = false;
973 remaining_to_increase += 1;
974 } else {
975 initial_slack[i] = 0;
976 bpp_increased[i] = true;
977 }
978 }
979
980 while (remaining_to_increase) {
981 next_index = -1;
982 min_initial_slack = -1;
983 for (i = 0; i < count; i++) {
984 if (!bpp_increased[i]) {
985 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
986 min_initial_slack = initial_slack[i];
987 next_index = i;
988 }
989 }
990 }
991
992 if (next_index == -1)
993 break;
994
995 link_timeslots_used = 0;
996
997 for (i = 0; i < count; i++)
998 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));
999
1000 fair_pbn_alloc =
1001 (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div);
1002
1003 if (initial_slack[next_index] > fair_pbn_alloc) {
1004 vars[next_index].pbn += fair_pbn_alloc;
1005 ret = drm_dp_atomic_find_time_slots(state,
1006 params[next_index].port->mgr,
1007 params[next_index].port,
1008 vars[next_index].pbn);
1009 if (ret < 0)
1010 return ret;
1011
1012 ret = drm_dp_mst_atomic_check(state);
1013 if (ret == 0) {
1014 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
1015 } else {
1016 vars[next_index].pbn -= fair_pbn_alloc;
1017 ret = drm_dp_atomic_find_time_slots(state,
1018 params[next_index].port->mgr,
1019 params[next_index].port,
1020 vars[next_index].pbn);
1021 if (ret < 0)
1022 return ret;
1023 }
1024 } else {
1025 vars[next_index].pbn += initial_slack[next_index];
1026 ret = drm_dp_atomic_find_time_slots(state,
1027 params[next_index].port->mgr,
1028 params[next_index].port,
1029 vars[next_index].pbn);
1030 if (ret < 0)
1031 return ret;
1032
1033 ret = drm_dp_mst_atomic_check(state);
1034 if (ret == 0) {
1035 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
1036 } else {
1037 vars[next_index].pbn -= initial_slack[next_index];
1038 ret = drm_dp_atomic_find_time_slots(state,
1039 params[next_index].port->mgr,
1040 params[next_index].port,
1041 vars[next_index].pbn);
1042 if (ret < 0)
1043 return ret;
1044 }
1045 }
1046
1047 bpp_increased[next_index] = true;
1048 remaining_to_increase--;
1049 }
1050 return 0;
1051 }
1052
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)1053 static int try_disable_dsc(struct drm_atomic_state *state,
1054 struct dc_link *dc_link,
1055 struct dsc_mst_fairness_params *params,
1056 struct dsc_mst_fairness_vars *vars,
1057 int count,
1058 int k)
1059 {
1060 int i;
1061 bool tried[MAX_PIPES];
1062 int kbps_increase[MAX_PIPES];
1063 int max_kbps_increase;
1064 int next_index;
1065 int remaining_to_try = 0;
1066 int ret;
1067 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1068 int var_pbn;
1069
1070 for (i = 0; i < count; i++) {
1071 if (vars[i + k].dsc_enabled
1072 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1073 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1074 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1075 tried[i] = false;
1076 remaining_to_try += 1;
1077 } else {
1078 kbps_increase[i] = 0;
1079 tried[i] = true;
1080 }
1081 }
1082
1083 while (remaining_to_try) {
1084 next_index = -1;
1085 max_kbps_increase = -1;
1086 for (i = 0; i < count; i++) {
1087 if (!tried[i]) {
1088 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1089 max_kbps_increase = kbps_increase[i];
1090 next_index = i;
1091 }
1092 }
1093 }
1094
1095 if (next_index == -1)
1096 break;
1097
1098 DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index);
1099 var_pbn = vars[next_index].pbn;
1100 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1101 ret = drm_dp_atomic_find_time_slots(state,
1102 params[next_index].port->mgr,
1103 params[next_index].port,
1104 vars[next_index].pbn);
1105 if (ret < 0) {
1106 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1107 __func__, __LINE__, next_index, ret);
1108 vars[next_index].pbn = var_pbn;
1109 return ret;
1110 }
1111
1112 ret = drm_dp_mst_atomic_check(state);
1113 if (ret == 0) {
1114 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index);
1115 vars[next_index].dsc_enabled = false;
1116 vars[next_index].bpp_x16 = 0;
1117 } else {
1118 DRM_DEBUG_DRIVER("MST_DSC index #%d, restore optimized pbn value\n", next_index);
1119 vars[next_index].pbn = var_pbn;
1120 ret = drm_dp_atomic_find_time_slots(state,
1121 params[next_index].port->mgr,
1122 params[next_index].port,
1123 vars[next_index].pbn);
1124 if (ret < 0) {
1125 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1126 __func__, __LINE__, next_index, ret);
1127 return ret;
1128 }
1129 }
1130
1131 tried[next_index] = true;
1132 remaining_to_try--;
1133 }
1134 return 0;
1135 }
1136
log_dsc_params(int count,struct dsc_mst_fairness_vars * vars,int k)1137 static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)
1138 {
1139 int i;
1140
1141 for (i = 0; i < count; i++)
1142 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n",
1143 i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);
1144 }
1145
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars,struct drm_dp_mst_topology_mgr * mgr,int * link_vars_start_index)1146 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
1147 struct dc_state *dc_state,
1148 struct dc_link *dc_link,
1149 struct dsc_mst_fairness_vars *vars,
1150 struct drm_dp_mst_topology_mgr *mgr,
1151 int *link_vars_start_index)
1152 {
1153 struct dc_stream_state *stream;
1154 struct dsc_mst_fairness_params params[MAX_PIPES];
1155 struct amdgpu_dm_connector *aconnector;
1156 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1157 int count = 0;
1158 int i, k, ret;
1159 bool debugfs_overwrite = false;
1160 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1161 struct drm_connector_state *new_conn_state;
1162
1163 memset(params, 0, sizeof(params));
1164
1165 if (IS_ERR(mst_state))
1166 return PTR_ERR(mst_state);
1167
1168 /* Set up params */
1169 DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count);
1170 for (i = 0; i < dc_state->stream_count; i++) {
1171 struct dc_dsc_policy dsc_policy = {0};
1172
1173 stream = dc_state->streams[i];
1174
1175 if (stream->link != dc_link)
1176 continue;
1177
1178 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1179 if (!aconnector)
1180 continue;
1181
1182 if (!aconnector->mst_output_port)
1183 continue;
1184
1185 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1186
1187 if (!new_conn_state) {
1188 DRM_DEBUG_DRIVER("%s:%d MST_DSC Skip the stream 0x%p with invalid new_conn_state\n",
1189 __func__, __LINE__, stream);
1190 continue;
1191 }
1192
1193 stream->timing.flags.DSC = 0;
1194
1195 params[count].timing = &stream->timing;
1196 params[count].sink = stream->sink;
1197 params[count].aconnector = aconnector;
1198 params[count].port = aconnector->mst_output_port;
1199 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1200 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1201 debugfs_overwrite = true;
1202 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1203 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1204 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1205 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1206 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1207 if (!dc_dsc_compute_bandwidth_range(
1208 stream->sink->ctx->dc->res_pool->dscs[0],
1209 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1210 dsc_policy.min_target_bpp * 16,
1211 dsc_policy.max_target_bpp * 16,
1212 &stream->sink->dsc_caps.dsc_dec_caps,
1213 &stream->timing,
1214 dc_link_get_highest_encoding_format(dc_link),
1215 ¶ms[count].bw_range))
1216 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
1217 dc_link_get_highest_encoding_format(dc_link));
1218
1219 DRM_DEBUG_DRIVER("MST_DSC #%d stream 0x%p - max_kbps = %u, min_kbps = %u, uncompressed_kbps = %u\n",
1220 count, stream, params[count].bw_range.max_kbps, params[count].bw_range.min_kbps,
1221 params[count].bw_range.stream_kbps);
1222 count++;
1223 }
1224
1225 DRM_DEBUG_DRIVER("%s: MST_DSC Params set up for %d streams\n", __func__, count);
1226
1227 if (count == 0) {
1228 ASSERT(0);
1229 return 0;
1230 }
1231
1232 /* k is start index of vars for current phy link used by mst hub */
1233 k = *link_vars_start_index;
1234 /* set vars start index for next mst hub phy link */
1235 *link_vars_start_index += count;
1236
1237 /* Try no compression */
1238 DRM_DEBUG_DRIVER("MST_DSC Try no compression\n");
1239 for (i = 0; i < count; i++) {
1240 vars[i + k].aconnector = params[i].aconnector;
1241 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1242 vars[i + k].dsc_enabled = false;
1243 vars[i + k].bpp_x16 = 0;
1244 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1245 vars[i + k].pbn);
1246 if (ret < 0)
1247 return ret;
1248 }
1249 ret = drm_dp_mst_atomic_check(state);
1250 if (ret == 0 && !debugfs_overwrite) {
1251 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1252 return 0;
1253 } else if (ret != -ENOSPC) {
1254 return ret;
1255 }
1256
1257 log_dsc_params(count, vars, k);
1258
1259 /* Try max compression */
1260 DRM_DEBUG_DRIVER("MST_DSC Try max compression\n");
1261 for (i = 0; i < count; i++) {
1262 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1263 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1264 vars[i + k].dsc_enabled = true;
1265 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1266 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1267 params[i].port, vars[i + k].pbn);
1268 if (ret < 0)
1269 return ret;
1270 } else {
1271 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1272 vars[i + k].dsc_enabled = false;
1273 vars[i + k].bpp_x16 = 0;
1274 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1275 params[i].port, vars[i + k].pbn);
1276 if (ret < 0)
1277 return ret;
1278 }
1279 }
1280 ret = drm_dp_mst_atomic_check(state);
1281 if (ret != 0)
1282 return ret;
1283
1284 log_dsc_params(count, vars, k);
1285
1286 /* Optimize degree of compression */
1287 DRM_DEBUG_DRIVER("MST_DSC Try optimize compression\n");
1288 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1289 if (ret < 0) {
1290 DRM_DEBUG_DRIVER("MST_DSC Failed to optimize compression\n");
1291 return ret;
1292 }
1293
1294 log_dsc_params(count, vars, k);
1295
1296 DRM_DEBUG_DRIVER("MST_DSC Try disable compression\n");
1297 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1298 if (ret < 0) {
1299 DRM_DEBUG_DRIVER("MST_DSC Failed to disable compression\n");
1300 return ret;
1301 }
1302
1303 log_dsc_params(count, vars, k);
1304
1305 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1306
1307 return 0;
1308 }
1309
is_dsc_need_re_compute(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)1310 static bool is_dsc_need_re_compute(
1311 struct drm_atomic_state *state,
1312 struct dc_state *dc_state,
1313 struct dc_link *dc_link)
1314 {
1315 int i, j;
1316 bool is_dsc_need_re_compute = false;
1317 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1318 int new_stream_on_link_num = 0;
1319 struct amdgpu_dm_connector *aconnector;
1320 struct dc_stream_state *stream;
1321 const struct dc *dc = dc_link->dc;
1322
1323 /* only check phy used by dsc mst branch */
1324 if (dc_link->type != dc_connection_mst_branch)
1325 goto out;
1326
1327 /* add a check for older MST DSC with no virtual DPCDs */
1328 if (needs_dsc_aux_workaround(dc_link) &&
1329 (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1330 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))
1331 goto out;
1332
1333 for (i = 0; i < MAX_PIPES; i++)
1334 stream_on_link[i] = NULL;
1335
1336 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_count);
1337
1338 /* check if there is mode change in new request */
1339 for (i = 0; i < dc_state->stream_count; i++) {
1340 struct drm_crtc_state *new_crtc_state;
1341 struct drm_connector_state *new_conn_state;
1342
1343 stream = dc_state->streams[i];
1344 if (!stream)
1345 continue;
1346
1347 DRM_DEBUG_DRIVER("%s:%d MST_DSC checking #%d stream 0x%p\n", __func__, __LINE__, i, stream);
1348
1349 /* check if stream using the same link for mst */
1350 if (stream->link != dc_link)
1351 continue;
1352
1353 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1354 if (!aconnector)
1355 continue;
1356
1357 stream_on_link[new_stream_on_link_num] = aconnector;
1358 new_stream_on_link_num++;
1359
1360 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1361 if (!new_conn_state) {
1362 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_conn_state for stream 0x%p, aconnector 0x%p\n",
1363 __func__, __LINE__, stream, aconnector);
1364 continue;
1365 }
1366
1367 if (IS_ERR(new_conn_state))
1368 continue;
1369
1370 if (!new_conn_state->crtc)
1371 continue;
1372
1373 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1374 if (!new_crtc_state) {
1375 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_crtc_state for crtc of stream 0x%p, aconnector 0x%p\n",
1376 __func__, __LINE__, stream, aconnector);
1377 continue;
1378 }
1379
1380 if (IS_ERR(new_crtc_state))
1381 continue;
1382
1383 if (new_crtc_state->enable && new_crtc_state->active) {
1384 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1385 new_crtc_state->connectors_changed) {
1386 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1387 "stream 0x%p in new dc_state\n",
1388 __func__, __LINE__, stream);
1389 is_dsc_need_re_compute = true;
1390 goto out;
1391 }
1392 }
1393 }
1394
1395 if (new_stream_on_link_num == 0) {
1396 DRM_DEBUG_DRIVER("%s:%d MST_DSC no mode change request for streams in new dc_state\n",
1397 __func__, __LINE__);
1398 is_dsc_need_re_compute = false;
1399 goto out;
1400 }
1401
1402 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",
1403 __func__, dc->current_state->stream_count);
1404
1405 /* check current_state if there stream on link but it is not in
1406 * new request state
1407 */
1408 for (i = 0; i < dc->current_state->stream_count; i++) {
1409 stream = dc->current_state->streams[i];
1410 /* only check stream on the mst hub */
1411 if (stream->link != dc_link)
1412 continue;
1413
1414 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1415 if (!aconnector)
1416 continue;
1417
1418 for (j = 0; j < new_stream_on_link_num; j++) {
1419 if (stream_on_link[j]) {
1420 if (aconnector == stream_on_link[j])
1421 break;
1422 }
1423 }
1424
1425 if (j == new_stream_on_link_num) {
1426 /* not in new state */
1427 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1428 "stream 0x%p in current dc_state but not in new dc_state\n",
1429 __func__, __LINE__, stream);
1430 is_dsc_need_re_compute = true;
1431 break;
1432 }
1433 }
1434
1435 out:
1436 DRM_DEBUG_DRIVER("%s: MST_DSC dsc recompute %s\n",
1437 __func__, is_dsc_need_re_compute ? "required" : "not required");
1438
1439 return is_dsc_need_re_compute;
1440 }
1441
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1442 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1443 struct dc_state *dc_state,
1444 struct dsc_mst_fairness_vars *vars)
1445 {
1446 int i, j;
1447 struct dc_stream_state *stream;
1448 bool computed_streams[MAX_PIPES];
1449 struct amdgpu_dm_connector *aconnector;
1450 struct drm_dp_mst_topology_mgr *mst_mgr;
1451 struct resource_pool *res_pool;
1452 int link_vars_start_index = 0;
1453 int ret = 0;
1454
1455 for (i = 0; i < dc_state->stream_count; i++)
1456 computed_streams[i] = false;
1457
1458 for (i = 0; i < dc_state->stream_count; i++) {
1459 stream = dc_state->streams[i];
1460 res_pool = stream->ctx->dc->res_pool;
1461
1462 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1463 continue;
1464
1465 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1466
1467 DRM_DEBUG_DRIVER("%s: MST_DSC compute mst dsc configs for stream 0x%p, aconnector 0x%p\n",
1468 __func__, stream, aconnector);
1469
1470 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1471 continue;
1472
1473 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1474 continue;
1475
1476 if (computed_streams[i])
1477 continue;
1478
1479 if (res_pool->funcs->remove_stream_from_ctx &&
1480 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1481 return -EINVAL;
1482
1483 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1484 continue;
1485
1486 mst_mgr = aconnector->mst_output_port->mgr;
1487 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1488 &link_vars_start_index);
1489 if (ret != 0)
1490 return ret;
1491
1492 for (j = 0; j < dc_state->stream_count; j++) {
1493 if (dc_state->streams[j]->link == stream->link)
1494 computed_streams[j] = true;
1495 }
1496 }
1497
1498 for (i = 0; i < dc_state->stream_count; i++) {
1499 stream = dc_state->streams[i];
1500
1501 if (stream->timing.flags.DSC == 1)
1502 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {
1503 DRM_DEBUG_DRIVER("%s:%d MST_DSC Failed to request dsc hw resource for stream 0x%p\n",
1504 __func__, __LINE__, stream);
1505 return -EINVAL;
1506 }
1507 }
1508
1509 return ret;
1510 }
1511
pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1512 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1513 struct dc_state *dc_state,
1514 struct dsc_mst_fairness_vars *vars)
1515 {
1516 int i, j;
1517 struct dc_stream_state *stream;
1518 bool computed_streams[MAX_PIPES];
1519 struct amdgpu_dm_connector *aconnector;
1520 struct drm_dp_mst_topology_mgr *mst_mgr;
1521 int link_vars_start_index = 0;
1522 int ret = 0;
1523
1524 for (i = 0; i < dc_state->stream_count; i++)
1525 computed_streams[i] = false;
1526
1527 for (i = 0; i < dc_state->stream_count; i++) {
1528 stream = dc_state->streams[i];
1529
1530 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1531 continue;
1532
1533 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1534
1535 DRM_DEBUG_DRIVER("MST_DSC pre compute mst dsc configs for #%d stream 0x%p, aconnector 0x%p\n",
1536 i, stream, aconnector);
1537
1538 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1539 continue;
1540
1541 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1542 continue;
1543
1544 if (computed_streams[i])
1545 continue;
1546
1547 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1548 continue;
1549
1550 mst_mgr = aconnector->mst_output_port->mgr;
1551 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1552 &link_vars_start_index);
1553 if (ret != 0)
1554 return ret;
1555
1556 for (j = 0; j < dc_state->stream_count; j++) {
1557 if (dc_state->streams[j]->link == stream->link)
1558 computed_streams[j] = true;
1559 }
1560 }
1561
1562 return ret;
1563 }
1564
find_crtc_index_in_state_by_stream(struct drm_atomic_state * state,struct dc_stream_state * stream)1565 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1566 struct dc_stream_state *stream)
1567 {
1568 int i;
1569 struct drm_crtc *crtc;
1570 struct drm_crtc_state *new_state, *old_state;
1571
1572 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1573 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1574
1575 if (dm_state->stream == stream)
1576 return i;
1577 }
1578 return -1;
1579 }
1580
is_link_to_dschub(struct dc_link * dc_link)1581 static bool is_link_to_dschub(struct dc_link *dc_link)
1582 {
1583 union dpcd_dsc_basic_capabilities *dsc_caps =
1584 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1585
1586 /* only check phy used by dsc mst branch */
1587 if (dc_link->type != dc_connection_mst_branch)
1588 return false;
1589
1590 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1591 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1592 return false;
1593 return true;
1594 }
1595
is_dsc_precompute_needed(struct drm_atomic_state * state)1596 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1597 {
1598 int i;
1599 struct drm_crtc *crtc;
1600 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1601 bool ret = false;
1602
1603 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1604 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1605
1606 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1607 ret = false;
1608 break;
1609 }
1610 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1611 if (is_link_to_dschub(dm_crtc_state->stream->link))
1612 ret = true;
1613 }
1614 return ret;
1615 }
1616
pre_validate_dsc(struct drm_atomic_state * state,struct dm_atomic_state ** dm_state_ptr,struct dsc_mst_fairness_vars * vars)1617 int pre_validate_dsc(struct drm_atomic_state *state,
1618 struct dm_atomic_state **dm_state_ptr,
1619 struct dsc_mst_fairness_vars *vars)
1620 {
1621 int i;
1622 struct dm_atomic_state *dm_state;
1623 struct dc_state *local_dc_state = NULL;
1624 int ret = 0;
1625
1626 if (!is_dsc_precompute_needed(state)) {
1627 DRM_INFO_ONCE("%s:%d MST_DSC dsc precompute is not needed\n", __func__, __LINE__);
1628 return 0;
1629 }
1630 ret = dm_atomic_get_state(state, dm_state_ptr);
1631 if (ret != 0) {
1632 DRM_INFO_ONCE("%s:%d MST_DSC dm_atomic_get_state() failed\n", __func__, __LINE__);
1633 return ret;
1634 }
1635 dm_state = *dm_state_ptr;
1636
1637 /*
1638 * create local vailable for dc_state. copy content of streams of dm_state->context
1639 * to local variable. make sure stream pointer of local variable not the same as stream
1640 * from dm_state->context.
1641 */
1642
1643 local_dc_state = vmalloc(sizeof(struct dc_state));
1644 if (!local_dc_state)
1645 return -ENOMEM;
1646 memcpy(local_dc_state, dm_state->context, sizeof(struct dc_state));
1647
1648 for (i = 0; i < local_dc_state->stream_count; i++) {
1649 struct dc_stream_state *stream = dm_state->context->streams[i];
1650 int ind = find_crtc_index_in_state_by_stream(state, stream);
1651
1652 if (ind >= 0) {
1653 struct drm_connector *connector;
1654 struct drm_connector_state *drm_new_conn_state;
1655 struct dm_connector_state *dm_new_conn_state;
1656 struct dm_crtc_state *dm_old_crtc_state;
1657
1658 connector =
1659 amdgpu_dm_find_first_crtc_matching_connector(state,
1660 state->crtcs[ind].ptr);
1661 if (!connector)
1662 continue;
1663
1664 drm_new_conn_state =
1665 drm_atomic_get_new_connector_state(state,
1666 connector);
1667 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1668 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1669
1670 local_dc_state->streams[i] =
1671 create_validate_stream_for_sink(connector,
1672 &state->crtcs[ind].new_state->mode,
1673 dm_new_conn_state,
1674 dm_old_crtc_state->stream);
1675 if (local_dc_state->streams[i] == NULL) {
1676 ret = -EINVAL;
1677 break;
1678 }
1679 }
1680 }
1681
1682 if (ret != 0)
1683 goto clean_exit;
1684
1685 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1686 if (ret != 0) {
1687 DRM_INFO_ONCE("%s:%d MST_DSC dsc pre_compute_mst_dsc_configs_for_state() failed\n",
1688 __func__, __LINE__);
1689 ret = -EINVAL;
1690 goto clean_exit;
1691 }
1692
1693 /*
1694 * compare local_streams -> timing with dm_state->context,
1695 * if the same set crtc_state->mode-change = 0;
1696 */
1697 for (i = 0; i < local_dc_state->stream_count; i++) {
1698 struct dc_stream_state *stream = dm_state->context->streams[i];
1699
1700 if (local_dc_state->streams[i] &&
1701 dc_is_timing_changed(stream, local_dc_state->streams[i])) {
1702 DRM_INFO_ONCE("%s:%d MST_DSC crtc[%d] needs mode_change\n", __func__, __LINE__, i);
1703 } else {
1704 int ind = find_crtc_index_in_state_by_stream(state, stream);
1705
1706 if (ind >= 0) {
1707 DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n",
1708 __func__, __LINE__, stream);
1709 state->crtcs[ind].new_state->mode_changed = 0;
1710 }
1711 }
1712 }
1713 clean_exit:
1714 for (i = 0; i < local_dc_state->stream_count; i++) {
1715 struct dc_stream_state *stream = dm_state->context->streams[i];
1716
1717 if (local_dc_state->streams[i] != stream)
1718 dc_stream_release(local_dc_state->streams[i]);
1719 }
1720
1721 vfree(local_dc_state);
1722
1723 return ret;
1724 }
1725
kbps_from_pbn(unsigned int pbn)1726 static uint32_t kbps_from_pbn(unsigned int pbn)
1727 {
1728 uint64_t kbps = (uint64_t)pbn;
1729
1730 kbps *= (1000000 / PEAK_FACTOR_X1000);
1731 kbps *= 8;
1732 kbps *= 54;
1733 kbps /= 64;
1734
1735 return (uint32_t)kbps;
1736 }
1737
is_dsc_common_config_possible(struct dc_stream_state * stream,struct dc_dsc_bw_range * bw_range)1738 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1739 struct dc_dsc_bw_range *bw_range)
1740 {
1741 struct dc_dsc_policy dsc_policy = {0};
1742 bool is_dsc_possible;
1743
1744 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1745 is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1746 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1747 dsc_policy.min_target_bpp * 16,
1748 dsc_policy.max_target_bpp * 16,
1749 &stream->sink->dsc_caps.dsc_dec_caps,
1750 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
1751
1752 return is_dsc_possible;
1753 }
1754 #endif
1755
1756 #if defined(CONFIG_DRM_AMD_DC_FP)
dp_get_link_current_set_bw(struct drm_dp_aux * aux,uint32_t * cur_link_bw)1757 static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)
1758 {
1759 uint32_t total_data_bw_efficiency_x10000 = 0;
1760 uint32_t link_rate_per_lane_kbps = 0;
1761 enum dc_link_rate link_rate;
1762 union lane_count_set lane_count;
1763 u8 dp_link_encoding;
1764 u8 link_bw_set = 0;
1765
1766 *cur_link_bw = 0;
1767
1768 if (drm_dp_dpcd_read(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &dp_link_encoding, 1) != 1 ||
1769 drm_dp_dpcd_read(aux, DP_LANE_COUNT_SET, &lane_count.raw, 1) != 1 ||
1770 drm_dp_dpcd_read(aux, DP_LINK_BW_SET, &link_bw_set, 1) != 1)
1771 return false;
1772
1773 switch (dp_link_encoding) {
1774 case DP_8b_10b_ENCODING:
1775 link_rate = link_bw_set;
1776 link_rate_per_lane_kbps = link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
1777 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
1778 total_data_bw_efficiency_x10000 /= 100;
1779 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
1780 break;
1781 case DP_128b_132b_ENCODING:
1782 switch (link_bw_set) {
1783 case DP_LINK_BW_10:
1784 link_rate = LINK_RATE_UHBR10;
1785 break;
1786 case DP_LINK_BW_13_5:
1787 link_rate = LINK_RATE_UHBR13_5;
1788 break;
1789 case DP_LINK_BW_20:
1790 link_rate = LINK_RATE_UHBR20;
1791 break;
1792 default:
1793 return false;
1794 }
1795
1796 link_rate_per_lane_kbps = link_rate * 10000;
1797 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
1798 break;
1799 default:
1800 return false;
1801 }
1802
1803 *cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;
1804 return true;
1805 }
1806 #endif
1807
dm_dp_mst_is_port_support_mode(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream)1808 enum dc_status dm_dp_mst_is_port_support_mode(
1809 struct amdgpu_dm_connector *aconnector,
1810 struct dc_stream_state *stream)
1811 {
1812 #if defined(CONFIG_DRM_AMD_DC_FP)
1813 int branch_max_throughput_mps = 0;
1814 struct dc_link_settings cur_link_settings;
1815 uint32_t end_to_end_bw_in_kbps = 0;
1816 uint32_t root_link_bw_in_kbps = 0;
1817 uint32_t virtual_channel_bw_in_kbps = 0;
1818 struct dc_dsc_bw_range bw_range = {0};
1819 struct dc_dsc_config_options dsc_options = {0};
1820 uint32_t stream_kbps;
1821
1822 /* DSC unnecessary case
1823 * Check if timing could be supported within end-to-end BW
1824 */
1825 stream_kbps =
1826 dc_bandwidth_in_kbps_from_timing(&stream->timing,
1827 dc_link_get_highest_encoding_format(stream->link));
1828 cur_link_settings = stream->link->verified_link_cap;
1829 root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings);
1830 virtual_channel_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
1831
1832 /* pick the end to end bw bottleneck */
1833 end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1834
1835 if (stream_kbps <= end_to_end_bw_in_kbps) {
1836 DRM_DEBUG_DRIVER("MST_DSC no dsc required. End-to-end bw sufficient\n");
1837 return DC_OK;
1838 }
1839
1840 /*DSC necessary case*/
1841 if (!aconnector->dsc_aux)
1842 return DC_FAIL_BANDWIDTH_VALIDATE;
1843
1844 if (is_dsc_common_config_possible(stream, &bw_range)) {
1845
1846 /*capable of dsc passthough. dsc bitstream along the entire path*/
1847 if (aconnector->mst_output_port->passthrough_aux) {
1848 if (bw_range.min_kbps > end_to_end_bw_in_kbps) {
1849 DRM_DEBUG_DRIVER("MST_DSC dsc passthrough and decode at endpoint"
1850 "Max dsc compression bw can't fit into end-to-end bw\n");
1851 return DC_FAIL_BANDWIDTH_VALIDATE;
1852 }
1853 } else {
1854 /*dsc bitstream decoded at the dp last link*/
1855 struct drm_dp_mst_port *immediate_upstream_port = NULL;
1856 uint32_t end_link_bw = 0;
1857
1858 /*Get last DP link BW capability. Mode shall be supported by Legacy peer*/
1859 if (aconnector->mst_output_port->pdt != DP_PEER_DEVICE_DP_LEGACY_CONV &&
1860 aconnector->mst_output_port->pdt != DP_PEER_DEVICE_NONE) {
1861 if (aconnector->vc_full_pbn != aconnector->mst_output_port->full_pbn) {
1862 dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw);
1863 aconnector->vc_full_pbn = aconnector->mst_output_port->full_pbn;
1864 aconnector->mst_local_bw = end_link_bw;
1865 } else {
1866 end_link_bw = aconnector->mst_local_bw;
1867 }
1868
1869 if (end_link_bw > 0 && stream_kbps > end_link_bw) {
1870 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1871 "Mode required bw can't fit into last link\n");
1872 return DC_FAIL_BANDWIDTH_VALIDATE;
1873 }
1874 }
1875
1876 /*Get virtual channel bandwidth between source and the link before the last link*/
1877 if (aconnector->mst_output_port->parent->port_parent)
1878 immediate_upstream_port = aconnector->mst_output_port->parent->port_parent;
1879
1880 if (immediate_upstream_port) {
1881 virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn);
1882 virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1883 } else {
1884 /* For topology LCT 1 case - only one mstb*/
1885 virtual_channel_bw_in_kbps = root_link_bw_in_kbps;
1886 }
1887
1888 if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
1889 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1890 "Max dsc compression can't fit into MST available bw\n");
1891 return DC_FAIL_BANDWIDTH_VALIDATE;
1892 }
1893 }
1894
1895 /*Confirm if we can obtain dsc config*/
1896 dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
1897 dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
1898 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
1899 &stream->sink->dsc_caps.dsc_dec_caps,
1900 &dsc_options,
1901 end_to_end_bw_in_kbps,
1902 &stream->timing,
1903 dc_link_get_highest_encoding_format(stream->link),
1904 &stream->timing.dsc_cfg)) {
1905 stream->timing.flags.DSC = 1;
1906 DRM_DEBUG_DRIVER("MST_DSC require dsc and dsc config found\n");
1907 } else {
1908 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find appropriate dsc config\n");
1909 return DC_FAIL_BANDWIDTH_VALIDATE;
1910 }
1911
1912 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1913 switch (stream->timing.pixel_encoding) {
1914 case PIXEL_ENCODING_RGB:
1915 case PIXEL_ENCODING_YCBCR444:
1916 branch_max_throughput_mps =
1917 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1918 break;
1919 case PIXEL_ENCODING_YCBCR422:
1920 case PIXEL_ENCODING_YCBCR420:
1921 branch_max_throughput_mps =
1922 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1923 break;
1924 default:
1925 break;
1926 }
1927
1928 if (branch_max_throughput_mps != 0 &&
1929 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) {
1930 DRM_DEBUG_DRIVER("MST_DSC require dsc but max throughput mps fails\n");
1931 return DC_FAIL_BANDWIDTH_VALIDATE;
1932 }
1933 } else {
1934 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n");
1935 return DC_FAIL_BANDWIDTH_VALIDATE;
1936 }
1937 #endif
1938 return DC_OK;
1939 }
1940