1 // SPDX-License-Identifier: GPL-2.0 2 3 /*************************************************************************** 4 * copyright : (C) 2001, 2002 by Frank Mori Hess 5 ***************************************************************************/ 6 7 #include "board.h" 8 #include <linux/ioport.h> 9 #include <linux/sched.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <asm/dma.h> 13 #include <linux/bitops.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/spinlock.h> 19 #include <linux/delay.h> 20 21 MODULE_LICENSE("GPL"); 22 MODULE_DESCRIPTION("GPIB library code for NEC uPD7210"); 23 nec7210_enable_eos(gpib_board_t * board,struct nec7210_priv * priv,uint8_t eos_byte,int compare_8_bits)24 int nec7210_enable_eos(gpib_board_t *board, struct nec7210_priv *priv, uint8_t eos_byte, 25 int compare_8_bits) 26 { 27 write_byte(priv, eos_byte, EOSR); 28 priv->auxa_bits |= HR_REOS; 29 if (compare_8_bits) 30 priv->auxa_bits |= HR_BIN; 31 else 32 priv->auxa_bits &= ~HR_BIN; 33 write_byte(priv, priv->auxa_bits, AUXMR); 34 return 0; 35 } 36 EXPORT_SYMBOL(nec7210_enable_eos); 37 nec7210_disable_eos(gpib_board_t * board,struct nec7210_priv * priv)38 void nec7210_disable_eos(gpib_board_t *board, struct nec7210_priv *priv) 39 { 40 priv->auxa_bits &= ~HR_REOS; 41 write_byte(priv, priv->auxa_bits, AUXMR); 42 } 43 EXPORT_SYMBOL(nec7210_disable_eos); 44 nec7210_parallel_poll(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * result)45 int nec7210_parallel_poll(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *result) 46 { 47 int ret; 48 49 clear_bit(COMMAND_READY_BN, &priv->state); 50 51 // execute parallel poll 52 write_byte(priv, AUX_EPP, AUXMR); 53 // wait for result FIXME: support timeouts 54 ret = wait_event_interruptible(board->wait, test_bit(COMMAND_READY_BN, &priv->state)); 55 if (ret) { 56 dev_dbg(board->gpib_dev, "gpib: parallel poll interrupted\n"); 57 return -ERESTARTSYS; 58 } 59 *result = read_byte(priv, CPTR); 60 61 return 0; 62 } 63 EXPORT_SYMBOL(nec7210_parallel_poll); 64 nec7210_parallel_poll_configure(gpib_board_t * board,struct nec7210_priv * priv,unsigned int configuration)65 void nec7210_parallel_poll_configure(gpib_board_t *board, 66 struct nec7210_priv *priv, unsigned int configuration) 67 { 68 write_byte(priv, PPR | configuration, AUXMR); 69 } 70 EXPORT_SYMBOL(nec7210_parallel_poll_configure); 71 nec7210_parallel_poll_response(gpib_board_t * board,struct nec7210_priv * priv,int ist)72 void nec7210_parallel_poll_response(gpib_board_t *board, struct nec7210_priv *priv, int ist) 73 { 74 if (ist) 75 write_byte(priv, AUX_SPPF, AUXMR); 76 else 77 write_byte(priv, AUX_CPPF, AUXMR); 78 } 79 EXPORT_SYMBOL(nec7210_parallel_poll_response); 80 /* This is really only adequate for chips that do a 488.2 style reqt/reqf 81 * based on bit 6 of the SPMR (see chapter 11.3.3 of 488.2). For simpler chips that simply 82 * set rsv directly based on bit 6, we either need to do more hardware setup to expose 83 * the 488.2 capability (for example with NI chips), or we need to implement the 84 * 488.2 set srv state machine in the driver (if that is even viable). 85 */ nec7210_serial_poll_response(gpib_board_t * board,struct nec7210_priv * priv,uint8_t status)86 void nec7210_serial_poll_response(gpib_board_t *board, struct nec7210_priv *priv, uint8_t status) 87 { 88 unsigned long flags; 89 90 spin_lock_irqsave(&board->spinlock, flags); 91 if (status & request_service_bit) { 92 priv->srq_pending = 1; 93 clear_bit(SPOLL_NUM, &board->status); 94 95 } else { 96 priv->srq_pending = 0; 97 } 98 write_byte(priv, status, SPMR); 99 spin_unlock_irqrestore(&board->spinlock, flags); 100 } 101 EXPORT_SYMBOL(nec7210_serial_poll_response); 102 nec7210_serial_poll_status(gpib_board_t * board,struct nec7210_priv * priv)103 uint8_t nec7210_serial_poll_status(gpib_board_t *board, struct nec7210_priv *priv) 104 { 105 return read_byte(priv, SPSR); 106 } 107 EXPORT_SYMBOL(nec7210_serial_poll_status); 108 nec7210_primary_address(const gpib_board_t * board,struct nec7210_priv * priv,unsigned int address)109 int nec7210_primary_address(const gpib_board_t *board, struct nec7210_priv *priv, 110 unsigned int address) 111 { 112 // put primary address in address0 113 write_byte(priv, address & ADDRESS_MASK, ADR); 114 return 0; 115 } 116 EXPORT_SYMBOL(nec7210_primary_address); 117 nec7210_secondary_address(const gpib_board_t * board,struct nec7210_priv * priv,unsigned int address,int enable)118 int nec7210_secondary_address(const gpib_board_t *board, struct nec7210_priv *priv, 119 unsigned int address, int enable) 120 { 121 if (enable) { 122 // put secondary address in address1 123 write_byte(priv, HR_ARS | (address & ADDRESS_MASK), ADR); 124 // go to address mode 2 125 priv->reg_bits[ADMR] &= ~HR_ADM0; 126 priv->reg_bits[ADMR] |= HR_ADM1; 127 } else { 128 // disable address1 register 129 write_byte(priv, HR_ARS | HR_DT | HR_DL, ADR); 130 // go to address mode 1 131 priv->reg_bits[ADMR] |= HR_ADM0; 132 priv->reg_bits[ADMR] &= ~HR_ADM1; 133 } 134 write_byte(priv, priv->reg_bits[ADMR], ADMR); 135 return 0; 136 } 137 EXPORT_SYMBOL(nec7210_secondary_address); 138 update_talker_state(struct nec7210_priv * priv,unsigned int address_status_bits)139 static void update_talker_state(struct nec7210_priv *priv, unsigned int address_status_bits) 140 { 141 if ((address_status_bits & HR_TA)) { 142 if ((address_status_bits & HR_NATN)) { 143 if (address_status_bits & HR_SPMS) 144 priv->talker_state = serial_poll_active; 145 else 146 priv->talker_state = talker_active; 147 } else { 148 priv->talker_state = talker_addressed; 149 } 150 } else { 151 priv->talker_state = talker_idle; 152 } 153 } 154 update_listener_state(struct nec7210_priv * priv,unsigned int address_status_bits)155 static void update_listener_state(struct nec7210_priv *priv, unsigned int address_status_bits) 156 { 157 if (address_status_bits & HR_LA) { 158 if ((address_status_bits & HR_NATN)) 159 priv->listener_state = listener_active; 160 else 161 priv->listener_state = listener_addressed; 162 } else { 163 priv->listener_state = listener_idle; 164 } 165 } 166 nec7210_update_status_nolock(gpib_board_t * board,struct nec7210_priv * priv)167 unsigned int nec7210_update_status_nolock(gpib_board_t *board, struct nec7210_priv *priv) 168 { 169 int address_status_bits; 170 u8 spoll_status; 171 172 if (!priv) 173 return 0; 174 175 address_status_bits = read_byte(priv, ADSR); 176 if (address_status_bits & HR_CIC) 177 set_bit(CIC_NUM, &board->status); 178 else 179 clear_bit(CIC_NUM, &board->status); 180 // check for talker/listener addressed 181 update_talker_state(priv, address_status_bits); 182 if (priv->talker_state == talker_active || priv->talker_state == talker_addressed) 183 set_bit(TACS_NUM, &board->status); 184 else 185 clear_bit(TACS_NUM, &board->status); 186 update_listener_state(priv, address_status_bits); 187 if (priv->listener_state == listener_active || 188 priv->listener_state == listener_addressed) 189 set_bit(LACS_NUM, &board->status); 190 else 191 clear_bit(LACS_NUM, &board->status); 192 if (address_status_bits & HR_NATN) 193 clear_bit(ATN_NUM, &board->status); 194 else 195 set_bit(ATN_NUM, &board->status); 196 spoll_status = nec7210_serial_poll_status(board, priv); 197 if (priv->srq_pending && (spoll_status & request_service_bit) == 0) { 198 priv->srq_pending = 0; 199 set_bit(SPOLL_NUM, &board->status); 200 } 201 // dev_dbg(board->gpib_dev, "status 0x%x, state 0x%x\n", board->status, priv->state); 202 203 /* we rely on the interrupt handler to set the 204 * rest of the status bits 205 */ 206 207 return board->status; 208 } 209 EXPORT_SYMBOL(nec7210_update_status_nolock); 210 nec7210_update_status(gpib_board_t * board,struct nec7210_priv * priv,unsigned int clear_mask)211 unsigned int nec7210_update_status(gpib_board_t *board, struct nec7210_priv *priv, 212 unsigned int clear_mask) 213 { 214 unsigned long flags; 215 unsigned int retval; 216 217 spin_lock_irqsave(&board->spinlock, flags); 218 board->status &= ~clear_mask; 219 retval = nec7210_update_status_nolock(board, priv); 220 spin_unlock_irqrestore(&board->spinlock, flags); 221 222 return retval; 223 } 224 EXPORT_SYMBOL(nec7210_update_status); 225 nec7210_set_reg_bits(struct nec7210_priv * priv,unsigned int reg,unsigned int mask,unsigned int bits)226 unsigned int nec7210_set_reg_bits(struct nec7210_priv *priv, unsigned int reg, 227 unsigned int mask, unsigned int bits) 228 { 229 priv->reg_bits[reg] &= ~mask; 230 priv->reg_bits[reg] |= mask & bits; 231 write_byte(priv, priv->reg_bits[reg], reg); 232 return priv->reg_bits[reg]; 233 } 234 EXPORT_SYMBOL(nec7210_set_reg_bits); 235 nec7210_set_handshake_mode(gpib_board_t * board,struct nec7210_priv * priv,int mode)236 void nec7210_set_handshake_mode(gpib_board_t *board, struct nec7210_priv *priv, int mode) 237 { 238 unsigned long flags; 239 240 mode &= HR_HANDSHAKE_MASK; 241 242 spin_lock_irqsave(&board->spinlock, flags); 243 if ((priv->auxa_bits & HR_HANDSHAKE_MASK) != mode) { 244 priv->auxa_bits &= ~HR_HANDSHAKE_MASK; 245 priv->auxa_bits |= mode; 246 write_byte(priv, priv->auxa_bits, AUXMR); 247 } 248 spin_unlock_irqrestore(&board->spinlock, flags); 249 } 250 EXPORT_SYMBOL(nec7210_set_handshake_mode); 251 nec7210_read_data_in(gpib_board_t * board,struct nec7210_priv * priv,int * end)252 uint8_t nec7210_read_data_in(gpib_board_t *board, struct nec7210_priv *priv, int *end) 253 { 254 unsigned long flags; 255 u8 data; 256 257 spin_lock_irqsave(&board->spinlock, flags); 258 data = read_byte(priv, DIR); 259 clear_bit(READ_READY_BN, &priv->state); 260 if (test_and_clear_bit(RECEIVED_END_BN, &priv->state)) 261 *end = 1; 262 else 263 *end = 0; 264 spin_unlock_irqrestore(&board->spinlock, flags); 265 266 return data; 267 } 268 EXPORT_SYMBOL(nec7210_read_data_in); 269 nec7210_take_control(gpib_board_t * board,struct nec7210_priv * priv,int syncronous)270 int nec7210_take_control(gpib_board_t *board, struct nec7210_priv *priv, int syncronous) 271 { 272 int i; 273 const int timeout = 100; 274 int retval = 0; 275 unsigned int adsr_bits = 0; 276 277 if (syncronous) 278 write_byte(priv, AUX_TCS, AUXMR); 279 else 280 write_byte(priv, AUX_TCA, AUXMR); 281 // busy wait until ATN is asserted 282 for (i = 0; i < timeout; i++) { 283 adsr_bits = read_byte(priv, ADSR); 284 if ((adsr_bits & HR_NATN) == 0) 285 break; 286 udelay(1); 287 } 288 if (i == timeout) 289 return -ETIMEDOUT; 290 291 clear_bit(WRITE_READY_BN, &priv->state); 292 293 return retval; 294 } 295 EXPORT_SYMBOL(nec7210_take_control); 296 nec7210_go_to_standby(gpib_board_t * board,struct nec7210_priv * priv)297 int nec7210_go_to_standby(gpib_board_t *board, struct nec7210_priv *priv) 298 { 299 int i; 300 const int timeout = 1000; 301 unsigned int adsr_bits = 0; 302 int retval = 0; 303 304 write_byte(priv, AUX_GTS, AUXMR); 305 // busy wait until ATN is released 306 for (i = 0; i < timeout; i++) { 307 adsr_bits = read_byte(priv, ADSR); 308 if (adsr_bits & HR_NATN) 309 break; 310 udelay(1); 311 } 312 // if busy wait has failed, try sleeping 313 if (i == timeout) { 314 for (i = 0; i < HZ; i++) { 315 set_current_state(TASK_INTERRUPTIBLE); 316 if (schedule_timeout(1)) 317 return -ERESTARTSYS; 318 adsr_bits = read_byte(priv, ADSR); 319 if (adsr_bits & HR_NATN) 320 break; 321 } 322 if (i == HZ) { 323 pr_err("nec7210: error waiting for NATN\n"); 324 return -ETIMEDOUT; 325 } 326 } 327 328 clear_bit(COMMAND_READY_BN, &priv->state); 329 return retval; 330 } 331 EXPORT_SYMBOL(nec7210_go_to_standby); 332 nec7210_request_system_control(gpib_board_t * board,struct nec7210_priv * priv,int request_control)333 void nec7210_request_system_control(gpib_board_t *board, struct nec7210_priv *priv, 334 int request_control) 335 { 336 if (request_control == 0) { 337 write_byte(priv, AUX_CREN, AUXMR); 338 write_byte(priv, AUX_CIFC, AUXMR); 339 write_byte(priv, AUX_DSC, AUXMR); 340 } 341 } 342 EXPORT_SYMBOL(nec7210_request_system_control); 343 nec7210_interface_clear(gpib_board_t * board,struct nec7210_priv * priv,int assert)344 void nec7210_interface_clear(gpib_board_t *board, struct nec7210_priv *priv, int assert) 345 { 346 if (assert) 347 write_byte(priv, AUX_SIFC, AUXMR); 348 else 349 write_byte(priv, AUX_CIFC, AUXMR); 350 } 351 EXPORT_SYMBOL(nec7210_interface_clear); 352 nec7210_remote_enable(gpib_board_t * board,struct nec7210_priv * priv,int enable)353 void nec7210_remote_enable(gpib_board_t *board, struct nec7210_priv *priv, int enable) 354 { 355 if (enable) 356 write_byte(priv, AUX_SREN, AUXMR); 357 else 358 write_byte(priv, AUX_CREN, AUXMR); 359 } 360 EXPORT_SYMBOL(nec7210_remote_enable); 361 nec7210_release_rfd_holdoff(gpib_board_t * board,struct nec7210_priv * priv)362 void nec7210_release_rfd_holdoff(gpib_board_t *board, struct nec7210_priv *priv) 363 { 364 unsigned long flags; 365 366 spin_lock_irqsave(&board->spinlock, flags); 367 if (test_bit(RFD_HOLDOFF_BN, &priv->state) && 368 test_bit(READ_READY_BN, &priv->state) == 0) { 369 write_byte(priv, AUX_FH, AUXMR); 370 clear_bit(RFD_HOLDOFF_BN, &priv->state); 371 } 372 spin_unlock_irqrestore(&board->spinlock, flags); 373 } 374 EXPORT_SYMBOL(nec7210_release_rfd_holdoff); 375 nec7210_t1_delay(gpib_board_t * board,struct nec7210_priv * priv,unsigned int nano_sec)376 unsigned int nec7210_t1_delay(gpib_board_t *board, struct nec7210_priv *priv, 377 unsigned int nano_sec) 378 { 379 unsigned int retval; 380 381 if (nano_sec <= 500) { 382 priv->auxb_bits |= HR_TRI; 383 retval = 500; 384 } else { 385 priv->auxb_bits &= ~HR_TRI; 386 retval = 2000; 387 } 388 write_byte(priv, priv->auxb_bits, AUXMR); 389 390 return retval; 391 } 392 EXPORT_SYMBOL(nec7210_t1_delay); 393 nec7210_return_to_local(const gpib_board_t * board,struct nec7210_priv * priv)394 void nec7210_return_to_local(const gpib_board_t *board, struct nec7210_priv *priv) 395 { 396 write_byte(priv, AUX_RTL, AUXMR); 397 } 398 EXPORT_SYMBOL(nec7210_return_to_local); 399 nec7210_atn_has_changed(gpib_board_t * board,struct nec7210_priv * priv)400 static inline short nec7210_atn_has_changed(gpib_board_t *board, struct nec7210_priv *priv) 401 { 402 short address_status_bits = read_byte(priv, ADSR); 403 404 if (address_status_bits & HR_NATN) { 405 if (test_bit(ATN_NUM, &board->status)) 406 return 1; 407 else 408 return 0; 409 } else { 410 if (test_bit(ATN_NUM, &board->status)) 411 return 0; 412 else 413 return 1; 414 } 415 return -1; 416 } 417 nec7210_command(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,size_t * bytes_written)418 int nec7210_command(gpib_board_t *board, struct nec7210_priv *priv, uint8_t 419 *buffer, size_t length, size_t *bytes_written) 420 { 421 int retval = 0; 422 unsigned long flags; 423 424 *bytes_written = 0; 425 426 clear_bit(BUS_ERROR_BN, &priv->state); 427 428 while (*bytes_written < length) { 429 if (wait_event_interruptible(board->wait, 430 test_bit(COMMAND_READY_BN, &priv->state) || 431 test_bit(BUS_ERROR_BN, &priv->state) || 432 test_bit(TIMO_NUM, &board->status))) { 433 dev_dbg(board->gpib_dev, "gpib command wait interrupted\n"); 434 retval = -ERESTARTSYS; 435 break; 436 } 437 if (test_bit(TIMO_NUM, &board->status)) 438 break; 439 if (test_and_clear_bit(BUS_ERROR_BN, &priv->state)) { 440 pr_err("nec7210: bus error on command byte\n"); 441 break; 442 } 443 444 spin_lock_irqsave(&board->spinlock, flags); 445 clear_bit(COMMAND_READY_BN, &priv->state); 446 write_byte(priv, buffer[*bytes_written], CDOR); 447 spin_unlock_irqrestore(&board->spinlock, flags); 448 449 ++(*bytes_written); 450 451 if (need_resched()) 452 schedule(); 453 } 454 // wait for last byte to get sent 455 if (wait_event_interruptible(board->wait, test_bit(COMMAND_READY_BN, &priv->state) || 456 test_bit(BUS_ERROR_BN, &priv->state) || 457 test_bit(TIMO_NUM, &board->status))) { 458 dev_dbg(board->gpib_dev, "gpib command wait interrupted\n"); 459 retval = -ERESTARTSYS; 460 } 461 if (test_bit(TIMO_NUM, &board->status)) { 462 dev_dbg(board->gpib_dev, "gpib command timed out\n"); 463 retval = -ETIMEDOUT; 464 } 465 if (test_and_clear_bit(BUS_ERROR_BN, &priv->state)) { 466 pr_err("nec7210: bus error on command byte\n"); 467 retval = -EIO; 468 } 469 470 return retval; 471 } 472 EXPORT_SYMBOL(nec7210_command); 473 pio_read(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,int * end,size_t * bytes_read)474 static int pio_read(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *buffer, 475 size_t length, int *end, size_t *bytes_read) 476 { 477 ssize_t retval = 0; 478 479 *bytes_read = 0; 480 *end = 0; 481 482 while (*bytes_read < length) { 483 if (wait_event_interruptible(board->wait, 484 test_bit(READ_READY_BN, &priv->state) || 485 test_bit(DEV_CLEAR_BN, &priv->state) || 486 test_bit(TIMO_NUM, &board->status))) { 487 dev_dbg(board->gpib_dev, "nec7210: pio read wait interrupted\n"); 488 retval = -ERESTARTSYS; 489 break; 490 } 491 if (test_bit(READ_READY_BN, &priv->state)) { 492 if (*bytes_read == 0) { 493 /* We set the handshake mode here because we know 494 * no new bytes will arrive (it has already arrived 495 * and is awaiting being read out of the chip) while we are changing 496 * modes. This ensures we can reliably keep track 497 * of the holdoff state. 498 */ 499 nec7210_set_handshake_mode(board, priv, HR_HLDA); 500 } 501 buffer[(*bytes_read)++] = nec7210_read_data_in(board, priv, end); 502 if (*end) 503 break; 504 } 505 if (test_bit(TIMO_NUM, &board->status)) { 506 dev_dbg(board->gpib_dev, "interrupted by timeout\n"); 507 retval = -ETIMEDOUT; 508 break; 509 } 510 if (test_bit(DEV_CLEAR_BN, &priv->state)) { 511 dev_dbg(board->gpib_dev, "interrupted by device clear\n"); 512 retval = -EINTR; 513 break; 514 } 515 516 if (*bytes_read < length) 517 nec7210_release_rfd_holdoff(board, priv); 518 519 if (need_resched()) 520 schedule(); 521 } 522 return retval; 523 } 524 525 #ifdef NEC_DMA __dma_read(gpib_board_t * board,struct nec7210_priv * priv,size_t length)526 static ssize_t __dma_read(gpib_board_t *board, struct nec7210_priv *priv, size_t length) 527 { 528 ssize_t retval = 0; 529 size_t count = 0; 530 unsigned long flags, dma_irq_flags; 531 532 if (length == 0) 533 return 0; 534 535 spin_lock_irqsave(&board->spinlock, flags); 536 537 dma_irq_flags = claim_dma_lock(); 538 disable_dma(priv->dma_channel); 539 /* program dma controller */ 540 clear_dma_ff(priv->dma_channel); 541 set_dma_count(priv->dma_channel, length); 542 set_dma_addr(priv->dma_channel, priv->dma_buffer_addr); 543 set_dma_mode(priv->dma_channel, DMA_MODE_READ); 544 release_dma_lock(dma_irq_flags); 545 546 enable_dma(priv->dma_channel); 547 548 set_bit(DMA_READ_IN_PROGRESS_BN, &priv->state); 549 clear_bit(READ_READY_BN, &priv->state); 550 551 // enable nec7210 dma 552 nec7210_set_reg_bits(priv, IMR2, HR_DMAI, HR_DMAI); 553 554 spin_unlock_irqrestore(&board->spinlock, flags); 555 556 // wait for data to transfer 557 if (wait_event_interruptible(board->wait, 558 test_bit(DMA_READ_IN_PROGRESS_BN, &priv->state) == 0 || 559 test_bit(DEV_CLEAR_BN, &priv->state) || 560 test_bit(TIMO_NUM, &board->status))) { 561 dev_dbg(board->gpib_dev, "nec7210: dma read wait interrupted\n"); 562 retval = -ERESTARTSYS; 563 } 564 if (test_bit(TIMO_NUM, &board->status)) 565 retval = -ETIMEDOUT; 566 if (test_bit(DEV_CLEAR_BN, &priv->state)) 567 retval = -EINTR; 568 569 // disable nec7210 dma 570 nec7210_set_reg_bits(priv, IMR2, HR_DMAI, 0); 571 572 // record how many bytes we transferred 573 flags = claim_dma_lock(); 574 clear_dma_ff(priv->dma_channel); 575 disable_dma(priv->dma_channel); 576 count += length - get_dma_residue(priv->dma_channel); 577 release_dma_lock(flags); 578 579 return retval ? retval : count; 580 } 581 dma_read(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length)582 static ssize_t dma_read(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *buffer, 583 size_t length) 584 { 585 size_t remain = length; 586 size_t transfer_size; 587 ssize_t retval = 0; 588 589 while (remain > 0) { 590 transfer_size = (priv->dma_buffer_length < remain) ? 591 priv->dma_buffer_length : remain; 592 retval = __dma_read(board, priv, transfer_size); 593 if (retval < 0) 594 break; 595 memcpy(buffer, priv->dma_buffer, transfer_size); 596 remain -= retval; 597 buffer += retval; 598 if (test_bit(RECEIVED_END_BN, &priv->state)) 599 break; 600 } 601 602 if (retval < 0) 603 return retval; 604 605 return length - remain; 606 } 607 #endif 608 nec7210_read(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,int * end,size_t * bytes_read)609 int nec7210_read(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *buffer, 610 size_t length, int *end, size_t *bytes_read) 611 { 612 ssize_t retval = 0; 613 614 *end = 0; 615 *bytes_read = 0; 616 617 if (length == 0) 618 return 0; 619 620 clear_bit(DEV_CLEAR_BN, &priv->state); // XXX wrong 621 622 nec7210_release_rfd_holdoff(board, priv); 623 624 retval = pio_read(board, priv, buffer, length, end, bytes_read); 625 626 return retval; 627 } 628 EXPORT_SYMBOL(nec7210_read); 629 pio_write_wait(gpib_board_t * board,struct nec7210_priv * priv,short wake_on_lacs,short wake_on_atn,short wake_on_bus_error)630 static int pio_write_wait(gpib_board_t *board, struct nec7210_priv *priv, 631 short wake_on_lacs, short wake_on_atn, short wake_on_bus_error) 632 { 633 // wait until byte is ready to be sent 634 if (wait_event_interruptible(board->wait, 635 (test_bit(TACS_NUM, &board->status) && 636 test_bit(WRITE_READY_BN, &priv->state)) || 637 test_bit(DEV_CLEAR_BN, &priv->state) || 638 (wake_on_bus_error && test_bit(BUS_ERROR_BN, &priv->state)) || 639 (wake_on_lacs && test_bit(LACS_NUM, &board->status)) || 640 (wake_on_atn && test_bit(ATN_NUM, &board->status)) || 641 test_bit(TIMO_NUM, &board->status))) { 642 dev_dbg(board->gpib_dev, "gpib write interrupted\n"); 643 return -ERESTARTSYS; 644 } 645 if (test_bit(TIMO_NUM, &board->status)) { 646 dev_dbg(board->gpib_dev, "nec7210: write timed out\n"); 647 return -ETIMEDOUT; 648 } 649 if (test_bit(DEV_CLEAR_BN, &priv->state)) { 650 dev_dbg(board->gpib_dev, "nec7210: write interrupted by clear\n"); 651 return -EINTR; 652 } 653 if (wake_on_bus_error && test_and_clear_bit(BUS_ERROR_BN, &priv->state)) { 654 dev_dbg(board->gpib_dev, "nec7210: bus error on write\n"); 655 return -EIO; 656 } 657 return 0; 658 } 659 pio_write(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,size_t * bytes_written)660 static int pio_write(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *buffer, 661 size_t length, size_t *bytes_written) 662 { 663 size_t last_count = 0; 664 ssize_t retval = 0; 665 unsigned long flags; 666 const int max_bus_errors = (length > 1000) ? length : 1000; 667 int bus_error_count = 0; 668 *bytes_written = 0; 669 670 clear_bit(BUS_ERROR_BN, &priv->state); 671 672 while (*bytes_written < length) { 673 if (need_resched()) 674 schedule(); 675 676 retval = pio_write_wait(board, priv, 0, 0, priv->type == NEC7210); 677 if (retval == -EIO) { 678 /* resend last byte on bus error */ 679 *bytes_written = last_count; 680 dev_dbg(board->gpib_dev, "resending %c\n", buffer[*bytes_written]); 681 /* we can get unrecoverable bus errors, 682 * so give up after a while 683 */ 684 bus_error_count++; 685 if (bus_error_count > max_bus_errors) 686 return retval; 687 continue; 688 } else { 689 if (retval < 0) 690 return retval; 691 } 692 spin_lock_irqsave(&board->spinlock, flags); 693 clear_bit(BUS_ERROR_BN, &priv->state); 694 clear_bit(WRITE_READY_BN, &priv->state); 695 last_count = *bytes_written; 696 write_byte(priv, buffer[(*bytes_written)++], CDOR); 697 spin_unlock_irqrestore(&board->spinlock, flags); 698 } 699 retval = pio_write_wait(board, priv, 1, 1, priv->type == NEC7210); 700 return retval; 701 } 702 703 #ifdef NEC_DMA __dma_write(gpib_board_t * board,struct nec7210_priv * priv,dma_addr_t address,size_t length)704 static ssize_t __dma_write(gpib_board_t *board, struct nec7210_priv *priv, dma_addr_t address, 705 size_t length) 706 { 707 unsigned long flags, dma_irq_flags; 708 int residue = 0; 709 int retval = 0; 710 711 spin_lock_irqsave(&board->spinlock, flags); 712 713 /* program dma controller */ 714 dma_irq_flags = claim_dma_lock(); 715 disable_dma(priv->dma_channel); 716 clear_dma_ff(priv->dma_channel); 717 set_dma_count(priv->dma_channel, length); 718 set_dma_addr(priv->dma_channel, address); 719 set_dma_mode(priv->dma_channel, DMA_MODE_WRITE); 720 enable_dma(priv->dma_channel); 721 release_dma_lock(dma_irq_flags); 722 723 // enable board's dma for output 724 nec7210_set_reg_bits(priv, IMR2, HR_DMAO, HR_DMAO); 725 726 clear_bit(WRITE_READY_BN, &priv->state); 727 set_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state); 728 729 spin_unlock_irqrestore(&board->spinlock, flags); 730 731 // suspend until message is sent 732 if (wait_event_interruptible(board->wait, 733 test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state) == 0 || 734 test_bit(BUS_ERROR_BN, &priv->state) || 735 test_bit(DEV_CLEAR_BN, &priv->state) || 736 test_bit(TIMO_NUM, &board->status))) { 737 dev_dbg(board->gpib_dev, "gpib write interrupted!\n"); 738 retval = -ERESTARTSYS; 739 } 740 if (test_bit(TIMO_NUM, &board->status)) 741 retval = -ETIMEDOUT; 742 if (test_and_clear_bit(DEV_CLEAR_BN, &priv->state)) 743 retval = -EINTR; 744 if (test_and_clear_bit(BUS_ERROR_BN, &priv->state)) 745 retval = -EIO; 746 747 // disable board's dma 748 nec7210_set_reg_bits(priv, IMR2, HR_DMAO, 0); 749 750 dma_irq_flags = claim_dma_lock(); 751 clear_dma_ff(priv->dma_channel); 752 disable_dma(priv->dma_channel); 753 residue = get_dma_residue(priv->dma_channel); 754 release_dma_lock(dma_irq_flags); 755 756 if (residue) 757 retval = -EPIPE; 758 759 return retval ? retval : length; 760 } 761 dma_write(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length)762 static ssize_t dma_write(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *buffer, 763 size_t length) 764 { 765 size_t remain = length; 766 size_t transfer_size; 767 ssize_t retval = 0; 768 769 while (remain > 0) { 770 transfer_size = (priv->dma_buffer_length < remain) ? 771 priv->dma_buffer_length : remain; 772 memcpy(priv->dma_buffer, buffer, transfer_size); 773 retval = __dma_write(board, priv, priv->dma_buffer_addr, transfer_size); 774 if (retval < 0) 775 break; 776 remain -= retval; 777 buffer += retval; 778 } 779 780 if (retval < 0) 781 return retval; 782 783 return length - remain; 784 } 785 #endif nec7210_write(gpib_board_t * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,int send_eoi,size_t * bytes_written)786 int nec7210_write(gpib_board_t *board, struct nec7210_priv *priv, uint8_t *buffer, size_t length, 787 int send_eoi, size_t *bytes_written) 788 { 789 int retval = 0; 790 791 *bytes_written = 0; 792 793 clear_bit(DEV_CLEAR_BN, &priv->state); //XXX 794 795 if (send_eoi) 796 length-- ; /* save the last byte for sending EOI */ 797 798 if (length > 0) { 799 // isa dma transfer 800 if (0 /*priv->dma_channel*/) { 801 /* 802 * dma writes are unreliable since they can't recover from bus errors 803 * (which happen when ATN is asserted in the middle of a write) 804 */ 805 #ifdef NEC_DMA 806 retval = dma_write(board, priv, buffer, length); 807 if (retval < 0) 808 return retval; 809 count += retval; 810 #endif 811 } else { // PIO transfer 812 size_t num_bytes; 813 814 retval = pio_write(board, priv, buffer, length, &num_bytes); 815 816 *bytes_written += num_bytes; 817 if (retval < 0) 818 return retval; 819 } 820 } 821 if (send_eoi) { 822 size_t num_bytes; 823 824 /* We need to wait to make sure we will immediately be able to write the data byte 825 * into the chip before sending the associated AUX_SEOI command. This is really 826 * only needed for length==1 since otherwise the earlier calls to pio_write 827 * will have dont the wait already. 828 */ 829 retval = pio_write_wait(board, priv, 0, 0, priv->type == NEC7210); 830 if (retval < 0) 831 return retval; 832 /*send EOI */ 833 write_byte(priv, AUX_SEOI, AUXMR); 834 835 retval = pio_write(board, priv, &buffer[*bytes_written], 1, &num_bytes); 836 *bytes_written += num_bytes; 837 if (retval < 0) 838 return retval; 839 } 840 841 return retval; 842 } 843 EXPORT_SYMBOL(nec7210_write); 844 845 /* 846 * interrupt service routine 847 */ nec7210_interrupt(gpib_board_t * board,struct nec7210_priv * priv)848 irqreturn_t nec7210_interrupt(gpib_board_t *board, struct nec7210_priv *priv) 849 { 850 int status1, status2; 851 852 // read interrupt status (also clears status) 853 status1 = read_byte(priv, ISR1); 854 status2 = read_byte(priv, ISR2); 855 856 return nec7210_interrupt_have_status(board, priv, status1, status2); 857 } 858 EXPORT_SYMBOL(nec7210_interrupt); 859 nec7210_interrupt_have_status(gpib_board_t * board,struct nec7210_priv * priv,int status1,int status2)860 irqreturn_t nec7210_interrupt_have_status(gpib_board_t *board, 861 struct nec7210_priv *priv, int status1, int status2) 862 { 863 #ifdef NEC_DMA 864 unsigned long dma_flags; 865 #endif 866 int retval = IRQ_NONE; 867 868 // record service request in status 869 if (status2 & HR_SRQI) 870 set_bit(SRQI_NUM, &board->status); 871 872 // change in lockout status 873 if (status2 & HR_LOKC) { 874 if (status2 & HR_LOK) 875 set_bit(LOK_NUM, &board->status); 876 else 877 clear_bit(LOK_NUM, &board->status); 878 } 879 880 // change in remote status 881 if (status2 & HR_REMC) { 882 if (status2 & HR_REM) 883 set_bit(REM_NUM, &board->status); 884 else 885 clear_bit(REM_NUM, &board->status); 886 } 887 888 // record reception of END 889 if (status1 & HR_END) { 890 set_bit(RECEIVED_END_BN, &priv->state); 891 if ((priv->auxa_bits & HR_HANDSHAKE_MASK) == HR_HLDE) 892 set_bit(RFD_HOLDOFF_BN, &priv->state); 893 } 894 895 // get incoming data in PIO mode 896 if ((status1 & HR_DI)) { 897 set_bit(READ_READY_BN, &priv->state); 898 if ((priv->auxa_bits & HR_HANDSHAKE_MASK) == HR_HLDA) 899 set_bit(RFD_HOLDOFF_BN, &priv->state); 900 } 901 #ifdef NEC_DMA 902 // check for dma read transfer complete 903 if (test_bit(DMA_READ_IN_PROGRESS_BN, &priv->state)) { 904 dma_flags = claim_dma_lock(); 905 disable_dma(priv->dma_channel); 906 clear_dma_ff(priv->dma_channel); 907 if ((status1 & HR_END) || get_dma_residue(priv->dma_channel) == 0) 908 clear_bit(DMA_READ_IN_PROGRESS_BN, &priv->state); 909 else 910 enable_dma(priv->dma_channel); 911 release_dma_lock(dma_flags); 912 } 913 #endif 914 if ((status1 & HR_DO)) { 915 if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state) == 0) 916 set_bit(WRITE_READY_BN, &priv->state); 917 #ifdef NEC_DMA 918 if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state)) { // write data, isa dma mode 919 // check if dma transfer is complete 920 dma_flags = claim_dma_lock(); 921 disable_dma(priv->dma_channel); 922 clear_dma_ff(priv->dma_channel); 923 if (get_dma_residue(priv->dma_channel) == 0) { 924 clear_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state); 925 // XXX race? byte may still be in CDOR reg 926 } else { 927 clear_bit(WRITE_READY_BN, &priv->state); 928 enable_dma(priv->dma_channel); 929 } 930 release_dma_lock(dma_flags); 931 } 932 #endif 933 } 934 935 // outgoing command can be sent 936 if (status2 & HR_CO) 937 set_bit(COMMAND_READY_BN, &priv->state); 938 939 // command pass through received 940 if (status1 & HR_CPT) { 941 unsigned int command; 942 943 command = read_byte(priv, CPTR) & gpib_command_mask; 944 write_byte(priv, AUX_NVAL, AUXMR); 945 // printk("gpib: command pass through 0x%x\n", command); 946 } 947 948 if (status1 & HR_ERR) 949 set_bit(BUS_ERROR_BN, &priv->state); 950 951 if (status1 & HR_DEC) { 952 unsigned short address_status_bits = read_byte(priv, ADSR); 953 954 // ignore device clear events if we are controller in charge 955 if ((address_status_bits & HR_CIC) == 0) { 956 push_gpib_event(board, EventDevClr); 957 set_bit(DEV_CLEAR_BN, &priv->state); 958 } 959 } 960 961 if (status1 & HR_DET) 962 push_gpib_event(board, EventDevTrg); 963 964 // Addressing status has changed 965 if (status2 & HR_ADSC) 966 set_bit(ADR_CHANGE_BN, &priv->state); 967 968 if ((status1 & priv->reg_bits[IMR1]) || 969 (status2 & (priv->reg_bits[IMR2] & IMR2_ENABLE_INTR_MASK)) || 970 nec7210_atn_has_changed(board, priv)) { 971 nec7210_update_status_nolock(board, priv); 972 dev_dbg(board->gpib_dev, "minor %i, stat %lx, isr1 0x%x, imr1 0x%x, isr2 0x%x, imr2 0x%x\n", 973 board->minor, board->status, status1, priv->reg_bits[IMR1], status2, 974 priv->reg_bits[IMR2]); 975 wake_up_interruptible(&board->wait); /* wake up sleeping process */ 976 retval = IRQ_HANDLED; 977 } 978 979 return retval; 980 } 981 EXPORT_SYMBOL(nec7210_interrupt_have_status); 982 nec7210_board_reset(struct nec7210_priv * priv,const gpib_board_t * board)983 void nec7210_board_reset(struct nec7210_priv *priv, const gpib_board_t *board) 984 { 985 /* 7210 chip reset */ 986 write_byte(priv, AUX_CR, AUXMR); 987 988 /* disable all interrupts */ 989 priv->reg_bits[IMR1] = 0; 990 write_byte(priv, priv->reg_bits[IMR1], IMR1); 991 priv->reg_bits[IMR2] = 0; 992 write_byte(priv, priv->reg_bits[IMR2], IMR2); 993 write_byte(priv, 0, SPMR); 994 995 /* clear registers by reading */ 996 read_byte(priv, CPTR); 997 read_byte(priv, ISR1); 998 read_byte(priv, ISR2); 999 1000 /* parallel poll unconfigure */ 1001 write_byte(priv, PPR | HR_PPU, AUXMR); 1002 1003 priv->reg_bits[ADMR] = HR_TRM0 | HR_TRM1; 1004 1005 priv->auxa_bits = AUXRA | HR_HLDA; 1006 write_byte(priv, priv->auxa_bits, AUXMR); 1007 1008 write_byte(priv, AUXRE | 0, AUXMR); 1009 1010 /* set INT pin to active high, enable command pass through of unknown commands */ 1011 priv->auxb_bits = AUXRB | HR_CPTE; 1012 write_byte(priv, priv->auxb_bits, AUXMR); 1013 write_byte(priv, AUXRE, AUXMR); 1014 } 1015 EXPORT_SYMBOL(nec7210_board_reset); 1016 nec7210_board_online(struct nec7210_priv * priv,const gpib_board_t * board)1017 void nec7210_board_online(struct nec7210_priv *priv, const gpib_board_t *board) 1018 { 1019 /* set GPIB address */ 1020 nec7210_primary_address(board, priv, board->pad); 1021 nec7210_secondary_address(board, priv, board->sad, board->sad >= 0); 1022 1023 // enable interrupts 1024 priv->reg_bits[IMR1] = HR_ERRIE | HR_DECIE | HR_ENDIE | 1025 HR_DETIE | HR_CPTIE | HR_DOIE | HR_DIIE; 1026 priv->reg_bits[IMR2] = IMR2_ENABLE_INTR_MASK; 1027 write_byte(priv, priv->reg_bits[IMR1], IMR1); 1028 write_byte(priv, priv->reg_bits[IMR2], IMR2); 1029 1030 write_byte(priv, AUX_PON, AUXMR); 1031 } 1032 EXPORT_SYMBOL(nec7210_board_online); 1033 1034 #ifdef CONFIG_HAS_IOPORT 1035 /* wrappers for io */ nec7210_ioport_read_byte(struct nec7210_priv * priv,unsigned int register_num)1036 uint8_t nec7210_ioport_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1037 { 1038 return inb(priv->iobase + register_num * priv->offset); 1039 } 1040 EXPORT_SYMBOL(nec7210_ioport_read_byte); 1041 nec7210_ioport_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1042 void nec7210_ioport_write_byte(struct nec7210_priv *priv, uint8_t data, unsigned int register_num) 1043 { 1044 if (register_num == AUXMR) 1045 /* locking makes absolutely sure noone accesses the 1046 * AUXMR register faster than once per microsecond 1047 */ 1048 nec7210_locking_ioport_write_byte(priv, data, register_num); 1049 else 1050 outb(data, priv->iobase + register_num * priv->offset); 1051 } 1052 EXPORT_SYMBOL(nec7210_ioport_write_byte); 1053 1054 /* locking variants of io wrappers, for chips that page-in registers */ nec7210_locking_ioport_read_byte(struct nec7210_priv * priv,unsigned int register_num)1055 uint8_t nec7210_locking_ioport_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1056 { 1057 u8 retval; 1058 unsigned long flags; 1059 1060 spin_lock_irqsave(&priv->register_page_lock, flags); 1061 retval = inb(priv->iobase + register_num * priv->offset); 1062 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1063 return retval; 1064 } 1065 EXPORT_SYMBOL(nec7210_locking_ioport_read_byte); 1066 nec7210_locking_ioport_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1067 void nec7210_locking_ioport_write_byte(struct nec7210_priv *priv, uint8_t data, 1068 unsigned int register_num) 1069 { 1070 unsigned long flags; 1071 1072 spin_lock_irqsave(&priv->register_page_lock, flags); 1073 if (register_num == AUXMR) 1074 udelay(1); 1075 outb(data, priv->iobase + register_num * priv->offset); 1076 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1077 } 1078 EXPORT_SYMBOL(nec7210_locking_ioport_write_byte); 1079 #endif 1080 nec7210_iomem_read_byte(struct nec7210_priv * priv,unsigned int register_num)1081 uint8_t nec7210_iomem_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1082 { 1083 return readb(priv->mmiobase + register_num * priv->offset); 1084 } 1085 EXPORT_SYMBOL(nec7210_iomem_read_byte); 1086 nec7210_iomem_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1087 void nec7210_iomem_write_byte(struct nec7210_priv *priv, uint8_t data, unsigned int register_num) 1088 { 1089 if (register_num == AUXMR) 1090 /* locking makes absolutely sure noone accesses the 1091 * AUXMR register faster than once per microsecond 1092 */ 1093 nec7210_locking_iomem_write_byte(priv, data, register_num); 1094 else 1095 writeb(data, priv->mmiobase + register_num * priv->offset); 1096 } 1097 EXPORT_SYMBOL(nec7210_iomem_write_byte); 1098 nec7210_locking_iomem_read_byte(struct nec7210_priv * priv,unsigned int register_num)1099 uint8_t nec7210_locking_iomem_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1100 { 1101 u8 retval; 1102 unsigned long flags; 1103 1104 spin_lock_irqsave(&priv->register_page_lock, flags); 1105 retval = readb(priv->mmiobase + register_num * priv->offset); 1106 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1107 return retval; 1108 } 1109 EXPORT_SYMBOL(nec7210_locking_iomem_read_byte); 1110 nec7210_locking_iomem_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1111 void nec7210_locking_iomem_write_byte(struct nec7210_priv *priv, uint8_t data, 1112 unsigned int register_num) 1113 { 1114 unsigned long flags; 1115 1116 spin_lock_irqsave(&priv->register_page_lock, flags); 1117 if (register_num == AUXMR) 1118 udelay(1); 1119 writeb(data, priv->mmiobase + register_num * priv->offset); 1120 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1121 } 1122 EXPORT_SYMBOL(nec7210_locking_iomem_write_byte); 1123 nec7210_init_module(void)1124 static int __init nec7210_init_module(void) 1125 { 1126 return 0; 1127 } 1128 nec7210_exit_module(void)1129 static void __exit nec7210_exit_module(void) 1130 { 1131 } 1132 1133 module_init(nec7210_init_module); 1134 module_exit(nec7210_exit_module); 1135