1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * drivers/clk/at91/pmc.h 4 * 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 */ 7 8 #ifndef __PMC_H_ 9 #define __PMC_H_ 10 11 #include <linux/io.h> 12 #include <linux/irqdomain.h> 13 #include <linux/regmap.h> 14 #include <linux/spinlock.h> 15 16 #include <dt-bindings/clock/at91.h> 17 18 extern spinlock_t pmc_pcr_lock; 19 20 struct pmc_data { 21 unsigned int ncore; 22 struct clk_hw **chws; 23 unsigned int nsystem; 24 struct clk_hw **shws; 25 unsigned int nperiph; 26 struct clk_hw **phws; 27 unsigned int ngck; 28 struct clk_hw **ghws; 29 unsigned int npck; 30 struct clk_hw **pchws; 31 32 struct clk_hw *hwtable[]; 33 }; 34 35 struct clk_range { 36 unsigned long min; 37 unsigned long max; 38 }; 39 40 #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} 41 42 struct clk_master_layout { 43 u32 offset; 44 u32 mask; 45 u8 pres_shift; 46 }; 47 48 extern const struct clk_master_layout at91rm9200_master_layout; 49 extern const struct clk_master_layout at91sam9x5_master_layout; 50 51 struct clk_master_characteristics { 52 struct clk_range output; 53 u32 divisors[5]; 54 u8 have_div3_pres; 55 }; 56 57 struct clk_pll_layout { 58 u32 pllr_mask; 59 u32 mul_mask; 60 u32 frac_mask; 61 u32 div_mask; 62 u32 endiv_mask; 63 u8 mul_shift; 64 u8 frac_shift; 65 u8 div_shift; 66 u8 endiv_shift; 67 u8 div2; 68 }; 69 70 extern const struct clk_pll_layout at91rm9200_pll_layout; 71 extern const struct clk_pll_layout at91sam9g45_pll_layout; 72 extern const struct clk_pll_layout at91sam9g20_pllb_layout; 73 extern const struct clk_pll_layout sama5d3_pll_layout; 74 75 struct clk_pll_characteristics { 76 struct clk_range input; 77 int num_output; 78 const struct clk_range *output; 79 const struct clk_range *core_output; 80 u16 *icpll; 81 u8 *out; 82 u8 upll : 1; 83 u32 acr; 84 }; 85 86 struct clk_programmable_layout { 87 u8 pres_mask; 88 u8 pres_shift; 89 u8 css_mask; 90 u8 have_slck_mck; 91 u8 is_pres_direct; 92 }; 93 94 extern const struct clk_programmable_layout at91rm9200_programmable_layout; 95 extern const struct clk_programmable_layout at91sam9g45_programmable_layout; 96 extern const struct clk_programmable_layout at91sam9x5_programmable_layout; 97 98 struct clk_pcr_layout { 99 u32 offset; 100 u32 cmd; 101 u32 div_mask; 102 u32 gckcss_mask; 103 u32 pid_mask; 104 }; 105 106 /** 107 * struct at91_clk_pms - Power management state for AT91 clock 108 * @rate: clock rate 109 * @parent_rate: clock parent rate 110 * @status: clock status (enabled or disabled) 111 * @parent: clock parent index 112 */ 113 struct at91_clk_pms { 114 unsigned long rate; 115 unsigned long parent_rate; 116 unsigned int status; 117 unsigned int parent; 118 }; 119 120 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 121 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 122 123 #define ndck(a, s) (a[s - 1].id + 1) 124 #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) 125 126 #define PMC_INIT_TABLE(_table, _count) \ 127 do { \ 128 u8 _i; \ 129 for (_i = 0; _i < (_count); _i++) \ 130 (_table)[_i] = _i; \ 131 } while (0) 132 133 #define PMC_FILL_TABLE(_to, _from, _count) \ 134 do { \ 135 u8 _i; \ 136 for (_i = 0; _i < (_count); _i++) { \ 137 (_to)[_i] = (_from)[_i]; \ 138 } \ 139 } while (0) 140 141 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, 142 unsigned int nperiph, unsigned int ngck, 143 unsigned int npck); 144 145 int of_at91_get_clk_range(struct device_node *np, const char *propname, 146 struct clk_range *range); 147 148 struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data); 149 150 struct clk_hw * __init 151 at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, 152 const char *parent_name); 153 154 struct clk_hw * __init 155 at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, 156 const char *parent_name); 157 158 struct clk_hw * __init 159 at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, 160 const char *parent_name); 161 162 struct clk_hw * __init 163 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 164 const struct clk_pcr_layout *layout, 165 const char *name, const char **parent_names, 166 struct clk_hw **parent_hws, u32 *mux_table, 167 u8 num_parents, u8 id, 168 const struct clk_range *range, int chg_pid); 169 170 struct clk_hw * __init 171 at91_clk_register_h32mx(struct regmap *regmap, const char *name, 172 const char *parent_name); 173 174 struct clk_hw * __init 175 at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, 176 const char * const *parent_names, 177 unsigned int num_parents, u8 bus_id); 178 179 struct clk_hw * __init 180 at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, 181 u32 frequency, u32 accuracy); 182 struct clk_hw * __init 183 at91_clk_register_main_osc(struct regmap *regmap, const char *name, 184 const char *parent_name, 185 struct clk_parent_data *parent_data, bool bypass); 186 struct clk_hw * __init 187 at91_clk_register_rm9200_main(struct regmap *regmap, 188 const char *name, 189 const char *parent_name, 190 struct clk_hw *parent_hw); 191 struct clk_hw * __init 192 at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, 193 const char **parent_names, 194 struct clk_hw **parent_hws, int num_parents); 195 196 struct clk_hw * __init 197 at91_clk_register_master_pres(struct regmap *regmap, const char *name, 198 int num_parents, const char **parent_names, 199 struct clk_hw **parent_hws, 200 const struct clk_master_layout *layout, 201 const struct clk_master_characteristics *characteristics, 202 spinlock_t *lock); 203 204 struct clk_hw * __init 205 at91_clk_register_master_div(struct regmap *regmap, const char *name, 206 const char *parent_names, struct clk_hw *parent_hw, 207 const struct clk_master_layout *layout, 208 const struct clk_master_characteristics *characteristics, 209 spinlock_t *lock, u32 flags, u32 safe_div); 210 211 struct clk_hw * __init 212 at91_clk_sama7g5_register_master(struct regmap *regmap, 213 const char *name, int num_parents, 214 const char **parent_names, 215 struct clk_hw **parent_hws, u32 *mux_table, 216 spinlock_t *lock, u8 id, bool critical, 217 int chg_pid); 218 219 struct clk_hw * __init 220 at91_clk_register_peripheral(struct regmap *regmap, const char *name, 221 const char *parent_name, struct clk_hw *parent_hw, 222 u32 id); 223 struct clk_hw * __init 224 at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, 225 const struct clk_pcr_layout *layout, 226 const char *name, const char *parent_name, 227 struct clk_hw *parent_hw, 228 u32 id, const struct clk_range *range, 229 int chg_pid, unsigned long flags); 230 231 struct clk_hw * __init 232 at91_clk_register_pll(struct regmap *regmap, const char *name, 233 const char *parent_name, u8 id, 234 const struct clk_pll_layout *layout, 235 const struct clk_pll_characteristics *characteristics); 236 struct clk_hw * __init 237 at91_clk_register_plldiv(struct regmap *regmap, const char *name, 238 const char *parent_name); 239 240 struct clk_hw * __init 241 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, 242 const char *name, const char *parent_name, 243 struct clk_hw *parent_hw, u8 id, 244 const struct clk_pll_characteristics *characteristics, 245 const struct clk_pll_layout *layout, u32 flags, 246 u32 safe_div); 247 248 struct clk_hw * __init 249 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 250 const char *name, const char *parent_name, 251 struct clk_hw *parent_hw, u8 id, 252 const struct clk_pll_characteristics *characteristics, 253 const struct clk_pll_layout *layout, u32 flags); 254 255 struct clk_hw * __init 256 at91_clk_register_programmable(struct regmap *regmap, const char *name, 257 const char **parent_names, struct clk_hw **parent_hws, 258 u8 num_parents, u8 id, 259 const struct clk_programmable_layout *layout, 260 u32 *mux_table); 261 262 struct clk_hw * __init 263 at91_clk_register_sam9260_slow(struct regmap *regmap, 264 const char *name, 265 const char **parent_names, 266 int num_parents); 267 268 struct clk_hw * __init 269 at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, 270 const char **parent_names, u8 num_parents); 271 272 struct clk_hw * __init 273 at91_clk_register_system(struct regmap *regmap, const char *name, 274 const char *parent_name, struct clk_hw *parent_hw, 275 u8 id, unsigned long flags); 276 277 struct clk_hw * __init 278 at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, 279 const char **parent_names, u8 num_parents); 280 struct clk_hw * __init 281 at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, 282 const char *parent_name); 283 struct clk_hw * __init 284 sam9x60_clk_register_usb(struct regmap *regmap, const char *name, 285 const char **parent_names, u8 num_parents); 286 struct clk_hw * __init 287 at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, 288 const char *parent_name, const u32 *divisors); 289 290 struct clk_hw * __init 291 at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, 292 const char *name, const char *parent_name, 293 struct clk_hw *parent_hw); 294 295 struct clk_hw * __init 296 at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, 297 const char *parent_name, struct clk_hw *parent_hw); 298 299 #endif /* __PMC_H_ */ 300