1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the Nuvoton NAU7802 ADC
4 *
5 * Copyright 2013 Free Electrons
6 */
7
8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/property.h>
13 #include <linux/wait.h>
14 #include <linux/log2.h>
15
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18
19 #define NAU7802_REG_PUCTRL 0x00
20 #define NAU7802_PUCTRL_RR(x) (x << 0)
21 #define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1)
22 #define NAU7802_PUCTRL_PUD(x) (x << 1)
23 #define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1)
24 #define NAU7802_PUCTRL_PUA(x) (x << 2)
25 #define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1)
26 #define NAU7802_PUCTRL_PUR(x) (x << 3)
27 #define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1)
28 #define NAU7802_PUCTRL_CS(x) (x << 4)
29 #define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1)
30 #define NAU7802_PUCTRL_CR(x) (x << 5)
31 #define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1)
32 #define NAU7802_PUCTRL_AVDDS(x) (x << 7)
33 #define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1)
34 #define NAU7802_REG_CTRL1 0x01
35 #define NAU7802_CTRL1_VLDO(x) (x << 3)
36 #define NAU7802_CTRL1_GAINS(x) (x)
37 #define NAU7802_CTRL1_GAINS_BITS 0x07
38 #define NAU7802_REG_CTRL2 0x02
39 #define NAU7802_CTRL2_CHS(x) (x << 7)
40 #define NAU7802_CTRL2_CRS(x) (x << 4)
41 #define NAU7802_SAMP_FREQ_320 0x07
42 #define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1)
43 #define NAU7802_REG_ADC_B2 0x12
44 #define NAU7802_REG_ADC_B1 0x13
45 #define NAU7802_REG_ADC_B0 0x14
46 #define NAU7802_REG_ADC_CTRL 0x15
47
48 #define NAU7802_MIN_CONVERSIONS 6
49
50 struct nau7802_state {
51 struct i2c_client *client;
52 s32 last_value;
53 struct mutex lock;
54 struct mutex data_lock;
55 u32 vref_mv;
56 u32 conversion_count;
57 u8 sample_rate;
58 u32 scale_avail[8];
59 struct completion value_ok;
60 };
61
62 #define NAU7802_CHANNEL(chan) { \
63 .type = IIO_VOLTAGE, \
64 .indexed = 1, \
65 .channel = (chan), \
66 .scan_index = (chan), \
67 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
68 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
69 BIT(IIO_CHAN_INFO_SAMP_FREQ) \
70 }
71
72 static const struct iio_chan_spec nau7802_chan_array[] = {
73 NAU7802_CHANNEL(0),
74 NAU7802_CHANNEL(1),
75 };
76
77 static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
78 10, 10, 10, 320};
79
nau7802_show_scales(struct device * dev,struct device_attribute * attr,char * buf)80 static ssize_t nau7802_show_scales(struct device *dev,
81 struct device_attribute *attr, char *buf)
82 {
83 struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
84 int i, len = 0;
85
86 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
87 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
88 st->scale_avail[i]);
89
90 buf[len-1] = '\n';
91
92 return len;
93 }
94
95 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
96
97 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
98 NULL, 0);
99
100 static struct attribute *nau7802_attributes[] = {
101 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
102 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
103 NULL
104 };
105
106 static const struct attribute_group nau7802_attribute_group = {
107 .attrs = nau7802_attributes,
108 };
109
nau7802_set_gain(struct nau7802_state * st,int gain)110 static int nau7802_set_gain(struct nau7802_state *st, int gain)
111 {
112 int ret;
113
114 mutex_lock(&st->lock);
115 st->conversion_count = 0;
116
117 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
118 if (ret < 0)
119 goto nau7802_sysfs_set_gain_out;
120 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
121 (ret & (~NAU7802_CTRL1_GAINS_BITS)) |
122 gain);
123
124 nau7802_sysfs_set_gain_out:
125 mutex_unlock(&st->lock);
126
127 return ret;
128 }
129
nau7802_read_conversion(struct nau7802_state * st)130 static int nau7802_read_conversion(struct nau7802_state *st)
131 {
132 int data;
133
134 mutex_lock(&st->data_lock);
135 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
136 if (data < 0)
137 goto nau7802_read_conversion_out;
138 st->last_value = data << 16;
139
140 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
141 if (data < 0)
142 goto nau7802_read_conversion_out;
143 st->last_value |= data << 8;
144
145 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
146 if (data < 0)
147 goto nau7802_read_conversion_out;
148 st->last_value |= data;
149
150 st->last_value = sign_extend32(st->last_value, 23);
151
152 nau7802_read_conversion_out:
153 mutex_unlock(&st->data_lock);
154
155 return data;
156 }
157
158 /*
159 * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
160 */
nau7802_sync(struct nau7802_state * st)161 static int nau7802_sync(struct nau7802_state *st)
162 {
163 int ret;
164
165 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
166 if (ret < 0)
167 return ret;
168 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
169 ret | NAU7802_PUCTRL_CS_BIT);
170
171 return ret;
172 }
173
nau7802_eoc_trigger(int irq,void * private)174 static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
175 {
176 struct iio_dev *indio_dev = private;
177 struct nau7802_state *st = iio_priv(indio_dev);
178 int status;
179
180 status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
181 if (status < 0)
182 return IRQ_HANDLED;
183
184 if (!(status & NAU7802_PUCTRL_CR_BIT))
185 return IRQ_NONE;
186
187 if (nau7802_read_conversion(st) < 0)
188 return IRQ_HANDLED;
189
190 /*
191 * Because there is actually only one ADC for both channels, we have to
192 * wait for enough conversions to happen before getting a significant
193 * value when changing channels and the values are far apart.
194 */
195 if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
196 st->conversion_count++;
197 if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
198 complete(&st->value_ok);
199
200 return IRQ_HANDLED;
201 }
202
nau7802_read_irq(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)203 static int nau7802_read_irq(struct iio_dev *indio_dev,
204 struct iio_chan_spec const *chan,
205 int *val)
206 {
207 struct nau7802_state *st = iio_priv(indio_dev);
208 int ret;
209
210 reinit_completion(&st->value_ok);
211 enable_irq(st->client->irq);
212
213 nau7802_sync(st);
214
215 /* read registers to ensure we flush everything */
216 ret = nau7802_read_conversion(st);
217 if (ret < 0)
218 goto read_chan_info_failure;
219
220 /* Wait for a conversion to finish */
221 ret = wait_for_completion_interruptible_timeout(&st->value_ok,
222 msecs_to_jiffies(1000));
223 if (ret == 0)
224 ret = -ETIMEDOUT;
225
226 if (ret < 0)
227 goto read_chan_info_failure;
228
229 disable_irq(st->client->irq);
230
231 *val = st->last_value;
232
233 return IIO_VAL_INT;
234
235 read_chan_info_failure:
236 disable_irq(st->client->irq);
237
238 return ret;
239 }
240
nau7802_read_poll(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)241 static int nau7802_read_poll(struct iio_dev *indio_dev,
242 struct iio_chan_spec const *chan,
243 int *val)
244 {
245 struct nau7802_state *st = iio_priv(indio_dev);
246 int ret;
247
248 nau7802_sync(st);
249
250 /* read registers to ensure we flush everything */
251 ret = nau7802_read_conversion(st);
252 if (ret < 0)
253 return ret;
254
255 /*
256 * Because there is actually only one ADC for both channels, we have to
257 * wait for enough conversions to happen before getting a significant
258 * value when changing channels and the values are far apart.
259 */
260 do {
261 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
262 if (ret < 0)
263 return ret;
264
265 while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
266 if (st->sample_rate != NAU7802_SAMP_FREQ_320)
267 msleep(20);
268 else
269 mdelay(4);
270 ret = i2c_smbus_read_byte_data(st->client,
271 NAU7802_REG_PUCTRL);
272 if (ret < 0)
273 return ret;
274 }
275
276 ret = nau7802_read_conversion(st);
277 if (ret < 0)
278 return ret;
279 if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
280 st->conversion_count++;
281 } while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
282
283 *val = st->last_value;
284
285 return IIO_VAL_INT;
286 }
287
nau7802_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)288 static int nau7802_read_raw(struct iio_dev *indio_dev,
289 struct iio_chan_spec const *chan,
290 int *val, int *val2, long mask)
291 {
292 struct nau7802_state *st = iio_priv(indio_dev);
293 int ret;
294
295 switch (mask) {
296 case IIO_CHAN_INFO_RAW:
297 mutex_lock(&st->lock);
298 /*
299 * Select the channel to use
300 * - Channel 1 is value 0 in the CHS register
301 * - Channel 2 is value 1 in the CHS register
302 */
303 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
304 if (ret < 0) {
305 mutex_unlock(&st->lock);
306 return ret;
307 }
308
309 if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
310 (!(ret & NAU7802_CTRL2_CHS_BIT) &&
311 chan->channel)) {
312 st->conversion_count = 0;
313 ret = i2c_smbus_write_byte_data(st->client,
314 NAU7802_REG_CTRL2,
315 NAU7802_CTRL2_CHS(chan->channel) |
316 NAU7802_CTRL2_CRS(st->sample_rate));
317
318 if (ret < 0) {
319 mutex_unlock(&st->lock);
320 return ret;
321 }
322 }
323
324 if (st->client->irq)
325 ret = nau7802_read_irq(indio_dev, chan, val);
326 else
327 ret = nau7802_read_poll(indio_dev, chan, val);
328
329 mutex_unlock(&st->lock);
330 return ret;
331
332 case IIO_CHAN_INFO_SCALE:
333 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
334 if (ret < 0)
335 return ret;
336
337 /*
338 * We have 24 bits of signed data, that means 23 bits of data
339 * plus the sign bit
340 */
341 *val = st->vref_mv;
342 *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
343
344 return IIO_VAL_FRACTIONAL_LOG2;
345
346 case IIO_CHAN_INFO_SAMP_FREQ:
347 *val = nau7802_sample_freq_avail[st->sample_rate];
348 *val2 = 0;
349 return IIO_VAL_INT;
350
351 default:
352 break;
353 }
354
355 return -EINVAL;
356 }
357
nau7802_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)358 static int nau7802_write_raw(struct iio_dev *indio_dev,
359 struct iio_chan_spec const *chan,
360 int val, int val2, long mask)
361 {
362 struct nau7802_state *st = iio_priv(indio_dev);
363 int i, ret;
364
365 switch (mask) {
366 case IIO_CHAN_INFO_SCALE:
367 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
368 if (val2 == st->scale_avail[i])
369 return nau7802_set_gain(st, i);
370
371 break;
372
373 case IIO_CHAN_INFO_SAMP_FREQ:
374 for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
375 if (val == nau7802_sample_freq_avail[i]) {
376 mutex_lock(&st->lock);
377 st->sample_rate = i;
378 st->conversion_count = 0;
379 ret = i2c_smbus_write_byte_data(st->client,
380 NAU7802_REG_CTRL2,
381 NAU7802_CTRL2_CRS(st->sample_rate));
382 mutex_unlock(&st->lock);
383 return ret;
384 }
385
386 break;
387
388 default:
389 break;
390 }
391
392 return -EINVAL;
393 }
394
nau7802_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)395 static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
396 struct iio_chan_spec const *chan,
397 long mask)
398 {
399 return IIO_VAL_INT_PLUS_NANO;
400 }
401
402 static const struct iio_info nau7802_info = {
403 .read_raw = &nau7802_read_raw,
404 .write_raw = &nau7802_write_raw,
405 .write_raw_get_fmt = nau7802_write_raw_get_fmt,
406 .attrs = &nau7802_attribute_group,
407 };
408
nau7802_probe(struct i2c_client * client)409 static int nau7802_probe(struct i2c_client *client)
410 {
411 struct iio_dev *indio_dev;
412 struct nau7802_state *st;
413 int i, ret;
414 u8 data;
415 u32 tmp = 0;
416
417 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
418 if (indio_dev == NULL)
419 return -ENOMEM;
420
421 st = iio_priv(indio_dev);
422
423 indio_dev->name = dev_name(&client->dev);
424 indio_dev->modes = INDIO_DIRECT_MODE;
425 indio_dev->info = &nau7802_info;
426
427 st->client = client;
428
429 /* Reset the device */
430 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
431 NAU7802_PUCTRL_RR_BIT);
432 if (ret < 0)
433 return ret;
434
435 /* Enter normal operation mode */
436 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
437 NAU7802_PUCTRL_PUD_BIT);
438 if (ret < 0)
439 return ret;
440
441 /*
442 * After about 200 usecs, the device should be ready and then
443 * the Power Up bit will be set to 1. If not, wait for it.
444 */
445 udelay(210);
446 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
447 if (ret < 0)
448 return ret;
449 if (!(ret & NAU7802_PUCTRL_PUR_BIT))
450 return ret;
451
452 device_property_read_u32(&client->dev, "nuvoton,vldo", &tmp);
453 st->vref_mv = tmp;
454
455 data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
456 NAU7802_PUCTRL_CS_BIT;
457 if (tmp >= 2400)
458 data |= NAU7802_PUCTRL_AVDDS_BIT;
459
460 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
461 if (ret < 0)
462 return ret;
463 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
464 if (ret < 0)
465 return ret;
466
467 if (tmp >= 2400) {
468 data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
469 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
470 data);
471 if (ret < 0)
472 return ret;
473 }
474
475 /* Populate available ADC input ranges */
476 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
477 st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
478 >> (23 + i);
479
480 init_completion(&st->value_ok);
481
482 /*
483 * The ADC fires continuously and we can't do anything about
484 * it. So we need to have the IRQ disabled by default, and we
485 * will enable them back when we will need them..
486 */
487 if (client->irq) {
488 ret = devm_request_threaded_irq(&client->dev, client->irq,
489 NULL,
490 nau7802_eoc_trigger,
491 IRQF_TRIGGER_HIGH | IRQF_ONESHOT |
492 IRQF_NO_AUTOEN,
493 client->dev.driver->name,
494 indio_dev);
495 if (ret) {
496 /*
497 * What may happen here is that our IRQ controller is
498 * not able to get level interrupt but this is required
499 * by this ADC as when going over 40 sample per second,
500 * the interrupt line may stay high between conversions.
501 * So, we continue no matter what but we switch to
502 * polling mode.
503 */
504 dev_info(&client->dev,
505 "Failed to allocate IRQ, using polling mode\n");
506 client->irq = 0;
507 }
508 }
509
510 if (!client->irq) {
511 /*
512 * We are polling, use the fastest sample rate by
513 * default
514 */
515 st->sample_rate = NAU7802_SAMP_FREQ_320;
516 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
517 NAU7802_CTRL2_CRS(st->sample_rate));
518 if (ret)
519 return ret;
520 }
521
522 /* Setup the ADC channels available on the board */
523 indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
524 indio_dev->channels = nau7802_chan_array;
525
526 mutex_init(&st->lock);
527 mutex_init(&st->data_lock);
528
529 return devm_iio_device_register(&client->dev, indio_dev);
530 }
531
532 static const struct i2c_device_id nau7802_i2c_id[] = {
533 { .name = "nau7802" },
534 { }
535 };
536 MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
537
538 static const struct of_device_id nau7802_dt_ids[] = {
539 { .compatible = "nuvoton,nau7802" },
540 { }
541 };
542 MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
543
544 static struct i2c_driver nau7802_driver = {
545 .probe = nau7802_probe,
546 .id_table = nau7802_i2c_id,
547 .driver = {
548 .name = "nau7802",
549 .of_match_table = nau7802_dt_ids,
550 },
551 };
552
553 module_i2c_driver(nau7802_driver);
554
555 MODULE_LICENSE("GPL");
556 MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
557 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
558 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
559