1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * linux/include/linux/mmc/host.h 4 * 5 * Host driver specific definitions. 6 */ 7 #ifndef LINUX_MMC_HOST_H 8 #define LINUX_MMC_HOST_H 9 10 #include <linux/sched.h> 11 #include <linux/device.h> 12 #include <linux/fault-inject.h> 13 #include <linux/debugfs.h> 14 15 #include <linux/mmc/core.h> 16 #include <linux/mmc/card.h> 17 #include <linux/mmc/pm.h> 18 #include <linux/dma-direction.h> 19 #include <linux/blk-crypto-profile.h> 20 #include <linux/mmc/sd_uhs2.h> 21 22 struct mmc_ios { 23 unsigned int clock; /* clock rate */ 24 unsigned short vdd; 25 unsigned int power_delay_ms; /* waiting for stable power */ 26 unsigned int power_off_delay_us; /* waiting for power discharge */ 27 28 /* vdd stores the bit number of the selected voltage range from below. */ 29 30 unsigned char bus_mode; /* command output mode */ 31 32 #define MMC_BUSMODE_OPENDRAIN 1 33 #define MMC_BUSMODE_PUSHPULL 2 34 35 unsigned char chip_select; /* SPI chip select */ 36 37 #define MMC_CS_DONTCARE 0 38 #define MMC_CS_HIGH 1 39 #define MMC_CS_LOW 2 40 41 unsigned char power_mode; /* power supply mode */ 42 43 #define MMC_POWER_OFF 0 44 #define MMC_POWER_UP 1 45 #define MMC_POWER_ON 2 46 #define MMC_POWER_UNDEFINED 3 47 48 unsigned char bus_width; /* data bus width */ 49 50 #define MMC_BUS_WIDTH_1 0 51 #define MMC_BUS_WIDTH_4 2 52 #define MMC_BUS_WIDTH_8 3 53 54 unsigned char timing; /* timing specification used */ 55 56 #define MMC_TIMING_LEGACY 0 57 #define MMC_TIMING_MMC_HS 1 58 #define MMC_TIMING_SD_HS 2 59 #define MMC_TIMING_UHS_SDR12 3 60 #define MMC_TIMING_UHS_SDR25 4 61 #define MMC_TIMING_UHS_SDR50 5 62 #define MMC_TIMING_UHS_SDR104 6 63 #define MMC_TIMING_UHS_DDR50 7 64 #define MMC_TIMING_MMC_DDR52 8 65 #define MMC_TIMING_MMC_HS200 9 66 #define MMC_TIMING_MMC_HS400 10 67 #define MMC_TIMING_SD_EXP 11 68 #define MMC_TIMING_SD_EXP_1_2V 12 69 #define MMC_TIMING_UHS2_SPEED_A 13 70 #define MMC_TIMING_UHS2_SPEED_A_HD 14 71 #define MMC_TIMING_UHS2_SPEED_B 15 72 #define MMC_TIMING_UHS2_SPEED_B_HD 16 73 74 unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ 75 76 #define MMC_SIGNAL_VOLTAGE_330 0 77 #define MMC_SIGNAL_VOLTAGE_180 1 78 #define MMC_SIGNAL_VOLTAGE_120 2 79 80 unsigned char vqmmc2_voltage; 81 #define MMC_VQMMC2_VOLTAGE_180 0 82 83 unsigned char drv_type; /* driver type (A, B, C, D) */ 84 85 #define MMC_SET_DRIVER_TYPE_B 0 86 #define MMC_SET_DRIVER_TYPE_A 1 87 #define MMC_SET_DRIVER_TYPE_C 2 88 #define MMC_SET_DRIVER_TYPE_D 3 89 90 bool enhanced_strobe; /* hs400es selection */ 91 }; 92 93 struct mmc_clk_phase { 94 bool valid; 95 u16 in_deg; 96 u16 out_deg; 97 }; 98 99 #define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS400 + 1) 100 struct mmc_clk_phase_map { 101 struct mmc_clk_phase phase[MMC_NUM_CLK_PHASES]; 102 }; 103 104 struct sd_uhs2_caps { 105 u32 dap; 106 u32 gap; 107 u32 group_desc; 108 u32 maxblk_len; 109 u32 n_fcu; 110 u8 n_lanes; 111 u8 addr64; 112 u8 card_type; 113 u8 phy_rev; 114 u8 speed_range; 115 u8 n_lss_sync; 116 u8 n_lss_dir; 117 u8 link_rev; 118 u8 host_type; 119 u8 n_data_gap; 120 121 u32 maxblk_len_set; 122 u32 n_fcu_set; 123 u8 n_lanes_set; 124 u8 n_lss_sync_set; 125 u8 n_lss_dir_set; 126 u8 n_data_gap_set; 127 u8 max_retry_set; 128 }; 129 130 enum sd_uhs2_operation { 131 UHS2_PHY_INIT = 0, 132 UHS2_SET_CONFIG, 133 UHS2_ENABLE_INT, 134 UHS2_DISABLE_INT, 135 UHS2_ENABLE_CLK, 136 UHS2_DISABLE_CLK, 137 UHS2_CHECK_DORMANT, 138 UHS2_SET_IOS, 139 }; 140 141 struct mmc_host; 142 143 enum mmc_err_stat { 144 MMC_ERR_CMD_TIMEOUT, 145 MMC_ERR_CMD_CRC, 146 MMC_ERR_DAT_TIMEOUT, 147 MMC_ERR_DAT_CRC, 148 MMC_ERR_AUTO_CMD, 149 MMC_ERR_ADMA, 150 MMC_ERR_TUNING, 151 MMC_ERR_CMDQ_RED, 152 MMC_ERR_CMDQ_GCE, 153 MMC_ERR_CMDQ_ICCE, 154 MMC_ERR_REQ_TIMEOUT, 155 MMC_ERR_CMDQ_REQ_TIMEOUT, 156 MMC_ERR_ICE_CFG, 157 MMC_ERR_CTRL_TIMEOUT, 158 MMC_ERR_UNEXPECTED_IRQ, 159 MMC_ERR_MAX, 160 }; 161 162 struct mmc_host_ops { 163 /* 164 * It is optional for the host to implement pre_req and post_req in 165 * order to support double buffering of requests (prepare one 166 * request while another request is active). 167 * pre_req() must always be followed by a post_req(). 168 * To undo a call made to pre_req(), call post_req() with 169 * a nonzero err condition. 170 */ 171 void (*post_req)(struct mmc_host *host, struct mmc_request *req, 172 int err); 173 void (*pre_req)(struct mmc_host *host, struct mmc_request *req); 174 void (*request)(struct mmc_host *host, struct mmc_request *req); 175 /* Submit one request to host in atomic context. */ 176 int (*request_atomic)(struct mmc_host *host, 177 struct mmc_request *req); 178 179 /* 180 * Avoid calling the next three functions too often or in a "fast 181 * path", since underlaying controller might implement them in an 182 * expensive and/or slow way. Also note that these functions might 183 * sleep, so don't call them in the atomic contexts! 184 */ 185 186 /* 187 * Notes to the set_ios callback: 188 * ios->clock might be 0. For some controllers, setting 0Hz 189 * as any other frequency works. However, some controllers 190 * explicitly need to disable the clock. Otherwise e.g. voltage 191 * switching might fail because the SDCLK is not really quiet. 192 */ 193 void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); 194 195 /* 196 * Return values for the get_ro callback should be: 197 * 0 for a read/write card 198 * 1 for a read-only card 199 * -ENOSYS when not supported (equal to NULL callback) 200 * or a negative errno value when something bad happened 201 */ 202 int (*get_ro)(struct mmc_host *host); 203 204 /* 205 * Return values for the get_cd callback should be: 206 * 0 for a absent card 207 * 1 for a present card 208 * -ENOSYS when not supported (equal to NULL callback) 209 * or a negative errno value when something bad happened 210 */ 211 int (*get_cd)(struct mmc_host *host); 212 213 void (*enable_sdio_irq)(struct mmc_host *host, int enable); 214 /* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */ 215 void (*ack_sdio_irq)(struct mmc_host *host); 216 217 /* optional callback for HC quirks */ 218 void (*init_card)(struct mmc_host *host, struct mmc_card *card); 219 220 int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios); 221 222 /* Check if the card is pulling dat[0] low */ 223 int (*card_busy)(struct mmc_host *host); 224 225 /* The tuning command opcode value is different for SD and eMMC cards */ 226 int (*execute_tuning)(struct mmc_host *host, u32 opcode); 227 228 /* Prepare HS400 target operating frequency depending host driver */ 229 int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); 230 231 /* Execute HS400 tuning depending host driver */ 232 int (*execute_hs400_tuning)(struct mmc_host *host, struct mmc_card *card); 233 234 /* Optional callback to prepare for SD high-speed tuning */ 235 int (*prepare_sd_hs_tuning)(struct mmc_host *host, struct mmc_card *card); 236 237 /* Optional callback to execute SD high-speed tuning */ 238 int (*execute_sd_hs_tuning)(struct mmc_host *host, struct mmc_card *card); 239 240 /* Prepare switch to DDR during the HS400 init sequence */ 241 int (*hs400_prepare_ddr)(struct mmc_host *host); 242 243 /* Prepare for switching from HS400 to HS200 */ 244 void (*hs400_downgrade)(struct mmc_host *host); 245 246 /* Complete selection of HS400 */ 247 void (*hs400_complete)(struct mmc_host *host); 248 249 /* Prepare enhanced strobe depending host driver */ 250 void (*hs400_enhanced_strobe)(struct mmc_host *host, 251 struct mmc_ios *ios); 252 int (*select_drive_strength)(struct mmc_card *card, 253 unsigned int max_dtr, int host_drv, 254 int card_drv, int *drv_type); 255 /* Reset the eMMC card via RST_n */ 256 void (*card_hw_reset)(struct mmc_host *host); 257 void (*card_event)(struct mmc_host *host); 258 259 /* 260 * Optional callback to support controllers with HW issues for multiple 261 * I/O. Returns the number of supported blocks for the request. 262 */ 263 int (*multi_io_quirk)(struct mmc_card *card, 264 unsigned int direction, int blk_size); 265 266 /* Initialize an SD express card, mandatory for MMC_CAP2_SD_EXP. */ 267 int (*init_sd_express)(struct mmc_host *host, struct mmc_ios *ios); 268 269 /* 270 * The uhs2_control callback is used to execute SD UHS-II specific 271 * operations. It's mandatory to implement for hosts that supports the 272 * SD UHS-II interface (MMC_CAP2_SD_UHS2). Expected return values are a 273 * negative errno in case of a failure or zero for success. 274 */ 275 int (*uhs2_control)(struct mmc_host *host, enum sd_uhs2_operation op); 276 }; 277 278 struct mmc_cqe_ops { 279 /* Allocate resources, and make the CQE operational */ 280 int (*cqe_enable)(struct mmc_host *host, struct mmc_card *card); 281 /* Free resources, and make the CQE non-operational */ 282 void (*cqe_disable)(struct mmc_host *host); 283 /* 284 * Issue a read, write or DCMD request to the CQE. Also deal with the 285 * effect of ->cqe_off(). 286 */ 287 int (*cqe_request)(struct mmc_host *host, struct mmc_request *mrq); 288 /* Free resources (e.g. DMA mapping) associated with the request */ 289 void (*cqe_post_req)(struct mmc_host *host, struct mmc_request *mrq); 290 /* 291 * Prepare the CQE and host controller to accept non-CQ commands. There 292 * is no corresponding ->cqe_on(), instead ->cqe_request() is required 293 * to deal with that. 294 */ 295 void (*cqe_off)(struct mmc_host *host); 296 /* 297 * Wait for all CQE tasks to complete. Return an error if recovery 298 * becomes necessary. 299 */ 300 int (*cqe_wait_for_idle)(struct mmc_host *host); 301 /* 302 * Notify CQE that a request has timed out. Return false if the request 303 * completed or true if a timeout happened in which case indicate if 304 * recovery is needed. 305 */ 306 bool (*cqe_timeout)(struct mmc_host *host, struct mmc_request *mrq, 307 bool *recovery_needed); 308 /* 309 * Stop all CQE activity and prepare the CQE and host controller to 310 * accept recovery commands. 311 */ 312 void (*cqe_recovery_start)(struct mmc_host *host); 313 /* 314 * Clear the queue and call mmc_cqe_request_done() on all requests. 315 * Requests that errored will have the error set on the mmc_request 316 * (data->error or cmd->error for DCMD). Requests that did not error 317 * will have zero data bytes transferred. 318 */ 319 void (*cqe_recovery_finish)(struct mmc_host *host); 320 }; 321 322 /** 323 * struct mmc_slot - MMC slot functions 324 * 325 * @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL 326 * @handler_priv: MMC/SD-card slot context 327 * 328 * Some MMC/SD host controllers implement slot-functions like card and 329 * write-protect detection natively. However, a large number of controllers 330 * leave these functions to the CPU. This struct provides a hook to attach 331 * such slot-function drivers. 332 */ 333 struct mmc_slot { 334 int cd_irq; 335 bool cd_wake_enabled; 336 void *handler_priv; 337 }; 338 339 struct regulator; 340 struct mmc_pwrseq; 341 struct notifier_block; 342 343 struct mmc_supply { 344 struct regulator *vmmc; /* Card power supply */ 345 struct regulator *vqmmc; /* Optional Vccq supply */ 346 struct regulator *vqmmc2; /* Optional supply for phy */ 347 348 struct notifier_block vmmc_nb; /* Notifier for vmmc */ 349 struct work_struct uv_work; /* Undervoltage work */ 350 }; 351 352 struct mmc_ctx { 353 struct task_struct *task; 354 }; 355 356 struct mmc_host { 357 struct device *parent; 358 struct device class_dev; 359 int index; 360 const struct mmc_host_ops *ops; 361 struct mmc_pwrseq *pwrseq; 362 unsigned int f_min; 363 unsigned int f_max; 364 unsigned int f_init; 365 u32 ocr_avail; 366 u32 ocr_avail_sdio; /* SDIO-specific OCR */ 367 u32 ocr_avail_sd; /* SD-specific OCR */ 368 u32 ocr_avail_mmc; /* MMC-specific OCR */ 369 struct wakeup_source *ws; /* Enable consume of uevents */ 370 u32 max_current_330; 371 u32 max_current_300; 372 u32 max_current_180; 373 374 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 375 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 376 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 377 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 378 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 379 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 380 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 381 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 382 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 383 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 384 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 385 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 386 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 387 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 388 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 389 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 390 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 391 392 u32 caps; /* Host capabilities */ 393 394 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ 395 #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ 396 #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ 397 #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ 398 #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ 399 #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ 400 #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ 401 #define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ 402 #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ 403 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ 404 #define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */ 405 #define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */ 406 #define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */ 407 #define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \ 408 MMC_CAP_1_2V_DDR) 409 #define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */ 410 #define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */ 411 #define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */ 412 #define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */ 413 #define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ 414 #define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ 415 #define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ 416 #define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \ 417 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \ 418 MMC_CAP_UHS_DDR50) 419 #define MMC_CAP_SYNC_RUNTIME_PM (1 << 21) /* Synced runtime PM suspends. */ 420 #define MMC_CAP_NEED_RSP_BUSY (1 << 22) /* Commands with R1B can't use R1. */ 421 #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ 422 #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ 423 #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ 424 #define MMC_CAP_DONE_COMPLETE (1 << 27) /* RW reqs can be completed within mmc_request_done() */ 425 #define MMC_CAP_CD_WAKE (1 << 28) /* Enable card detect wake */ 426 #define MMC_CAP_CMD_DURING_TFR (1 << 29) /* Commands during data transfer */ 427 #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ 428 #define MMC_CAP_HW_RESET (1 << 31) /* Reset the eMMC card via RST_n */ 429 430 u32 caps2; /* More host capabilities */ 431 432 #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ 433 #define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ 434 #define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3) /* Can do full power cycle in suspend */ 435 #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ 436 #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ 437 #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ 438 MMC_CAP2_HS200_1_2V_SDR) 439 #define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */ 440 #define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */ 441 #define MMC_CAP2_SD_UHS2 (1 << 9) /* SD UHS-II support */ 442 #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ 443 #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ 444 #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ 445 #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ 446 #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ 447 #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ 448 MMC_CAP2_HS400_1_2V) 449 #define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V) 450 #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) 451 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) 452 #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ 453 #define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */ 454 #define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ 455 #define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */ 456 #define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ 457 #define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */ 458 #define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */ 459 #define MMC_CAP2_AVOID_3_3V (1 << 25) /* Host must negotiate down from 3.3V */ 460 #define MMC_CAP2_MERGE_CAPABLE (1 << 26) /* Host can merge a segment over the segment size */ 461 #ifdef CONFIG_MMC_CRYPTO 462 #define MMC_CAP2_CRYPTO (1 << 27) /* Host supports inline encryption */ 463 #else 464 #define MMC_CAP2_CRYPTO 0 465 #endif 466 #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ 467 #define MMC_CAP2_CRYPTO_NO_REPROG (1 << 29) /* Host handles inline crypto key reprogramming */ 468 469 bool uhs2_sd_tran; /* UHS-II flag for SD_TRAN state */ 470 bool uhs2_app_cmd; /* UHS-II flag for APP command */ 471 struct sd_uhs2_caps uhs2_caps; /* Host UHS-II capabilities */ 472 473 int fixed_drv_type; /* fixed driver type for non-removable media */ 474 475 mmc_pm_flag_t pm_caps; /* supported pm features */ 476 477 /* host specific block data */ 478 unsigned int max_seg_size; /* lim->max_segment_size */ 479 unsigned short max_segs; /* lim->max_segments */ 480 unsigned short unused; 481 unsigned int max_req_size; /* maximum number of bytes in one req */ 482 unsigned int max_blk_size; /* maximum size of one mmc block */ 483 unsigned int max_blk_count; /* maximum number of blocks in one req */ 484 unsigned int max_busy_timeout; /* max busy timeout in ms */ 485 486 /* private data */ 487 spinlock_t lock; /* lock for claim and bus ops */ 488 489 struct mmc_ios ios; /* current io bus settings */ 490 491 bool claimed; /* host exclusively claimed */ 492 493 /* group bitfields together to minimize padding */ 494 unsigned int use_spi_crc:1; 495 unsigned int doing_init_tune:1; /* initial tuning in progress */ 496 unsigned int doing_retune:1; /* re-tuning in progress */ 497 unsigned int retune_crc_disable:1; /* don't trigger retune upon crc */ 498 unsigned int can_dma_map_merge:1; /* merging can be used */ 499 unsigned int vqmmc_enabled:1; /* vqmmc regulator is enabled */ 500 501 /* 502 * Indicates if an undervoltage event has already been handled. 503 * This prevents repeated regulator notifiers from triggering 504 * multiple REGULATOR_EVENT_UNDER_VOLTAGE events. 505 */ 506 unsigned int undervoltage:1; /* Undervoltage state */ 507 508 int rescan_disable; /* disable card detection */ 509 int rescan_entered; /* used with nonremovable devices */ 510 511 bool can_retune; /* re-tuning can be used */ 512 bool retune_now; /* do re-tuning at next req */ 513 bool retune_paused; /* re-tuning is temporarily disabled */ 514 int need_retune; /* re-tuning is needed */ 515 int hold_retune; /* hold off re-tuning */ 516 unsigned int retune_period; /* re-tuning period in secs */ 517 struct timer_list retune_timer; /* for periodic re-tuning */ 518 519 bool trigger_card_event; /* card_event necessary */ 520 521 struct mmc_card *card; /* device attached to this host */ 522 523 wait_queue_head_t wq; 524 struct mmc_ctx *claimer; /* context that has host claimed */ 525 int claim_cnt; /* "claim" nesting count */ 526 struct mmc_ctx default_ctx; /* default context */ 527 528 struct delayed_work detect; 529 int detect_change; /* card detect flag */ 530 struct mmc_slot slot; 531 532 const struct mmc_bus_ops *bus_ops; /* current bus driver */ 533 534 unsigned int sdio_irqs; 535 struct task_struct *sdio_irq_thread; 536 struct work_struct sdio_irq_work; 537 bool sdio_irq_pending; 538 atomic_t sdio_irq_thread_abort; 539 540 mmc_pm_flag_t pm_flags; /* requested pm features */ 541 542 struct led_trigger *led; /* activity led */ 543 544 #ifdef CONFIG_REGULATOR 545 bool regulator_enabled; /* regulator state */ 546 #endif 547 struct mmc_supply supply; 548 549 struct dentry *debugfs_root; 550 551 /* Ongoing data transfer that allows commands during transfer */ 552 struct mmc_request *ongoing_mrq; 553 554 #ifdef CONFIG_FAIL_MMC_REQUEST 555 struct fault_attr fail_mmc_request; 556 #endif 557 558 unsigned int actual_clock; /* Actual HC clock rate */ 559 560 unsigned int slotno; /* used for sdio acpi binding */ 561 562 int dsr_req; /* DSR value is valid */ 563 u32 dsr; /* optional driver stage (DSR) value */ 564 565 /* Command Queue Engine (CQE) support */ 566 const struct mmc_cqe_ops *cqe_ops; 567 void *cqe_private; 568 int cqe_qdepth; 569 bool cqe_enabled; 570 bool cqe_on; 571 572 /* Inline encryption support */ 573 #ifdef CONFIG_MMC_CRYPTO 574 struct blk_crypto_profile crypto_profile; 575 #endif 576 577 /* Host Software Queue support */ 578 bool hsq_enabled; 579 int hsq_depth; 580 581 u32 err_stats[MMC_ERR_MAX]; 582 u32 max_sd_hs_hz; 583 unsigned long private[] ____cacheline_aligned; 584 }; 585 586 struct device_node; 587 588 struct mmc_host *devm_mmc_alloc_host(struct device *dev, int extra); 589 int mmc_add_host(struct mmc_host *); 590 void mmc_remove_host(struct mmc_host *); 591 void mmc_of_parse_clk_phase(struct device *dev, 592 struct mmc_clk_phase_map *map); 593 int mmc_of_parse(struct mmc_host *host); 594 int mmc_of_parse_voltage(struct mmc_host *host, u32 *mask); 595 596 static inline void *mmc_priv(struct mmc_host *host) 597 { 598 return (void *)host->private; 599 } 600 601 static inline struct mmc_host *mmc_from_priv(void *priv) 602 { 603 return container_of(priv, struct mmc_host, private); 604 } 605 606 #ifdef CONFIG_MMC_CRYPTO 607 static inline struct mmc_host * 608 mmc_from_crypto_profile(struct blk_crypto_profile *profile) 609 { 610 return container_of(profile, struct mmc_host, crypto_profile); 611 } 612 #endif 613 614 #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) 615 616 #define mmc_dev(x) ((x)->parent) 617 #define mmc_classdev(x) (&(x)->class_dev) 618 #define mmc_hostname(x) (dev_name(&(x)->class_dev)) 619 620 void mmc_detect_change(struct mmc_host *, unsigned long delay); 621 void mmc_request_done(struct mmc_host *, struct mmc_request *); 622 void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq); 623 624 void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq); 625 626 /* 627 * May be called from host driver's system/runtime suspend/resume callbacks, 628 * to know if SDIO IRQs has been claimed. 629 */ 630 static inline bool sdio_irq_claimed(struct mmc_host *host) 631 { 632 return host->sdio_irqs > 0; 633 } 634 635 static inline void mmc_signal_sdio_irq(struct mmc_host *host) 636 { 637 host->ops->enable_sdio_irq(host, 0); 638 host->sdio_irq_pending = true; 639 if (host->sdio_irq_thread) 640 wake_up_process(host->sdio_irq_thread); 641 } 642 643 void sdio_signal_irq(struct mmc_host *host); 644 645 #ifdef CONFIG_REGULATOR 646 int mmc_regulator_set_ocr(struct mmc_host *mmc, 647 struct regulator *supply, 648 unsigned short vdd_bit); 649 int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios); 650 int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, struct mmc_ios *ios); 651 #else 652 static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, 653 struct regulator *supply, 654 unsigned short vdd_bit) 655 { 656 return 0; 657 } 658 659 static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc, 660 struct mmc_ios *ios) 661 { 662 return -EINVAL; 663 } 664 665 static inline int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, 666 struct mmc_ios *ios) 667 { 668 return -EINVAL; 669 } 670 #endif 671 672 int mmc_regulator_get_supply(struct mmc_host *mmc); 673 int mmc_regulator_enable_vqmmc(struct mmc_host *mmc); 674 void mmc_regulator_disable_vqmmc(struct mmc_host *mmc); 675 676 static inline int mmc_card_is_removable(struct mmc_host *host) 677 { 678 return !(host->caps & MMC_CAP_NONREMOVABLE); 679 } 680 681 static inline int mmc_card_keep_power(struct mmc_host *host) 682 { 683 return host->pm_flags & MMC_PM_KEEP_POWER; 684 } 685 686 static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) 687 { 688 return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; 689 } 690 691 /* TODO: Move to private header */ 692 static inline int mmc_card_hs(struct mmc_card *card) 693 { 694 return card->host->ios.timing == MMC_TIMING_SD_HS || 695 card->host->ios.timing == MMC_TIMING_MMC_HS; 696 } 697 698 /* TODO: Move to private header */ 699 static inline int mmc_card_uhs(struct mmc_card *card) 700 { 701 return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && 702 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; 703 } 704 705 static inline bool mmc_card_uhs2(struct mmc_host *host) 706 { 707 return host->ios.timing == MMC_TIMING_UHS2_SPEED_A || 708 host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD || 709 host->ios.timing == MMC_TIMING_UHS2_SPEED_B || 710 host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD; 711 } 712 713 void mmc_retune_timer_stop(struct mmc_host *host); 714 715 static inline void mmc_retune_needed(struct mmc_host *host) 716 { 717 if (host->can_retune) 718 host->need_retune = 1; 719 } 720 721 static inline bool mmc_can_retune(struct mmc_host *host) 722 { 723 return host->can_retune == 1; 724 } 725 726 static inline bool mmc_doing_retune(struct mmc_host *host) 727 { 728 return host->doing_retune == 1; 729 } 730 731 static inline bool mmc_doing_tune(struct mmc_host *host) 732 { 733 return host->doing_retune == 1 || host->doing_init_tune == 1; 734 } 735 736 static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data) 737 { 738 return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 739 } 740 741 static inline void mmc_debugfs_err_stats_inc(struct mmc_host *host, 742 enum mmc_err_stat stat) 743 { 744 host->err_stats[stat] += 1; 745 } 746 747 static inline int mmc_card_uhs2_hd_mode(struct mmc_host *host) 748 { 749 return host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD || 750 host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD; 751 } 752 753 int mmc_sd_switch(struct mmc_card *card, bool mode, int group, 754 u8 value, u8 *resp); 755 int mmc_send_status(struct mmc_card *card, u32 *status); 756 int mmc_send_tuning_timeout(struct mmc_host *host, u32 opcode, int *cmd_error, 757 u32 timeout_ms); 758 int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); 759 int mmc_send_abort_tuning(struct mmc_host *host, u32 opcode); 760 int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); 761 int mmc_read_tuning(struct mmc_host *host, unsigned int blksz, unsigned int blocks); 762 763 #endif /* LINUX_MMC_HOST_H */ 764