1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/init.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/slab.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/time.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 22 #include "mxs-saif.h" 23 24 #define MXS_SET_ADDR 0x4 25 #define MXS_CLR_ADDR 0x8 26 27 #define MXS_SAIF_BUSY_TIMEOUT_US 10000 28 29 static struct mxs_saif *mxs_saif[2]; 30 31 /* 32 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 33 * is provided by other SAIF, we provide a interface here to get its master 34 * from its master_id. 35 * Note that the master could be itself. 36 */ 37 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif *saif) 38 { 39 return mxs_saif[saif->master_id]; 40 } 41 42 static int __mxs_saif_put_mclk(struct mxs_saif *saif) 43 { 44 u32 stat; 45 int ret; 46 47 ret = readx_poll_timeout(__raw_readl, saif->base + SAIF_STAT, stat, 48 (stat & BM_SAIF_STAT_BUSY) == 0, 49 MXS_SAIF_BUSY_TIMEOUT_US, 50 USEC_PER_SEC); 51 if (ret) { 52 dev_err(saif->dev, "error: busy\n"); 53 return -EBUSY; 54 } 55 56 /* disable MCLK output */ 57 __raw_writel(BM_SAIF_CTRL_CLKGATE, 58 saif->base + SAIF_CTRL + MXS_SET_ADDR); 59 __raw_writel(BM_SAIF_CTRL_RUN, 60 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 61 62 saif->mclk_in_use = 0; 63 64 return 0; 65 } 66 67 static int __mxs_saif_get_mclk(struct mxs_saif *saif) 68 { 69 u32 stat; 70 struct mxs_saif *master_saif; 71 72 if (!saif) 73 return -EINVAL; 74 75 /* Clear Reset */ 76 __raw_writel(BM_SAIF_CTRL_SFTRST, 77 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 78 79 /* FIXME: need clear clk gate for register r/w */ 80 __raw_writel(BM_SAIF_CTRL_CLKGATE, 81 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 82 83 master_saif = mxs_saif_get_master(saif); 84 if (saif != master_saif) { 85 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 86 return -EINVAL; 87 } 88 89 stat = __raw_readl(saif->base + SAIF_STAT); 90 if (stat & BM_SAIF_STAT_BUSY) { 91 dev_err(saif->dev, "error: busy\n"); 92 return -EBUSY; 93 } 94 95 saif->mclk_in_use = 1; 96 97 return 0; 98 } 99 100 /* 101 * SAIF is a little different with other normal SOC DAIs on clock using. 102 * 103 * For MXS, two SAIF modules are instantiated on-chip. 104 * Each SAIF has a set of clock pins and can be operating in master 105 * mode simultaneously if they are connected to different off-chip codecs. 106 * Also, one of the two SAIFs can master or drive the clock pins while the 107 * other SAIF, in slave mode, receives clocking from the master SAIF. 108 * This also means that both SAIFs must operate at the same sample rate. 109 * 110 * We abstract this as each saif has a master, the master could be 111 * itself or other saifs. In the generic saif driver, saif does not need 112 * to know the different clkmux. Saif only needs to know who is its master 113 * and operating its master to generate the proper clock rate for it. 114 * The master id is provided in mach-specific layer according to different 115 * clkmux setting. 116 */ 117 118 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 119 int clk_id, unsigned int freq, int dir) 120 { 121 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 122 int ret; 123 124 switch (clk_id) { 125 case MXS_SAIF_MCLK: 126 saif->mclk = freq; 127 break; 128 default: 129 return -EINVAL; 130 } 131 132 if (!saif->mclk_in_use && freq) { 133 ret = __mxs_saif_get_mclk(saif); 134 if (ret) 135 return ret; 136 137 /* enable MCLK output */ 138 __raw_writel(BM_SAIF_CTRL_RUN, 139 saif->base + SAIF_CTRL + MXS_SET_ADDR); 140 } else if (saif->mclk_in_use && freq == 0) { 141 ret = __mxs_saif_put_mclk(saif); 142 if (ret) 143 return ret; 144 } 145 146 return 0; 147 } 148 149 /* 150 * Set SAIF clock and MCLK 151 */ 152 static int mxs_saif_set_clk(struct mxs_saif *saif, 153 unsigned int mclk, 154 unsigned int rate) 155 { 156 u32 scr; 157 int ret; 158 struct mxs_saif *master_saif; 159 160 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 161 162 /* Set master saif to generate proper clock */ 163 master_saif = mxs_saif_get_master(saif); 164 if (!master_saif) 165 return -EINVAL; 166 167 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 168 169 /* Checking if can playback and capture simutaneously */ 170 if (master_saif->ongoing && rate != master_saif->cur_rate) { 171 dev_err(saif->dev, 172 "can not change clock, master saif%d(rate %d) is ongoing\n", 173 master_saif->id, master_saif->cur_rate); 174 return -EINVAL; 175 } 176 177 scr = __raw_readl(master_saif->base + SAIF_CTRL); 178 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 179 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 180 181 /* 182 * Set SAIF clock 183 * 184 * The SAIF clock should be either 384*fs or 512*fs. 185 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. 186 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. 187 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. 188 * 189 * If MCLK is not used, we just set saif clk to 512*fs. 190 */ 191 ret = clk_prepare_enable(master_saif->clk); 192 if (ret) 193 return ret; 194 195 if (master_saif->mclk_in_use) { 196 switch (mclk / rate) { 197 case 32: 198 case 64: 199 case 128: 200 case 256: 201 case 512: 202 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 203 ret = clk_set_rate(master_saif->clk, 512 * rate); 204 break; 205 case 48: 206 case 96: 207 case 192: 208 case 384: 209 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 210 ret = clk_set_rate(master_saif->clk, 384 * rate); 211 break; 212 default: 213 /* SAIF MCLK should be a sub-rate of 512x or 384x */ 214 clk_disable_unprepare(master_saif->clk); 215 return -EINVAL; 216 } 217 } else { 218 ret = clk_set_rate(master_saif->clk, 512 * rate); 219 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 220 } 221 222 clk_disable_unprepare(master_saif->clk); 223 224 if (ret) 225 return ret; 226 227 master_saif->cur_rate = rate; 228 229 if (!master_saif->mclk_in_use) { 230 __raw_writel(scr, master_saif->base + SAIF_CTRL); 231 return 0; 232 } 233 234 /* 235 * Program the over-sample rate for MCLK output 236 * 237 * The available MCLK range is 32x, 48x... 512x. The rate 238 * could be from 8kHz to 192kH. 239 */ 240 switch (mclk / rate) { 241 case 32: 242 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 243 break; 244 case 64: 245 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 246 break; 247 case 128: 248 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 249 break; 250 case 256: 251 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 252 break; 253 case 512: 254 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 255 break; 256 case 48: 257 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 258 break; 259 case 96: 260 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 261 break; 262 case 192: 263 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 264 break; 265 case 384: 266 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 267 break; 268 default: 269 return -EINVAL; 270 } 271 272 __raw_writel(scr, master_saif->base + SAIF_CTRL); 273 274 return 0; 275 } 276 277 /* 278 * Put and disable MCLK. 279 */ 280 int mxs_saif_put_mclk(unsigned int saif_id) 281 { 282 struct mxs_saif *saif = mxs_saif[saif_id]; 283 u32 stat; 284 285 if (!saif) 286 return -EINVAL; 287 288 stat = __raw_readl(saif->base + SAIF_STAT); 289 if (stat & BM_SAIF_STAT_BUSY) { 290 dev_err(saif->dev, "error: busy\n"); 291 return -EBUSY; 292 } 293 294 clk_disable_unprepare(saif->clk); 295 296 /* disable MCLK output */ 297 __raw_writel(BM_SAIF_CTRL_CLKGATE, 298 saif->base + SAIF_CTRL + MXS_SET_ADDR); 299 __raw_writel(BM_SAIF_CTRL_RUN, 300 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 301 302 saif->mclk_in_use = 0; 303 return 0; 304 } 305 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 306 307 /* 308 * Get MCLK and set clock rate, then enable it 309 * 310 * This interface is used for codecs who are using MCLK provided 311 * by saif. 312 */ 313 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 314 unsigned int rate) 315 { 316 struct mxs_saif *saif = mxs_saif[saif_id]; 317 int ret; 318 319 if (!saif) 320 return -EINVAL; 321 322 ret = __mxs_saif_get_mclk(saif); 323 if (ret) 324 return ret; 325 326 ret = mxs_saif_set_clk(saif, mclk, rate); 327 if (ret) 328 return ret; 329 330 ret = clk_prepare_enable(saif->clk); 331 if (ret) 332 return ret; 333 334 /* enable MCLK output */ 335 __raw_writel(BM_SAIF_CTRL_RUN, 336 saif->base + SAIF_CTRL + MXS_SET_ADDR); 337 338 return 0; 339 } 340 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 341 342 /* 343 * SAIF DAI format configuration. 344 * Should only be called when port is inactive. 345 */ 346 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 347 { 348 u32 scr, stat; 349 u32 scr0; 350 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 351 352 stat = __raw_readl(saif->base + SAIF_STAT); 353 if (stat & BM_SAIF_STAT_BUSY) { 354 dev_err(cpu_dai->dev, "error: busy\n"); 355 return -EBUSY; 356 } 357 358 /* If SAIF1 is configured as slave, the clk gate needs to be cleared 359 * before the register can be written. 360 */ 361 if (saif->id != saif->master_id) { 362 __raw_writel(BM_SAIF_CTRL_SFTRST, 363 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 364 __raw_writel(BM_SAIF_CTRL_CLKGATE, 365 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 366 } 367 368 scr0 = __raw_readl(saif->base + SAIF_CTRL); 369 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 370 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 371 scr = 0; 372 373 /* DAI mode */ 374 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 375 case SND_SOC_DAIFMT_I2S: 376 /* data frame low 1clk before data */ 377 scr |= BM_SAIF_CTRL_DELAY; 378 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 379 break; 380 case SND_SOC_DAIFMT_LEFT_J: 381 /* data frame high with data */ 382 scr &= ~BM_SAIF_CTRL_DELAY; 383 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 384 scr &= ~BM_SAIF_CTRL_JUSTIFY; 385 break; 386 default: 387 return -EINVAL; 388 } 389 390 /* DAI clock inversion */ 391 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 392 case SND_SOC_DAIFMT_IB_IF: 393 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 394 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 395 break; 396 case SND_SOC_DAIFMT_IB_NF: 397 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 398 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 399 break; 400 case SND_SOC_DAIFMT_NB_IF: 401 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 402 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 403 break; 404 case SND_SOC_DAIFMT_NB_NF: 405 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 406 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 407 break; 408 } 409 410 /* 411 * Note: We simply just support master mode since SAIF TX can only 412 * work as master. 413 * Here the master is relative to codec side. 414 * Saif internally could be slave when working on EXTMASTER mode. 415 * We just hide this to machine driver. 416 */ 417 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 418 case SND_SOC_DAIFMT_BP_FP: 419 if (saif->id == saif->master_id) 420 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 421 else 422 scr |= BM_SAIF_CTRL_SLAVE_MODE; 423 424 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 425 break; 426 default: 427 return -EINVAL; 428 } 429 430 return 0; 431 } 432 433 static int mxs_saif_startup(struct snd_pcm_substream *substream, 434 struct snd_soc_dai *cpu_dai) 435 { 436 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 437 int ret; 438 439 /* clear error status to 0 for each re-open */ 440 saif->fifo_underrun = 0; 441 saif->fifo_overrun = 0; 442 443 /* Clear Reset for normal operations */ 444 __raw_writel(BM_SAIF_CTRL_SFTRST, 445 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 446 447 /* clear clock gate */ 448 __raw_writel(BM_SAIF_CTRL_CLKGATE, 449 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 450 451 ret = clk_prepare(saif->clk); 452 if (ret) 453 return ret; 454 455 return 0; 456 } 457 458 static void mxs_saif_shutdown(struct snd_pcm_substream *substream, 459 struct snd_soc_dai *cpu_dai) 460 { 461 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 462 463 clk_unprepare(saif->clk); 464 } 465 466 /* 467 * Should only be called when port is inactive. 468 * although can be called multiple times by upper layers. 469 */ 470 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 471 struct snd_pcm_hw_params *params, 472 struct snd_soc_dai *cpu_dai) 473 { 474 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 475 struct mxs_saif *master_saif; 476 u32 scr, stat; 477 int ret; 478 479 master_saif = mxs_saif_get_master(saif); 480 if (!master_saif) 481 return -EINVAL; 482 483 /* mclk should already be set */ 484 if (!saif->mclk && saif->mclk_in_use) { 485 dev_err(cpu_dai->dev, "set mclk first\n"); 486 return -EINVAL; 487 } 488 489 stat = __raw_readl(saif->base + SAIF_STAT); 490 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { 491 dev_err(cpu_dai->dev, "error: busy\n"); 492 return -EBUSY; 493 } 494 495 /* 496 * Set saif clk based on sample rate. 497 * If mclk is used, we also set mclk, if not, saif->mclk is 498 * default 0, means not used. 499 */ 500 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 501 if (ret) { 502 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 503 return ret; 504 } 505 506 if (saif != master_saif) { 507 /* 508 * Set an initial clock rate for the saif internal logic to work 509 * properly. This is important when working in EXTMASTER mode 510 * that uses the other saif's BITCLK&LRCLK but it still needs a 511 * basic clock which should be fast enough for the internal 512 * logic. 513 */ 514 ret = clk_enable(saif->clk); 515 if (ret) 516 return ret; 517 518 ret = clk_set_rate(saif->clk, 24000000); 519 clk_disable(saif->clk); 520 if (ret) 521 return ret; 522 523 ret = clk_prepare(master_saif->clk); 524 if (ret) 525 return ret; 526 } 527 528 scr = __raw_readl(saif->base + SAIF_CTRL); 529 530 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 531 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 532 switch (params_format(params)) { 533 case SNDRV_PCM_FORMAT_S16_LE: 534 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 535 break; 536 case SNDRV_PCM_FORMAT_S20_3LE: 537 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 538 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 539 break; 540 case SNDRV_PCM_FORMAT_S24_LE: 541 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 542 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 543 break; 544 default: 545 return -EINVAL; 546 } 547 548 /* Tx/Rx config */ 549 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 550 /* enable TX mode */ 551 scr &= ~BM_SAIF_CTRL_READ_MODE; 552 } else { 553 /* enable RX mode */ 554 scr |= BM_SAIF_CTRL_READ_MODE; 555 } 556 557 __raw_writel(scr, saif->base + SAIF_CTRL); 558 return 0; 559 } 560 561 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 562 struct snd_soc_dai *cpu_dai) 563 { 564 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 565 566 /* enable FIFO error irqs */ 567 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 568 saif->base + SAIF_CTRL + MXS_SET_ADDR); 569 570 return 0; 571 } 572 573 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 574 struct snd_soc_dai *cpu_dai) 575 { 576 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 577 struct mxs_saif *master_saif; 578 u32 delay; 579 int ret; 580 581 master_saif = mxs_saif_get_master(saif); 582 if (!master_saif) 583 return -EINVAL; 584 585 switch (cmd) { 586 case SNDRV_PCM_TRIGGER_START: 587 case SNDRV_PCM_TRIGGER_RESUME: 588 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 589 if (saif->state == MXS_SAIF_STATE_RUNNING) 590 return 0; 591 592 dev_dbg(cpu_dai->dev, "start\n"); 593 594 ret = clk_enable(master_saif->clk); 595 if (ret) { 596 dev_err(saif->dev, "Failed to enable master clock\n"); 597 return ret; 598 } 599 600 /* 601 * If the saif's master is not itself, we also need to enable 602 * itself clk for its internal basic logic to work. 603 */ 604 if (saif != master_saif) { 605 ret = clk_enable(saif->clk); 606 if (ret) { 607 dev_err(saif->dev, "Failed to enable master clock\n"); 608 clk_disable(master_saif->clk); 609 return ret; 610 } 611 612 __raw_writel(BM_SAIF_CTRL_RUN, 613 saif->base + SAIF_CTRL + MXS_SET_ADDR); 614 } 615 616 if (!master_saif->mclk_in_use) 617 __raw_writel(BM_SAIF_CTRL_RUN, 618 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 619 620 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 621 /* 622 * write data to saif data register to trigger 623 * the transfer. 624 * For 24-bit format the 32-bit FIFO register stores 625 * only one channel, so we need to write twice. 626 * This is also safe for the other non 24-bit formats. 627 */ 628 __raw_writel(0, saif->base + SAIF_DATA); 629 __raw_writel(0, saif->base + SAIF_DATA); 630 } else { 631 /* 632 * read data from saif data register to trigger 633 * the receive. 634 * For 24-bit format the 32-bit FIFO register stores 635 * only one channel, so we need to read twice. 636 * This is also safe for the other non 24-bit formats. 637 */ 638 __raw_readl(saif->base + SAIF_DATA); 639 __raw_readl(saif->base + SAIF_DATA); 640 } 641 642 master_saif->ongoing = 1; 643 saif->state = MXS_SAIF_STATE_RUNNING; 644 645 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 646 __raw_readl(saif->base + SAIF_CTRL), 647 __raw_readl(saif->base + SAIF_STAT)); 648 649 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 650 __raw_readl(master_saif->base + SAIF_CTRL), 651 __raw_readl(master_saif->base + SAIF_STAT)); 652 break; 653 case SNDRV_PCM_TRIGGER_SUSPEND: 654 case SNDRV_PCM_TRIGGER_STOP: 655 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 656 if (saif->state == MXS_SAIF_STATE_STOPPED) 657 return 0; 658 659 dev_dbg(cpu_dai->dev, "stop\n"); 660 661 /* wait a while for the current sample to complete */ 662 delay = USEC_PER_SEC / master_saif->cur_rate; 663 664 if (!master_saif->mclk_in_use) { 665 __raw_writel(BM_SAIF_CTRL_RUN, 666 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 667 udelay(delay); 668 } 669 clk_disable(master_saif->clk); 670 671 if (saif != master_saif) { 672 __raw_writel(BM_SAIF_CTRL_RUN, 673 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 674 udelay(delay); 675 clk_disable(saif->clk); 676 } 677 678 master_saif->ongoing = 0; 679 saif->state = MXS_SAIF_STATE_STOPPED; 680 681 break; 682 default: 683 return -EINVAL; 684 } 685 686 return 0; 687 } 688 689 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 690 #define MXS_SAIF_FORMATS \ 691 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 692 SNDRV_PCM_FMTBIT_S24_LE) 693 694 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 695 .startup = mxs_saif_startup, 696 .shutdown = mxs_saif_shutdown, 697 .trigger = mxs_saif_trigger, 698 .prepare = mxs_saif_prepare, 699 .hw_params = mxs_saif_hw_params, 700 .set_sysclk = mxs_saif_set_dai_sysclk, 701 .set_fmt = mxs_saif_set_dai_fmt, 702 }; 703 704 static struct snd_soc_dai_driver mxs_saif_dai = { 705 .name = "mxs-saif", 706 .playback = { 707 .channels_min = 2, 708 .channels_max = 2, 709 .rates = MXS_SAIF_RATES, 710 .formats = MXS_SAIF_FORMATS, 711 }, 712 .capture = { 713 .channels_min = 2, 714 .channels_max = 2, 715 .rates = MXS_SAIF_RATES, 716 .formats = MXS_SAIF_FORMATS, 717 }, 718 .ops = &mxs_saif_dai_ops, 719 }; 720 721 static const struct snd_soc_component_driver mxs_saif_component = { 722 .name = "mxs-saif", 723 .legacy_dai_naming = 1, 724 }; 725 726 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 727 { 728 struct mxs_saif *saif = dev_id; 729 unsigned int stat; 730 731 stat = __raw_readl(saif->base + SAIF_STAT); 732 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 733 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 734 return IRQ_NONE; 735 736 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 737 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 738 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 739 saif->base + SAIF_STAT + MXS_CLR_ADDR); 740 } 741 742 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 743 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 744 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 745 saif->base + SAIF_STAT + MXS_CLR_ADDR); 746 } 747 748 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 749 __raw_readl(saif->base + SAIF_CTRL), 750 __raw_readl(saif->base + SAIF_STAT)); 751 752 return IRQ_HANDLED; 753 } 754 755 static int mxs_saif_mclk_init(struct platform_device *pdev) 756 { 757 struct mxs_saif *saif = platform_get_drvdata(pdev); 758 struct device_node *np = pdev->dev.of_node; 759 struct clk *clk; 760 int ret; 761 762 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 763 __clk_get_name(saif->clk), 0, 764 saif->base + SAIF_CTRL, 765 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 766 0, NULL); 767 if (IS_ERR(clk)) { 768 ret = PTR_ERR(clk); 769 if (ret == -EEXIST) 770 return 0; 771 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 772 return PTR_ERR(clk); 773 } 774 775 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 776 if (ret) 777 return ret; 778 779 return 0; 780 } 781 782 static int mxs_saif_probe(struct platform_device *pdev) 783 { 784 struct device_node *np = pdev->dev.of_node; 785 struct mxs_saif *saif; 786 int irq, ret; 787 struct device_node *master; 788 789 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 790 if (!saif) 791 return -ENOMEM; 792 793 ret = of_alias_get_id(np, "saif"); 794 if (ret < 0) 795 return ret; 796 else 797 saif->id = ret; 798 799 if (saif->id >= ARRAY_SIZE(mxs_saif)) { 800 dev_err(&pdev->dev, "get wrong saif id\n"); 801 return -EINVAL; 802 } 803 804 /* 805 * If there is no "fsl,saif-master" phandle, it's a saif 806 * master. Otherwise, it's a slave and its phandle points 807 * to the master. 808 */ 809 master = of_parse_phandle(np, "fsl,saif-master", 0); 810 if (!master) { 811 saif->master_id = saif->id; 812 } else { 813 ret = of_alias_get_id(master, "saif"); 814 of_node_put(master); 815 if (ret < 0) 816 return ret; 817 else 818 saif->master_id = ret; 819 820 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 821 dev_err(&pdev->dev, "get wrong master id\n"); 822 return -EINVAL; 823 } 824 } 825 826 mxs_saif[saif->id] = saif; 827 828 saif->clk = devm_clk_get(&pdev->dev, NULL); 829 if (IS_ERR(saif->clk)) { 830 ret = PTR_ERR(saif->clk); 831 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 832 ret); 833 return ret; 834 } 835 836 saif->base = devm_platform_ioremap_resource(pdev, 0); 837 if (IS_ERR(saif->base)) 838 return PTR_ERR(saif->base); 839 840 irq = platform_get_irq(pdev, 0); 841 if (irq < 0) 842 return irq; 843 844 saif->dev = &pdev->dev; 845 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 846 dev_name(&pdev->dev), saif); 847 if (ret) { 848 dev_err(&pdev->dev, "failed to request irq\n"); 849 return ret; 850 } 851 852 platform_set_drvdata(pdev, saif); 853 854 /* We only support saif0 being tx and clock master */ 855 if (saif->id == 0) { 856 ret = mxs_saif_mclk_init(pdev); 857 if (ret) 858 dev_warn(&pdev->dev, "failed to init clocks\n"); 859 } 860 861 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 862 &mxs_saif_dai, 1); 863 if (ret) { 864 dev_err(&pdev->dev, "register DAI failed\n"); 865 return ret; 866 } 867 868 ret = mxs_pcm_platform_register(&pdev->dev); 869 if (ret) { 870 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 871 return ret; 872 } 873 874 return 0; 875 } 876 877 static const struct of_device_id mxs_saif_dt_ids[] = { 878 { .compatible = "fsl,imx28-saif", }, 879 { /* sentinel */ } 880 }; 881 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 882 883 static struct platform_driver mxs_saif_driver = { 884 .probe = mxs_saif_probe, 885 886 .driver = { 887 .name = "mxs-saif", 888 .of_match_table = mxs_saif_dt_ids, 889 }, 890 }; 891 892 module_platform_driver(mxs_saif_driver); 893 894 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 895 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 896 MODULE_LICENSE("GPL"); 897 MODULE_ALIAS("platform:mxs-saif"); 898