1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/m68k/mvme147/config.c
4 *
5 * Copyright (C) 1996 Dave Frascone [chaos@mindspring.com]
6 * Cloned from Richard Hirst [richard@sleepie.demon.co.uk]
7 *
8 * Based on:
9 *
10 * Copyright (C) 1993 Hamish Macdonald
11 */
12
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/mm.h>
16 #include <linux/tty.h>
17 #include <linux/clocksource.h>
18 #include <linux/console.h>
19 #include <linux/linkage.h>
20 #include <linux/init.h>
21 #include <linux/major.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/rtc/m48t59.h>
25
26 #include <asm/bootinfo.h>
27 #include <asm/bootinfo-vme.h>
28 #include <asm/byteorder.h>
29 #include <asm/setup.h>
30 #include <asm/irq.h>
31 #include <asm/traps.h>
32 #include <asm/machdep.h>
33 #include <asm/mvme147hw.h>
34 #include <asm/config.h>
35
36 #include "mvme147.h"
37
38 static void mvme147_get_model(char *model);
39 static void __init mvme147_sched_init(void);
40 extern void mvme147_reset (void);
41
42
mvme147_parse_bootinfo(const struct bi_record * bi)43 int __init mvme147_parse_bootinfo(const struct bi_record *bi)
44 {
45 uint16_t tag = be16_to_cpu(bi->tag);
46 if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO)
47 return 0;
48 else
49 return 1;
50 }
51
mvme147_reset(void)52 void mvme147_reset(void)
53 {
54 pr_info("\r\n\nCalled mvme147_reset\r\n");
55 m147_pcc->watchdog = 0x0a; /* Clear timer */
56 m147_pcc->watchdog = 0xa5; /* Enable watchdog - 100ms to reset */
57 while (1)
58 ;
59 }
60
mvme147_get_model(char * model)61 static void mvme147_get_model(char *model)
62 {
63 sprintf(model, "Motorola MVME147");
64 }
65
66 /*
67 * This function is called during kernel startup to initialize
68 * the mvme147 IRQ handling routines.
69 */
70
mvme147_init_IRQ(void)71 static void __init mvme147_init_IRQ(void)
72 {
73 m68k_setup_user_interrupt(VEC_USER, 192);
74 }
75
config_mvme147(void)76 void __init config_mvme147(void)
77 {
78 mach_sched_init = mvme147_sched_init;
79 mach_init_IRQ = mvme147_init_IRQ;
80 mach_reset = mvme147_reset;
81 mach_get_model = mvme147_get_model;
82
83 /* Board type is only set by newer versions of vmelilo/tftplilo */
84 if (!vme_brdtype)
85 vme_brdtype = VME_TYPE_MVME147;
86 }
87
88 static struct resource m48t59_rsrc[] = {
89 DEFINE_RES_MEM(MVME147_RTC_BASE, 0x800),
90 };
91
92 static struct m48t59_plat_data m48t59_data = {
93 .type = M48T59RTC_TYPE_M48T02,
94 .yy_offset = 70,
95 };
96
mvme147_platform_init(void)97 static int __init mvme147_platform_init(void)
98 {
99 if (!MACH_IS_MVME147)
100 return 0;
101
102 platform_device_register_resndata(NULL, "rtc-m48t59", -1,
103 m48t59_rsrc, ARRAY_SIZE(m48t59_rsrc),
104 &m48t59_data, sizeof(m48t59_data));
105 return 0;
106 }
107
108 arch_initcall(mvme147_platform_init);
109
110 static u64 mvme147_read_clk(struct clocksource *cs);
111
112 static struct clocksource mvme147_clk = {
113 .name = "pcc",
114 .rating = 250,
115 .read = mvme147_read_clk,
116 .mask = CLOCKSOURCE_MASK(32),
117 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
118 };
119
120 static u32 clk_total;
121
122 #define PCC_TIMER_CLOCK_FREQ 160000
123 #define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ)
124 #define PCC_TIMER_PRELOAD (0x10000 - PCC_TIMER_CYCLES)
125
126 /* Using pcc tick timer 1 */
127
mvme147_timer_int(int irq,void * dev_id)128 static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
129 {
130 unsigned long flags;
131
132 local_irq_save(flags);
133 m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
134 PCC_TIMER_TIC_EN;
135 m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
136 PCC_LEVEL_TIMER1;
137 clk_total += PCC_TIMER_CYCLES;
138 legacy_timer_tick(1);
139 local_irq_restore(flags);
140
141 return IRQ_HANDLED;
142 }
143
144
mvme147_sched_init(void)145 static void __init mvme147_sched_init(void)
146 {
147 if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQF_TIMER,
148 "timer 1", NULL))
149 pr_err("Couldn't register timer interrupt\n");
150
151 /* Init the clock with a value */
152 /* The clock counter increments until 0xFFFF then reloads */
153 m147_pcc->t1_preload = PCC_TIMER_PRELOAD;
154 m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
155 PCC_TIMER_TIC_EN;
156 m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
157 PCC_LEVEL_TIMER1;
158
159 clocksource_register_hz(&mvme147_clk, PCC_TIMER_CLOCK_FREQ);
160 }
161
mvme147_read_clk(struct clocksource * cs)162 static u64 mvme147_read_clk(struct clocksource *cs)
163 {
164 unsigned long flags;
165 u8 overflow, tmp;
166 u16 count;
167 u32 ticks;
168
169 local_irq_save(flags);
170 tmp = m147_pcc->t1_cntrl >> 4;
171 count = m147_pcc->t1_count;
172 overflow = m147_pcc->t1_cntrl >> 4;
173 if (overflow != tmp)
174 count = m147_pcc->t1_count;
175 count -= PCC_TIMER_PRELOAD;
176 ticks = count + overflow * PCC_TIMER_CYCLES;
177 ticks += clk_total;
178 local_irq_restore(flags);
179
180 return ticks;
181 }
182
scc_delay(void)183 static void scc_delay(void)
184 {
185 __asm__ __volatile__ ("nop; nop;");
186 }
187
scc_write(char ch)188 static void scc_write(char ch)
189 {
190 do {
191 scc_delay();
192 } while (!(in_8(M147_SCC_A_ADDR) & BIT(2)));
193 scc_delay();
194 out_8(M147_SCC_A_ADDR, 8);
195 scc_delay();
196 out_8(M147_SCC_A_ADDR, ch);
197 }
198
mvme147_scc_write(struct console * co,const char * str,unsigned int count)199 void mvme147_scc_write(struct console *co, const char *str, unsigned int count)
200 {
201 unsigned long flags;
202
203 local_irq_save(flags);
204 while (count--) {
205 if (*str == '\n')
206 scc_write('\r');
207 scc_write(*str++);
208 }
209 local_irq_restore(flags);
210 }
211