1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6
7 struct pcie_tlp_log;
8
9 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
10 #define MAX_NR_DEVFNS 256
11
12 #define MAX_NR_LANES 16
13
14 #define PCI_FIND_CAP_TTL 48
15
16 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
17
18 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
19
20 /*
21 * Power stable to PERST# inactive.
22 *
23 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
24 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
25 * "T_PVPERL".
26 */
27 #define PCIE_T_PVPERL_MS 100
28
29 /*
30 * REFCLK stable before PERST# inactive.
31 *
32 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
33 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
34 * "T_PERST-CLK".
35 */
36 #define PCIE_T_PERST_CLK_US 100
37
38 /*
39 * End of conventional reset (PERST# de-asserted) to first configuration
40 * request (device able to respond with a "Request Retry Status" completion),
41 * from PCIe r6.0, sec 6.6.1.
42 */
43 #define PCIE_T_RRS_READY_MS 100
44
45 /*
46 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
47 * Recommends 1ms to 10ms timeout to check L2 ready.
48 */
49 #define PCIE_PME_TO_L2_TIMEOUT_US 10000
50
51 /*
52 * PCIe r6.0, sec 6.6.1 <Conventional Reset>
53 *
54 * - "With a Downstream Port that does not support Link speeds greater
55 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
56 * from a Conventional Reset before sending a Configuration Request to
57 * the device immediately below that Port."
58 *
59 * - "With a Downstream Port that supports Link speeds greater than
60 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
61 * completes before sending a Configuration Request to the device
62 * immediately below that Port."
63 */
64 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100
65
66 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
67 #define PCIE_MSG_TYPE_R_RC 0
68 #define PCIE_MSG_TYPE_R_ADDR 1
69 #define PCIE_MSG_TYPE_R_ID 2
70 #define PCIE_MSG_TYPE_R_BC 3
71 #define PCIE_MSG_TYPE_R_LOCAL 4
72 #define PCIE_MSG_TYPE_R_GATHER 5
73
74 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */
75 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19
76
77 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */
78 #define PCIE_MSG_CODE_ASSERT_INTA 0x20
79 #define PCIE_MSG_CODE_ASSERT_INTB 0x21
80 #define PCIE_MSG_CODE_ASSERT_INTC 0x22
81 #define PCIE_MSG_CODE_ASSERT_INTD 0x23
82 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24
83 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25
84 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26
85 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27
86
87 extern const unsigned char pcie_link_speed[];
88 extern bool pci_early_dump;
89
90 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
91 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
92 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
93
94 /* Functions internal to the PCI core code */
95
96 #ifdef CONFIG_DMI
97 extern const struct attribute_group pci_dev_smbios_attr_group;
98 #endif
99
100 enum pci_mmap_api {
101 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
102 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
103 };
104 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
105 enum pci_mmap_api mmap_api);
106
107 bool pci_reset_supported(struct pci_dev *dev);
108 void pci_init_reset_methods(struct pci_dev *dev);
109 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
110 int pci_bus_error_reset(struct pci_dev *dev);
111 int __pci_reset_bus(struct pci_bus *bus);
112
113 struct pci_cap_saved_data {
114 u16 cap_nr;
115 bool cap_extended;
116 unsigned int size;
117 u32 data[];
118 };
119
120 struct pci_cap_saved_state {
121 struct hlist_node next;
122 struct pci_cap_saved_data cap;
123 };
124
125 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
126 void pci_free_cap_save_buffers(struct pci_dev *dev);
127 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
128 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
129 u16 cap, unsigned int size);
130 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
131 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
132 u16 cap);
133
134 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
135 #define PCI_PM_D3HOT_WAIT 10 /* msec */
136 #define PCI_PM_D3COLD_WAIT 100 /* msec */
137
138 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
139 void pci_refresh_power_state(struct pci_dev *dev);
140 int pci_power_up(struct pci_dev *dev);
141 void pci_disable_enabled_device(struct pci_dev *dev);
142 int pci_finish_runtime_suspend(struct pci_dev *dev);
143 void pcie_clear_device_status(struct pci_dev *dev);
144 void pcie_clear_root_pme_status(struct pci_dev *dev);
145 bool pci_check_pme_status(struct pci_dev *dev);
146 void pci_pme_wakeup_bus(struct pci_bus *bus);
147 void pci_pme_restore(struct pci_dev *dev);
148 bool pci_dev_need_resume(struct pci_dev *dev);
149 void pci_dev_adjust_pme(struct pci_dev *dev);
150 void pci_dev_complete_resume(struct pci_dev *pci_dev);
151 void pci_config_pm_runtime_get(struct pci_dev *dev);
152 void pci_config_pm_runtime_put(struct pci_dev *dev);
153 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev);
154 void pci_pm_init(struct pci_dev *dev);
155 void pci_ea_init(struct pci_dev *dev);
156 void pci_msi_init(struct pci_dev *dev);
157 void pci_msix_init(struct pci_dev *dev);
158 bool pci_bridge_d3_possible(struct pci_dev *dev);
159 void pci_bridge_d3_update(struct pci_dev *dev);
160 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
161
pci_bus_rrs_vendor_id(u32 l)162 static inline bool pci_bus_rrs_vendor_id(u32 l)
163 {
164 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
165 }
166
pci_wakeup_event(struct pci_dev * dev)167 static inline void pci_wakeup_event(struct pci_dev *dev)
168 {
169 /* Wait 100 ms before the system can be put into a sleep state. */
170 pm_wakeup_event(&dev->dev, 100);
171 }
172
173 /**
174 * pci_bar_index_is_valid - Check whether a BAR index is within valid range
175 * @bar: BAR index
176 *
177 * Protects against overflowing &struct pci_dev.resource array.
178 *
179 * Return: true for valid index, false otherwise.
180 */
pci_bar_index_is_valid(int bar)181 static inline bool pci_bar_index_is_valid(int bar)
182 {
183 if (bar >= 0 && bar < PCI_NUM_RESOURCES)
184 return true;
185
186 return false;
187 }
188
pci_has_subordinate(struct pci_dev * pci_dev)189 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
190 {
191 return !!(pci_dev->subordinate);
192 }
193
pci_power_manageable(struct pci_dev * pci_dev)194 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
195 {
196 /*
197 * Currently we allow normal PCI devices and PCI bridges transition
198 * into D3 if their bridge_d3 is set.
199 */
200 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
201 }
202
pcie_downstream_port(const struct pci_dev * dev)203 static inline bool pcie_downstream_port(const struct pci_dev *dev)
204 {
205 int type = pci_pcie_type(dev);
206
207 return type == PCI_EXP_TYPE_ROOT_PORT ||
208 type == PCI_EXP_TYPE_DOWNSTREAM ||
209 type == PCI_EXP_TYPE_PCIE_BRIDGE;
210 }
211
212 void pci_vpd_init(struct pci_dev *dev);
213 extern const struct attribute_group pci_dev_vpd_attr_group;
214
215 /* PCI Virtual Channel */
216 int pci_save_vc_state(struct pci_dev *dev);
217 void pci_restore_vc_state(struct pci_dev *dev);
218 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
219
220 /* PCI /proc functions */
221 #ifdef CONFIG_PROC_FS
222 int pci_proc_attach_device(struct pci_dev *dev);
223 int pci_proc_detach_device(struct pci_dev *dev);
224 int pci_proc_detach_bus(struct pci_bus *bus);
225 #else
pci_proc_attach_device(struct pci_dev * dev)226 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)227 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)228 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
229 #endif
230
231 /* Functions for PCI Hotplug drivers to use */
232 int pci_hp_add_bridge(struct pci_dev *dev);
233 bool pci_hp_spurious_link_change(struct pci_dev *pdev);
234
235 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
236 void pci_create_legacy_files(struct pci_bus *bus);
237 void pci_remove_legacy_files(struct pci_bus *bus);
238 #else
pci_create_legacy_files(struct pci_bus * bus)239 static inline void pci_create_legacy_files(struct pci_bus *bus) { }
pci_remove_legacy_files(struct pci_bus * bus)240 static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
241 #endif
242
243 /* Lock for read/write access to pci device and bus lists */
244 extern struct rw_semaphore pci_bus_sem;
245 extern struct mutex pci_slot_mutex;
246
247 extern raw_spinlock_t pci_lock;
248
249 extern unsigned int pci_pm_d3hot_delay;
250
251 #ifdef CONFIG_PCI_MSI
252 void pci_no_msi(void);
253 #else
pci_no_msi(void)254 static inline void pci_no_msi(void) { }
255 #endif
256
257 void pci_realloc_get_opt(char *);
258
pci_no_d1d2(struct pci_dev * dev)259 static inline int pci_no_d1d2(struct pci_dev *dev)
260 {
261 unsigned int parent_dstates = 0;
262
263 if (dev->bus->self)
264 parent_dstates = dev->bus->self->no_d1d2;
265 return (dev->no_d1d2 || parent_dstates);
266
267 }
268
269 #ifdef CONFIG_SYSFS
270 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
271 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
272 extern const struct attribute_group *pci_dev_groups[];
273 extern const struct attribute_group *pci_dev_attr_groups[];
274 extern const struct attribute_group *pcibus_groups[];
275 extern const struct attribute_group *pci_bus_groups[];
276 extern const struct attribute_group pci_doe_sysfs_group;
277 #else
pci_create_sysfs_dev_files(struct pci_dev * pdev)278 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
pci_remove_sysfs_dev_files(struct pci_dev * pdev)279 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
280 #define pci_dev_groups NULL
281 #define pci_dev_attr_groups NULL
282 #define pcibus_groups NULL
283 #define pci_bus_groups NULL
284 #endif
285
286 extern unsigned long pci_hotplug_io_size;
287 extern unsigned long pci_hotplug_mmio_size;
288 extern unsigned long pci_hotplug_mmio_pref_size;
289 extern unsigned long pci_hotplug_bus_size;
290 extern unsigned long pci_cardbus_io_size;
291 extern unsigned long pci_cardbus_mem_size;
292
293 /**
294 * pci_match_one_device - Tell if a PCI device structure has a matching
295 * PCI device id structure
296 * @id: single PCI device id structure to match
297 * @dev: the PCI device structure to match against
298 *
299 * Returns the matching pci_device_id structure or %NULL if there is no match.
300 */
301 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)302 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
303 {
304 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
305 (id->device == PCI_ANY_ID || id->device == dev->device) &&
306 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
307 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
308 !((id->class ^ dev->class) & id->class_mask))
309 return id;
310 return NULL;
311 }
312
313 /* PCI slot sysfs helper code */
314 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
315
316 extern struct kset *pci_slots_kset;
317
318 struct pci_slot_attribute {
319 struct attribute attr;
320 ssize_t (*show)(struct pci_slot *, char *);
321 ssize_t (*store)(struct pci_slot *, const char *, size_t);
322 };
323 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
324
325 enum pci_bar_type {
326 pci_bar_unknown, /* Standard PCI BAR probe */
327 pci_bar_io, /* An I/O port BAR */
328 pci_bar_mem32, /* A 32-bit memory BAR */
329 pci_bar_mem64, /* A 64-bit memory BAR */
330 };
331
332 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
333 void pci_put_host_bridge_device(struct device *dev);
334
335 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
336 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
337 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
338
339 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
340 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
341 int rrs_timeout);
342 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
343 int rrs_timeout);
344 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
345
346 int pci_setup_device(struct pci_dev *dev);
347 void __pci_size_stdbars(struct pci_dev *dev, int count,
348 unsigned int pos, u32 *sizes);
349 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
350 struct resource *res, unsigned int reg, u32 *sizes);
351 void pci_configure_ari(struct pci_dev *dev);
352 void __pci_bus_size_bridges(struct pci_bus *bus,
353 struct list_head *realloc_head);
354 void __pci_bus_assign_resources(const struct pci_bus *bus,
355 struct list_head *realloc_head,
356 struct list_head *fail_head);
357 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
358 void pci_walk_bus_locked(struct pci_bus *top,
359 int (*cb)(struct pci_dev *, void *),
360 void *userdata);
361
362 const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
363 bool pci_resource_is_optional(const struct pci_dev *dev, int resno);
364
365 /**
366 * pci_resource_num - Reverse lookup resource number from device resources
367 * @dev: PCI device
368 * @res: Resource to lookup index for (MUST be a @dev's resource)
369 *
370 * Perform reverse lookup to determine the resource number for @res within
371 * @dev resource array. NOTE: The caller is responsible for ensuring @res is
372 * among @dev's resources!
373 *
374 * Returns: resource number.
375 */
pci_resource_num(const struct pci_dev * dev,const struct resource * res)376 static inline int pci_resource_num(const struct pci_dev *dev,
377 const struct resource *res)
378 {
379 int resno = res - &dev->resource[0];
380
381 /* Passing a resource that is not among dev's resources? */
382 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES);
383
384 return resno;
385 }
386
387 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
388 void pci_disable_bridge_window(struct pci_dev *dev);
389 struct pci_bus *pci_bus_get(struct pci_bus *bus);
390 void pci_bus_put(struct pci_bus *bus);
391
392 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
393 ({ \
394 ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
395 (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
396 (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
397 (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
398 (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
399 (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
400 PCI_SPEED_UNKNOWN); \
401 })
402
403 /* PCIe link information from Link Capabilities 2 */
404 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
405 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
406 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
407 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
408 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
409 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
410 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
411 PCI_SPEED_UNKNOWN)
412
413 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
414 ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
415 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
416 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
417 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
418 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
419 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
420 PCI_SPEED_UNKNOWN)
421
422 /* PCIe speed to Mb/s reduced by encoding overhead */
423 #define PCIE_SPEED2MBS_ENC(speed) \
424 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
425 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
426 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
427 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
428 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
429 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
430 0)
431
pcie_dev_speed_mbps(enum pci_bus_speed speed)432 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
433 {
434 switch (speed) {
435 case PCIE_SPEED_2_5GT:
436 return 2500;
437 case PCIE_SPEED_5_0GT:
438 return 5000;
439 case PCIE_SPEED_8_0GT:
440 return 8000;
441 case PCIE_SPEED_16_0GT:
442 return 16000;
443 case PCIE_SPEED_32_0GT:
444 return 32000;
445 case PCIE_SPEED_64_0GT:
446 return 64000;
447 default:
448 break;
449 }
450
451 return -EINVAL;
452 }
453
454 u8 pcie_get_supported_speeds(struct pci_dev *dev);
455 const char *pci_speed_string(enum pci_bus_speed speed);
456 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
457 void pcie_report_downtraining(struct pci_dev *dev);
458
__pcie_update_link_speed(struct pci_bus * bus,u16 linksta,u16 linksta2)459 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2)
460 {
461 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
462 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0;
463 }
464 void pcie_update_link_speed(struct pci_bus *bus);
465
466 /* Single Root I/O Virtualization */
467 struct pci_sriov {
468 int pos; /* Capability position */
469 int nres; /* Number of resources */
470 u32 cap; /* SR-IOV Capabilities */
471 u16 ctrl; /* SR-IOV Control */
472 u16 total_VFs; /* Total VFs associated with the PF */
473 u16 initial_VFs; /* Initial VFs associated with the PF */
474 u16 num_VFs; /* Number of VFs available */
475 u16 offset; /* First VF Routing ID offset */
476 u16 stride; /* Following VF stride */
477 u16 vf_device; /* VF device ID */
478 u32 pgsz; /* Page size for BAR alignment */
479 u8 link; /* Function Dependency Link */
480 u8 max_VF_buses; /* Max buses consumed by VFs */
481 u16 driver_max_VFs; /* Max num VFs driver supports */
482 struct pci_dev *dev; /* Lowest numbered PF */
483 struct pci_dev *self; /* This PF */
484 u32 class; /* VF device */
485 u8 hdr_type; /* VF header type */
486 u16 subsystem_vendor; /* VF subsystem vendor */
487 u16 subsystem_device; /* VF subsystem device */
488 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
489 bool drivers_autoprobe; /* Auto probing of VFs by driver */
490 };
491
492 #ifdef CONFIG_PCI_DOE
493 void pci_doe_init(struct pci_dev *pdev);
494 void pci_doe_destroy(struct pci_dev *pdev);
495 void pci_doe_disconnected(struct pci_dev *pdev);
496 #else
pci_doe_init(struct pci_dev * pdev)497 static inline void pci_doe_init(struct pci_dev *pdev) { }
pci_doe_destroy(struct pci_dev * pdev)498 static inline void pci_doe_destroy(struct pci_dev *pdev) { }
pci_doe_disconnected(struct pci_dev * pdev)499 static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
500 #endif
501
502 #ifdef CONFIG_PCI_NPEM
503 void pci_npem_create(struct pci_dev *dev);
504 void pci_npem_remove(struct pci_dev *dev);
505 #else
pci_npem_create(struct pci_dev * dev)506 static inline void pci_npem_create(struct pci_dev *dev) { }
pci_npem_remove(struct pci_dev * dev)507 static inline void pci_npem_remove(struct pci_dev *dev) { }
508 #endif
509
510 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS)
511 void pci_doe_sysfs_init(struct pci_dev *pci_dev);
512 void pci_doe_sysfs_teardown(struct pci_dev *pdev);
513 #else
pci_doe_sysfs_init(struct pci_dev * pdev)514 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { }
pci_doe_sysfs_teardown(struct pci_dev * pdev)515 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { }
516 #endif
517
518 /**
519 * pci_dev_set_io_state - Set the new error state if possible.
520 *
521 * @dev: PCI device to set new error_state
522 * @new: the state we want dev to be in
523 *
524 * If the device is experiencing perm_failure, it has to remain in that state.
525 * Any other transition is allowed.
526 *
527 * Returns true if state has been changed to the requested state.
528 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)529 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
530 pci_channel_state_t new)
531 {
532 pci_channel_state_t old;
533
534 switch (new) {
535 case pci_channel_io_perm_failure:
536 xchg(&dev->error_state, pci_channel_io_perm_failure);
537 return true;
538 case pci_channel_io_frozen:
539 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
540 pci_channel_io_frozen);
541 return old != pci_channel_io_perm_failure;
542 case pci_channel_io_normal:
543 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
544 pci_channel_io_normal);
545 return old != pci_channel_io_perm_failure;
546 default:
547 return false;
548 }
549 }
550
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)551 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
552 {
553 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
554 pci_doe_disconnected(dev);
555
556 return 0;
557 }
558
559 /* pci_dev priv_flags */
560 #define PCI_DEV_ADDED 0
561 #define PCI_DPC_RECOVERED 1
562 #define PCI_DPC_RECOVERING 2
563 #define PCI_DEV_REMOVED 3
564 #define PCI_LINK_CHANGED 4
565 #define PCI_LINK_CHANGING 5
566 #define PCI_LINK_LBMS_SEEN 6
567 #define PCI_DEV_ALLOW_BINDING 7
568
pci_dev_assign_added(struct pci_dev * dev)569 static inline void pci_dev_assign_added(struct pci_dev *dev)
570 {
571 smp_mb__before_atomic();
572 set_bit(PCI_DEV_ADDED, &dev->priv_flags);
573 smp_mb__after_atomic();
574 }
575
pci_dev_test_and_clear_added(struct pci_dev * dev)576 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev)
577 {
578 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags);
579 }
580
pci_dev_is_added(const struct pci_dev * dev)581 static inline bool pci_dev_is_added(const struct pci_dev *dev)
582 {
583 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
584 }
585
pci_dev_test_and_set_removed(struct pci_dev * dev)586 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev)
587 {
588 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags);
589 }
590
pci_dev_allow_binding(struct pci_dev * dev)591 static inline void pci_dev_allow_binding(struct pci_dev *dev)
592 {
593 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags);
594 }
595
pci_dev_binding_disallowed(struct pci_dev * dev)596 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev)
597 {
598 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags);
599 }
600
601 #ifdef CONFIG_PCIEAER
602 #include <linux/aer.h>
603
604 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
605
606 struct aer_err_info {
607 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
608 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES];
609 int error_dev_num;
610 const char *level; /* printk level */
611
612 unsigned int id:16;
613
614 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
615 unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */
616 unsigned int __pad1:4;
617 unsigned int multi_error_valid:1;
618
619 unsigned int first_error:5;
620 unsigned int __pad2:2;
621 unsigned int tlp_header_valid:1;
622
623 unsigned int status; /* COR/UNCOR Error Status */
624 unsigned int mask; /* COR/UNCOR Error Mask */
625 struct pcie_tlp_log tlp; /* TLP Header */
626 };
627
628 int aer_get_device_error_info(struct aer_err_info *info, int i);
629 void aer_print_error(struct aer_err_info *info, int i);
630
631 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2,
632 unsigned int tlp_len, bool flit,
633 struct pcie_tlp_log *log);
634 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc);
635 void pcie_print_tlp_log(const struct pci_dev *dev,
636 const struct pcie_tlp_log *log, const char *level,
637 const char *pfx);
638 #endif /* CONFIG_PCIEAER */
639
640 #ifdef CONFIG_PCIEPORTBUS
641 /* Cached RCEC Endpoint Association */
642 struct rcec_ea {
643 u8 nextbusn;
644 u8 lastbusn;
645 u32 bitmap;
646 };
647 #endif
648
649 #ifdef CONFIG_PCIE_DPC
650 void pci_save_dpc_state(struct pci_dev *dev);
651 void pci_restore_dpc_state(struct pci_dev *dev);
652 void pci_dpc_init(struct pci_dev *pdev);
653 void dpc_process_error(struct pci_dev *pdev);
654 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
655 bool pci_dpc_recovered(struct pci_dev *pdev);
656 unsigned int dpc_tlp_log_len(struct pci_dev *dev);
657 #else
pci_save_dpc_state(struct pci_dev * dev)658 static inline void pci_save_dpc_state(struct pci_dev *dev) { }
pci_restore_dpc_state(struct pci_dev * dev)659 static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
pci_dpc_init(struct pci_dev * pdev)660 static inline void pci_dpc_init(struct pci_dev *pdev) { }
pci_dpc_recovered(struct pci_dev * pdev)661 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
662 #endif
663
664 #ifdef CONFIG_PCIEPORTBUS
665 void pci_rcec_init(struct pci_dev *dev);
666 void pci_rcec_exit(struct pci_dev *dev);
667 void pcie_link_rcec(struct pci_dev *rcec);
668 void pcie_walk_rcec(struct pci_dev *rcec,
669 int (*cb)(struct pci_dev *, void *),
670 void *userdata);
671 #else
pci_rcec_init(struct pci_dev * dev)672 static inline void pci_rcec_init(struct pci_dev *dev) { }
pci_rcec_exit(struct pci_dev * dev)673 static inline void pci_rcec_exit(struct pci_dev *dev) { }
pcie_link_rcec(struct pci_dev * rcec)674 static inline void pcie_link_rcec(struct pci_dev *rcec) { }
pcie_walk_rcec(struct pci_dev * rcec,int (* cb)(struct pci_dev *,void *),void * userdata)675 static inline void pcie_walk_rcec(struct pci_dev *rcec,
676 int (*cb)(struct pci_dev *, void *),
677 void *userdata) { }
678 #endif
679
680 #ifdef CONFIG_PCI_ATS
681 /* Address Translation Service */
682 void pci_ats_init(struct pci_dev *dev);
683 void pci_restore_ats_state(struct pci_dev *dev);
684 #else
pci_ats_init(struct pci_dev * d)685 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)686 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
687 #endif /* CONFIG_PCI_ATS */
688
689 #ifdef CONFIG_PCI_PRI
690 void pci_pri_init(struct pci_dev *dev);
691 void pci_restore_pri_state(struct pci_dev *pdev);
692 #else
pci_pri_init(struct pci_dev * dev)693 static inline void pci_pri_init(struct pci_dev *dev) { }
pci_restore_pri_state(struct pci_dev * pdev)694 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
695 #endif
696
697 #ifdef CONFIG_PCI_PASID
698 void pci_pasid_init(struct pci_dev *dev);
699 void pci_restore_pasid_state(struct pci_dev *pdev);
700 #else
pci_pasid_init(struct pci_dev * dev)701 static inline void pci_pasid_init(struct pci_dev *dev) { }
pci_restore_pasid_state(struct pci_dev * pdev)702 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
703 #endif
704
705 #ifdef CONFIG_PCI_IOV
706 int pci_iov_init(struct pci_dev *dev);
707 void pci_iov_release(struct pci_dev *dev);
708 void pci_iov_remove(struct pci_dev *dev);
709 void pci_iov_update_resource(struct pci_dev *dev, int resno);
710 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
711 void pci_restore_iov_state(struct pci_dev *dev);
712 int pci_iov_bus_range(struct pci_bus *bus);
pci_resource_is_iov(int resno)713 static inline bool pci_resource_is_iov(int resno)
714 {
715 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END;
716 }
717 extern const struct attribute_group sriov_pf_dev_attr_group;
718 extern const struct attribute_group sriov_vf_dev_attr_group;
719 #else
pci_iov_init(struct pci_dev * dev)720 static inline int pci_iov_init(struct pci_dev *dev)
721 {
722 return -ENODEV;
723 }
pci_iov_release(struct pci_dev * dev)724 static inline void pci_iov_release(struct pci_dev *dev) { }
pci_iov_remove(struct pci_dev * dev)725 static inline void pci_iov_remove(struct pci_dev *dev) { }
pci_iov_update_resource(struct pci_dev * dev,int resno)726 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { }
pci_sriov_resource_alignment(struct pci_dev * dev,int resno)727 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
728 int resno)
729 {
730 return 0;
731 }
pci_restore_iov_state(struct pci_dev * dev)732 static inline void pci_restore_iov_state(struct pci_dev *dev) { }
pci_iov_bus_range(struct pci_bus * bus)733 static inline int pci_iov_bus_range(struct pci_bus *bus)
734 {
735 return 0;
736 }
pci_resource_is_iov(int resno)737 static inline bool pci_resource_is_iov(int resno)
738 {
739 return false;
740 }
741 #endif /* CONFIG_PCI_IOV */
742
743 #ifdef CONFIG_PCIE_TPH
744 void pci_restore_tph_state(struct pci_dev *dev);
745 void pci_save_tph_state(struct pci_dev *dev);
746 void pci_no_tph(void);
747 void pci_tph_init(struct pci_dev *dev);
748 #else
pci_restore_tph_state(struct pci_dev * dev)749 static inline void pci_restore_tph_state(struct pci_dev *dev) { }
pci_save_tph_state(struct pci_dev * dev)750 static inline void pci_save_tph_state(struct pci_dev *dev) { }
pci_no_tph(void)751 static inline void pci_no_tph(void) { }
pci_tph_init(struct pci_dev * dev)752 static inline void pci_tph_init(struct pci_dev *dev) { }
753 #endif
754
755 #ifdef CONFIG_PCIE_PTM
756 void pci_ptm_init(struct pci_dev *dev);
757 void pci_save_ptm_state(struct pci_dev *dev);
758 void pci_restore_ptm_state(struct pci_dev *dev);
759 void pci_suspend_ptm(struct pci_dev *dev);
760 void pci_resume_ptm(struct pci_dev *dev);
761 #else
pci_ptm_init(struct pci_dev * dev)762 static inline void pci_ptm_init(struct pci_dev *dev) { }
pci_save_ptm_state(struct pci_dev * dev)763 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
pci_restore_ptm_state(struct pci_dev * dev)764 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
pci_suspend_ptm(struct pci_dev * dev)765 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
pci_resume_ptm(struct pci_dev * dev)766 static inline void pci_resume_ptm(struct pci_dev *dev) { }
767 #endif
768
769 unsigned long pci_cardbus_resource_alignment(struct resource *);
770
pci_resource_alignment(struct pci_dev * dev,struct resource * res)771 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
772 struct resource *res)
773 {
774 int resno = pci_resource_num(dev, res);
775
776 if (pci_resource_is_iov(resno))
777 return pci_sriov_resource_alignment(dev, resno);
778 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
779 return pci_cardbus_resource_alignment(res);
780 return resource_alignment(res);
781 }
782
783 void pci_acs_init(struct pci_dev *dev);
784 #ifdef CONFIG_PCI_QUIRKS
785 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
786 int pci_dev_specific_enable_acs(struct pci_dev *dev);
787 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
788 int pcie_failed_link_retrain(struct pci_dev *dev);
789 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)790 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
791 u16 acs_flags)
792 {
793 return -ENOTTY;
794 }
pci_dev_specific_enable_acs(struct pci_dev * dev)795 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
796 {
797 return -ENOTTY;
798 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)799 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
800 {
801 return -ENOTTY;
802 }
pcie_failed_link_retrain(struct pci_dev * dev)803 static inline int pcie_failed_link_retrain(struct pci_dev *dev)
804 {
805 return -ENOTTY;
806 }
807 #endif
808
809 /* PCI error reporting and recovery */
810 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
811 pci_channel_state_t state,
812 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
813
814 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
815 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
816
817 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */
818 void pci_save_ltr_state(struct pci_dev *dev);
819 void pci_restore_ltr_state(struct pci_dev *dev);
820 void pci_configure_aspm_l1ss(struct pci_dev *dev);
821 void pci_save_aspm_l1ss_state(struct pci_dev *dev);
822 void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
823
824 #ifdef CONFIG_PCIEASPM
825 void pcie_aspm_init_link_state(struct pci_dev *pdev);
826 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
827 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
828 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
829 void pci_configure_ltr(struct pci_dev *pdev);
830 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
831 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)832 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)833 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev,bool locked)834 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)835 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
pci_configure_ltr(struct pci_dev * pdev)836 static inline void pci_configure_ltr(struct pci_dev *pdev) { }
pci_bridge_reconfigure_ltr(struct pci_dev * pdev)837 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
838 #endif
839
840 #ifdef CONFIG_PCIE_ECRC
841 void pcie_set_ecrc_checking(struct pci_dev *dev);
842 void pcie_ecrc_get_policy(char *str);
843 #else
pcie_set_ecrc_checking(struct pci_dev * dev)844 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)845 static inline void pcie_ecrc_get_policy(char *str) { }
846 #endif
847
848 #ifdef CONFIG_PCIEPORTBUS
849 void pcie_reset_lbms(struct pci_dev *port);
850 #else
pcie_reset_lbms(struct pci_dev * port)851 static inline void pcie_reset_lbms(struct pci_dev *port) {}
852 #endif
853
854 struct pci_dev_reset_methods {
855 u16 vendor;
856 u16 device;
857 int (*reset)(struct pci_dev *dev, bool probe);
858 };
859
860 struct pci_reset_fn_method {
861 int (*reset_fn)(struct pci_dev *pdev, bool probe);
862 char *name;
863 };
864 extern const struct pci_reset_fn_method pci_reset_fn_methods[];
865
866 #ifdef CONFIG_PCI_QUIRKS
867 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
868 #else
pci_dev_specific_reset(struct pci_dev * dev,bool probe)869 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
870 {
871 return -ENOTTY;
872 }
873 #endif
874
875 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
876 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
877 struct resource *res);
878 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)879 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
880 u16 segment, struct resource *res)
881 {
882 return -ENODEV;
883 }
884 #endif
885
886 void pci_rebar_init(struct pci_dev *pdev);
887 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
888 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)889 static inline u64 pci_rebar_size_to_bytes(int size)
890 {
891 return 1ULL << (size + 20);
892 }
893
894 struct device_node;
895
896 #define PCI_EQ_RESV 0xff
897
898 enum equalization_preset_type {
899 EQ_PRESET_TYPE_8GTS,
900 EQ_PRESET_TYPE_16GTS,
901 EQ_PRESET_TYPE_32GTS,
902 EQ_PRESET_TYPE_64GTS,
903 EQ_PRESET_TYPE_MAX
904 };
905
906 struct pci_eq_presets {
907 u16 eq_presets_8gts[MAX_NR_LANES];
908 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES];
909 };
910
911 #ifdef CONFIG_OF
912 int of_get_pci_domain_nr(struct device_node *node);
913 int of_pci_get_max_link_speed(struct device_node *node);
914 u32 of_pci_get_slot_power_limit(struct device_node *node,
915 u8 *slot_power_limit_value,
916 u8 *slot_power_limit_scale);
917 bool of_pci_preserve_config(struct device_node *node);
918 int pci_set_of_node(struct pci_dev *dev);
919 void pci_release_of_node(struct pci_dev *dev);
920 void pci_set_bus_of_node(struct pci_bus *bus);
921 void pci_release_bus_of_node(struct pci_bus *bus);
922
923 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
924 bool of_pci_supply_present(struct device_node *np);
925 int of_pci_get_equalization_presets(struct device *dev,
926 struct pci_eq_presets *presets,
927 int num_lanes);
928 #else
929 static inline int
of_get_pci_domain_nr(struct device_node * node)930 of_get_pci_domain_nr(struct device_node *node)
931 {
932 return -1;
933 }
934
935 static inline int
of_pci_get_max_link_speed(struct device_node * node)936 of_pci_get_max_link_speed(struct device_node *node)
937 {
938 return -EINVAL;
939 }
940
941 static inline u32
of_pci_get_slot_power_limit(struct device_node * node,u8 * slot_power_limit_value,u8 * slot_power_limit_scale)942 of_pci_get_slot_power_limit(struct device_node *node,
943 u8 *slot_power_limit_value,
944 u8 *slot_power_limit_scale)
945 {
946 if (slot_power_limit_value)
947 *slot_power_limit_value = 0;
948 if (slot_power_limit_scale)
949 *slot_power_limit_scale = 0;
950 return 0;
951 }
952
of_pci_preserve_config(struct device_node * node)953 static inline bool of_pci_preserve_config(struct device_node *node)
954 {
955 return false;
956 }
957
pci_set_of_node(struct pci_dev * dev)958 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
pci_release_of_node(struct pci_dev * dev)959 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)960 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)961 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
962
devm_of_pci_bridge_init(struct device * dev,struct pci_host_bridge * bridge)963 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
964 {
965 return 0;
966 }
967
of_pci_supply_present(struct device_node * np)968 static inline bool of_pci_supply_present(struct device_node *np)
969 {
970 return false;
971 }
972
of_pci_get_equalization_presets(struct device * dev,struct pci_eq_presets * presets,int num_lanes)973 static inline int of_pci_get_equalization_presets(struct device *dev,
974 struct pci_eq_presets *presets,
975 int num_lanes)
976 {
977 presets->eq_presets_8gts[0] = PCI_EQ_RESV;
978 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++)
979 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV;
980
981 return 0;
982 }
983 #endif /* CONFIG_OF */
984
985 struct of_changeset;
986
987 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES
988 void of_pci_make_dev_node(struct pci_dev *pdev);
989 void of_pci_remove_node(struct pci_dev *pdev);
990 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
991 struct device_node *np);
992 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge);
993 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge);
994 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge,
995 struct of_changeset *ocs,
996 struct device_node *np);
997 #else
of_pci_make_dev_node(struct pci_dev * pdev)998 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
of_pci_remove_node(struct pci_dev * pdev)999 static inline void of_pci_remove_node(struct pci_dev *pdev) { }
of_pci_make_host_bridge_node(struct pci_host_bridge * bridge)1000 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { }
of_pci_remove_host_bridge_node(struct pci_host_bridge * bridge)1001 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { }
1002 #endif
1003
1004 #ifdef CONFIG_PCIEAER
1005 void pci_no_aer(void);
1006 void pci_aer_init(struct pci_dev *dev);
1007 void pci_aer_exit(struct pci_dev *dev);
1008 extern const struct attribute_group aer_stats_attr_group;
1009 extern const struct attribute_group aer_attr_group;
1010 void pci_aer_clear_fatal_status(struct pci_dev *dev);
1011 int pci_aer_clear_status(struct pci_dev *dev);
1012 int pci_aer_raw_clear_status(struct pci_dev *dev);
1013 void pci_save_aer_state(struct pci_dev *dev);
1014 void pci_restore_aer_state(struct pci_dev *dev);
1015 #else
pci_no_aer(void)1016 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)1017 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)1018 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)1019 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_status(struct pci_dev * dev)1020 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_aer_raw_clear_status(struct pci_dev * dev)1021 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_save_aer_state(struct pci_dev * dev)1022 static inline void pci_save_aer_state(struct pci_dev *dev) { }
pci_restore_aer_state(struct pci_dev * dev)1023 static inline void pci_restore_aer_state(struct pci_dev *dev) { }
1024 #endif
1025
1026 #ifdef CONFIG_ACPI
1027 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge);
1028 int pci_acpi_program_hp_params(struct pci_dev *dev);
1029 extern const struct attribute_group pci_dev_acpi_attr_group;
1030 void pci_set_acpi_fwnode(struct pci_dev *dev);
1031 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
1032 bool acpi_pci_power_manageable(struct pci_dev *dev);
1033 bool acpi_pci_bridge_d3(struct pci_dev *dev);
1034 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1035 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
1036 void acpi_pci_refresh_power_state(struct pci_dev *dev);
1037 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
1038 bool acpi_pci_need_resume(struct pci_dev *dev);
1039 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
1040 #else
pci_acpi_preserve_config(struct pci_host_bridge * bridge)1041 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge)
1042 {
1043 return false;
1044 }
pci_dev_acpi_reset(struct pci_dev * dev,bool probe)1045 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
1046 {
1047 return -ENOTTY;
1048 }
pci_set_acpi_fwnode(struct pci_dev * dev)1049 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
pci_acpi_program_hp_params(struct pci_dev * dev)1050 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
1051 {
1052 return -ENODEV;
1053 }
acpi_pci_power_manageable(struct pci_dev * dev)1054 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
1055 {
1056 return false;
1057 }
acpi_pci_bridge_d3(struct pci_dev * dev)1058 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
1059 {
1060 return false;
1061 }
acpi_pci_set_power_state(struct pci_dev * dev,pci_power_t state)1062 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1063 {
1064 return -ENODEV;
1065 }
acpi_pci_get_power_state(struct pci_dev * dev)1066 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
1067 {
1068 return PCI_UNKNOWN;
1069 }
acpi_pci_refresh_power_state(struct pci_dev * dev)1070 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
acpi_pci_wakeup(struct pci_dev * dev,bool enable)1071 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
1072 {
1073 return -ENODEV;
1074 }
acpi_pci_need_resume(struct pci_dev * dev)1075 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
1076 {
1077 return false;
1078 }
acpi_pci_choose_state(struct pci_dev * pdev)1079 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
1080 {
1081 return PCI_POWER_ERROR;
1082 }
1083 #endif
1084
1085 #ifdef CONFIG_PCIEASPM
1086 extern const struct attribute_group aspm_ctrl_attr_group;
1087 #endif
1088
1089 #ifdef CONFIG_X86_INTEL_MID
1090 bool pci_use_mid_pm(void);
1091 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
1092 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
1093 #else
pci_use_mid_pm(void)1094 static inline bool pci_use_mid_pm(void)
1095 {
1096 return false;
1097 }
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)1098 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
1099 {
1100 return -ENODEV;
1101 }
mid_pci_get_power_state(struct pci_dev * pdev)1102 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
1103 {
1104 return PCI_UNKNOWN;
1105 }
1106 #endif
1107
1108 #ifdef CONFIG_PCI_MSI
1109 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag);
1110 #else
pci_msix_write_tph_tag(struct pci_dev * pdev,unsigned int index,u16 tag)1111 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag)
1112 {
1113 return -ENODEV;
1114 }
1115 #endif
1116
1117 /*
1118 * Config Address for PCI Configuration Mechanism #1
1119 *
1120 * See PCI Local Bus Specification, Revision 3.0,
1121 * Section 3.2.2.3.2, Figure 3-2, p. 50.
1122 */
1123
1124 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
1125 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
1126 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
1127
1128 #define PCI_CONF1_BUS_MASK 0xff
1129 #define PCI_CONF1_DEV_MASK 0x1f
1130 #define PCI_CONF1_FUNC_MASK 0x7
1131 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
1132
1133 #define PCI_CONF1_ENABLE BIT(31)
1134 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
1135 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
1136 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
1137 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
1138
1139 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
1140 (PCI_CONF1_ENABLE | \
1141 PCI_CONF1_BUS(bus) | \
1142 PCI_CONF1_DEV(dev) | \
1143 PCI_CONF1_FUNC(func) | \
1144 PCI_CONF1_REG(reg))
1145
1146 /*
1147 * Extension of PCI Config Address for accessing extended PCIe registers
1148 *
1149 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
1150 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
1151 * are used for specifying additional 4 high bits of PCI Express register.
1152 */
1153
1154 #define PCI_CONF1_EXT_REG_SHIFT 16
1155 #define PCI_CONF1_EXT_REG_MASK 0xf00
1156 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
1157
1158 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
1159 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
1160 PCI_CONF1_EXT_REG(reg))
1161
1162 #endif /* DRIVERS_PCI_H */
1163