1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6 #include <linux/arm-smccc.h>
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_platform.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/soc/mediatek/mtk_sip_svc.h>
19 #include <soc/mediatek/smi.h>
20 #include <dt-bindings/memory/mt2701-larb-port.h>
21 #include <dt-bindings/memory/mtk-memory-port.h>
22
23 /* SMI COMMON */
24 #define SMI_L1LEN 0x100
25
26 #define SMI_L1_ARB 0x200
27 #define SMI_BUS_SEL 0x220
28 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
29 /* All are MMU0 defaultly. Only specialize mmu1 here. */
30 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
31
32 #define SMI_READ_FIFO_TH 0x230
33 #define SMI_M4U_TH 0x234
34 #define SMI_FIFO_TH1 0x238
35 #define SMI_FIFO_TH2 0x23c
36 #define SMI_DCM 0x300
37 #define SMI_DUMMY 0x444
38
39 /* SMI LARB */
40 #define SMI_LARB_SLP_CON 0xc
41 #define SLP_PROT_EN BIT(0)
42 #define SLP_PROT_RDY BIT(16)
43
44 #define SMI_LARB_CMD_THRT_CON 0x24
45 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
46 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4)
47
48 #define SMI_LARB_SW_FLAG 0x40
49 #define SMI_LARB_SW_FLAG_1 0x1
50
51 #define SMI_LARB_OSTDL_PORT 0x200
52 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
53
54 /* Below are about mmu enable registers, they are different in SoCs */
55 /* gen1: mt2701 */
56 #define REG_SMI_SECUR_CON_BASE 0x5c0
57
58 /* every register control 8 port, register offset 0x4 */
59 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
60 #define REG_SMI_SECUR_CON_ADDR(id) \
61 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
62
63 /*
64 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
65 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
66 * or non-security.
67 */
68 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
69 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
70 /* mt2701 domain should be set to 3 */
71 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
72
73 /* gen2: */
74 /* mt8167 */
75 #define MT8167_SMI_LARB_MMU_EN 0xfc0
76
77 /* mt8173 */
78 #define MT8173_SMI_LARB_MMU_EN 0xf00
79
80 /* general */
81 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
82 #define F_MMU_EN BIT(0)
83 #define BANK_SEL(id) ({ \
84 u32 _id = (id) & 0x3; \
85 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
86 })
87
88 #define SMI_COMMON_INIT_REGS_NR 6
89 #define SMI_LARB_PORT_NR_MAX 32
90
91 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
92 #define MTK_SMI_FLAG_SW_FLAG BIT(1)
93 #define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
94 #define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
95 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
96
97 struct mtk_smi_reg_pair {
98 unsigned int offset;
99 u32 value;
100 };
101
102 enum mtk_smi_type {
103 MTK_SMI_GEN1,
104 MTK_SMI_GEN2, /* gen2 smi common */
105 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
106 };
107
108 /* larbs: Require apb/smi clocks while gals is optional. */
109 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
110 #define MTK_SMI_LARB_REQ_CLK_NR 2
111 #define MTK_SMI_LARB_OPT_CLK_NR 1
112
113 /*
114 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
115 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
116 */
117 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
118 #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
119 #define MTK_SMI_COM_REQ_CLK_NR 2
120 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
121 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
122
123 struct mtk_smi_common_plat {
124 enum mtk_smi_type type;
125 bool has_gals;
126 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
127
128 const struct mtk_smi_reg_pair *init;
129 };
130
131 struct mtk_smi_larb_gen {
132 int port_in_larb[MTK_LARB_NR_MAX + 1];
133 int (*config_port)(struct device *dev);
134 unsigned int larb_direct_to_common_mask;
135 unsigned int flags_general;
136 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
137 };
138
139 struct mtk_smi {
140 struct device *dev;
141 unsigned int clk_num;
142 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX];
143 struct clk *clk_async; /*only needed by mt2701*/
144 union {
145 void __iomem *smi_ao_base; /* only for gen1 */
146 void __iomem *base; /* only for gen2 */
147 };
148 struct device *smi_common_dev; /* for sub common */
149 const struct mtk_smi_common_plat *plat;
150 };
151
152 struct mtk_smi_larb { /* larb: local arbiter */
153 struct mtk_smi smi;
154 void __iomem *base;
155 struct device *smi_common_dev; /* common or sub-common dev */
156 const struct mtk_smi_larb_gen *larb_gen;
157 int larbid;
158 u32 *mmu;
159 unsigned char *bank;
160 };
161
162 static int
mtk_smi_larb_bind(struct device * dev,struct device * master,void * data)163 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
164 {
165 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
166 struct mtk_smi_larb_iommu *larb_mmu = data;
167 unsigned int i;
168
169 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
170 if (dev == larb_mmu[i].dev) {
171 larb->larbid = i;
172 larb->mmu = &larb_mmu[i].mmu;
173 larb->bank = larb_mmu[i].bank;
174 return 0;
175 }
176 }
177 return -ENODEV;
178 }
179
180 static void
mtk_smi_larb_unbind(struct device * dev,struct device * master,void * data)181 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
182 {
183 /* Do nothing as the iommu is always enabled. */
184 }
185
186 static const struct component_ops mtk_smi_larb_component_ops = {
187 .bind = mtk_smi_larb_bind,
188 .unbind = mtk_smi_larb_unbind,
189 };
190
mtk_smi_larb_config_port_gen1(struct device * dev)191 static int mtk_smi_larb_config_port_gen1(struct device *dev)
192 {
193 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
194 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
195 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
196 int i, m4u_port_id, larb_port_num;
197 u32 sec_con_val, reg_val;
198
199 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
200 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
201 - larb_gen->port_in_larb[larb->larbid];
202
203 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
204 if (*larb->mmu & BIT(i)) {
205 /* bit[port + 3] controls the virtual or physical */
206 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
207 } else {
208 /* do not need to enable m4u for this port */
209 continue;
210 }
211 reg_val = readl(common->smi_ao_base
212 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
213 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
214 reg_val |= sec_con_val;
215 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
216 writel(reg_val,
217 common->smi_ao_base
218 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
219 }
220 return 0;
221 }
222
mtk_smi_larb_config_port_mt8167(struct device * dev)223 static int mtk_smi_larb_config_port_mt8167(struct device *dev)
224 {
225 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
226
227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
228 return 0;
229 }
230
mtk_smi_larb_config_port_mt8173(struct device * dev)231 static int mtk_smi_larb_config_port_mt8173(struct device *dev)
232 {
233 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
234
235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
236 return 0;
237 }
238
mtk_smi_larb_config_port_gen2_general(struct device * dev)239 static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
240 {
241 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
242 u32 reg, flags_general = larb->larb_gen->flags_general;
243 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
244 struct arm_smccc_res res;
245 int i;
246
247 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
248 return 0;
249
250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
252 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
253 reg |= SMI_LARB_THRT_RD_NU_LMT;
254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
255 }
256
257 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
259
260 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
262
263 /*
264 * When mmu_en bits are in security world, the bank_sel still is in the
265 * LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no
266 * effect in this case.
267 */
268 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) {
269 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB,
270 larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);
271 if (res.a0 != 0) {
272 dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0);
273 return -EINVAL;
274 }
275 }
276
277 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
279 reg |= F_MMU_EN;
280 reg |= BANK_SEL(larb->bank[i]);
281 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
282 }
283 return 0;
284 }
285
286 static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
287 [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
288 [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
291 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
292 [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
293 [6] = {0x06, 0x01, 0x06, 0x0a,},
294 [7] = {0x0c, 0x0c, 0x12,},
295 [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
296 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
297 0x03, 0x01, 0x1e, 0x01, 0x05,},
298 [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
299 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
300 [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
301 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
302 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
303 [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
304 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
305 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
306 [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
307 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
308 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
309 [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
310 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
311 [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
312 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
313 0x02, 0x02, 0x01, 0x01,},
314 [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
315 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
316 0x0c, 0x01, 0x01,},
317 [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
318 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
319 [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
320 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
321 [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
322 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
323 [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
324 [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
325 [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
326 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
327 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
328 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
329 0x01,},
330 [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
331 [24] = {0x12, 0x06, 0x12, 0x06,},
332 [25] = {0x01},
333 };
334
335 static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] = {
336 [0] = {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,},
337 [1] = {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,},
338 [2] = {0x5, 0x5, 0x5, 0x5, 0x1,},
339 [3] = {},
340 [4] = {0x28, 0x19, 0xb, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x1,},
341 [5] = {0x1, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x16,},
342 [6] = {},
343 [7] = {0x1, 0x3, 0x2, 0x1, 0x1, 0x5, 0x2, 0x12, 0x13, 0x4, 0x4, 0x1,
344 0x4, 0x2, 0x1,},
345 [8] = {},
346 [9] = {0xa, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4,
347 0xa, 0x3, 0x4, 0xe, 0x1, 0x7, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
348 0x1, 0x1, 0x1, 0x1, 0x1,},
349 [10] = {},
350 [11] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
351 0x1, 0x1, 0x1, 0xe, 0x1, 0x7, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2,
352 0xf, 0x8, 0x1, 0x1, 0x1,},
353 [12] = {},
354 [13] = {0x2, 0xc, 0xc, 0xe, 0x6, 0x6, 0x6, 0x6, 0x6, 0x12, 0x6, 0x28,
355 0x2, 0xc, 0xc, 0x28, 0x12, 0x6,},
356 [14] = {},
357 [15] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2,
358 0x4, 0x2, 0x8, 0x4, 0x4,},
359 [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2,
360 0x4, 0x2, 0x8, 0x4, 0x4,},
361 [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2,
362 0x4, 0x2, 0x8, 0x4, 0x4,},
363 [18] = {0x2, 0x2, 0x4, 0x2,},
364 [19] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1,},
365 };
366
367 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
368 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
369 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
370 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */
371 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
372 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
373 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
374 [6] = {0x06, 0x01, 0x06, 0x0a,},
375 [7] = {0x0c, 0x0c, 0x12,},
376 [8] = {0x0c, 0x0c, 0x12,},
377 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
378 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
379 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
380 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
381 0x0d, 0x06, 0x10, 0x10,},
382 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
383 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
384 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
385 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
386 0x01, 0x02, 0x02, 0x08, 0x02,},
387 [15] = {},
388 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
389 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
390 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
391 [18] = {0x12, 0x06, 0x12, 0x06,},
392 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
393 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
394 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
395 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
396 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
397 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
398 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
399 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
400 [23] = {0x18, 0x01,},
401 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
402 0x01, 0x01,},
403 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
404 0x02, 0x01,},
405 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
406 0x02, 0x01,},
407 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
408 0x02, 0x01,},
409 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
410 };
411
412 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
413 .port_in_larb = {
414 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
415 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
416 },
417 .config_port = mtk_smi_larb_config_port_gen1,
418 };
419
420 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
421 .config_port = mtk_smi_larb_config_port_gen2_general,
422 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
423 };
424
425 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
426 .config_port = mtk_smi_larb_config_port_gen2_general,
427 .larb_direct_to_common_mask =
428 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
429 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
430 };
431
432 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
433 /* mt8167 do not need the port in larb */
434 .config_port = mtk_smi_larb_config_port_mt8167,
435 };
436
437 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
438 /* mt8173 do not need the port in larb */
439 .config_port = mtk_smi_larb_config_port_mt8173,
440 };
441
442 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
443 .config_port = mtk_smi_larb_config_port_gen2_general,
444 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
445 /* IPU0 | IPU1 | CCU */
446 };
447
448 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
449 .config_port = mtk_smi_larb_config_port_gen2_general,
450 .flags_general = MTK_SMI_FLAG_SLEEP_CTL,
451 };
452
453 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
454 .config_port = mtk_smi_larb_config_port_gen2_general,
455 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
456 MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
457 .ostd = mtk_smi_larb_mt8188_ostd,
458 };
459
460 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
461 .config_port = mtk_smi_larb_config_port_gen2_general,
462 .ostd = mtk_smi_larb_mt8192_ostd,
463 };
464
465 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
466 .config_port = mtk_smi_larb_config_port_gen2_general,
467 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
468 MTK_SMI_FLAG_SLEEP_CTL,
469 .ostd = mtk_smi_larb_mt8195_ostd,
470 };
471
472 static const struct of_device_id mtk_smi_larb_of_ids[] = {
473 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
474 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
475 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
476 {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
477 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
478 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
479 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
480 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
481 {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
482 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
483 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
484 {}
485 };
486 MODULE_DEVICE_TABLE(of, mtk_smi_larb_of_ids);
487
mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb * larb)488 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
489 {
490 int ret;
491 u32 tmp;
492
493 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
494 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
495 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
496 if (ret) {
497 /* TODO: Reset this larb if it fails here. */
498 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
499 }
500 return ret;
501 }
502
mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb * larb)503 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
504 {
505 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
506 }
507
mtk_smi_device_link_common(struct device * dev,struct device ** com_dev)508 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
509 {
510 struct platform_device *smi_com_pdev;
511 struct device_node *smi_com_node;
512 struct device *smi_com_dev;
513 struct device_link *link;
514
515 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
516 if (!smi_com_node)
517 return -EINVAL;
518
519 smi_com_pdev = of_find_device_by_node(smi_com_node);
520 of_node_put(smi_com_node);
521 if (smi_com_pdev) {
522 /* smi common is the supplier, Make sure it is ready before */
523 if (!platform_get_drvdata(smi_com_pdev)) {
524 put_device(&smi_com_pdev->dev);
525 return -EPROBE_DEFER;
526 }
527 smi_com_dev = &smi_com_pdev->dev;
528 link = device_link_add(dev, smi_com_dev,
529 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
530 if (!link) {
531 dev_err(dev, "Unable to link smi-common dev\n");
532 put_device(&smi_com_pdev->dev);
533 return -ENODEV;
534 }
535 *com_dev = smi_com_dev;
536 } else {
537 dev_err(dev, "Failed to get the smi_common device\n");
538 return -EINVAL;
539 }
540 return 0;
541 }
542
mtk_smi_dts_clk_init(struct device * dev,struct mtk_smi * smi,const char * const clks[],unsigned int clk_nr_required,unsigned int clk_nr_optional)543 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
544 const char * const clks[],
545 unsigned int clk_nr_required,
546 unsigned int clk_nr_optional)
547 {
548 int i, ret;
549
550 for (i = 0; i < clk_nr_required; i++)
551 smi->clks[i].id = clks[i];
552 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
553 if (ret)
554 return ret;
555
556 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
557 smi->clks[i].id = clks[i];
558 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
559 smi->clks + clk_nr_required);
560 smi->clk_num = clk_nr_required + clk_nr_optional;
561 return ret;
562 }
563
mtk_smi_larb_probe(struct platform_device * pdev)564 static int mtk_smi_larb_probe(struct platform_device *pdev)
565 {
566 struct mtk_smi_larb *larb;
567 struct device *dev = &pdev->dev;
568 int ret;
569
570 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
571 if (!larb)
572 return -ENOMEM;
573
574 larb->larb_gen = of_device_get_match_data(dev);
575 larb->base = devm_platform_ioremap_resource(pdev, 0);
576 if (IS_ERR(larb->base))
577 return PTR_ERR(larb->base);
578
579 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
580 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
581 if (ret)
582 return ret;
583
584 larb->smi.dev = dev;
585
586 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
587 if (ret < 0)
588 return ret;
589
590 pm_runtime_enable(dev);
591 platform_set_drvdata(pdev, larb);
592 ret = component_add(dev, &mtk_smi_larb_component_ops);
593 if (ret)
594 goto err_pm_disable;
595 return 0;
596
597 err_pm_disable:
598 pm_runtime_disable(dev);
599 device_link_remove(dev, larb->smi_common_dev);
600 return ret;
601 }
602
mtk_smi_larb_remove(struct platform_device * pdev)603 static void mtk_smi_larb_remove(struct platform_device *pdev)
604 {
605 struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
606
607 device_link_remove(&pdev->dev, larb->smi_common_dev);
608 pm_runtime_disable(&pdev->dev);
609 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
610 }
611
mtk_smi_larb_resume(struct device * dev)612 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
613 {
614 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
615 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
616 int ret;
617
618 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
619 if (ret)
620 return ret;
621
622 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
623 mtk_smi_larb_sleep_ctrl_disable(larb);
624
625 /* Configure the basic setting for this larb */
626 return larb_gen->config_port(dev);
627 }
628
mtk_smi_larb_suspend(struct device * dev)629 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
630 {
631 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
632 int ret;
633
634 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
635 ret = mtk_smi_larb_sleep_ctrl_enable(larb);
636 if (ret)
637 return ret;
638 }
639
640 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
641 return 0;
642 }
643
644 static const struct dev_pm_ops smi_larb_pm_ops = {
645 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
646 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
647 pm_runtime_force_resume)
648 };
649
650 static struct platform_driver mtk_smi_larb_driver = {
651 .probe = mtk_smi_larb_probe,
652 .remove = mtk_smi_larb_remove,
653 .driver = {
654 .name = "mtk-smi-larb",
655 .of_match_table = mtk_smi_larb_of_ids,
656 .pm = &smi_larb_pm_ops,
657 }
658 };
659
660 static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
661 {SMI_L1_ARB, 0x1b},
662 {SMI_M4U_TH, 0xce810c85},
663 {SMI_FIFO_TH1, 0x43214c8},
664 {SMI_READ_FIFO_TH, 0x191f},
665 };
666
667 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
668 {SMI_L1LEN, 0xb},
669 {SMI_M4U_TH, 0xe100e10},
670 {SMI_FIFO_TH1, 0x506090a},
671 {SMI_FIFO_TH2, 0x506090a},
672 {SMI_DCM, 0x4f1},
673 {SMI_DUMMY, 0x1},
674 };
675
676 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
677 .type = MTK_SMI_GEN1,
678 };
679
680 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
681 .type = MTK_SMI_GEN2,
682 };
683
684 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
685 .type = MTK_SMI_GEN2,
686 .has_gals = true,
687 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
688 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
689 };
690
691 static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
692 .type = MTK_SMI_GEN2,
693 .bus_sel = F_MMU1_LARB(0),
694 .init = mtk_smi_common_mt6795_init,
695 };
696
697 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
698 .type = MTK_SMI_GEN2,
699 .has_gals = true,
700 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
701 F_MMU1_LARB(7),
702 };
703
704 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
705 .type = MTK_SMI_GEN2,
706 .has_gals = true,
707 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
708 };
709
710 static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
711 .type = MTK_SMI_GEN2,
712 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
713 .init = mtk_smi_common_mt8195_init,
714 };
715
716 static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
717 .type = MTK_SMI_GEN2,
718 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
719 .init = mtk_smi_common_mt8195_init,
720 };
721
722 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
723 .type = MTK_SMI_GEN2,
724 .has_gals = true,
725 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
726 F_MMU1_LARB(6),
727 };
728
729 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
730 .type = MTK_SMI_GEN2,
731 .has_gals = true,
732 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
733 F_MMU1_LARB(7),
734 .init = mtk_smi_common_mt8195_init,
735 };
736
737 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
738 .type = MTK_SMI_GEN2,
739 .has_gals = true,
740 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
741 .init = mtk_smi_common_mt8195_init,
742 };
743
744 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
745 .type = MTK_SMI_GEN2_SUB_COMM,
746 .has_gals = true,
747 };
748
749 static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = {
750 .type = MTK_SMI_GEN2,
751 .bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4),
752 };
753
754 static const struct of_device_id mtk_smi_common_of_ids[] = {
755 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
756 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
757 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
758 {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
759 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
760 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
761 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
762 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
763 {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
764 {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
765 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
766 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
767 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
768 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
769 {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
770 {}
771 };
772 MODULE_DEVICE_TABLE(of, mtk_smi_common_of_ids);
773
mtk_smi_common_probe(struct platform_device * pdev)774 static int mtk_smi_common_probe(struct platform_device *pdev)
775 {
776 struct device *dev = &pdev->dev;
777 struct mtk_smi *common;
778 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
779
780 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
781 if (!common)
782 return -ENOMEM;
783 common->dev = dev;
784 common->plat = of_device_get_match_data(dev);
785
786 if (common->plat->has_gals) {
787 if (common->plat->type == MTK_SMI_GEN2)
788 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
789 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
790 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
791 }
792 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
793 if (ret)
794 return ret;
795
796 /*
797 * for mtk smi gen 1, we need to get the ao(always on) base to config
798 * m4u port, and we need to enable the aync clock for transform the smi
799 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
800 * base.
801 */
802 if (common->plat->type == MTK_SMI_GEN1) {
803 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
804 if (IS_ERR(common->smi_ao_base))
805 return PTR_ERR(common->smi_ao_base);
806
807 common->clk_async = devm_clk_get_enabled(dev, "async");
808 if (IS_ERR(common->clk_async))
809 return PTR_ERR(common->clk_async);
810 } else {
811 common->base = devm_platform_ioremap_resource(pdev, 0);
812 if (IS_ERR(common->base))
813 return PTR_ERR(common->base);
814 }
815
816 /* link its smi-common if this is smi-sub-common */
817 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
818 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
819 if (ret < 0)
820 return ret;
821 }
822
823 pm_runtime_enable(dev);
824 platform_set_drvdata(pdev, common);
825 return 0;
826 }
827
mtk_smi_common_remove(struct platform_device * pdev)828 static void mtk_smi_common_remove(struct platform_device *pdev)
829 {
830 struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
831
832 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
833 device_link_remove(&pdev->dev, common->smi_common_dev);
834 pm_runtime_disable(&pdev->dev);
835 }
836
mtk_smi_common_resume(struct device * dev)837 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
838 {
839 struct mtk_smi *common = dev_get_drvdata(dev);
840 const struct mtk_smi_reg_pair *init = common->plat->init;
841 u32 bus_sel = common->plat->bus_sel; /* default is 0 */
842 int ret, i;
843
844 ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
845 if (ret)
846 return ret;
847
848 if (common->plat->type != MTK_SMI_GEN2)
849 return 0;
850
851 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
852 writel_relaxed(init[i].value, common->base + init[i].offset);
853
854 writel(bus_sel, common->base + SMI_BUS_SEL);
855 return 0;
856 }
857
mtk_smi_common_suspend(struct device * dev)858 static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
859 {
860 struct mtk_smi *common = dev_get_drvdata(dev);
861
862 clk_bulk_disable_unprepare(common->clk_num, common->clks);
863 return 0;
864 }
865
866 static const struct dev_pm_ops smi_common_pm_ops = {
867 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
868 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
869 pm_runtime_force_resume)
870 };
871
872 static struct platform_driver mtk_smi_common_driver = {
873 .probe = mtk_smi_common_probe,
874 .remove = mtk_smi_common_remove,
875 .driver = {
876 .name = "mtk-smi-common",
877 .of_match_table = mtk_smi_common_of_ids,
878 .pm = &smi_common_pm_ops,
879 }
880 };
881
882 static struct platform_driver * const smidrivers[] = {
883 &mtk_smi_common_driver,
884 &mtk_smi_larb_driver,
885 };
886
mtk_smi_init(void)887 static int __init mtk_smi_init(void)
888 {
889 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
890 }
891 module_init(mtk_smi_init);
892
mtk_smi_exit(void)893 static void __exit mtk_smi_exit(void)
894 {
895 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
896 }
897 module_exit(mtk_smi_exit);
898
899 MODULE_DESCRIPTION("MediaTek SMI driver");
900 MODULE_LICENSE("GPL v2");
901