1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/hdmi.h> 11 #include <linux/i2c.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of_platform.h> 18 #include <linux/of.h> 19 #include <linux/of_graph.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 24 #include <sound/hdmi-codec.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_bridge.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_print.h> 31 #include <drm/drm_probe_helper.h> 32 33 #include "mtk_cec.h" 34 #include "mtk_hdmi.h" 35 #include "mtk_hdmi_regs.h" 36 37 #define NCTS_BYTES 7 38 39 enum mtk_hdmi_clk_id { 40 MTK_HDMI_CLK_HDMI_PIXEL, 41 MTK_HDMI_CLK_HDMI_PLL, 42 MTK_HDMI_CLK_AUD_BCLK, 43 MTK_HDMI_CLK_AUD_SPDIF, 44 MTK_HDMI_CLK_COUNT 45 }; 46 47 enum hdmi_aud_input_type { 48 HDMI_AUD_INPUT_I2S = 0, 49 HDMI_AUD_INPUT_SPDIF, 50 }; 51 52 enum hdmi_aud_i2s_fmt { 53 HDMI_I2S_MODE_RJT_24BIT = 0, 54 HDMI_I2S_MODE_RJT_16BIT, 55 HDMI_I2S_MODE_LJT_24BIT, 56 HDMI_I2S_MODE_LJT_16BIT, 57 HDMI_I2S_MODE_I2S_24BIT, 58 HDMI_I2S_MODE_I2S_16BIT 59 }; 60 61 enum hdmi_aud_mclk { 62 HDMI_AUD_MCLK_128FS, 63 HDMI_AUD_MCLK_192FS, 64 HDMI_AUD_MCLK_256FS, 65 HDMI_AUD_MCLK_384FS, 66 HDMI_AUD_MCLK_512FS, 67 HDMI_AUD_MCLK_768FS, 68 HDMI_AUD_MCLK_1152FS, 69 }; 70 71 enum hdmi_aud_channel_type { 72 HDMI_AUD_CHAN_TYPE_1_0 = 0, 73 HDMI_AUD_CHAN_TYPE_1_1, 74 HDMI_AUD_CHAN_TYPE_2_0, 75 HDMI_AUD_CHAN_TYPE_2_1, 76 HDMI_AUD_CHAN_TYPE_3_0, 77 HDMI_AUD_CHAN_TYPE_3_1, 78 HDMI_AUD_CHAN_TYPE_4_0, 79 HDMI_AUD_CHAN_TYPE_4_1, 80 HDMI_AUD_CHAN_TYPE_5_0, 81 HDMI_AUD_CHAN_TYPE_5_1, 82 HDMI_AUD_CHAN_TYPE_6_0, 83 HDMI_AUD_CHAN_TYPE_6_1, 84 HDMI_AUD_CHAN_TYPE_7_0, 85 HDMI_AUD_CHAN_TYPE_7_1, 86 HDMI_AUD_CHAN_TYPE_3_0_LRS, 87 HDMI_AUD_CHAN_TYPE_3_1_LRS, 88 HDMI_AUD_CHAN_TYPE_4_0_CLRS, 89 HDMI_AUD_CHAN_TYPE_4_1_CLRS, 90 HDMI_AUD_CHAN_TYPE_6_1_CS, 91 HDMI_AUD_CHAN_TYPE_6_1_CH, 92 HDMI_AUD_CHAN_TYPE_6_1_OH, 93 HDMI_AUD_CHAN_TYPE_6_1_CHR, 94 HDMI_AUD_CHAN_TYPE_7_1_LH_RH, 95 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, 96 HDMI_AUD_CHAN_TYPE_7_1_LC_RC, 97 HDMI_AUD_CHAN_TYPE_7_1_LW_RW, 98 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, 99 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, 100 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, 101 HDMI_AUD_CHAN_TYPE_7_1_CS_CH, 102 HDMI_AUD_CHAN_TYPE_7_1_CS_OH, 103 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, 104 HDMI_AUD_CHAN_TYPE_7_1_CH_OH, 105 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, 106 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, 107 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, 108 HDMI_AUD_CHAN_TYPE_6_0_CS, 109 HDMI_AUD_CHAN_TYPE_6_0_CH, 110 HDMI_AUD_CHAN_TYPE_6_0_OH, 111 HDMI_AUD_CHAN_TYPE_6_0_CHR, 112 HDMI_AUD_CHAN_TYPE_7_0_LH_RH, 113 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, 114 HDMI_AUD_CHAN_TYPE_7_0_LC_RC, 115 HDMI_AUD_CHAN_TYPE_7_0_LW_RW, 116 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, 117 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, 118 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, 119 HDMI_AUD_CHAN_TYPE_7_0_CS_CH, 120 HDMI_AUD_CHAN_TYPE_7_0_CS_OH, 121 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, 122 HDMI_AUD_CHAN_TYPE_7_0_CH_OH, 123 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, 124 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, 125 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, 126 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, 127 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF 128 }; 129 130 enum hdmi_aud_channel_swap_type { 131 HDMI_AUD_SWAP_LR, 132 HDMI_AUD_SWAP_LFE_CC, 133 HDMI_AUD_SWAP_LSRS, 134 HDMI_AUD_SWAP_RLS_RRS, 135 HDMI_AUD_SWAP_LR_STATUS, 136 }; 137 138 struct hdmi_audio_param { 139 enum hdmi_audio_coding_type aud_codec; 140 enum hdmi_audio_sample_size aud_sample_size; 141 enum hdmi_aud_input_type aud_input_type; 142 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 143 enum hdmi_aud_mclk aud_mclk; 144 enum hdmi_aud_channel_type aud_input_chan_type; 145 struct hdmi_codec_params codec_params; 146 }; 147 148 struct mtk_hdmi_conf { 149 bool tz_disabled; 150 bool cea_modes_only; 151 unsigned long max_mode_clock; 152 }; 153 154 struct mtk_hdmi { 155 struct drm_bridge bridge; 156 struct drm_bridge *next_bridge; 157 struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */ 158 struct device *dev; 159 const struct mtk_hdmi_conf *conf; 160 struct phy *phy; 161 struct device *cec_dev; 162 struct i2c_adapter *ddc_adpt; 163 struct clk *clk[MTK_HDMI_CLK_COUNT]; 164 struct drm_display_mode mode; 165 bool dvi_mode; 166 struct regmap *sys_regmap; 167 unsigned int sys_offset; 168 void __iomem *regs; 169 struct platform_device *audio_pdev; 170 struct hdmi_audio_param aud_param; 171 bool audio_enable; 172 bool powered; 173 bool enabled; 174 hdmi_codec_plugged_cb plugged_cb; 175 struct device *codec_dev; 176 struct mutex update_plugged_status_lock; 177 }; 178 179 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) 180 { 181 return container_of(b, struct mtk_hdmi, bridge); 182 } 183 184 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) 185 { 186 return readl(hdmi->regs + offset); 187 } 188 189 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) 190 { 191 writel(val, hdmi->regs + offset); 192 } 193 194 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 195 { 196 void __iomem *reg = hdmi->regs + offset; 197 u32 tmp; 198 199 tmp = readl(reg); 200 tmp &= ~bits; 201 writel(tmp, reg); 202 } 203 204 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 205 { 206 void __iomem *reg = hdmi->regs + offset; 207 u32 tmp; 208 209 tmp = readl(reg); 210 tmp |= bits; 211 writel(tmp, reg); 212 } 213 214 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) 215 { 216 void __iomem *reg = hdmi->regs + offset; 217 u32 tmp; 218 219 tmp = readl(reg); 220 tmp = (tmp & ~mask) | (val & mask); 221 writel(tmp, reg); 222 } 223 224 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 225 { 226 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, 227 VIDEO_SOURCE_SEL); 228 } 229 230 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 231 { 232 struct arm_smccc_res res; 233 234 /* 235 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 236 * output. This bit can only be controlled in ARM supervisor mode. 237 * The ARM trusted firmware provides an API for the HDMI driver to set 238 * this control bit to enable HDMI output in supervisor mode. 239 */ 240 if (hdmi->conf && hdmi->conf->tz_disabled) 241 regmap_update_bits(hdmi->sys_regmap, 242 hdmi->sys_offset + HDMI_SYS_CFG20, 243 0x80008005, enable ? 0x80000005 : 0x8000); 244 else 245 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 246 0x80000000, 0, 0, 0, 0, 0, &res); 247 248 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 249 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 250 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 251 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 252 } 253 254 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 255 { 256 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 257 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 258 } 259 260 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 261 { 262 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 263 } 264 265 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 266 { 267 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 268 } 269 270 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 271 { 272 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 273 HDMI_RST, HDMI_RST); 274 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 275 HDMI_RST, 0); 276 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 277 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 278 ANLG_ON, ANLG_ON); 279 } 280 281 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 282 { 283 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, 284 CFG2_NOTICE_EN); 285 } 286 287 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 288 { 289 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); 290 } 291 292 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 293 { 294 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); 295 } 296 297 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 298 u8 len) 299 { 300 u32 ctrl_reg = GRL_CTRL; 301 int i; 302 u8 *frame_data; 303 enum hdmi_infoframe_type frame_type; 304 u8 frame_ver; 305 u8 frame_len; 306 u8 checksum; 307 int ctrl_frame_en = 0; 308 309 frame_type = *buffer++; 310 frame_ver = *buffer++; 311 frame_len = *buffer++; 312 checksum = *buffer++; 313 frame_data = buffer; 314 315 dev_dbg(hdmi->dev, 316 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 317 frame_type, frame_ver, frame_len, checksum); 318 319 switch (frame_type) { 320 case HDMI_INFOFRAME_TYPE_AVI: 321 ctrl_frame_en = CTRL_AVI_EN; 322 ctrl_reg = GRL_CTRL; 323 break; 324 case HDMI_INFOFRAME_TYPE_SPD: 325 ctrl_frame_en = CTRL_SPD_EN; 326 ctrl_reg = GRL_CTRL; 327 break; 328 case HDMI_INFOFRAME_TYPE_AUDIO: 329 ctrl_frame_en = CTRL_AUDIO_EN; 330 ctrl_reg = GRL_CTRL; 331 break; 332 case HDMI_INFOFRAME_TYPE_VENDOR: 333 ctrl_frame_en = VS_EN; 334 ctrl_reg = GRL_ACP_ISRC_CTRL; 335 break; 336 default: 337 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); 338 return; 339 } 340 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 341 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); 342 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); 343 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); 344 345 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); 346 for (i = 0; i < frame_len; i++) 347 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); 348 349 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); 350 } 351 352 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 353 { 354 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, 355 AUDIO_PACKET_OFF); 356 } 357 358 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 359 { 360 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 361 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 362 usleep_range(2000, 4000); 363 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 364 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 365 } 366 367 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 368 { 369 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 370 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 371 COLOR_8BIT_MODE); 372 } 373 374 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 375 { 376 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 377 usleep_range(2000, 4000); 378 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 379 } 380 381 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 382 { 383 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, 384 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 385 usleep_range(2000, 4000); 386 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, 387 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 388 } 389 390 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 391 { 392 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, 393 CTS_CTRL_SOFT); 394 } 395 396 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 397 bool enable) 398 { 399 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, 400 NCTS_WRI_ANYTIME); 401 } 402 403 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 404 struct drm_display_mode *mode) 405 { 406 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); 407 408 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 409 mode->clock == 74250 && 410 mode->vdisplay == 1080) 411 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 412 else 413 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 414 } 415 416 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 417 enum hdmi_aud_channel_swap_type swap) 418 { 419 u8 swap_bit; 420 421 switch (swap) { 422 case HDMI_AUD_SWAP_LR: 423 swap_bit = LR_SWAP; 424 break; 425 case HDMI_AUD_SWAP_LFE_CC: 426 swap_bit = LFE_CC_SWAP; 427 break; 428 case HDMI_AUD_SWAP_LSRS: 429 swap_bit = LSRS_SWAP; 430 break; 431 case HDMI_AUD_SWAP_RLS_RRS: 432 swap_bit = RLS_RRS_SWAP; 433 break; 434 case HDMI_AUD_SWAP_LR_STATUS: 435 swap_bit = LR_STATUS_SWAP; 436 break; 437 default: 438 swap_bit = LFE_CC_SWAP; 439 break; 440 } 441 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); 442 } 443 444 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 445 enum hdmi_audio_sample_size bit_num) 446 { 447 u32 val; 448 449 switch (bit_num) { 450 case HDMI_AUDIO_SAMPLE_SIZE_16: 451 val = AOUT_16BIT; 452 break; 453 case HDMI_AUDIO_SAMPLE_SIZE_20: 454 val = AOUT_20BIT; 455 break; 456 case HDMI_AUDIO_SAMPLE_SIZE_24: 457 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 458 val = AOUT_24BIT; 459 break; 460 } 461 462 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); 463 } 464 465 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 466 enum hdmi_aud_i2s_fmt i2s_fmt) 467 { 468 u32 val; 469 470 val = mtk_hdmi_read(hdmi, GRL_CFG0); 471 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 472 473 switch (i2s_fmt) { 474 case HDMI_I2S_MODE_RJT_24BIT: 475 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 476 break; 477 case HDMI_I2S_MODE_RJT_16BIT: 478 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 479 break; 480 case HDMI_I2S_MODE_LJT_24BIT: 481 default: 482 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 483 break; 484 case HDMI_I2S_MODE_LJT_16BIT: 485 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 486 break; 487 case HDMI_I2S_MODE_I2S_24BIT: 488 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 489 break; 490 case HDMI_I2S_MODE_I2S_16BIT: 491 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 492 break; 493 } 494 mtk_hdmi_write(hdmi, GRL_CFG0, val); 495 } 496 497 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 498 { 499 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 500 u8 val; 501 502 /* Disable high bitrate, set DST packet normal/double */ 503 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 504 505 if (dst) 506 val = DST_NORMAL_DOUBLE | SACD_DST; 507 else 508 val = 0; 509 510 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); 511 } 512 513 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 514 enum hdmi_aud_channel_type channel_type, 515 u8 channel_count) 516 { 517 unsigned int ch_switch; 518 u8 i2s_uv; 519 520 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 521 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 522 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 523 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 524 525 if (channel_count == 2) { 526 i2s_uv = I2S_UV_CH_EN(0); 527 } else if (channel_count == 3 || channel_count == 4) { 528 if (channel_count == 4 && 529 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 530 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 531 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 532 else 533 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 534 } else if (channel_count == 6 || channel_count == 5) { 535 if (channel_count == 6 && 536 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 537 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 538 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 539 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 540 } else { 541 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 542 I2S_UV_CH_EN(0); 543 } 544 } else if (channel_count == 8 || channel_count == 7) { 545 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 546 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 547 } else { 548 i2s_uv = I2S_UV_CH_EN(0); 549 } 550 551 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); 552 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 553 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 554 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); 555 } 556 557 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 558 enum hdmi_aud_input_type input_type) 559 { 560 u32 val; 561 562 val = mtk_hdmi_read(hdmi, GRL_CFG1); 563 if (input_type == HDMI_AUD_INPUT_I2S && 564 (val & CFG1_SPDIF) == CFG1_SPDIF) { 565 val &= ~CFG1_SPDIF; 566 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 567 (val & CFG1_SPDIF) == 0) { 568 val |= CFG1_SPDIF; 569 } 570 mtk_hdmi_write(hdmi, GRL_CFG1, val); 571 } 572 573 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 574 u8 *channel_status) 575 { 576 int i; 577 578 for (i = 0; i < 5; i++) { 579 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 580 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); 581 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); 582 } 583 for (; i < 24; i++) { 584 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); 585 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); 586 } 587 } 588 589 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 590 { 591 u32 val; 592 593 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 594 if (val & MIX_CTRL_SRC_EN) { 595 val &= ~MIX_CTRL_SRC_EN; 596 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 597 usleep_range(255, 512); 598 val |= MIX_CTRL_SRC_EN; 599 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 600 } 601 } 602 603 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 604 { 605 u32 val; 606 607 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 608 val &= ~MIX_CTRL_SRC_EN; 609 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 610 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); 611 } 612 613 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 614 enum hdmi_aud_mclk mclk) 615 { 616 u32 val; 617 618 val = mtk_hdmi_read(hdmi, GRL_CFG5); 619 val &= CFG5_CD_RATIO_MASK; 620 621 switch (mclk) { 622 case HDMI_AUD_MCLK_128FS: 623 val |= CFG5_FS128; 624 break; 625 case HDMI_AUD_MCLK_256FS: 626 val |= CFG5_FS256; 627 break; 628 case HDMI_AUD_MCLK_384FS: 629 val |= CFG5_FS384; 630 break; 631 case HDMI_AUD_MCLK_512FS: 632 val |= CFG5_FS512; 633 break; 634 case HDMI_AUD_MCLK_768FS: 635 val |= CFG5_FS768; 636 break; 637 default: 638 val |= CFG5_FS256; 639 break; 640 } 641 mtk_hdmi_write(hdmi, GRL_CFG5, val); 642 } 643 644 struct hdmi_acr_n { 645 unsigned int clock; 646 unsigned int n[3]; 647 }; 648 649 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ 650 static const struct hdmi_acr_n hdmi_rec_n_table[] = { 651 /* Clock, N: 32kHz 44.1kHz 48kHz */ 652 { 25175, { 4576, 7007, 6864 } }, 653 { 74176, { 11648, 17836, 11648 } }, 654 { 148352, { 11648, 8918, 5824 } }, 655 { 296703, { 5824, 4459, 5824 } }, 656 { 297000, { 3072, 4704, 5120 } }, 657 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ 658 }; 659 660 /** 661 * hdmi_recommended_n() - Return N value recommended by HDMI specification 662 * @freq: audio sample rate in Hz 663 * @clock: rounded TMDS clock in kHz 664 */ 665 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) 666 { 667 const struct hdmi_acr_n *recommended; 668 unsigned int i; 669 670 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { 671 if (clock == hdmi_rec_n_table[i].clock) 672 break; 673 } 674 recommended = hdmi_rec_n_table + i; 675 676 switch (freq) { 677 case 32000: 678 return recommended->n[0]; 679 case 44100: 680 return recommended->n[1]; 681 case 48000: 682 return recommended->n[2]; 683 case 88200: 684 return recommended->n[1] * 2; 685 case 96000: 686 return recommended->n[2] * 2; 687 case 176400: 688 return recommended->n[1] * 4; 689 case 192000: 690 return recommended->n[2] * 4; 691 default: 692 return (128 * freq) / 1000; 693 } 694 } 695 696 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) 697 { 698 switch (clock) { 699 case 25175: 700 return 25174825; /* 25.2/1.001 MHz */ 701 case 74176: 702 return 74175824; /* 74.25/1.001 MHz */ 703 case 148352: 704 return 148351648; /* 148.5/1.001 MHz */ 705 case 296703: 706 return 296703297; /* 297/1.001 MHz */ 707 default: 708 return clock * 1000; 709 } 710 } 711 712 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, 713 unsigned int tmds_clock, unsigned int n) 714 { 715 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, 716 128 * audio_sample_rate); 717 } 718 719 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 720 unsigned int cts) 721 { 722 unsigned char val[NCTS_BYTES]; 723 int i; 724 725 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 726 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 727 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 728 memset(val, 0, sizeof(val)); 729 730 val[0] = (cts >> 24) & 0xff; 731 val[1] = (cts >> 16) & 0xff; 732 val[2] = (cts >> 8) & 0xff; 733 val[3] = cts & 0xff; 734 735 val[4] = (n >> 16) & 0xff; 736 val[5] = (n >> 8) & 0xff; 737 val[6] = n & 0xff; 738 739 for (i = 0; i < NCTS_BYTES; i++) 740 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); 741 } 742 743 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 744 unsigned int sample_rate, 745 unsigned int clock) 746 { 747 unsigned int n, cts; 748 749 n = hdmi_recommended_n(sample_rate, clock); 750 cts = hdmi_expected_cts(sample_rate, clock, n); 751 752 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 753 __func__, sample_rate, clock, n, cts); 754 755 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, 756 AUDIO_I2S_NCTS_SEL); 757 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 758 } 759 760 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 761 { 762 switch (channel_type) { 763 case HDMI_AUD_CHAN_TYPE_1_0: 764 case HDMI_AUD_CHAN_TYPE_1_1: 765 case HDMI_AUD_CHAN_TYPE_2_0: 766 return 2; 767 case HDMI_AUD_CHAN_TYPE_2_1: 768 case HDMI_AUD_CHAN_TYPE_3_0: 769 return 3; 770 case HDMI_AUD_CHAN_TYPE_3_1: 771 case HDMI_AUD_CHAN_TYPE_4_0: 772 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 773 return 4; 774 case HDMI_AUD_CHAN_TYPE_4_1: 775 case HDMI_AUD_CHAN_TYPE_5_0: 776 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 777 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 778 return 5; 779 case HDMI_AUD_CHAN_TYPE_5_1: 780 case HDMI_AUD_CHAN_TYPE_6_0: 781 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 782 case HDMI_AUD_CHAN_TYPE_6_0_CS: 783 case HDMI_AUD_CHAN_TYPE_6_0_CH: 784 case HDMI_AUD_CHAN_TYPE_6_0_OH: 785 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 786 return 6; 787 case HDMI_AUD_CHAN_TYPE_6_1: 788 case HDMI_AUD_CHAN_TYPE_6_1_CS: 789 case HDMI_AUD_CHAN_TYPE_6_1_CH: 790 case HDMI_AUD_CHAN_TYPE_6_1_OH: 791 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 792 case HDMI_AUD_CHAN_TYPE_7_0: 793 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 794 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 795 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 796 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 797 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 798 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 799 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 800 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 801 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 802 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 803 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 804 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 805 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 806 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 807 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 808 return 7; 809 case HDMI_AUD_CHAN_TYPE_7_1: 810 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 811 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 812 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 813 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 814 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 815 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 816 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 817 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 818 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 819 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 820 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 821 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 822 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 823 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 824 return 8; 825 default: 826 return 2; 827 } 828 } 829 830 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 831 { 832 unsigned long rate; 833 int ret; 834 835 /* The DPI driver already should have set TVDPLL to the correct rate */ 836 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 837 if (ret) { 838 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 839 ret); 840 return ret; 841 } 842 843 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 844 845 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 846 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 847 rate); 848 else 849 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 850 851 mtk_hdmi_hw_config_sys(hdmi); 852 mtk_hdmi_hw_set_deep_color_mode(hdmi); 853 return 0; 854 } 855 856 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 857 struct drm_display_mode *mode) 858 { 859 mtk_hdmi_hw_reset(hdmi); 860 mtk_hdmi_hw_enable_notice(hdmi, true); 861 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 862 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 863 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 864 865 mtk_hdmi_hw_msic_setting(hdmi, mode); 866 } 867 868 869 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 870 { 871 enum hdmi_aud_channel_type chan_type; 872 u8 chan_count; 873 bool dst; 874 875 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 876 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); 877 878 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 879 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 880 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 881 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 882 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 883 } 884 885 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 886 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 887 888 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 889 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 890 mtk_hdmi_hw_audio_config(hdmi, dst); 891 892 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 893 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 894 else 895 chan_type = hdmi->aud_param.aud_input_chan_type; 896 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 897 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 898 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 899 } 900 901 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 902 struct drm_display_mode *display_mode) 903 { 904 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 905 906 mtk_hdmi_hw_ncts_enable(hdmi, false); 907 mtk_hdmi_hw_aud_src_disable(hdmi); 908 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); 909 910 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 911 switch (sample_rate) { 912 case 32000: 913 case 44100: 914 case 48000: 915 case 88200: 916 case 96000: 917 break; 918 default: 919 return -EINVAL; 920 } 921 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 922 } else { 923 switch (sample_rate) { 924 case 32000: 925 case 44100: 926 case 48000: 927 break; 928 default: 929 return -EINVAL; 930 } 931 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 932 } 933 934 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 935 936 mtk_hdmi_hw_aud_src_reenable(hdmi); 937 return 0; 938 } 939 940 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 941 struct drm_display_mode *display_mode) 942 { 943 mtk_hdmi_hw_aud_mute(hdmi); 944 mtk_hdmi_hw_send_aud_packet(hdmi, false); 945 946 mtk_hdmi_aud_set_input(hdmi); 947 mtk_hdmi_aud_set_src(hdmi, display_mode); 948 mtk_hdmi_hw_aud_set_channel_status(hdmi, 949 hdmi->aud_param.codec_params.iec.status); 950 951 usleep_range(50, 100); 952 953 mtk_hdmi_hw_ncts_enable(hdmi, true); 954 mtk_hdmi_hw_send_aud_packet(hdmi, true); 955 mtk_hdmi_hw_aud_unmute(hdmi); 956 return 0; 957 } 958 959 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 960 struct drm_display_mode *mode) 961 { 962 struct hdmi_avi_infoframe frame; 963 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 964 ssize_t err; 965 966 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 967 hdmi->curr_conn, mode); 968 if (err < 0) { 969 dev_err(hdmi->dev, 970 "Failed to get AVI infoframe from mode: %zd\n", err); 971 return err; 972 } 973 974 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 975 if (err < 0) { 976 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 977 return err; 978 } 979 980 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 981 return 0; 982 } 983 984 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi) 985 { 986 struct drm_bridge *bridge = &hdmi->bridge; 987 struct hdmi_spd_infoframe frame; 988 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; 989 ssize_t err; 990 991 err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product); 992 if (err < 0) { 993 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 994 err); 995 return err; 996 } 997 998 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 999 if (err < 0) { 1000 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 1001 return err; 1002 } 1003 1004 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1005 return 0; 1006 } 1007 1008 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 1009 { 1010 struct hdmi_audio_infoframe frame; 1011 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 1012 ssize_t err; 1013 1014 err = hdmi_audio_infoframe_init(&frame); 1015 if (err < 0) { 1016 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 1017 err); 1018 return err; 1019 } 1020 1021 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 1022 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 1023 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 1024 frame.channels = mtk_hdmi_aud_get_chnl_count( 1025 hdmi->aud_param.aud_input_chan_type); 1026 1027 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 1028 if (err < 0) { 1029 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 1030 err); 1031 return err; 1032 } 1033 1034 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1035 return 0; 1036 } 1037 1038 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 1039 struct drm_display_mode *mode) 1040 { 1041 struct hdmi_vendor_infoframe frame; 1042 u8 buffer[10]; 1043 ssize_t err; 1044 1045 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1046 hdmi->curr_conn, mode); 1047 if (err) { 1048 dev_err(hdmi->dev, 1049 "Failed to get vendor infoframe from mode: %zd\n", err); 1050 return err; 1051 } 1052 1053 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1054 if (err < 0) { 1055 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1056 err); 1057 return err; 1058 } 1059 1060 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1061 return 0; 1062 } 1063 1064 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) 1065 { 1066 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1067 1068 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1069 aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1070 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1071 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1072 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; 1073 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1074 1075 return 0; 1076 } 1077 1078 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 1079 { 1080 mtk_hdmi_hw_send_aud_packet(hdmi, true); 1081 hdmi->audio_enable = true; 1082 } 1083 1084 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 1085 { 1086 mtk_hdmi_hw_send_aud_packet(hdmi, false); 1087 hdmi->audio_enable = false; 1088 } 1089 1090 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, 1091 struct hdmi_audio_param *param) 1092 { 1093 if (!hdmi->audio_enable) { 1094 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1095 return -EINVAL; 1096 } 1097 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", 1098 param->aud_codec, param->aud_input_type, 1099 param->aud_input_chan_type, param->codec_params.sample_rate); 1100 memcpy(&hdmi->aud_param, param, sizeof(*param)); 1101 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1102 } 1103 1104 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 1105 struct drm_display_mode *mode) 1106 { 1107 int ret; 1108 1109 mtk_hdmi_hw_vid_black(hdmi, true); 1110 mtk_hdmi_hw_aud_mute(hdmi); 1111 mtk_hdmi_hw_send_av_mute(hdmi); 1112 phy_power_off(hdmi->phy); 1113 1114 ret = mtk_hdmi_video_change_vpll(hdmi, 1115 mode->clock * 1000); 1116 if (ret) { 1117 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 1118 return ret; 1119 } 1120 mtk_hdmi_video_set_display_mode(hdmi, mode); 1121 1122 phy_power_on(hdmi->phy); 1123 mtk_hdmi_aud_output_config(hdmi, mode); 1124 1125 mtk_hdmi_hw_vid_black(hdmi, false); 1126 mtk_hdmi_hw_aud_unmute(hdmi); 1127 mtk_hdmi_hw_send_av_unmute(hdmi); 1128 1129 return 0; 1130 } 1131 1132 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 1133 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 1134 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 1135 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 1136 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 1137 }; 1138 1139 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, 1140 struct device_node *np) 1141 { 1142 int i; 1143 1144 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { 1145 hdmi->clk[i] = of_clk_get_by_name(np, 1146 mtk_hdmi_clk_names[i]); 1147 if (IS_ERR(hdmi->clk[i])) 1148 return PTR_ERR(hdmi->clk[i]); 1149 } 1150 return 0; 1151 } 1152 1153 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 1154 { 1155 int ret; 1156 1157 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1158 if (ret) 1159 return ret; 1160 1161 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1162 if (ret) { 1163 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1164 return ret; 1165 } 1166 1167 return 0; 1168 } 1169 1170 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 1171 { 1172 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1173 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1174 } 1175 1176 static enum drm_connector_status 1177 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) 1178 { 1179 bool connected; 1180 1181 mutex_lock(&hdmi->update_plugged_status_lock); 1182 connected = mtk_cec_hpd_high(hdmi->cec_dev); 1183 if (hdmi->plugged_cb && hdmi->codec_dev) 1184 hdmi->plugged_cb(hdmi->codec_dev, connected); 1185 mutex_unlock(&hdmi->update_plugged_status_lock); 1186 1187 return connected ? 1188 connector_status_connected : connector_status_disconnected; 1189 } 1190 1191 static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi) 1192 { 1193 return mtk_hdmi_update_plugged_status(hdmi); 1194 } 1195 1196 static enum drm_mode_status 1197 mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 1198 const struct drm_display_info *info, 1199 const struct drm_display_mode *mode) 1200 { 1201 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1202 1203 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1204 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1205 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 1206 1207 if (hdmi->conf) { 1208 if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode)) 1209 return MODE_BAD; 1210 1211 if (hdmi->conf->max_mode_clock && 1212 mode->clock > hdmi->conf->max_mode_clock) 1213 return MODE_CLOCK_HIGH; 1214 } 1215 1216 if (mode->clock < 27000) 1217 return MODE_CLOCK_LOW; 1218 if (mode->clock > 297000) 1219 return MODE_CLOCK_HIGH; 1220 1221 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 1222 } 1223 1224 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 1225 { 1226 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1227 1228 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) { 1229 static enum drm_connector_status status; 1230 1231 status = mtk_hdmi_detect(hdmi); 1232 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 1233 drm_bridge_hpd_notify(&hdmi->bridge, status); 1234 } 1235 } 1236 1237 /* 1238 * Bridge callbacks 1239 */ 1240 1241 static enum drm_connector_status mtk_hdmi_bridge_detect(struct drm_bridge *bridge) 1242 { 1243 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1244 1245 return mtk_hdmi_detect(hdmi); 1246 } 1247 1248 static const struct drm_edid *mtk_hdmi_bridge_edid_read(struct drm_bridge *bridge, 1249 struct drm_connector *connector) 1250 { 1251 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1252 const struct drm_edid *drm_edid; 1253 1254 if (!hdmi->ddc_adpt) 1255 return NULL; 1256 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_adpt); 1257 if (drm_edid) { 1258 /* 1259 * FIXME: This should use !connector->display_info.has_audio (or 1260 * !connector->display_info.is_hdmi) from a path that has read 1261 * the EDID and called drm_edid_connector_update(). 1262 */ 1263 const struct edid *edid = drm_edid_raw(drm_edid); 1264 1265 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 1266 } 1267 1268 return drm_edid; 1269 } 1270 1271 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge, 1272 enum drm_bridge_attach_flags flags) 1273 { 1274 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1275 int ret; 1276 1277 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { 1278 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n", 1279 __func__); 1280 return -EINVAL; 1281 } 1282 1283 if (hdmi->next_bridge) { 1284 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 1285 bridge, flags); 1286 if (ret) 1287 return ret; 1288 } 1289 1290 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 1291 1292 return 0; 1293 } 1294 1295 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1296 const struct drm_display_mode *mode, 1297 struct drm_display_mode *adjusted_mode) 1298 { 1299 return true; 1300 } 1301 1302 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 1303 struct drm_atomic_state *state) 1304 { 1305 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1306 1307 if (!hdmi->enabled) 1308 return; 1309 1310 phy_power_off(hdmi->phy); 1311 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1312 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1313 1314 hdmi->curr_conn = NULL; 1315 1316 hdmi->enabled = false; 1317 } 1318 1319 static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, 1320 struct drm_atomic_state *state) 1321 { 1322 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1323 1324 if (!hdmi->powered) 1325 return; 1326 1327 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1328 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1329 1330 hdmi->powered = false; 1331 } 1332 1333 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1334 const struct drm_display_mode *mode, 1335 const struct drm_display_mode *adjusted_mode) 1336 { 1337 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1338 1339 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", 1340 adjusted_mode->name, adjusted_mode->hdisplay); 1341 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", 1342 adjusted_mode->hsync_start, adjusted_mode->hsync_end, 1343 adjusted_mode->htotal); 1344 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", 1345 adjusted_mode->hskew, adjusted_mode->vdisplay); 1346 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", 1347 adjusted_mode->vsync_start, adjusted_mode->vsync_end, 1348 adjusted_mode->vtotal); 1349 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", 1350 adjusted_mode->vscan, adjusted_mode->flags); 1351 1352 drm_mode_copy(&hdmi->mode, adjusted_mode); 1353 } 1354 1355 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1356 struct drm_atomic_state *state) 1357 { 1358 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1359 1360 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1361 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1362 1363 hdmi->powered = true; 1364 } 1365 1366 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1367 struct drm_display_mode *mode) 1368 { 1369 mtk_hdmi_setup_audio_infoframe(hdmi); 1370 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1371 mtk_hdmi_setup_spd_infoframe(hdmi); 1372 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1373 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1374 } 1375 1376 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 1377 struct drm_atomic_state *state) 1378 { 1379 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1380 1381 /* Retrieve the connector through the atomic state. */ 1382 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, 1383 bridge->encoder); 1384 1385 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1386 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1387 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1388 phy_power_on(hdmi->phy); 1389 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1390 1391 hdmi->enabled = true; 1392 } 1393 1394 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1395 .mode_valid = mtk_hdmi_bridge_mode_valid, 1396 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1397 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1398 .atomic_reset = drm_atomic_helper_bridge_reset, 1399 .attach = mtk_hdmi_bridge_attach, 1400 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1401 .atomic_disable = mtk_hdmi_bridge_atomic_disable, 1402 .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable, 1403 .mode_set = mtk_hdmi_bridge_mode_set, 1404 .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable, 1405 .atomic_enable = mtk_hdmi_bridge_atomic_enable, 1406 .detect = mtk_hdmi_bridge_detect, 1407 .edid_read = mtk_hdmi_bridge_edid_read, 1408 }; 1409 1410 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, 1411 struct platform_device *pdev) 1412 { 1413 struct device *dev = &pdev->dev; 1414 struct device_node *np = dev->of_node; 1415 struct device_node *cec_np, *remote, *i2c_np; 1416 struct platform_device *cec_pdev; 1417 struct regmap *regmap; 1418 int ret; 1419 1420 ret = mtk_hdmi_get_all_clk(hdmi, np); 1421 if (ret) { 1422 if (ret != -EPROBE_DEFER) 1423 dev_err(dev, "Failed to get clocks: %d\n", ret); 1424 1425 return ret; 1426 } 1427 1428 /* The CEC module handles HDMI hotplug detection */ 1429 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); 1430 if (!cec_np) { 1431 dev_err(dev, "Failed to find CEC node\n"); 1432 return -EINVAL; 1433 } 1434 1435 cec_pdev = of_find_device_by_node(cec_np); 1436 if (!cec_pdev) { 1437 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", 1438 cec_np); 1439 of_node_put(cec_np); 1440 return -EPROBE_DEFER; 1441 } 1442 of_node_put(cec_np); 1443 hdmi->cec_dev = &cec_pdev->dev; 1444 1445 /* 1446 * The mediatek,syscon-hdmi property contains a phandle link to the 1447 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG 1448 * registers it contains. 1449 */ 1450 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); 1451 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, 1452 &hdmi->sys_offset); 1453 if (IS_ERR(regmap)) 1454 ret = PTR_ERR(regmap); 1455 if (ret) { 1456 dev_err(dev, 1457 "Failed to get system configuration registers: %d\n", 1458 ret); 1459 goto put_device; 1460 } 1461 hdmi->sys_regmap = regmap; 1462 1463 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 1464 if (IS_ERR(hdmi->regs)) { 1465 ret = PTR_ERR(hdmi->regs); 1466 goto put_device; 1467 } 1468 1469 remote = of_graph_get_remote_node(np, 1, 0); 1470 if (!remote) { 1471 ret = -EINVAL; 1472 goto put_device; 1473 } 1474 1475 if (!of_device_is_compatible(remote, "hdmi-connector")) { 1476 hdmi->next_bridge = of_drm_find_bridge(remote); 1477 if (!hdmi->next_bridge) { 1478 dev_err(dev, "Waiting for external bridge\n"); 1479 of_node_put(remote); 1480 ret = -EPROBE_DEFER; 1481 goto put_device; 1482 } 1483 } 1484 1485 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); 1486 if (!i2c_np) { 1487 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", 1488 remote); 1489 of_node_put(remote); 1490 ret = -EINVAL; 1491 goto put_device; 1492 } 1493 of_node_put(remote); 1494 1495 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); 1496 of_node_put(i2c_np); 1497 if (!hdmi->ddc_adpt) { 1498 dev_err(dev, "Failed to get ddc i2c adapter by node\n"); 1499 ret = -EINVAL; 1500 goto put_device; 1501 } 1502 1503 return 0; 1504 put_device: 1505 put_device(hdmi->cec_dev); 1506 return ret; 1507 } 1508 1509 /* 1510 * HDMI audio codec callbacks 1511 */ 1512 1513 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1514 struct hdmi_codec_daifmt *daifmt, 1515 struct hdmi_codec_params *params) 1516 { 1517 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1518 struct hdmi_audio_param hdmi_params; 1519 unsigned int chan = params->cea.channels; 1520 1521 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1522 params->sample_rate, params->sample_width, chan); 1523 1524 if (!hdmi->bridge.encoder) 1525 return -ENODEV; 1526 1527 switch (chan) { 1528 case 2: 1529 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1530 break; 1531 case 4: 1532 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; 1533 break; 1534 case 6: 1535 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; 1536 break; 1537 case 8: 1538 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; 1539 break; 1540 default: 1541 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); 1542 return -EINVAL; 1543 } 1544 1545 switch (params->sample_rate) { 1546 case 32000: 1547 case 44100: 1548 case 48000: 1549 case 88200: 1550 case 96000: 1551 case 176400: 1552 case 192000: 1553 break; 1554 default: 1555 dev_err(hdmi->dev, "rate[%d] not supported!\n", 1556 params->sample_rate); 1557 return -EINVAL; 1558 } 1559 1560 switch (daifmt->fmt) { 1561 case HDMI_I2S: 1562 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1563 hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1564 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1565 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1566 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1567 break; 1568 case HDMI_SPDIF: 1569 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1570 hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1571 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; 1572 break; 1573 default: 1574 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, 1575 daifmt->fmt); 1576 return -EINVAL; 1577 } 1578 1579 memcpy(&hdmi_params.codec_params, params, 1580 sizeof(hdmi_params.codec_params)); 1581 1582 mtk_hdmi_audio_set_param(hdmi, &hdmi_params); 1583 1584 return 0; 1585 } 1586 1587 static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1588 { 1589 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1590 1591 mtk_hdmi_audio_enable(hdmi); 1592 1593 return 0; 1594 } 1595 1596 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1597 { 1598 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1599 1600 mtk_hdmi_audio_disable(hdmi); 1601 } 1602 1603 static int 1604 mtk_hdmi_audio_mute(struct device *dev, void *data, 1605 bool enable, int direction) 1606 { 1607 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1608 1609 if (enable) 1610 mtk_hdmi_hw_aud_mute(hdmi); 1611 else 1612 mtk_hdmi_hw_aud_unmute(hdmi); 1613 1614 return 0; 1615 } 1616 1617 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1618 { 1619 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1620 1621 if (hdmi->enabled) 1622 memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len)); 1623 else 1624 memset(buf, 0, len); 1625 return 0; 1626 } 1627 1628 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, 1629 hdmi_codec_plugged_cb fn, 1630 struct device *codec_dev) 1631 { 1632 struct mtk_hdmi *hdmi = data; 1633 1634 mutex_lock(&hdmi->update_plugged_status_lock); 1635 hdmi->plugged_cb = fn; 1636 hdmi->codec_dev = codec_dev; 1637 mutex_unlock(&hdmi->update_plugged_status_lock); 1638 1639 mtk_hdmi_update_plugged_status(hdmi); 1640 1641 return 0; 1642 } 1643 1644 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1645 .hw_params = mtk_hdmi_audio_hw_params, 1646 .audio_startup = mtk_hdmi_audio_startup, 1647 .audio_shutdown = mtk_hdmi_audio_shutdown, 1648 .mute_stream = mtk_hdmi_audio_mute, 1649 .get_eld = mtk_hdmi_audio_get_eld, 1650 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, 1651 }; 1652 1653 static void mtk_hdmi_unregister_audio_driver(void *data) 1654 { 1655 platform_device_unregister(data); 1656 } 1657 1658 static int mtk_hdmi_register_audio_driver(struct device *dev) 1659 { 1660 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1661 struct hdmi_codec_pdata codec_data = { 1662 .ops = &mtk_hdmi_audio_codec_ops, 1663 .max_i2s_channels = 2, 1664 .i2s = 1, 1665 .data = hdmi, 1666 .no_capture_mute = 1, 1667 }; 1668 int ret; 1669 1670 hdmi->audio_pdev = platform_device_register_data(dev, 1671 HDMI_CODEC_DRV_NAME, 1672 PLATFORM_DEVID_AUTO, 1673 &codec_data, 1674 sizeof(codec_data)); 1675 if (IS_ERR(hdmi->audio_pdev)) 1676 return PTR_ERR(hdmi->audio_pdev); 1677 1678 ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver, 1679 hdmi->audio_pdev); 1680 if (ret) 1681 return ret; 1682 1683 return 0; 1684 } 1685 1686 static int mtk_hdmi_probe(struct platform_device *pdev) 1687 { 1688 struct mtk_hdmi *hdmi; 1689 struct device *dev = &pdev->dev; 1690 int ret; 1691 1692 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1693 if (!hdmi) 1694 return -ENOMEM; 1695 1696 hdmi->dev = dev; 1697 hdmi->conf = of_device_get_match_data(dev); 1698 1699 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); 1700 if (ret) 1701 return ret; 1702 1703 hdmi->phy = devm_phy_get(dev, "hdmi"); 1704 if (IS_ERR(hdmi->phy)) 1705 return dev_err_probe(dev, PTR_ERR(hdmi->phy), 1706 "Failed to get HDMI PHY\n"); 1707 1708 mutex_init(&hdmi->update_plugged_status_lock); 1709 platform_set_drvdata(pdev, hdmi); 1710 1711 ret = mtk_hdmi_output_init(hdmi); 1712 if (ret) 1713 return dev_err_probe(dev, ret, 1714 "Failed to initialize hdmi output\n"); 1715 1716 ret = mtk_hdmi_register_audio_driver(dev); 1717 if (ret) 1718 return dev_err_probe(dev, ret, 1719 "Failed to register audio driver\n"); 1720 1721 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; 1722 hdmi->bridge.of_node = pdev->dev.of_node; 1723 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 1724 | DRM_BRIDGE_OP_HPD; 1725 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1726 hdmi->bridge.vendor = "MediaTek"; 1727 hdmi->bridge.product = "On-Chip HDMI"; 1728 1729 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 1730 if (ret) 1731 return dev_err_probe(dev, ret, "Failed to add bridge\n"); 1732 1733 ret = mtk_hdmi_clk_enable_audio(hdmi); 1734 if (ret) 1735 return dev_err_probe(dev, ret, 1736 "Failed to enable audio clocks\n"); 1737 1738 return 0; 1739 } 1740 1741 static void mtk_hdmi_remove(struct platform_device *pdev) 1742 { 1743 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1744 1745 mtk_hdmi_clk_disable_audio(hdmi); 1746 } 1747 1748 static __maybe_unused int mtk_hdmi_suspend(struct device *dev) 1749 { 1750 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1751 1752 mtk_hdmi_clk_disable_audio(hdmi); 1753 1754 return 0; 1755 } 1756 1757 static __maybe_unused int mtk_hdmi_resume(struct device *dev) 1758 { 1759 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1760 1761 return mtk_hdmi_clk_enable_audio(hdmi); 1762 } 1763 1764 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume); 1765 1766 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = { 1767 .tz_disabled = true, 1768 }; 1769 1770 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = { 1771 .max_mode_clock = 148500, 1772 .cea_modes_only = true, 1773 }; 1774 1775 static const struct of_device_id mtk_hdmi_of_ids[] = { 1776 { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 }, 1777 { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 }, 1778 { .compatible = "mediatek,mt8173-hdmi" }, 1779 { /* sentinel */ } 1780 }; 1781 MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids); 1782 1783 static struct platform_driver mtk_hdmi_driver = { 1784 .probe = mtk_hdmi_probe, 1785 .remove = mtk_hdmi_remove, 1786 .driver = { 1787 .name = "mediatek-drm-hdmi", 1788 .of_match_table = mtk_hdmi_of_ids, 1789 .pm = &mtk_hdmi_pm_ops, 1790 }, 1791 }; 1792 1793 static struct platform_driver * const mtk_hdmi_drivers[] = { 1794 &mtk_hdmi_ddc_driver, 1795 &mtk_cec_driver, 1796 &mtk_hdmi_driver, 1797 }; 1798 1799 static int __init mtk_hdmitx_init(void) 1800 { 1801 return platform_register_drivers(mtk_hdmi_drivers, 1802 ARRAY_SIZE(mtk_hdmi_drivers)); 1803 } 1804 1805 static void __exit mtk_hdmitx_exit(void) 1806 { 1807 platform_unregister_drivers(mtk_hdmi_drivers, 1808 ARRAY_SIZE(mtk_hdmi_drivers)); 1809 } 1810 1811 module_init(mtk_hdmitx_init); 1812 module_exit(mtk_hdmitx_exit); 1813 1814 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1815 MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1816 MODULE_LICENSE("GPL v2"); 1817