1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
5 */
6
7 #include <linux/device.h>
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/nvmem-provider.h>
11 #include <linux/platform_device.h>
12 #include <linux/property.h>
13
14 struct mtk_efuse_pdata {
15 bool uses_post_processing;
16 };
17
18 struct mtk_efuse_priv {
19 void __iomem *base;
20 };
21
mtk_reg_read(void * context,unsigned int reg,void * _val,size_t bytes)22 static int mtk_reg_read(void *context,
23 unsigned int reg, void *_val, size_t bytes)
24 {
25 struct mtk_efuse_priv *priv = context;
26 void __iomem *addr = priv->base + reg;
27 u8 *val = _val;
28 int i;
29
30 for (i = 0; i < bytes; i++, val++)
31 *val = readb(addr + i);
32
33 return 0;
34 }
35
mtk_efuse_gpu_speedbin_pp(void * context,const char * id,int index,unsigned int offset,void * data,size_t bytes)36 static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index,
37 unsigned int offset, void *data, size_t bytes)
38 {
39 u8 *val = data;
40
41 if (val[0] < 8)
42 val[0] = BIT(val[0]);
43
44 return 0;
45 }
46
mtk_efuse_fixup_dt_cell_info(struct nvmem_device * nvmem,struct nvmem_cell_info * cell)47 static void mtk_efuse_fixup_dt_cell_info(struct nvmem_device *nvmem,
48 struct nvmem_cell_info *cell)
49 {
50 size_t sz = strlen(cell->name);
51
52 /*
53 * On some SoCs, the GPU speedbin is not read as bitmask but as
54 * a number with range [0-7] (max 3 bits): post process to use
55 * it in OPP tables to describe supported-hw.
56 */
57 if (cell->nbits <= 3 &&
58 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0)
59 cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
60 }
61
mtk_efuse_probe(struct platform_device * pdev)62 static int mtk_efuse_probe(struct platform_device *pdev)
63 {
64 struct device *dev = &pdev->dev;
65 struct resource *res;
66 struct nvmem_device *nvmem;
67 struct nvmem_config econfig = {};
68 struct mtk_efuse_priv *priv;
69 const struct mtk_efuse_pdata *pdata;
70 struct platform_device *socinfo;
71
72 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
73 if (!priv)
74 return -ENOMEM;
75
76 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
77 if (IS_ERR(priv->base))
78 return PTR_ERR(priv->base);
79
80 pdata = device_get_match_data(dev);
81 econfig.add_legacy_fixed_of_cells = true;
82 econfig.stride = 1;
83 econfig.word_size = 1;
84 econfig.reg_read = mtk_reg_read;
85 econfig.size = resource_size(res);
86 econfig.priv = priv;
87 econfig.dev = dev;
88 if (pdata->uses_post_processing)
89 econfig.fixup_dt_cell_info = &mtk_efuse_fixup_dt_cell_info;
90 nvmem = devm_nvmem_register(dev, &econfig);
91 if (IS_ERR(nvmem))
92 return PTR_ERR(nvmem);
93
94 socinfo = platform_device_register_data(&pdev->dev, "mtk-socinfo",
95 PLATFORM_DEVID_AUTO, NULL, 0);
96 if (IS_ERR(socinfo))
97 dev_info(dev, "MediaTek SoC Information will be unavailable\n");
98
99 platform_set_drvdata(pdev, socinfo);
100 return 0;
101 }
102
103 static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
104 .uses_post_processing = true,
105 };
106
107 static const struct mtk_efuse_pdata mtk_efuse_pdata = {
108 .uses_post_processing = false,
109 };
110
111 static const struct of_device_id mtk_efuse_of_match[] = {
112 { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
113 { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
114 { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
115 {/* sentinel */},
116 };
117 MODULE_DEVICE_TABLE(of, mtk_efuse_of_match);
118
mtk_efuse_remove(struct platform_device * pdev)119 static void mtk_efuse_remove(struct platform_device *pdev)
120 {
121 struct platform_device *socinfo = platform_get_drvdata(pdev);
122
123 if (!IS_ERR_OR_NULL(socinfo))
124 platform_device_unregister(socinfo);
125 }
126
127 static struct platform_driver mtk_efuse_driver = {
128 .probe = mtk_efuse_probe,
129 .remove = mtk_efuse_remove,
130 .driver = {
131 .name = "mediatek,efuse",
132 .of_match_table = mtk_efuse_of_match,
133 },
134 };
135
mtk_efuse_init(void)136 static int __init mtk_efuse_init(void)
137 {
138 int ret;
139
140 ret = platform_driver_register(&mtk_efuse_driver);
141 if (ret) {
142 pr_err("Failed to register efuse driver\n");
143 return ret;
144 }
145
146 return 0;
147 }
148
mtk_efuse_exit(void)149 static void __exit mtk_efuse_exit(void)
150 {
151 return platform_driver_unregister(&mtk_efuse_driver);
152 }
153
154 subsys_initcall(mtk_efuse_init);
155 module_exit(mtk_efuse_exit);
156
157 MODULE_AUTHOR("Andrew-CT Chen <andrew-ct.chen@mediatek.com>");
158 MODULE_DESCRIPTION("Mediatek EFUSE driver");
159 MODULE_LICENSE("GPL v2");
160