1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/iopoll.h> 10 #include <linux/irq.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/phy/phy.h> 14 #include <linux/platform_device.h> 15 #include <linux/reset.h> 16 #include <linux/units.h> 17 18 #include <video/mipi_display.h> 19 #include <video/videomode.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_bridge_connector.h> 24 #include <drm/drm_mipi_dsi.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_probe_helper.h> 29 #include <drm/drm_simple_kms_helper.h> 30 31 #include "mtk_ddp_comp.h" 32 #include "mtk_disp_drv.h" 33 #include "mtk_drm_drv.h" 34 35 #define DSI_START 0x00 36 37 #define DSI_INTEN 0x08 38 39 #define DSI_INTSTA 0x0c 40 #define LPRX_RD_RDY_INT_FLAG BIT(0) 41 #define CMD_DONE_INT_FLAG BIT(1) 42 #define TE_RDY_INT_FLAG BIT(2) 43 #define VM_DONE_INT_FLAG BIT(3) 44 #define EXT_TE_RDY_INT_FLAG BIT(4) 45 #define DSI_BUSY BIT(31) 46 47 #define DSI_CON_CTRL 0x10 48 #define DSI_RESET BIT(0) 49 #define DSI_EN BIT(1) 50 #define DPHY_RESET BIT(2) 51 52 #define DSI_MODE_CTRL 0x14 53 #define MODE (3) 54 #define CMD_MODE 0 55 #define SYNC_PULSE_MODE 1 56 #define SYNC_EVENT_MODE 2 57 #define BURST_MODE 3 58 #define FRM_MODE BIT(16) 59 #define MIX_MODE BIT(17) 60 61 #define DSI_TXRX_CTRL 0x18 62 #define VC_NUM BIT(1) 63 #define LANE_NUM GENMASK(5, 2) 64 #define DIS_EOT BIT(6) 65 #define NULL_EN BIT(7) 66 #define TE_FREERUN BIT(8) 67 #define EXT_TE_EN BIT(9) 68 #define EXT_TE_EDGE BIT(10) 69 #define MAX_RTN_SIZE GENMASK(15, 12) 70 #define HSTX_CKLP_EN BIT(16) 71 72 #define DSI_PSCTRL 0x1c 73 #define DSI_PS_WC GENMASK(13, 0) 74 #define DSI_PS_SEL GENMASK(17, 16) 75 #define PACKED_PS_16BIT_RGB565 0 76 #define PACKED_PS_18BIT_RGB666 1 77 #define LOOSELY_PS_24BIT_RGB666 2 78 #define PACKED_PS_24BIT_RGB888 3 79 80 #define DSI_VSA_NL 0x20 81 #define DSI_VBP_NL 0x24 82 #define DSI_VFP_NL 0x28 83 #define DSI_VACT_NL 0x2C 84 #define VACT_NL GENMASK(14, 0) 85 #define DSI_SIZE_CON 0x38 86 #define DSI_HEIGHT GENMASK(30, 16) 87 #define DSI_WIDTH GENMASK(14, 0) 88 #define DSI_HSA_WC 0x50 89 #define DSI_HBP_WC 0x54 90 #define DSI_HFP_WC 0x58 91 #define HFP_HS_VB_PS_WC GENMASK(30, 16) 92 #define HFP_HS_EN BIT(31) 93 94 #define DSI_CMDQ_SIZE 0x60 95 #define CMDQ_SIZE 0x3f 96 #define CMDQ_SIZE_SEL BIT(15) 97 98 #define DSI_HSTX_CKL_WC 0x64 99 #define HSTX_CKL_WC GENMASK(15, 2) 100 101 #define DSI_RX_DATA0 0x74 102 #define DSI_RX_DATA1 0x78 103 #define DSI_RX_DATA2 0x7c 104 #define DSI_RX_DATA3 0x80 105 106 #define DSI_RACK 0x84 107 #define RACK BIT(0) 108 109 #define DSI_PHY_LCCON 0x104 110 #define LC_HS_TX_EN BIT(0) 111 #define LC_ULPM_EN BIT(1) 112 #define LC_WAKEUP_EN BIT(2) 113 114 #define DSI_PHY_LD0CON 0x108 115 #define LD0_HS_TX_EN BIT(0) 116 #define LD0_ULPM_EN BIT(1) 117 #define LD0_WAKEUP_EN BIT(2) 118 119 #define DSI_PHY_TIMECON0 0x110 120 #define LPX GENMASK(7, 0) 121 #define HS_PREP GENMASK(15, 8) 122 #define HS_ZERO GENMASK(23, 16) 123 #define HS_TRAIL GENMASK(31, 24) 124 125 #define DSI_PHY_TIMECON1 0x114 126 #define TA_GO GENMASK(7, 0) 127 #define TA_SURE GENMASK(15, 8) 128 #define TA_GET GENMASK(23, 16) 129 #define DA_HS_EXIT GENMASK(31, 24) 130 131 #define DSI_PHY_TIMECON2 0x118 132 #define CONT_DET GENMASK(7, 0) 133 #define DA_HS_SYNC GENMASK(15, 8) 134 #define CLK_ZERO GENMASK(23, 16) 135 #define CLK_TRAIL GENMASK(31, 24) 136 137 #define DSI_PHY_TIMECON3 0x11c 138 #define CLK_HS_PREP GENMASK(7, 0) 139 #define CLK_HS_POST GENMASK(15, 8) 140 #define CLK_HS_EXIT GENMASK(23, 16) 141 142 /* DSI_VM_CMD_CON */ 143 #define VM_CMD_EN BIT(0) 144 #define TS_VFP_EN BIT(5) 145 146 /* DSI_SHADOW_DEBUG */ 147 #define FORCE_COMMIT BIT(0) 148 #define BYPASS_SHADOW BIT(1) 149 150 /* CMDQ related bits */ 151 #define CONFIG GENMASK(7, 0) 152 #define SHORT_PACKET 0 153 #define LONG_PACKET 2 154 #define BTA BIT(2) 155 #define HSTX BIT(3) 156 #define DATA_ID GENMASK(15, 8) 157 #define DATA_0 GENMASK(23, 16) 158 #define DATA_1 GENMASK(31, 24) 159 160 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) 161 162 #define MTK_DSI_HOST_IS_READ(type) \ 163 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 164 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 165 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 166 (type == MIPI_DSI_DCS_READ)) 167 168 struct mtk_phy_timing { 169 u32 lpx; 170 u32 da_hs_prepare; 171 u32 da_hs_zero; 172 u32 da_hs_trail; 173 174 u32 ta_go; 175 u32 ta_sure; 176 u32 ta_get; 177 u32 da_hs_exit; 178 179 u32 clk_hs_zero; 180 u32 clk_hs_trail; 181 182 u32 clk_hs_prepare; 183 u32 clk_hs_post; 184 u32 clk_hs_exit; 185 }; 186 187 struct phy; 188 189 struct mtk_dsi_driver_data { 190 const u32 reg_cmdq_off; 191 const u32 reg_vm_cmd_off; 192 const u32 reg_shadow_dbg_off; 193 bool has_shadow_ctl; 194 bool has_size_ctl; 195 bool cmdq_long_packet_ctl; 196 bool support_per_frame_lp; 197 }; 198 199 struct mtk_dsi { 200 struct device *dev; 201 struct mipi_dsi_host host; 202 struct drm_encoder encoder; 203 struct drm_bridge bridge; 204 struct drm_bridge *next_bridge; 205 struct drm_connector *connector; 206 struct phy *phy; 207 208 void __iomem *regs; 209 210 struct clk *engine_clk; 211 struct clk *digital_clk; 212 struct clk *hs_clk; 213 214 u32 data_rate; 215 216 unsigned long mode_flags; 217 enum mipi_dsi_pixel_format format; 218 unsigned int lanes; 219 struct videomode vm; 220 struct mtk_phy_timing phy_timing; 221 int refcount; 222 bool enabled; 223 bool lanes_ready; 224 u32 irq_data; 225 wait_queue_head_t irq_wait_queue; 226 const struct mtk_dsi_driver_data *driver_data; 227 }; 228 229 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) 230 { 231 return container_of(b, struct mtk_dsi, bridge); 232 } 233 234 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) 235 { 236 return container_of(h, struct mtk_dsi, host); 237 } 238 239 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) 240 { 241 u32 temp = readl(dsi->regs + offset); 242 243 writel((temp & ~mask) | (data & mask), dsi->regs + offset); 244 } 245 246 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 247 { 248 u32 timcon0, timcon1, timcon2, timcon3; 249 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); 250 struct mtk_phy_timing *timing = &dsi->phy_timing; 251 252 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; 253 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; 254 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - 255 timing->da_hs_prepare; 256 timing->da_hs_trail = timing->da_hs_prepare + 1; 257 258 timing->ta_go = 4 * timing->lpx - 2; 259 timing->ta_sure = timing->lpx + 2; 260 timing->ta_get = 4 * timing->lpx; 261 timing->da_hs_exit = 2 * timing->lpx + 1; 262 263 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); 264 timing->clk_hs_post = timing->clk_hs_prepare + 8; 265 timing->clk_hs_trail = timing->clk_hs_prepare; 266 timing->clk_hs_zero = timing->clk_hs_trail * 4; 267 timing->clk_hs_exit = 2 * timing->clk_hs_trail; 268 269 timcon0 = FIELD_PREP(LPX, timing->lpx) | 270 FIELD_PREP(HS_PREP, timing->da_hs_prepare) | 271 FIELD_PREP(HS_ZERO, timing->da_hs_zero) | 272 FIELD_PREP(HS_TRAIL, timing->da_hs_trail); 273 274 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) | 275 FIELD_PREP(TA_SURE, timing->ta_sure) | 276 FIELD_PREP(TA_GET, timing->ta_get) | 277 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit); 278 279 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) | 280 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) | 281 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail); 282 283 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) | 284 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) | 285 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit); 286 287 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); 288 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); 289 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); 290 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); 291 } 292 293 static void mtk_dsi_enable(struct mtk_dsi *dsi) 294 { 295 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); 296 } 297 298 static void mtk_dsi_disable(struct mtk_dsi *dsi) 299 { 300 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); 301 } 302 303 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) 304 { 305 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); 306 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); 307 } 308 309 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi) 310 { 311 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET); 312 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0); 313 } 314 315 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) 316 { 317 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 318 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 319 } 320 321 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) 322 { 323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 324 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); 325 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); 326 } 327 328 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) 329 { 330 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); 331 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 332 } 333 334 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) 335 { 336 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 337 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); 338 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); 339 } 340 341 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) 342 { 343 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN; 344 } 345 346 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) 347 { 348 if (enter && !mtk_dsi_clk_hs_state(dsi)) 349 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); 350 else if (!enter && mtk_dsi_clk_hs_state(dsi)) 351 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 352 } 353 354 static void mtk_dsi_set_mode(struct mtk_dsi *dsi) 355 { 356 u32 vid_mode = CMD_MODE; 357 358 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 359 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 360 vid_mode = BURST_MODE; 361 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 362 vid_mode = SYNC_PULSE_MODE; 363 else 364 vid_mode = SYNC_EVENT_MODE; 365 } 366 367 writel(vid_mode, dsi->regs + DSI_MODE_CTRL); 368 } 369 370 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) 371 { 372 mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN); 373 mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN); 374 } 375 376 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) 377 { 378 u32 regval, tmp_reg = 0; 379 u8 i; 380 381 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */ 382 for (i = 0; i < dsi->lanes; i++) 383 tmp_reg |= BIT(i); 384 385 regval = FIELD_PREP(LANE_NUM, tmp_reg); 386 387 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 388 regval |= HSTX_CKLP_EN; 389 390 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 391 regval |= DIS_EOT; 392 393 writel(regval, dsi->regs + DSI_TXRX_CTRL); 394 } 395 396 static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) 397 { 398 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl; 399 400 if (dsi->format == MIPI_DSI_FMT_RGB565) 401 dsi_buf_bpp = 2; 402 else 403 dsi_buf_bpp = 3; 404 405 /* Word count */ 406 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp); 407 ps_val = ps_wc; 408 409 /* Pixel Stream type */ 410 switch (dsi->format) { 411 default: 412 fallthrough; 413 case MIPI_DSI_FMT_RGB888: 414 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888); 415 break; 416 case MIPI_DSI_FMT_RGB666: 417 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666); 418 break; 419 case MIPI_DSI_FMT_RGB666_PACKED: 420 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666); 421 break; 422 case MIPI_DSI_FMT_RGB565: 423 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565); 424 break; 425 } 426 427 if (config_vact) { 428 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive); 429 writel(vact_nl, dsi->regs + DSI_VACT_NL); 430 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); 431 } 432 writel(ps_val, dsi->regs + DSI_PSCTRL); 433 } 434 435 static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi) 436 { 437 u32 horizontal_sync_active_byte; 438 u32 horizontal_backporch_byte; 439 u32 horizontal_frontporch_byte; 440 u32 hfp_byte_adjust, v_active_adjust; 441 u32 cklp_wc_min_adjust, cklp_wc_max_adjust; 442 u32 dsi_tmp_buf_bpp; 443 unsigned int da_hs_trail; 444 unsigned int ps_wc, hs_vb_ps_wc; 445 u32 v_active_roundup, hstx_cklp_wc; 446 u32 hstx_cklp_wc_max, hstx_cklp_wc_min; 447 struct videomode *vm = &dsi->vm; 448 449 if (dsi->format == MIPI_DSI_FMT_RGB565) 450 dsi_tmp_buf_bpp = 2; 451 else 452 dsi_tmp_buf_bpp = 3; 453 454 da_hs_trail = dsi->phy_timing.da_hs_trail; 455 ps_wc = vm->hactive * dsi_tmp_buf_bpp; 456 457 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 458 horizontal_sync_active_byte = 459 vm->hsync_len * dsi_tmp_buf_bpp - 10; 460 horizontal_backporch_byte = 461 vm->hback_porch * dsi_tmp_buf_bpp - 10; 462 hfp_byte_adjust = 12; 463 v_active_adjust = 32 + horizontal_sync_active_byte; 464 cklp_wc_min_adjust = 12 + 2 + 4 + horizontal_sync_active_byte; 465 cklp_wc_max_adjust = 20 + 6 + 4 + horizontal_sync_active_byte; 466 } else { 467 horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4; 468 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * 469 dsi_tmp_buf_bpp - 10; 470 cklp_wc_min_adjust = 4; 471 cklp_wc_max_adjust = 12 + 4 + 4; 472 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 473 hfp_byte_adjust = 18; 474 v_active_adjust = 28; 475 } else { 476 hfp_byte_adjust = 12; 477 v_active_adjust = 22; 478 } 479 } 480 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp - hfp_byte_adjust; 481 v_active_roundup = (v_active_adjust + horizontal_backporch_byte + ps_wc + 482 horizontal_frontporch_byte) % dsi->lanes; 483 if (v_active_roundup) 484 horizontal_backporch_byte += dsi->lanes - v_active_roundup; 485 hstx_cklp_wc_min = (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_hs_trail + 1) 486 * dsi->lanes / 6 - 1; 487 hstx_cklp_wc_max = (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backporch_byte + 488 ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1; 489 490 hstx_cklp_wc = FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc_max) / 2); 491 writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC); 492 493 hs_vb_ps_wc = ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit + 494 dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * dsi->lanes; 495 horizontal_frontporch_byte |= FIELD_PREP(HFP_HS_EN, 1) | 496 FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc); 497 498 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); 499 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 500 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); 501 } 502 503 static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi) 504 { 505 u32 horizontal_sync_active_byte; 506 u32 horizontal_backporch_byte; 507 u32 horizontal_frontporch_byte; 508 u32 horizontal_front_back_byte; 509 u32 data_phy_cycles_byte; 510 u32 dsi_tmp_buf_bpp, data_phy_cycles; 511 u32 delta; 512 struct mtk_phy_timing *timing = &dsi->phy_timing; 513 struct videomode *vm = &dsi->vm; 514 struct drm_device *drm = dsi->bridge.dev; 515 516 if (dsi->format == MIPI_DSI_FMT_RGB565) 517 dsi_tmp_buf_bpp = 2; 518 else 519 dsi_tmp_buf_bpp = 3; 520 521 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); 522 523 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 524 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10; 525 else 526 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * 527 dsi_tmp_buf_bpp - 10; 528 529 data_phy_cycles = timing->lpx + timing->da_hs_prepare + 530 timing->da_hs_zero + timing->da_hs_exit + 3; 531 532 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; 533 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2; 534 535 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; 536 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; 537 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta; 538 539 if (horizontal_front_back_byte > data_phy_cycles_byte) { 540 horizontal_frontporch_byte -= data_phy_cycles_byte * 541 horizontal_frontporch_byte / 542 horizontal_front_back_byte; 543 544 horizontal_backporch_byte -= data_phy_cycles_byte * 545 horizontal_backporch_byte / 546 horizontal_front_back_byte; 547 } else { 548 drm_warn(drm, "HFP + HBP less than d-phy, FPS will under 60Hz\n"); 549 } 550 551 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) && 552 (dsi->lanes == 4)) { 553 horizontal_sync_active_byte = 554 roundup(horizontal_sync_active_byte, dsi->lanes) - 2; 555 horizontal_frontporch_byte = 556 roundup(horizontal_frontporch_byte, dsi->lanes) - 2; 557 horizontal_backporch_byte = 558 roundup(horizontal_backporch_byte, dsi->lanes) - 2; 559 horizontal_backporch_byte -= 560 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; 561 } 562 563 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); 564 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 565 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); 566 } 567 568 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) 569 { 570 struct videomode *vm = &dsi->vm; 571 572 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); 573 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); 574 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); 575 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 576 577 if (dsi->driver_data->has_size_ctl) 578 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) | 579 FIELD_PREP(DSI_WIDTH, vm->hactive), 580 dsi->regs + DSI_SIZE_CON); 581 582 if (dsi->driver_data->support_per_frame_lp) 583 mtk_dsi_config_vdo_timing_per_frame_lp(dsi); 584 else 585 mtk_dsi_config_vdo_timing_per_line_lp(dsi); 586 587 mtk_dsi_ps_control(dsi, false); 588 } 589 590 static void mtk_dsi_start(struct mtk_dsi *dsi) 591 { 592 writel(0, dsi->regs + DSI_START); 593 writel(1, dsi->regs + DSI_START); 594 } 595 596 static void mtk_dsi_stop(struct mtk_dsi *dsi) 597 { 598 writel(0, dsi->regs + DSI_START); 599 } 600 601 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) 602 { 603 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); 604 } 605 606 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) 607 { 608 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 609 610 writel(inten, dsi->regs + DSI_INTEN); 611 } 612 613 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) 614 { 615 dsi->irq_data |= irq_bit; 616 } 617 618 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) 619 { 620 dsi->irq_data &= ~irq_bit; 621 } 622 623 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, 624 unsigned int timeout) 625 { 626 s32 ret = 0; 627 unsigned long jiffies = msecs_to_jiffies(timeout); 628 struct drm_device *drm = dsi->bridge.dev; 629 630 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, 631 dsi->irq_data & irq_flag, 632 jiffies); 633 if (ret == 0) { 634 drm_warn(drm, "Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); 635 636 mtk_dsi_enable(dsi); 637 mtk_dsi_reset_engine(dsi); 638 } 639 640 return ret; 641 } 642 643 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) 644 { 645 struct mtk_dsi *dsi = dev_id; 646 u32 status, tmp; 647 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 648 649 status = readl(dsi->regs + DSI_INTSTA) & flag; 650 651 if (status) { 652 do { 653 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); 654 tmp = readl(dsi->regs + DSI_INTSTA); 655 } while (tmp & DSI_BUSY); 656 657 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); 658 mtk_dsi_irq_data_set(dsi, status); 659 wake_up_interruptible(&dsi->irq_wait_queue); 660 } 661 662 return IRQ_HANDLED; 663 } 664 665 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) 666 { 667 mtk_dsi_irq_data_clear(dsi, irq_flag); 668 mtk_dsi_set_cmd_mode(dsi); 669 struct drm_device *drm = dsi->bridge.dev; 670 671 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { 672 drm_err(drm, "failed to switch cmd mode\n"); 673 return -ETIME; 674 } else { 675 return 0; 676 } 677 } 678 679 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 680 { 681 if (!dsi->lanes_ready) { 682 dsi->lanes_ready = true; 683 mtk_dsi_rxtx_control(dsi); 684 usleep_range(30, 100); 685 mtk_dsi_reset_dphy(dsi); 686 mtk_dsi_clk_ulp_mode_leave(dsi); 687 mtk_dsi_lane0_ulp_mode_leave(dsi); 688 mtk_dsi_clk_hs_mode(dsi, 0); 689 usleep_range(1000, 3000); 690 /* The reaction time after pulling up the mipi signal for dsi_rx */ 691 } 692 } 693 694 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 695 { 696 struct device *dev = dsi->host.dev; 697 int ret; 698 u32 bit_per_pixel; 699 700 if (++dsi->refcount != 1) 701 return 0; 702 703 ret = mipi_dsi_pixel_format_to_bpp(dsi->format); 704 if (ret < 0) { 705 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format); 706 return ret; 707 } 708 bit_per_pixel = ret; 709 710 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel, 711 dsi->lanes); 712 713 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); 714 if (ret < 0) { 715 dev_err(dev, "Failed to set data rate: %d\n", ret); 716 goto err_refcount; 717 } 718 719 phy_power_on(dsi->phy); 720 721 ret = clk_prepare_enable(dsi->engine_clk); 722 if (ret < 0) { 723 dev_err(dev, "Failed to enable engine clock: %d\n", ret); 724 goto err_phy_power_off; 725 } 726 727 ret = clk_prepare_enable(dsi->digital_clk); 728 if (ret < 0) { 729 dev_err(dev, "Failed to enable digital clock: %d\n", ret); 730 goto err_disable_engine_clk; 731 } 732 733 mtk_dsi_enable(dsi); 734 735 if (dsi->driver_data->has_shadow_ctl) 736 writel(FORCE_COMMIT | BYPASS_SHADOW, 737 dsi->regs + dsi->driver_data->reg_shadow_dbg_off); 738 739 mtk_dsi_reset_engine(dsi); 740 mtk_dsi_phy_timconfig(dsi); 741 742 mtk_dsi_ps_control(dsi, true); 743 mtk_dsi_set_vm_cmd(dsi); 744 mtk_dsi_config_vdo_timing(dsi); 745 mtk_dsi_set_interrupt_enable(dsi); 746 mtk_dsi_lane_ready(dsi); 747 mtk_dsi_clk_hs_mode(dsi, 1); 748 749 return 0; 750 err_disable_engine_clk: 751 clk_disable_unprepare(dsi->engine_clk); 752 err_phy_power_off: 753 phy_power_off(dsi->phy); 754 err_refcount: 755 dsi->refcount--; 756 return ret; 757 } 758 759 static void mtk_dsi_poweroff(struct mtk_dsi *dsi) 760 { 761 if (WARN_ON(dsi->refcount == 0)) 762 return; 763 764 if (--dsi->refcount != 0) 765 return; 766 767 /* 768 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since 769 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(), 770 * which needs irq for vblank, and mtk_dsi_stop() will disable irq. 771 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), 772 * after dsi is fully set. 773 */ 774 mtk_dsi_stop(dsi); 775 776 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 777 mtk_dsi_reset_engine(dsi); 778 mtk_dsi_lane0_ulp_mode_enter(dsi); 779 mtk_dsi_clk_ulp_mode_enter(dsi); 780 /* set the lane number as 0 to pull down mipi */ 781 writel(0, dsi->regs + DSI_TXRX_CTRL); 782 783 mtk_dsi_disable(dsi); 784 785 clk_disable_unprepare(dsi->engine_clk); 786 clk_disable_unprepare(dsi->digital_clk); 787 788 phy_power_off(dsi->phy); 789 790 dsi->lanes_ready = false; 791 } 792 793 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 794 { 795 if (dsi->enabled) 796 return; 797 798 mtk_dsi_set_mode(dsi); 799 mtk_dsi_start(dsi); 800 801 dsi->enabled = true; 802 } 803 804 static void mtk_output_dsi_disable(struct mtk_dsi *dsi) 805 { 806 if (!dsi->enabled) 807 return; 808 809 dsi->enabled = false; 810 } 811 812 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge, 813 struct drm_encoder *encoder, 814 enum drm_bridge_attach_flags flags) 815 { 816 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 817 818 /* Attach the panel or bridge to the dsi bridge */ 819 return drm_bridge_attach(encoder, dsi->next_bridge, 820 &dsi->bridge, flags); 821 } 822 823 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge, 824 const struct drm_display_mode *mode, 825 const struct drm_display_mode *adjusted) 826 { 827 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 828 829 drm_display_mode_to_videomode(adjusted, &dsi->vm); 830 } 831 832 static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge, 833 struct drm_atomic_commit *state) 834 { 835 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 836 837 mtk_output_dsi_disable(dsi); 838 } 839 840 static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 841 struct drm_atomic_commit *state) 842 { 843 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 844 845 if (dsi->refcount == 0) 846 return; 847 848 mtk_output_dsi_enable(dsi); 849 } 850 851 static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 852 struct drm_atomic_commit *state) 853 { 854 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 855 struct drm_device *drm = bridge->dev; 856 int ret; 857 858 ret = mtk_dsi_poweron(dsi); 859 if (ret < 0) 860 drm_err(drm, "failed to power on dsi\n"); 861 } 862 863 static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge, 864 struct drm_atomic_commit *state) 865 { 866 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 867 868 mtk_dsi_poweroff(dsi); 869 } 870 871 static enum drm_mode_status 872 mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge, 873 const struct drm_display_info *info, 874 const struct drm_display_mode *mode) 875 { 876 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 877 int bpp; 878 879 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 880 if (bpp < 0) 881 return MODE_ERROR; 882 883 if (mode->clock * bpp / dsi->lanes > 1500000) 884 return MODE_CLOCK_HIGH; 885 886 return MODE_OK; 887 } 888 889 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { 890 .attach = mtk_dsi_bridge_attach, 891 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 892 .atomic_disable = mtk_dsi_bridge_atomic_disable, 893 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 894 .atomic_enable = mtk_dsi_bridge_atomic_enable, 895 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable, 896 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable, 897 .atomic_reset = drm_atomic_helper_bridge_reset, 898 .mode_valid = mtk_dsi_bridge_mode_valid, 899 .mode_set = mtk_dsi_bridge_mode_set, 900 }; 901 902 void mtk_dsi_ddp_start(struct device *dev) 903 { 904 struct mtk_dsi *dsi = dev_get_drvdata(dev); 905 906 mtk_dsi_poweron(dsi); 907 } 908 909 void mtk_dsi_ddp_stop(struct device *dev) 910 { 911 struct mtk_dsi *dsi = dev_get_drvdata(dev); 912 913 mtk_dsi_poweroff(dsi); 914 } 915 916 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) 917 { 918 int ret; 919 920 ret = drm_simple_encoder_init(drm, &dsi->encoder, 921 DRM_MODE_ENCODER_DSI); 922 if (ret) { 923 drm_err(drm, "Failed to encoder init to drm\n"); 924 return ret; 925 } 926 927 ret = mtk_find_possible_crtcs(drm, dsi->host.dev); 928 if (ret < 0) 929 goto err_cleanup_encoder; 930 dsi->encoder.possible_crtcs = ret; 931 932 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 933 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 934 if (ret) 935 goto err_cleanup_encoder; 936 937 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); 938 if (IS_ERR(dsi->connector)) { 939 drm_err(drm, "Unable to create bridge connector\n"); 940 ret = PTR_ERR(dsi->connector); 941 goto err_cleanup_encoder; 942 } 943 944 return 0; 945 946 err_cleanup_encoder: 947 drm_encoder_cleanup(&dsi->encoder); 948 return ret; 949 } 950 951 unsigned int mtk_dsi_encoder_index(struct device *dev) 952 { 953 struct mtk_dsi *dsi = dev_get_drvdata(dev); 954 unsigned int encoder_index = drm_encoder_index(&dsi->encoder); 955 956 dev_dbg(dev, "encoder index:%d\n", encoder_index); 957 return encoder_index; 958 } 959 960 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 961 { 962 int ret; 963 struct drm_device *drm = data; 964 struct mtk_dsi *dsi = dev_get_drvdata(dev); 965 966 ret = mtk_dsi_encoder_init(drm, dsi); 967 if (ret) 968 return ret; 969 970 return device_reset_optional(dev); 971 } 972 973 static void mtk_dsi_unbind(struct device *dev, struct device *master, 974 void *data) 975 { 976 struct mtk_dsi *dsi = dev_get_drvdata(dev); 977 978 drm_encoder_cleanup(&dsi->encoder); 979 } 980 981 static const struct component_ops mtk_dsi_component_ops = { 982 .bind = mtk_dsi_bind, 983 .unbind = mtk_dsi_unbind, 984 }; 985 986 static int mtk_dsi_host_attach(struct mipi_dsi_host *host, 987 struct mipi_dsi_device *device) 988 { 989 struct mtk_dsi *dsi = host_to_dsi(host); 990 struct device *dev = host->dev; 991 struct drm_device *drm = dsi->bridge.dev; 992 int ret; 993 994 dsi->lanes = device->lanes; 995 dsi->format = device->format; 996 dsi->mode_flags = device->mode_flags; 997 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); 998 if (IS_ERR(dsi->next_bridge)) { 999 ret = PTR_ERR(dsi->next_bridge); 1000 if (ret == -EPROBE_DEFER) 1001 return ret; 1002 1003 /* Old devicetree has only one endpoint */ 1004 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0); 1005 if (IS_ERR(dsi->next_bridge)) 1006 return PTR_ERR(dsi->next_bridge); 1007 } 1008 1009 drm_bridge_add(&dsi->bridge); 1010 1011 ret = component_add(host->dev, &mtk_dsi_component_ops); 1012 if (ret) { 1013 drm_err(drm, "failed to add dsi_host component: %d\n", ret); 1014 drm_bridge_remove(&dsi->bridge); 1015 return ret; 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int mtk_dsi_host_detach(struct mipi_dsi_host *host, 1022 struct mipi_dsi_device *device) 1023 { 1024 struct mtk_dsi *dsi = host_to_dsi(host); 1025 1026 component_del(host->dev, &mtk_dsi_component_ops); 1027 drm_bridge_remove(&dsi->bridge); 1028 return 0; 1029 } 1030 1031 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) 1032 { 1033 int ret; 1034 u32 val; 1035 struct drm_device *drm = dsi->bridge.dev; 1036 1037 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), 1038 4, 2000000); 1039 if (ret) { 1040 drm_warn(drm, "polling dsi wait not busy timeout!\n"); 1041 1042 mtk_dsi_enable(dsi); 1043 mtk_dsi_reset_engine(dsi); 1044 } 1045 } 1046 1047 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) 1048 { 1049 switch (type) { 1050 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1051 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1052 return 1; 1053 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1054 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1055 return 2; 1056 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1057 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1058 return read_data[1] + read_data[2] * 16; 1059 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1060 DRM_INFO("type is 0x02, try again\n"); 1061 break; 1062 default: 1063 DRM_INFO("type(0x%x) not recognized\n", type); 1064 break; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) 1071 { 1072 const char *tx_buf = msg->tx_buf; 1073 u8 config, cmdq_size, cmdq_off, type = msg->type; 1074 u32 reg_val, cmdq_mask, i; 1075 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; 1076 1077 if (MTK_DSI_HOST_IS_READ(type)) 1078 config = BTA; 1079 else 1080 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; 1081 1082 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1083 config |= HSTX; 1084 1085 if (msg->tx_len > 2) { 1086 cmdq_size = 1 + (msg->tx_len + 3) / 4; 1087 cmdq_off = 4; 1088 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; 1089 reg_val = (msg->tx_len << 16) | (type << 8) | config; 1090 } else { 1091 cmdq_size = 1; 1092 cmdq_off = 2; 1093 cmdq_mask = CONFIG | DATA_ID; 1094 reg_val = (type << 8) | config; 1095 } 1096 1097 for (i = 0; i < msg->tx_len; i++) 1098 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), 1099 (0xffUL << (((i + cmdq_off) & 3U) * 8U)), 1100 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); 1101 1102 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); 1103 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); 1104 if (dsi->driver_data->cmdq_long_packet_ctl) { 1105 /* Disable setting cmdq_size automatically for long packets */ 1106 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL); 1107 } 1108 } 1109 1110 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, 1111 const struct mipi_dsi_msg *msg, u8 flag) 1112 { 1113 mtk_dsi_wait_for_idle(dsi); 1114 mtk_dsi_irq_data_clear(dsi, flag); 1115 mtk_dsi_cmdq(dsi, msg); 1116 mtk_dsi_start(dsi); 1117 1118 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) 1119 return -ETIME; 1120 else 1121 return 0; 1122 } 1123 1124 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, 1125 const struct mipi_dsi_msg *msg) 1126 { 1127 struct mtk_dsi *dsi = host_to_dsi(host); 1128 struct drm_device *drm = dsi->bridge.dev; 1129 ssize_t recv_cnt; 1130 u8 read_data[16]; 1131 void *src_addr; 1132 u8 irq_flag = CMD_DONE_INT_FLAG; 1133 u32 dsi_mode; 1134 int ret, i; 1135 1136 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL); 1137 if (dsi_mode & MODE) { 1138 mtk_dsi_stop(dsi); 1139 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 1140 if (ret) 1141 goto restore_dsi_mode; 1142 } 1143 1144 if (MTK_DSI_HOST_IS_READ(msg->type)) 1145 irq_flag |= LPRX_RD_RDY_INT_FLAG; 1146 1147 mtk_dsi_lane_ready(dsi); 1148 1149 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag); 1150 if (ret) 1151 goto restore_dsi_mode; 1152 1153 if (!MTK_DSI_HOST_IS_READ(msg->type)) { 1154 recv_cnt = 0; 1155 goto restore_dsi_mode; 1156 } 1157 1158 if (!msg->rx_buf) { 1159 drm_err(drm, "dsi receive buffer size may be NULL\n"); 1160 ret = -EINVAL; 1161 goto restore_dsi_mode; 1162 } 1163 1164 for (i = 0; i < 16; i++) 1165 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); 1166 1167 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); 1168 1169 if (recv_cnt > 2) 1170 src_addr = &read_data[4]; 1171 else 1172 src_addr = &read_data[1]; 1173 1174 if (recv_cnt > 10) 1175 recv_cnt = 10; 1176 1177 if (recv_cnt > msg->rx_len) 1178 recv_cnt = msg->rx_len; 1179 1180 if (recv_cnt) 1181 memcpy(msg->rx_buf, src_addr, recv_cnt); 1182 1183 drm_info(drm, "dsi get %zd byte data from the panel address(0x%x)\n", 1184 recv_cnt, *((u8 *)(msg->tx_buf))); 1185 1186 restore_dsi_mode: 1187 if (dsi_mode & MODE) { 1188 mtk_dsi_set_mode(dsi); 1189 mtk_dsi_start(dsi); 1190 } 1191 1192 return ret < 0 ? ret : recv_cnt; 1193 } 1194 1195 static const struct mipi_dsi_host_ops mtk_dsi_ops = { 1196 .attach = mtk_dsi_host_attach, 1197 .detach = mtk_dsi_host_detach, 1198 .transfer = mtk_dsi_host_transfer, 1199 }; 1200 1201 static int mtk_dsi_probe(struct platform_device *pdev) 1202 { 1203 struct mtk_dsi *dsi; 1204 struct device *dev = &pdev->dev; 1205 int irq_num; 1206 int ret; 1207 1208 dsi = devm_drm_bridge_alloc(dev, struct mtk_dsi, bridge, 1209 &mtk_dsi_bridge_funcs); 1210 if (IS_ERR(dsi)) 1211 return PTR_ERR(dsi); 1212 1213 dsi->driver_data = of_device_get_match_data(dev); 1214 1215 dsi->engine_clk = devm_clk_get(dev, "engine"); 1216 if (IS_ERR(dsi->engine_clk)) 1217 return dev_err_probe(dev, PTR_ERR(dsi->engine_clk), 1218 "Failed to get engine clock\n"); 1219 1220 1221 dsi->digital_clk = devm_clk_get(dev, "digital"); 1222 if (IS_ERR(dsi->digital_clk)) 1223 return dev_err_probe(dev, PTR_ERR(dsi->digital_clk), 1224 "Failed to get digital clock\n"); 1225 1226 dsi->hs_clk = devm_clk_get(dev, "hs"); 1227 if (IS_ERR(dsi->hs_clk)) 1228 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n"); 1229 1230 dsi->regs = devm_platform_ioremap_resource(pdev, 0); 1231 if (IS_ERR(dsi->regs)) 1232 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n"); 1233 1234 dsi->phy = devm_phy_get(dev, "dphy"); 1235 if (IS_ERR(dsi->phy)) 1236 return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n"); 1237 1238 irq_num = platform_get_irq(pdev, 0); 1239 if (irq_num < 0) 1240 return irq_num; 1241 1242 dsi->host.ops = &mtk_dsi_ops; 1243 dsi->host.dev = dev; 1244 1245 init_waitqueue_head(&dsi->irq_wait_queue); 1246 1247 platform_set_drvdata(pdev, dsi); 1248 1249 ret = mipi_dsi_host_register(&dsi->host); 1250 if (ret < 0) 1251 return dev_err_probe(dev, ret, "Failed to register DSI host\n"); 1252 1253 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, 1254 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi); 1255 if (ret) { 1256 mipi_dsi_host_unregister(&dsi->host); 1257 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n"); 1258 } 1259 1260 dsi->bridge.of_node = dev->of_node; 1261 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1262 1263 return 0; 1264 } 1265 1266 static void mtk_dsi_remove(struct platform_device *pdev) 1267 { 1268 struct mtk_dsi *dsi = platform_get_drvdata(pdev); 1269 1270 mtk_output_dsi_disable(dsi); 1271 mipi_dsi_host_unregister(&dsi->host); 1272 } 1273 1274 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { 1275 .reg_cmdq_off = 0x200, 1276 .reg_vm_cmd_off = 0x130, 1277 .reg_shadow_dbg_off = 0x190 1278 }; 1279 1280 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { 1281 .reg_cmdq_off = 0x180, 1282 .reg_vm_cmd_off = 0x130, 1283 .reg_shadow_dbg_off = 0x190 1284 }; 1285 1286 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { 1287 .reg_cmdq_off = 0x200, 1288 .reg_vm_cmd_off = 0x130, 1289 .reg_shadow_dbg_off = 0x190, 1290 .has_shadow_ctl = true, 1291 .has_size_ctl = true, 1292 }; 1293 1294 static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { 1295 .reg_cmdq_off = 0xd00, 1296 .reg_vm_cmd_off = 0x200, 1297 .reg_shadow_dbg_off = 0xc00, 1298 .has_shadow_ctl = true, 1299 .has_size_ctl = true, 1300 }; 1301 1302 static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { 1303 .reg_cmdq_off = 0xd00, 1304 .reg_vm_cmd_off = 0x200, 1305 .reg_shadow_dbg_off = 0xc00, 1306 .has_shadow_ctl = true, 1307 .has_size_ctl = true, 1308 .cmdq_long_packet_ctl = true, 1309 .support_per_frame_lp = true, 1310 }; 1311 1312 static const struct of_device_id mtk_dsi_of_match[] = { 1313 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data }, 1314 { .compatible = "mediatek,mt8167-dsi", .data = &mt2701_dsi_driver_data }, 1315 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data }, 1316 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data }, 1317 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data }, 1318 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data }, 1319 { /* sentinel */ } 1320 }; 1321 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match); 1322 1323 struct platform_driver mtk_dsi_driver = { 1324 .probe = mtk_dsi_probe, 1325 .remove = mtk_dsi_remove, 1326 .driver = { 1327 .name = "mtk-dsi", 1328 .of_match_table = mtk_dsi_of_match, 1329 }, 1330 }; 1331