1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Authors:
5 * YT Shen <yt.shen@mediatek.com>
6 * CK Hu <ck.hu@mediatek.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
15 #include <drm/drm_print.h>
16
17 #include "mtk_crtc.h"
18 #include "mtk_ddp_comp.h"
19 #include "mtk_disp_drv.h"
20 #include "mtk_drm_drv.h"
21 #include "mtk_plane.h"
22
23
24 #define DISP_REG_DITHER_EN 0x0000
25 #define DITHER_EN BIT(0)
26 #define DISP_REG_DITHER_CFG 0x0020
27 #define DITHER_RELAY_MODE BIT(0)
28 #define DITHER_ENGINE_EN BIT(1)
29 #define DISP_DITHERING BIT(2)
30 #define DISP_REG_DITHER_SIZE 0x0030
31 #define DISP_REG_DITHER_5 0x0114
32 #define DISP_REG_DITHER_7 0x011c
33 #define DISP_REG_DITHER_15 0x013c
34 #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
35 #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
36 #define DITHER_NEW_BIT_MODE BIT(0)
37 #define DISP_REG_DITHER_16 0x0140
38 #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
39 #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
40 #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
41 #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
42
43 #define DISP_REG_DSC_CON 0x0000
44 #define DSC_EN BIT(0)
45 #define DSC_DUAL_INOUT BIT(2)
46 #define DSC_BYPASS BIT(4)
47 #define DSC_UFOE_SEL BIT(16)
48
49 #define DISP_REG_OD_EN 0x0000
50 #define DISP_REG_OD_CFG 0x0020
51 #define OD_RELAYMODE BIT(0)
52 #define DISP_REG_OD_SIZE 0x0030
53
54 #define DISP_REG_POSTMASK_EN 0x0000
55 #define POSTMASK_EN BIT(0)
56 #define DISP_REG_POSTMASK_CFG 0x0020
57 #define POSTMASK_RELAY_MODE BIT(0)
58 #define DISP_REG_POSTMASK_SIZE 0x0030
59
60 #define DISP_REG_UFO_START 0x0000
61 #define UFO_BYPASS BIT(2)
62
63 struct mtk_ddp_comp_dev {
64 struct clk *clk;
65 void __iomem *regs;
66 struct cmdq_client_reg cmdq_reg;
67 };
68
mtk_ddp_write(struct cmdq_pkt * cmdq_pkt,unsigned int value,struct cmdq_client_reg * cmdq_reg,void __iomem * regs,unsigned int offset)69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
71 unsigned int offset)
72 {
73 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
74 if (cmdq_pkt)
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
76 cmdq_reg->offset + offset, value);
77 else
78 #endif
79 writel(value, regs + offset);
80 }
81
mtk_ddp_write_relaxed(struct cmdq_pkt * cmdq_pkt,unsigned int value,struct cmdq_client_reg * cmdq_reg,void __iomem * regs,unsigned int offset)82 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
84 unsigned int offset)
85 {
86 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
87 if (cmdq_pkt)
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
89 cmdq_reg->offset + offset, value);
90 else
91 #endif
92 writel_relaxed(value, regs + offset);
93 }
94
mtk_ddp_write_mask(struct cmdq_pkt * cmdq_pkt,unsigned int value,struct cmdq_client_reg * cmdq_reg,void __iomem * regs,unsigned int offset,unsigned int mask)95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
97 unsigned int offset, unsigned int mask)
98 {
99 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
100 if (cmdq_pkt) {
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
102 cmdq_reg->offset + offset, value, mask);
103 } else {
104 #endif
105 u32 tmp = readl(regs + offset);
106
107 tmp = (tmp & ~mask) | (value & mask);
108 writel(tmp, regs + offset);
109 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
110 }
111 #endif
112 }
113
mtk_ddp_clk_enable(struct device * dev)114 static int mtk_ddp_clk_enable(struct device *dev)
115 {
116 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
117
118 return clk_prepare_enable(priv->clk);
119 }
120
mtk_ddp_clk_disable(struct device * dev)121 static void mtk_ddp_clk_disable(struct device *dev)
122 {
123 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
124
125 clk_disable_unprepare(priv->clk);
126 }
127
mtk_dither_set_common(void __iomem * regs,struct cmdq_client_reg * cmdq_reg,unsigned int bpc,unsigned int cfg,unsigned int dither_en,struct cmdq_pkt * cmdq_pkt)128 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
129 unsigned int bpc, unsigned int cfg,
130 unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
131 {
132 /* If bpc equal to 0, the dithering function didn't be enabled */
133 if (bpc == 0)
134 return;
135
136 if (bpc >= MTK_MIN_BPC) {
137 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
138 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
139 mtk_ddp_write(cmdq_pkt,
140 DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
141 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
142 DITHER_NEW_BIT_MODE,
143 cmdq_reg, regs, DISP_REG_DITHER_15);
144 mtk_ddp_write(cmdq_pkt,
145 DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
146 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
147 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
148 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
149 cmdq_reg, regs, DISP_REG_DITHER_16);
150 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
151 }
152 }
153
mtk_dither_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)154 static void mtk_dither_config(struct device *dev, unsigned int w,
155 unsigned int h, unsigned int vrefresh,
156 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
157 {
158 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
159
160 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
162 DISP_REG_DITHER_CFG);
163 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
164 DITHER_ENGINE_EN, cmdq_pkt);
165 }
166
mtk_dither_start(struct device * dev)167 static void mtk_dither_start(struct device *dev)
168 {
169 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
170
171 writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
172 }
173
mtk_dither_stop(struct device * dev)174 static void mtk_dither_stop(struct device *dev)
175 {
176 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
177
178 writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
179 }
180
mtk_dither_set(struct device * dev,unsigned int bpc,unsigned int cfg,struct cmdq_pkt * cmdq_pkt)181 static void mtk_dither_set(struct device *dev, unsigned int bpc,
182 unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
183 {
184 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
185
186 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
187 DISP_DITHERING, cmdq_pkt);
188 }
189
mtk_dsc_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)190 static void mtk_dsc_config(struct device *dev, unsigned int w,
191 unsigned int h, unsigned int vrefresh,
192 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
193 {
194 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
195
196 /* dsc bypass mode */
197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
198 DISP_REG_DSC_CON, DSC_BYPASS);
199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
200 DISP_REG_DSC_CON, DSC_UFOE_SEL);
201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
202 DISP_REG_DSC_CON, DSC_DUAL_INOUT);
203 }
204
mtk_dsc_start(struct device * dev)205 static void mtk_dsc_start(struct device *dev)
206 {
207 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
208
209 /* write with mask to reserve the value set in mtk_dsc_config */
210 mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
211 }
212
mtk_dsc_stop(struct device * dev)213 static void mtk_dsc_stop(struct device *dev)
214 {
215 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
216
217 writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
218 }
219
mtk_od_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)220 static void mtk_od_config(struct device *dev, unsigned int w,
221 unsigned int h, unsigned int vrefresh,
222 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
223 {
224 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
225
226 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
228 mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
229 }
230
mtk_od_start(struct device * dev)231 static void mtk_od_start(struct device *dev)
232 {
233 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
234
235 writel(1, priv->regs + DISP_REG_OD_EN);
236 }
237
mtk_postmask_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)238 static void mtk_postmask_config(struct device *dev, unsigned int w,
239 unsigned int h, unsigned int vrefresh,
240 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
241 {
242 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
243
244 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
245 DISP_REG_POSTMASK_SIZE);
246 mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
247 priv->regs, DISP_REG_POSTMASK_CFG);
248 }
249
mtk_postmask_start(struct device * dev)250 static void mtk_postmask_start(struct device *dev)
251 {
252 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
253
254 writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
255 }
256
mtk_postmask_stop(struct device * dev)257 static void mtk_postmask_stop(struct device *dev)
258 {
259 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
260
261 writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
262 }
263
mtk_ufoe_start(struct device * dev)264 static void mtk_ufoe_start(struct device *dev)
265 {
266 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
267
268 writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
269 }
270
271 static const struct mtk_ddp_comp_funcs ddp_aal = {
272 .clk_enable = mtk_aal_clk_enable,
273 .clk_disable = mtk_aal_clk_disable,
274 .gamma_get_lut_size = mtk_aal_gamma_get_lut_size,
275 .gamma_set = mtk_aal_gamma_set,
276 .config = mtk_aal_config,
277 .start = mtk_aal_start,
278 .stop = mtk_aal_stop,
279 };
280
281 static const struct mtk_ddp_comp_funcs ddp_ccorr = {
282 .clk_enable = mtk_ccorr_clk_enable,
283 .clk_disable = mtk_ccorr_clk_disable,
284 .config = mtk_ccorr_config,
285 .start = mtk_ccorr_start,
286 .stop = mtk_ccorr_stop,
287 .ctm_set = mtk_ccorr_ctm_set,
288 };
289
290 static const struct mtk_ddp_comp_funcs ddp_color = {
291 .clk_enable = mtk_color_clk_enable,
292 .clk_disable = mtk_color_clk_disable,
293 .config = mtk_color_config,
294 .start = mtk_color_start,
295 };
296
297 static const struct mtk_ddp_comp_funcs ddp_dither = {
298 .clk_enable = mtk_ddp_clk_enable,
299 .clk_disable = mtk_ddp_clk_disable,
300 .config = mtk_dither_config,
301 .start = mtk_dither_start,
302 .stop = mtk_dither_stop,
303 };
304
305 static const struct mtk_ddp_comp_funcs ddp_dpi = {
306 .start = mtk_dpi_start,
307 .stop = mtk_dpi_stop,
308 .encoder_index = mtk_dpi_encoder_index,
309 };
310
311 static const struct mtk_ddp_comp_funcs ddp_dsc = {
312 .clk_enable = mtk_ddp_clk_enable,
313 .clk_disable = mtk_ddp_clk_disable,
314 .config = mtk_dsc_config,
315 .start = mtk_dsc_start,
316 .stop = mtk_dsc_stop,
317 };
318
319 static const struct mtk_ddp_comp_funcs ddp_dsi = {
320 .start = mtk_dsi_ddp_start,
321 .stop = mtk_dsi_ddp_stop,
322 .encoder_index = mtk_dsi_encoder_index,
323 };
324
325 static const struct mtk_ddp_comp_funcs ddp_gamma = {
326 .clk_enable = mtk_gamma_clk_enable,
327 .clk_disable = mtk_gamma_clk_disable,
328 .gamma_get_lut_size = mtk_gamma_get_lut_size,
329 .gamma_set = mtk_gamma_set,
330 .config = mtk_gamma_config,
331 .start = mtk_gamma_start,
332 .stop = mtk_gamma_stop,
333 };
334
335 static const struct mtk_ddp_comp_funcs ddp_merge = {
336 .clk_enable = mtk_merge_clk_enable,
337 .clk_disable = mtk_merge_clk_disable,
338 .start = mtk_merge_start,
339 .stop = mtk_merge_stop,
340 .config = mtk_merge_config,
341 };
342
343 static const struct mtk_ddp_comp_funcs ddp_od = {
344 .clk_enable = mtk_ddp_clk_enable,
345 .clk_disable = mtk_ddp_clk_disable,
346 .config = mtk_od_config,
347 .start = mtk_od_start,
348 };
349
350 static const struct mtk_ddp_comp_funcs ddp_ovl = {
351 .clk_enable = mtk_ovl_clk_enable,
352 .clk_disable = mtk_ovl_clk_disable,
353 .config = mtk_ovl_config,
354 .start = mtk_ovl_start,
355 .stop = mtk_ovl_stop,
356 .register_vblank_cb = mtk_ovl_register_vblank_cb,
357 .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
358 .enable_vblank = mtk_ovl_enable_vblank,
359 .disable_vblank = mtk_ovl_disable_vblank,
360 .supported_rotations = mtk_ovl_supported_rotations,
361 .layer_nr = mtk_ovl_layer_nr,
362 .layer_check = mtk_ovl_layer_check,
363 .layer_config = mtk_ovl_layer_config,
364 .bgclr_in_on = mtk_ovl_bgclr_in_on,
365 .bgclr_in_off = mtk_ovl_bgclr_in_off,
366 .get_formats = mtk_ovl_get_formats,
367 .get_num_formats = mtk_ovl_get_num_formats,
368 };
369
370 static const struct mtk_ddp_comp_funcs ddp_postmask = {
371 .clk_enable = mtk_ddp_clk_enable,
372 .clk_disable = mtk_ddp_clk_disable,
373 .config = mtk_postmask_config,
374 .start = mtk_postmask_start,
375 .stop = mtk_postmask_stop,
376 };
377
378 static const struct mtk_ddp_comp_funcs ddp_rdma = {
379 .clk_enable = mtk_rdma_clk_enable,
380 .clk_disable = mtk_rdma_clk_disable,
381 .config = mtk_rdma_config,
382 .start = mtk_rdma_start,
383 .stop = mtk_rdma_stop,
384 .register_vblank_cb = mtk_rdma_register_vblank_cb,
385 .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
386 .enable_vblank = mtk_rdma_enable_vblank,
387 .disable_vblank = mtk_rdma_disable_vblank,
388 .layer_nr = mtk_rdma_layer_nr,
389 .layer_config = mtk_rdma_layer_config,
390 .get_formats = mtk_rdma_get_formats,
391 .get_num_formats = mtk_rdma_get_num_formats,
392 };
393
394 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
395 .clk_enable = mtk_ddp_clk_enable,
396 .clk_disable = mtk_ddp_clk_disable,
397 .start = mtk_ufoe_start,
398 };
399
400 static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
401 .power_on = mtk_ovl_adaptor_power_on,
402 .power_off = mtk_ovl_adaptor_power_off,
403 .clk_enable = mtk_ovl_adaptor_clk_enable,
404 .clk_disable = mtk_ovl_adaptor_clk_disable,
405 .config = mtk_ovl_adaptor_config,
406 .start = mtk_ovl_adaptor_start,
407 .stop = mtk_ovl_adaptor_stop,
408 .layer_nr = mtk_ovl_adaptor_layer_nr,
409 .layer_config = mtk_ovl_adaptor_layer_config,
410 .register_vblank_cb = mtk_ovl_adaptor_register_vblank_cb,
411 .unregister_vblank_cb = mtk_ovl_adaptor_unregister_vblank_cb,
412 .enable_vblank = mtk_ovl_adaptor_enable_vblank,
413 .disable_vblank = mtk_ovl_adaptor_disable_vblank,
414 .dma_dev_get = mtk_ovl_adaptor_dma_dev_get,
415 .connect = mtk_ovl_adaptor_connect,
416 .disconnect = mtk_ovl_adaptor_disconnect,
417 .add = mtk_ovl_adaptor_add_comp,
418 .remove = mtk_ovl_adaptor_remove_comp,
419 .get_formats = mtk_ovl_adaptor_get_formats,
420 .get_num_formats = mtk_ovl_adaptor_get_num_formats,
421 .mode_valid = mtk_ovl_adaptor_mode_valid,
422 };
423
424 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
425 [MTK_DISP_AAL] = "aal",
426 [MTK_DISP_BLS] = "bls",
427 [MTK_DISP_CCORR] = "ccorr",
428 [MTK_DISP_COLOR] = "color",
429 [MTK_DISP_DITHER] = "dither",
430 [MTK_DISP_DSC] = "dsc",
431 [MTK_DISP_GAMMA] = "gamma",
432 [MTK_DISP_MERGE] = "merge",
433 [MTK_DISP_MUTEX] = "mutex",
434 [MTK_DISP_OD] = "od",
435 [MTK_DISP_OVL] = "ovl",
436 [MTK_DISP_OVL_2L] = "ovl-2l",
437 [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
438 [MTK_DISP_POSTMASK] = "postmask",
439 [MTK_DISP_PWM] = "pwm",
440 [MTK_DISP_RDMA] = "rdma",
441 [MTK_DISP_UFOE] = "ufoe",
442 [MTK_DISP_WDMA] = "wdma",
443 [MTK_DP_INTF] = "dp-intf",
444 [MTK_DPI] = "dpi",
445 [MTK_DSI] = "dsi",
446 };
447
448 struct mtk_ddp_comp_match {
449 enum mtk_ddp_comp_type type;
450 int alias_id;
451 const struct mtk_ddp_comp_funcs *funcs;
452 };
453
454 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
455 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
456 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
457 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
458 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
459 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
460 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
461 [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
462 [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
463 [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
464 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
465 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
466 [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
467 [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
468 [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
469 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
470 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
471 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
472 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
473 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
474 [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
475 [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
476 [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
477 [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
478 [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
479 [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
480 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
481 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
482 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
483 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
484 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
485 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
486 [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
487 [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
488 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
489 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
490 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
491 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
492 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
493 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
494 [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
495 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
496 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
497 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
498 };
499
mtk_ddp_comp_find(struct device * dev,const unsigned int * path,unsigned int path_len,struct mtk_ddp_comp * ddp_comp)500 static bool mtk_ddp_comp_find(struct device *dev,
501 const unsigned int *path,
502 unsigned int path_len,
503 struct mtk_ddp_comp *ddp_comp)
504 {
505 unsigned int i;
506
507 if (path == NULL)
508 return false;
509
510 for (i = 0U; i < path_len; i++)
511 if (dev == ddp_comp[path[i]].dev)
512 return true;
513
514 return false;
515 }
516
mtk_ddp_comp_find_in_route(struct device * dev,const struct mtk_drm_route * routes,unsigned int num_routes,struct mtk_ddp_comp * ddp_comp)517 static int mtk_ddp_comp_find_in_route(struct device *dev,
518 const struct mtk_drm_route *routes,
519 unsigned int num_routes,
520 struct mtk_ddp_comp *ddp_comp)
521 {
522 unsigned int i;
523
524 if (!routes)
525 return -EINVAL;
526
527 for (i = 0; i < num_routes; i++)
528 if (dev == ddp_comp[routes[i].route_ddp].dev)
529 return BIT(routes[i].crtc_id);
530
531 return -ENODEV;
532 }
533
mtk_ddp_path_available(const unsigned int * path,unsigned int path_len,struct device_node ** comp_node)534 static bool mtk_ddp_path_available(const unsigned int *path,
535 unsigned int path_len,
536 struct device_node **comp_node)
537 {
538 unsigned int i;
539
540 if (!path || !path_len)
541 return false;
542
543 for (i = 0U; i < path_len; i++) {
544 /* OVL_ADAPTOR doesn't have a device node */
545 if (path[i] == DDP_COMPONENT_DRM_OVL_ADAPTOR)
546 continue;
547
548 if (!comp_node[path[i]])
549 return false;
550 }
551
552 return true;
553 }
554
mtk_ddp_comp_get_id(struct device_node * node,enum mtk_ddp_comp_type comp_type)555 int mtk_ddp_comp_get_id(struct device_node *node,
556 enum mtk_ddp_comp_type comp_type)
557 {
558 int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
559 int i;
560
561 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
562 if (comp_type == mtk_ddp_matches[i].type &&
563 (id < 0 || id == mtk_ddp_matches[i].alias_id))
564 return i;
565 }
566
567 return -EINVAL;
568 }
569
mtk_find_possible_crtcs(struct drm_device * drm,struct device * dev)570 int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
571 {
572 struct mtk_drm_private *private = drm->dev_private;
573 const struct mtk_mmsys_driver_data *data;
574 struct mtk_drm_private *priv_n;
575 int i = 0, j;
576 int ret;
577
578 for (j = 0; j < private->data->mmsys_dev_num; j++) {
579 priv_n = private->all_drm_private[j];
580 data = priv_n->data;
581
582 if (mtk_ddp_path_available(data->main_path, data->main_len,
583 priv_n->comp_node)) {
584 if (mtk_ddp_comp_find(dev, data->main_path,
585 data->main_len,
586 priv_n->ddp_comp))
587 return BIT(i);
588 i++;
589 }
590
591 if (mtk_ddp_path_available(data->ext_path, data->ext_len,
592 priv_n->comp_node)) {
593 if (mtk_ddp_comp_find(dev, data->ext_path,
594 data->ext_len,
595 priv_n->ddp_comp))
596 return BIT(i);
597 i++;
598 }
599
600 if (mtk_ddp_path_available(data->third_path, data->third_len,
601 priv_n->comp_node)) {
602 if (mtk_ddp_comp_find(dev, data->third_path,
603 data->third_len,
604 priv_n->ddp_comp))
605 return BIT(i);
606 i++;
607 }
608 }
609
610 ret = mtk_ddp_comp_find_in_route(dev,
611 private->data->conn_routes,
612 private->data->num_conn_routes,
613 private->ddp_comp);
614
615 if (ret < 0)
616 DRM_INFO("Failed to find comp in ddp table, ret = %d\n", ret);
617
618 return ret;
619 }
620
mtk_ddp_comp_init(struct device_node * node,struct mtk_ddp_comp * comp,unsigned int comp_id)621 int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
622 unsigned int comp_id)
623 {
624 struct platform_device *comp_pdev;
625 enum mtk_ddp_comp_type type;
626 struct mtk_ddp_comp_dev *priv;
627 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
628 int ret;
629 #endif
630
631 if (comp_id >= DDP_COMPONENT_DRM_ID_MAX)
632 return -EINVAL;
633
634 type = mtk_ddp_matches[comp_id].type;
635
636 comp->id = comp_id;
637 comp->funcs = mtk_ddp_matches[comp_id].funcs;
638 /* Not all drm components have a DTS device node, such as ovl_adaptor,
639 * which is the drm bring up sub driver
640 */
641 if (!node)
642 return 0;
643
644 comp_pdev = of_find_device_by_node(node);
645 if (!comp_pdev) {
646 DRM_INFO("Waiting for device %s\n", node->full_name);
647 return -EPROBE_DEFER;
648 }
649 comp->dev = &comp_pdev->dev;
650
651 if (type == MTK_DISP_AAL ||
652 type == MTK_DISP_BLS ||
653 type == MTK_DISP_CCORR ||
654 type == MTK_DISP_COLOR ||
655 type == MTK_DISP_GAMMA ||
656 type == MTK_DISP_MERGE ||
657 type == MTK_DISP_OVL ||
658 type == MTK_DISP_OVL_2L ||
659 type == MTK_DISP_PWM ||
660 type == MTK_DISP_RDMA ||
661 type == MTK_DPI ||
662 type == MTK_DP_INTF ||
663 type == MTK_DSI)
664 return 0;
665
666 priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
667 if (!priv)
668 return -ENOMEM;
669
670 priv->regs = of_iomap(node, 0);
671 priv->clk = of_clk_get(node, 0);
672 if (IS_ERR(priv->clk))
673 return PTR_ERR(priv->clk);
674
675 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
676 ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
677 if (ret)
678 dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
679 #endif
680
681 platform_set_drvdata(comp_pdev, priv);
682
683 return 0;
684 }
685