1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/completion.h>
36 #include <linux/pci.h>
37 #include <linux/errno.h>
38 #include <linux/sched.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41 #include <asm/io.h>
42 #include <rdma/ib_mad.h>
43
44 #include "mthca_dev.h"
45 #include "mthca_config_reg.h"
46 #include "mthca_cmd.h"
47 #include "mthca_memfree.h"
48
49 #define CMD_POLL_TOKEN 0xffff
50
51 enum {
52 HCR_IN_PARAM_OFFSET = 0x00,
53 HCR_IN_MODIFIER_OFFSET = 0x08,
54 HCR_OUT_PARAM_OFFSET = 0x0c,
55 HCR_TOKEN_OFFSET = 0x14,
56 HCR_STATUS_OFFSET = 0x18,
57
58 HCR_OPMOD_SHIFT = 12,
59 HCA_E_BIT = 22,
60 HCR_GO_BIT = 23
61 };
62
63 enum {
64 /* initialization and general commands */
65 CMD_SYS_EN = 0x1,
66 CMD_SYS_DIS = 0x2,
67 CMD_MAP_FA = 0xfff,
68 CMD_UNMAP_FA = 0xffe,
69 CMD_RUN_FW = 0xff6,
70 CMD_MOD_STAT_CFG = 0x34,
71 CMD_QUERY_DEV_LIM = 0x3,
72 CMD_QUERY_FW = 0x4,
73 CMD_ENABLE_LAM = 0xff8,
74 CMD_DISABLE_LAM = 0xff7,
75 CMD_QUERY_DDR = 0x5,
76 CMD_QUERY_ADAPTER = 0x6,
77 CMD_INIT_HCA = 0x7,
78 CMD_CLOSE_HCA = 0x8,
79 CMD_INIT_IB = 0x9,
80 CMD_CLOSE_IB = 0xa,
81 CMD_QUERY_HCA = 0xb,
82 CMD_SET_IB = 0xc,
83 CMD_ACCESS_DDR = 0x2e,
84 CMD_MAP_ICM = 0xffa,
85 CMD_UNMAP_ICM = 0xff9,
86 CMD_MAP_ICM_AUX = 0xffc,
87 CMD_UNMAP_ICM_AUX = 0xffb,
88 CMD_SET_ICM_SIZE = 0xffd,
89
90 /* TPT commands */
91 CMD_SW2HW_MPT = 0xd,
92 CMD_QUERY_MPT = 0xe,
93 CMD_HW2SW_MPT = 0xf,
94 CMD_READ_MTT = 0x10,
95 CMD_WRITE_MTT = 0x11,
96 CMD_SYNC_TPT = 0x2f,
97
98 /* EQ commands */
99 CMD_MAP_EQ = 0x12,
100 CMD_SW2HW_EQ = 0x13,
101 CMD_HW2SW_EQ = 0x14,
102 CMD_QUERY_EQ = 0x15,
103
104 /* CQ commands */
105 CMD_SW2HW_CQ = 0x16,
106 CMD_HW2SW_CQ = 0x17,
107 CMD_QUERY_CQ = 0x18,
108 CMD_RESIZE_CQ = 0x2c,
109
110 /* SRQ commands */
111 CMD_SW2HW_SRQ = 0x35,
112 CMD_HW2SW_SRQ = 0x36,
113 CMD_QUERY_SRQ = 0x37,
114 CMD_ARM_SRQ = 0x40,
115
116 /* QP/EE commands */
117 CMD_RST2INIT_QPEE = 0x19,
118 CMD_INIT2RTR_QPEE = 0x1a,
119 CMD_RTR2RTS_QPEE = 0x1b,
120 CMD_RTS2RTS_QPEE = 0x1c,
121 CMD_SQERR2RTS_QPEE = 0x1d,
122 CMD_2ERR_QPEE = 0x1e,
123 CMD_RTS2SQD_QPEE = 0x1f,
124 CMD_SQD2SQD_QPEE = 0x38,
125 CMD_SQD2RTS_QPEE = 0x20,
126 CMD_ERR2RST_QPEE = 0x21,
127 CMD_QUERY_QPEE = 0x22,
128 CMD_INIT2INIT_QPEE = 0x2d,
129 CMD_SUSPEND_QPEE = 0x32,
130 CMD_UNSUSPEND_QPEE = 0x33,
131 /* special QPs and management commands */
132 CMD_CONF_SPECIAL_QP = 0x23,
133 CMD_MAD_IFC = 0x24,
134
135 /* multicast commands */
136 CMD_READ_MGM = 0x25,
137 CMD_WRITE_MGM = 0x26,
138 CMD_MGID_HASH = 0x27,
139
140 /* miscellaneous commands */
141 CMD_DIAG_RPRT = 0x30,
142 CMD_NOP = 0x31,
143
144 /* debug commands */
145 CMD_QUERY_DEBUG_MSG = 0x2a,
146 CMD_SET_DEBUG_MSG = 0x2b,
147 };
148
149 /*
150 * According to Mellanox code, FW may be starved and never complete
151 * commands. So we can't use strict timeouts described in PRM -- we
152 * just arbitrarily select 60 seconds for now.
153 */
154 #if 0
155 /*
156 * Round up and add 1 to make sure we get the full wait time (since we
157 * will be starting in the middle of a jiffy)
158 */
159 enum {
160 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
161 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
162 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
163 CMD_TIME_CLASS_D = 60 * HZ
164 };
165 #else
166 enum {
167 CMD_TIME_CLASS_A = 60 * HZ,
168 CMD_TIME_CLASS_B = 60 * HZ,
169 CMD_TIME_CLASS_C = 60 * HZ,
170 CMD_TIME_CLASS_D = 60 * HZ
171 };
172 #endif
173
174 enum {
175 GO_BIT_TIMEOUT = HZ * 10
176 };
177
178 struct mthca_cmd_context {
179 struct completion done;
180 int result;
181 int next;
182 u64 out_param;
183 u16 token;
184 u8 status;
185 };
186
187 static int fw_cmd_doorbell = 0;
188 module_param(fw_cmd_doorbell, int, 0644);
189 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
190 "(and supported by FW)");
191
go_bit(struct mthca_dev * dev)192 static inline int go_bit(struct mthca_dev *dev)
193 {
194 return readl(dev->hcr + HCR_STATUS_OFFSET) &
195 swab32(1 << HCR_GO_BIT);
196 }
197
mthca_cmd_post_dbell(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token)198 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
199 u64 in_param,
200 u64 out_param,
201 u32 in_modifier,
202 u8 op_modifier,
203 u16 op,
204 u16 token)
205 {
206 void __iomem *ptr = dev->cmd.dbell_map;
207 u16 *offs = dev->cmd.dbell_offsets;
208
209 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
210 wmb();
211 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
212 wmb();
213 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
214 wmb();
215 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
216 wmb();
217 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
218 wmb();
219 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
220 wmb();
221 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
222 (1 << HCA_E_BIT) |
223 (op_modifier << HCR_OPMOD_SHIFT) |
224 op), ptr + offs[6]);
225 wmb();
226 __raw_writel((__force u32) 0, ptr + offs[7]);
227 wmb();
228 }
229
mthca_cmd_post_hcr(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)230 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
231 u64 in_param,
232 u64 out_param,
233 u32 in_modifier,
234 u8 op_modifier,
235 u16 op,
236 u16 token,
237 int event)
238 {
239 if (event) {
240 unsigned long end = jiffies + GO_BIT_TIMEOUT;
241
242 while (go_bit(dev) && time_before(jiffies, end)) {
243 set_current_state(TASK_RUNNING);
244 schedule();
245 }
246 }
247
248 if (go_bit(dev))
249 return -EAGAIN;
250
251 /*
252 * We use writel (instead of something like memcpy_toio)
253 * because writes of less than 32 bits to the HCR don't work
254 * (and some architectures such as ia64 implement memcpy_toio
255 * in terms of writeb).
256 */
257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
260 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
261 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
262 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
263
264 /* __raw_writel may not order writes. */
265 wmb();
266
267 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
268 (event ? (1 << HCA_E_BIT) : 0) |
269 (op_modifier << HCR_OPMOD_SHIFT) |
270 op), dev->hcr + 6 * 4);
271
272 return 0;
273 }
274
mthca_cmd_post(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)275 static int mthca_cmd_post(struct mthca_dev *dev,
276 u64 in_param,
277 u64 out_param,
278 u32 in_modifier,
279 u8 op_modifier,
280 u16 op,
281 u16 token,
282 int event)
283 {
284 int err = 0;
285
286 mutex_lock(&dev->cmd.hcr_mutex);
287
288 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
289 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
290 op_modifier, op, token);
291 else
292 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
293 op_modifier, op, token, event);
294
295 mutex_unlock(&dev->cmd.hcr_mutex);
296 return err;
297 }
298
299
mthca_status_to_errno(u8 status)300 static int mthca_status_to_errno(u8 status)
301 {
302 static const int trans_table[] = {
303 [MTHCA_CMD_STAT_INTERNAL_ERR] = -EIO,
304 [MTHCA_CMD_STAT_BAD_OP] = -EPERM,
305 [MTHCA_CMD_STAT_BAD_PARAM] = -EINVAL,
306 [MTHCA_CMD_STAT_BAD_SYS_STATE] = -ENXIO,
307 [MTHCA_CMD_STAT_BAD_RESOURCE] = -EBADF,
308 [MTHCA_CMD_STAT_RESOURCE_BUSY] = -EBUSY,
309 [MTHCA_CMD_STAT_DDR_MEM_ERR] = -ENOMEM,
310 [MTHCA_CMD_STAT_EXCEED_LIM] = -ENOMEM,
311 [MTHCA_CMD_STAT_BAD_RES_STATE] = -EBADF,
312 [MTHCA_CMD_STAT_BAD_INDEX] = -EBADF,
313 [MTHCA_CMD_STAT_BAD_NVMEM] = -EFAULT,
314 [MTHCA_CMD_STAT_BAD_QPEE_STATE] = -EINVAL,
315 [MTHCA_CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
316 [MTHCA_CMD_STAT_REG_BOUND] = -EBUSY,
317 [MTHCA_CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
318 [MTHCA_CMD_STAT_BAD_PKT] = -EBADMSG,
319 [MTHCA_CMD_STAT_BAD_SIZE] = -ENOMEM,
320 };
321
322 if (status >= ARRAY_SIZE(trans_table) ||
323 (status != MTHCA_CMD_STAT_OK
324 && trans_table[status] == 0))
325 return -EINVAL;
326
327 return trans_table[status];
328 }
329
330
mthca_cmd_poll(struct mthca_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)331 static int mthca_cmd_poll(struct mthca_dev *dev,
332 u64 in_param,
333 u64 *out_param,
334 int out_is_imm,
335 u32 in_modifier,
336 u8 op_modifier,
337 u16 op,
338 unsigned long timeout)
339 {
340 int err = 0;
341 unsigned long end;
342 u8 status;
343
344 down(&dev->cmd.poll_sem);
345
346 err = mthca_cmd_post(dev, in_param,
347 out_param ? *out_param : 0,
348 in_modifier, op_modifier,
349 op, CMD_POLL_TOKEN, 0);
350 if (err)
351 goto out;
352
353 end = timeout + jiffies;
354 while (go_bit(dev) && time_before(jiffies, end)) {
355 set_current_state(TASK_RUNNING);
356 schedule();
357 }
358
359 if (go_bit(dev)) {
360 err = -EBUSY;
361 goto out;
362 }
363
364 if (out_is_imm && out_param) {
365 *out_param =
366 (u64) be32_to_cpu((__force __be32)
367 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
368 (u64) be32_to_cpu((__force __be32)
369 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
370 } else if (out_is_imm) {
371 err = -EINVAL;
372 goto out;
373 }
374
375 status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
376 if (status) {
377 mthca_dbg(dev, "Command %02x completed with status %02x\n",
378 op, status);
379 err = mthca_status_to_errno(status);
380 }
381
382 out:
383 up(&dev->cmd.poll_sem);
384 return err;
385 }
386
mthca_cmd_event(struct mthca_dev * dev,u16 token,u8 status,u64 out_param)387 void mthca_cmd_event(struct mthca_dev *dev,
388 u16 token,
389 u8 status,
390 u64 out_param)
391 {
392 struct mthca_cmd_context *context =
393 &dev->cmd.context[token & dev->cmd.token_mask];
394
395 /* previously timed out command completing at long last */
396 if (token != context->token)
397 return;
398
399 context->result = 0;
400 context->status = status;
401 context->out_param = out_param;
402
403 complete(&context->done);
404 }
405
mthca_cmd_wait(struct mthca_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)406 static int mthca_cmd_wait(struct mthca_dev *dev,
407 u64 in_param,
408 u64 *out_param,
409 int out_is_imm,
410 u32 in_modifier,
411 u8 op_modifier,
412 u16 op,
413 unsigned long timeout)
414 {
415 int err = 0;
416 struct mthca_cmd_context *context;
417
418 down(&dev->cmd.event_sem);
419
420 spin_lock(&dev->cmd.context_lock);
421 BUG_ON(dev->cmd.free_head < 0);
422 context = &dev->cmd.context[dev->cmd.free_head];
423 context->token += dev->cmd.token_mask + 1;
424 dev->cmd.free_head = context->next;
425 spin_unlock(&dev->cmd.context_lock);
426
427 init_completion(&context->done);
428
429 err = mthca_cmd_post(dev, in_param,
430 out_param ? *out_param : 0,
431 in_modifier, op_modifier,
432 op, context->token, 1);
433 if (err)
434 goto out;
435
436 if (!wait_for_completion_timeout(&context->done, timeout)) {
437 err = -EBUSY;
438 goto out;
439 }
440
441 err = context->result;
442 if (err)
443 goto out;
444
445 if (context->status) {
446 mthca_dbg(dev, "Command %02x completed with status %02x\n",
447 op, context->status);
448 err = mthca_status_to_errno(context->status);
449 }
450
451 if (out_is_imm && out_param) {
452 *out_param = context->out_param;
453 } else if (out_is_imm) {
454 err = -EINVAL;
455 goto out;
456 }
457
458 out:
459 spin_lock(&dev->cmd.context_lock);
460 context->next = dev->cmd.free_head;
461 dev->cmd.free_head = context - dev->cmd.context;
462 spin_unlock(&dev->cmd.context_lock);
463
464 up(&dev->cmd.event_sem);
465 return err;
466 }
467
468 /* Invoke a command with an output mailbox */
mthca_cmd_box(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)469 static int mthca_cmd_box(struct mthca_dev *dev,
470 u64 in_param,
471 u64 out_param,
472 u32 in_modifier,
473 u8 op_modifier,
474 u16 op,
475 unsigned long timeout)
476 {
477 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
478 return mthca_cmd_wait(dev, in_param, &out_param, 0,
479 in_modifier, op_modifier, op,
480 timeout);
481 else
482 return mthca_cmd_poll(dev, in_param, &out_param, 0,
483 in_modifier, op_modifier, op,
484 timeout);
485 }
486
487 /* Invoke a command with no output parameter */
mthca_cmd(struct mthca_dev * dev,u64 in_param,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)488 static int mthca_cmd(struct mthca_dev *dev,
489 u64 in_param,
490 u32 in_modifier,
491 u8 op_modifier,
492 u16 op,
493 unsigned long timeout)
494 {
495 return mthca_cmd_box(dev, in_param, 0, in_modifier,
496 op_modifier, op, timeout);
497 }
498
499 /*
500 * Invoke a command with an immediate output parameter (and copy the
501 * output into the caller's out_param pointer after the command
502 * executes).
503 */
mthca_cmd_imm(struct mthca_dev * dev,u64 in_param,u64 * out_param,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)504 static int mthca_cmd_imm(struct mthca_dev *dev,
505 u64 in_param,
506 u64 *out_param,
507 u32 in_modifier,
508 u8 op_modifier,
509 u16 op,
510 unsigned long timeout)
511 {
512 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
513 return mthca_cmd_wait(dev, in_param, out_param, 1,
514 in_modifier, op_modifier, op,
515 timeout);
516 else
517 return mthca_cmd_poll(dev, in_param, out_param, 1,
518 in_modifier, op_modifier, op,
519 timeout);
520 }
521
mthca_cmd_init(struct mthca_dev * dev)522 int mthca_cmd_init(struct mthca_dev *dev)
523 {
524 mutex_init(&dev->cmd.hcr_mutex);
525 sema_init(&dev->cmd.poll_sem, 1);
526 dev->cmd.flags = 0;
527
528 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
529 MTHCA_HCR_SIZE);
530 if (!dev->hcr) {
531 mthca_err(dev, "Couldn't map command register.");
532 return -ENOMEM;
533 }
534
535 dev->cmd.pool = dma_pool_create("mthca_cmd", &dev->pdev->dev,
536 MTHCA_MAILBOX_SIZE,
537 MTHCA_MAILBOX_SIZE, 0);
538 if (!dev->cmd.pool) {
539 iounmap(dev->hcr);
540 return -ENOMEM;
541 }
542
543 return 0;
544 }
545
mthca_cmd_cleanup(struct mthca_dev * dev)546 void mthca_cmd_cleanup(struct mthca_dev *dev)
547 {
548 dma_pool_destroy(dev->cmd.pool);
549 iounmap(dev->hcr);
550 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
551 iounmap(dev->cmd.dbell_map);
552 }
553
554 /*
555 * Switch to using events to issue FW commands (should be called after
556 * event queue to command events has been initialized).
557 */
mthca_cmd_use_events(struct mthca_dev * dev)558 int mthca_cmd_use_events(struct mthca_dev *dev)
559 {
560 int i;
561
562 dev->cmd.context = kmalloc_objs(struct mthca_cmd_context,
563 dev->cmd.max_cmds);
564 if (!dev->cmd.context)
565 return -ENOMEM;
566
567 for (i = 0; i < dev->cmd.max_cmds; ++i) {
568 dev->cmd.context[i].token = i;
569 dev->cmd.context[i].next = i + 1;
570 }
571
572 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
573 dev->cmd.free_head = 0;
574
575 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
576 spin_lock_init(&dev->cmd.context_lock);
577
578 for (dev->cmd.token_mask = 1;
579 dev->cmd.token_mask < dev->cmd.max_cmds;
580 dev->cmd.token_mask <<= 1)
581 ; /* nothing */
582 --dev->cmd.token_mask;
583
584 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
585
586 down(&dev->cmd.poll_sem);
587
588 return 0;
589 }
590
591 /*
592 * Switch back to polling (used when shutting down the device)
593 */
mthca_cmd_use_polling(struct mthca_dev * dev)594 void mthca_cmd_use_polling(struct mthca_dev *dev)
595 {
596 int i;
597
598 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
599
600 for (i = 0; i < dev->cmd.max_cmds; ++i)
601 down(&dev->cmd.event_sem);
602
603 kfree(dev->cmd.context);
604
605 up(&dev->cmd.poll_sem);
606 }
607
mthca_alloc_mailbox(struct mthca_dev * dev,gfp_t gfp_mask)608 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
609 gfp_t gfp_mask)
610 {
611 struct mthca_mailbox *mailbox;
612
613 mailbox = kmalloc_obj(*mailbox, gfp_mask);
614 if (!mailbox)
615 return ERR_PTR(-ENOMEM);
616
617 mailbox->buf = dma_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
618 if (!mailbox->buf) {
619 kfree(mailbox);
620 return ERR_PTR(-ENOMEM);
621 }
622
623 return mailbox;
624 }
625
mthca_free_mailbox(struct mthca_dev * dev,struct mthca_mailbox * mailbox)626 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
627 {
628 if (!mailbox)
629 return;
630
631 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
632 kfree(mailbox);
633 }
634
mthca_SYS_EN(struct mthca_dev * dev)635 int mthca_SYS_EN(struct mthca_dev *dev)
636 {
637 u64 out = 0;
638 int ret;
639
640 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D);
641
642 if (ret == -ENOMEM)
643 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
644 "sladdr=%d, SPD source=%s\n",
645 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
646 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
647
648 return ret;
649 }
650
mthca_SYS_DIS(struct mthca_dev * dev)651 int mthca_SYS_DIS(struct mthca_dev *dev)
652 {
653 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
654 }
655
mthca_map_cmd(struct mthca_dev * dev,u16 op,struct mthca_icm * icm,u64 virt)656 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
657 u64 virt)
658 {
659 struct mthca_mailbox *mailbox;
660 struct mthca_icm_iter iter;
661 __be64 *pages;
662 int lg;
663 int nent = 0;
664 int i;
665 int err = 0;
666 int ts = 0, tc = 0;
667
668 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
669 if (IS_ERR(mailbox))
670 return PTR_ERR(mailbox);
671 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
672 pages = mailbox->buf;
673
674 for (mthca_icm_first(icm, &iter);
675 !mthca_icm_last(&iter);
676 mthca_icm_next(&iter)) {
677 /*
678 * We have to pass pages that are aligned to their
679 * size, so find the least significant 1 in the
680 * address or size and use that as our log2 size.
681 */
682 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
683 if (lg < MTHCA_ICM_PAGE_SHIFT) {
684 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
685 MTHCA_ICM_PAGE_SIZE,
686 (unsigned long long) mthca_icm_addr(&iter),
687 mthca_icm_size(&iter));
688 err = -EINVAL;
689 goto out;
690 }
691 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
692 if (virt != -1) {
693 pages[nent * 2] = cpu_to_be64(virt);
694 virt += 1ULL << lg;
695 }
696
697 pages[nent * 2 + 1] =
698 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
699 (lg - MTHCA_ICM_PAGE_SHIFT));
700 ts += 1 << (lg - 10);
701 ++tc;
702
703 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
704 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
705 CMD_TIME_CLASS_B);
706 if (err)
707 goto out;
708 nent = 0;
709 }
710 }
711 }
712
713 if (nent)
714 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
715 CMD_TIME_CLASS_B);
716
717 switch (op) {
718 case CMD_MAP_FA:
719 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
720 break;
721 case CMD_MAP_ICM_AUX:
722 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
723 break;
724 case CMD_MAP_ICM:
725 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
726 tc, ts, (unsigned long long) virt - (ts << 10));
727 break;
728 }
729
730 out:
731 mthca_free_mailbox(dev, mailbox);
732 return err;
733 }
734
mthca_MAP_FA(struct mthca_dev * dev,struct mthca_icm * icm)735 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm)
736 {
737 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1);
738 }
739
mthca_UNMAP_FA(struct mthca_dev * dev)740 int mthca_UNMAP_FA(struct mthca_dev *dev)
741 {
742 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B);
743 }
744
mthca_RUN_FW(struct mthca_dev * dev)745 int mthca_RUN_FW(struct mthca_dev *dev)
746 {
747 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A);
748 }
749
mthca_setup_cmd_doorbells(struct mthca_dev * dev,u64 base)750 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
751 {
752 phys_addr_t addr;
753 u16 max_off = 0;
754 int i;
755
756 for (i = 0; i < 8; ++i)
757 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
758
759 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
760 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
761 "length 0x%x crosses a page boundary\n",
762 (unsigned long long) base, max_off);
763 return;
764 }
765
766 addr = pci_resource_start(dev->pdev, 2) +
767 ((pci_resource_len(dev->pdev, 2) - 1) & base);
768 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
769 if (!dev->cmd.dbell_map)
770 return;
771
772 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
773 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
774 }
775
mthca_QUERY_FW(struct mthca_dev * dev)776 int mthca_QUERY_FW(struct mthca_dev *dev)
777 {
778 struct mthca_mailbox *mailbox;
779 u32 *outbox;
780 u64 base;
781 u32 tmp;
782 int err = 0;
783 u8 lg;
784 int i;
785
786 #define QUERY_FW_OUT_SIZE 0x100
787 #define QUERY_FW_VER_OFFSET 0x00
788 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
789 #define QUERY_FW_ERR_START_OFFSET 0x30
790 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
791
792 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
793 #define QUERY_FW_CMD_DB_OFFSET 0x50
794 #define QUERY_FW_CMD_DB_BASE 0x60
795
796 #define QUERY_FW_START_OFFSET 0x20
797 #define QUERY_FW_END_OFFSET 0x28
798
799 #define QUERY_FW_SIZE_OFFSET 0x00
800 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
801 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
802 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
803
804 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
805 if (IS_ERR(mailbox))
806 return PTR_ERR(mailbox);
807 outbox = mailbox->buf;
808
809 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
810 CMD_TIME_CLASS_A);
811
812 if (err)
813 goto out;
814
815 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
816 /*
817 * FW subminor version is at more significant bits than minor
818 * version, so swap here.
819 */
820 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
821 ((dev->fw_ver & 0xffff0000ull) >> 16) |
822 ((dev->fw_ver & 0x0000ffffull) << 16);
823
824 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
825 dev->cmd.max_cmds = 1 << lg;
826
827 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
828 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
829
830 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
831 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
832
833 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
834 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
835
836 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
837 if (tmp & 0x1) {
838 mthca_dbg(dev, "FW supports commands through doorbells\n");
839
840 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
841 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
842 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
843 QUERY_FW_CMD_DB_OFFSET + (i << 1));
844
845 mthca_setup_cmd_doorbells(dev, base);
846 }
847
848 if (mthca_is_memfree(dev)) {
849 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
850 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
851 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
852 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
853 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
854
855 /*
856 * Round up number of system pages needed in case
857 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
858 */
859 dev->fw.arbel.fw_pages =
860 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
861 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
862
863 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
864 (unsigned long long) dev->fw.arbel.clr_int_base,
865 (unsigned long long) dev->fw.arbel.eq_arm_base,
866 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
867 } else {
868 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
869 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
870
871 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
872 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
873 (unsigned long long) dev->fw.tavor.fw_start,
874 (unsigned long long) dev->fw.tavor.fw_end);
875 }
876
877 out:
878 mthca_free_mailbox(dev, mailbox);
879 return err;
880 }
881
mthca_ENABLE_LAM(struct mthca_dev * dev)882 int mthca_ENABLE_LAM(struct mthca_dev *dev)
883 {
884 struct mthca_mailbox *mailbox;
885 u8 info;
886 u32 *outbox;
887 int err = 0;
888
889 #define ENABLE_LAM_OUT_SIZE 0x100
890 #define ENABLE_LAM_START_OFFSET 0x00
891 #define ENABLE_LAM_END_OFFSET 0x08
892 #define ENABLE_LAM_INFO_OFFSET 0x13
893
894 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
895 #define ENABLE_LAM_INFO_ECC_MASK 0x3
896
897 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
898 if (IS_ERR(mailbox))
899 return PTR_ERR(mailbox);
900 outbox = mailbox->buf;
901
902 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
903 CMD_TIME_CLASS_C);
904
905 if (err)
906 goto out;
907
908 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
909 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
910 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
911
912 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
913 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
914 mthca_info(dev, "FW reports that HCA-attached memory "
915 "is %s hidden; does not match PCI config\n",
916 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
917 "" : "not");
918 }
919 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
920 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
921
922 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
923 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
924 (unsigned long long) dev->ddr_start,
925 (unsigned long long) dev->ddr_end);
926
927 out:
928 mthca_free_mailbox(dev, mailbox);
929 return err;
930 }
931
mthca_DISABLE_LAM(struct mthca_dev * dev)932 int mthca_DISABLE_LAM(struct mthca_dev *dev)
933 {
934 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
935 }
936
mthca_QUERY_DDR(struct mthca_dev * dev)937 int mthca_QUERY_DDR(struct mthca_dev *dev)
938 {
939 struct mthca_mailbox *mailbox;
940 u8 info;
941 u32 *outbox;
942 int err = 0;
943
944 #define QUERY_DDR_OUT_SIZE 0x100
945 #define QUERY_DDR_START_OFFSET 0x00
946 #define QUERY_DDR_END_OFFSET 0x08
947 #define QUERY_DDR_INFO_OFFSET 0x13
948
949 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
950 #define QUERY_DDR_INFO_ECC_MASK 0x3
951
952 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
953 if (IS_ERR(mailbox))
954 return PTR_ERR(mailbox);
955 outbox = mailbox->buf;
956
957 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
958 CMD_TIME_CLASS_A);
959
960 if (err)
961 goto out;
962
963 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
964 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
965 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
966
967 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
968 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
969 mthca_info(dev, "FW reports that HCA-attached memory "
970 "is %s hidden; does not match PCI config\n",
971 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
972 "" : "not");
973 }
974 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
975 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
976
977 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
978 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
979 (unsigned long long) dev->ddr_start,
980 (unsigned long long) dev->ddr_end);
981
982 out:
983 mthca_free_mailbox(dev, mailbox);
984 return err;
985 }
986
mthca_QUERY_DEV_LIM(struct mthca_dev * dev,struct mthca_dev_lim * dev_lim)987 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
988 struct mthca_dev_lim *dev_lim)
989 {
990 struct mthca_mailbox *mailbox;
991 u32 *outbox;
992 u8 field;
993 u16 size;
994 u16 stat_rate;
995 int err;
996
997 #define QUERY_DEV_LIM_OUT_SIZE 0x100
998 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
999 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
1000 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
1001 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
1002 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
1003 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
1004 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
1005 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
1006 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
1007 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
1008 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
1009 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
1010 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
1011 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
1012 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
1013 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
1014 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
1015 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
1016 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
1017 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
1018 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
1019 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
1020 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
1021 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
1022 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
1023 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
1024 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
1025 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
1026 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
1027 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
1028 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
1029 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
1030 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
1031 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
1032 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
1033 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
1034 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1035 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1036 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1037 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1038 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1039 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1040 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1041 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1042 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1043 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1044 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1045 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1046 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1047 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1048 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1049 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1050 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1051 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1052 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1053 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1054 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1055 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1056 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1057
1058 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1059 if (IS_ERR(mailbox))
1060 return PTR_ERR(mailbox);
1061 outbox = mailbox->buf;
1062
1063 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1064 CMD_TIME_CLASS_A);
1065
1066 if (err)
1067 goto out;
1068
1069 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1070 dev_lim->reserved_qps = 1 << (field & 0xf);
1071 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1072 dev_lim->max_qps = 1 << (field & 0x1f);
1073 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1074 dev_lim->reserved_srqs = 1 << (field >> 4);
1075 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1076 dev_lim->max_srqs = 1 << (field & 0x1f);
1077 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1078 dev_lim->reserved_eecs = 1 << (field & 0xf);
1079 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1080 dev_lim->max_eecs = 1 << (field & 0x1f);
1081 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1082 dev_lim->max_cq_sz = 1 << field;
1083 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1084 dev_lim->reserved_cqs = 1 << (field & 0xf);
1085 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1086 dev_lim->max_cqs = 1 << (field & 0x1f);
1087 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1088 dev_lim->max_mpts = 1 << (field & 0x3f);
1089 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1090 dev_lim->reserved_eqs = 1 << (field & 0xf);
1091 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1092 dev_lim->max_eqs = 1 << (field & 0x7);
1093 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1094 if (mthca_is_memfree(dev))
1095 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
1096 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
1097 else
1098 dev_lim->reserved_mtts = 1 << (field >> 4);
1099 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1100 dev_lim->max_mrw_sz = 1 << field;
1101 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1102 dev_lim->reserved_mrws = 1 << (field & 0xf);
1103 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1104 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1105 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1106 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1107 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1108 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1109 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1110 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1111 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1112 dev_lim->local_ca_ack_delay = field & 0x1f;
1113 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1114 dev_lim->max_mtu = field >> 4;
1115 dev_lim->max_port_width = field & 0xf;
1116 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1117 dev_lim->max_vl = field >> 4;
1118 dev_lim->num_ports = field & 0xf;
1119 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1120 dev_lim->max_gids = 1 << (field & 0xf);
1121 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1122 dev_lim->stat_rate_support = stat_rate;
1123 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1124 dev_lim->max_pkeys = 1 << (field & 0xf);
1125 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1126 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1127 dev_lim->reserved_uars = field >> 4;
1128 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1129 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1130 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1131 dev_lim->min_page_sz = 1 << field;
1132 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1133 dev_lim->max_sg = field;
1134
1135 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1136 dev_lim->max_desc_sz = size;
1137
1138 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1139 dev_lim->max_qp_per_mcg = 1 << field;
1140 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1141 dev_lim->reserved_mgms = field & 0xf;
1142 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1143 dev_lim->max_mcgs = 1 << field;
1144 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1145 dev_lim->reserved_pds = field >> 4;
1146 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1147 dev_lim->max_pds = 1 << (field & 0x3f);
1148 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1149 dev_lim->reserved_rdds = field >> 4;
1150 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1151 dev_lim->max_rdds = 1 << (field & 0x3f);
1152
1153 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1154 dev_lim->eec_entry_sz = size;
1155 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1156 dev_lim->qpc_entry_sz = size;
1157 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1158 dev_lim->eeec_entry_sz = size;
1159 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1160 dev_lim->eqpc_entry_sz = size;
1161 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1162 dev_lim->eqc_entry_sz = size;
1163 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1164 dev_lim->cqc_entry_sz = size;
1165 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1166 dev_lim->srq_entry_sz = size;
1167 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1168 dev_lim->uar_scratch_entry_sz = size;
1169
1170 if (mthca_is_memfree(dev)) {
1171 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1172 dev_lim->max_srq_sz = 1 << field;
1173 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1174 dev_lim->max_qp_sz = 1 << field;
1175 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1176 dev_lim->hca.arbel.resize_srq = field & 1;
1177 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1178 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1179 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1180 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1181 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1182 dev_lim->mpt_entry_sz = size;
1183 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1184 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1185 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1186 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1187 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1188 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1189 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1190 dev_lim->hca.arbel.lam_required = field & 1;
1191 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1192 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1193
1194 if (dev_lim->hca.arbel.bmme_flags & 1)
1195 mthca_dbg(dev, "Base MM extensions: yes "
1196 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1197 dev_lim->hca.arbel.bmme_flags,
1198 dev_lim->hca.arbel.max_pbl_sz,
1199 dev_lim->hca.arbel.reserved_lkey);
1200 else
1201 mthca_dbg(dev, "Base MM extensions: no\n");
1202
1203 mthca_dbg(dev, "Max ICM size %lld MB\n",
1204 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1205 } else {
1206 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1207 dev_lim->max_srq_sz = (1 << field) - 1;
1208 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1209 dev_lim->max_qp_sz = (1 << field) - 1;
1210 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1211 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1212 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1213 }
1214
1215 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1216 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1217 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1218 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1219 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1220 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1221 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1222 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1223 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1224 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1225 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1226 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1227 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1228 dev_lim->max_pds, dev_lim->reserved_mgms);
1229 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1230 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1231
1232 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1233
1234 out:
1235 mthca_free_mailbox(dev, mailbox);
1236 return err;
1237 }
1238
get_board_id(void * vsd,char * board_id)1239 static void get_board_id(void *vsd, char *board_id)
1240 {
1241 int i;
1242
1243 #define VSD_OFFSET_SIG1 0x00
1244 #define VSD_OFFSET_SIG2 0xde
1245 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1246 #define VSD_OFFSET_TS_BOARD_ID 0x20
1247
1248 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1249
1250 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1251
1252 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1253 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1254 strscpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1255 } else {
1256 /*
1257 * The board ID is a string but the firmware byte
1258 * swaps each 4-byte word before passing it back to
1259 * us. Therefore we need to swab it before printing.
1260 */
1261 for (i = 0; i < 4; ++i)
1262 ((u32 *) board_id)[i] =
1263 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1264 }
1265 }
1266
mthca_QUERY_ADAPTER(struct mthca_dev * dev,struct mthca_adapter * adapter)1267 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1268 struct mthca_adapter *adapter)
1269 {
1270 struct mthca_mailbox *mailbox;
1271 u32 *outbox;
1272 int err;
1273
1274 #define QUERY_ADAPTER_OUT_SIZE 0x100
1275 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1276 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1277 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1278 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1279 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1280
1281 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1282 if (IS_ERR(mailbox))
1283 return PTR_ERR(mailbox);
1284 outbox = mailbox->buf;
1285
1286 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1287 CMD_TIME_CLASS_A);
1288
1289 if (err)
1290 goto out;
1291
1292 if (!mthca_is_memfree(dev)) {
1293 MTHCA_GET(adapter->vendor_id, outbox,
1294 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1295 MTHCA_GET(adapter->device_id, outbox,
1296 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1297 MTHCA_GET(adapter->revision_id, outbox,
1298 QUERY_ADAPTER_REVISION_ID_OFFSET);
1299 }
1300 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1301
1302 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1303 adapter->board_id);
1304
1305 out:
1306 mthca_free_mailbox(dev, mailbox);
1307 return err;
1308 }
1309
mthca_INIT_HCA(struct mthca_dev * dev,struct mthca_init_hca_param * param)1310 int mthca_INIT_HCA(struct mthca_dev *dev,
1311 struct mthca_init_hca_param *param)
1312 {
1313 struct mthca_mailbox *mailbox;
1314 __be32 *inbox;
1315 int err;
1316
1317 #define INIT_HCA_IN_SIZE 0x200
1318 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1319 #define INIT_HCA_FLAGS2_OFFSET 0x014
1320 #define INIT_HCA_QPC_OFFSET 0x020
1321 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1322 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1323 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1324 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1325 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1326 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1327 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1328 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1329 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1330 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1331 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1332 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1333 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1334 #define INIT_HCA_UDAV_OFFSET 0x0b0
1335 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1336 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1337 #define INIT_HCA_MCAST_OFFSET 0x0c0
1338 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1339 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1340 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1341 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1342 #define INIT_HCA_TPT_OFFSET 0x0f0
1343 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1344 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1345 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1346 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1347 #define INIT_HCA_UAR_OFFSET 0x120
1348 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1349 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1350 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1351 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1352 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1353 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1354
1355 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1356 if (IS_ERR(mailbox))
1357 return PTR_ERR(mailbox);
1358 inbox = mailbox->buf;
1359
1360 memset(inbox, 0, INIT_HCA_IN_SIZE);
1361
1362 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1363 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1364
1365 #if defined(__LITTLE_ENDIAN)
1366 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1367 #elif defined(__BIG_ENDIAN)
1368 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1369 #else
1370 #error Host endianness not defined
1371 #endif
1372 /* Check port for UD address vector: */
1373 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1374
1375 /* Enable IPoIB checksumming if we can: */
1376 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1377 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1378
1379 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1380
1381 /* QPC/EEC/CQC/EQC/RDB attributes */
1382
1383 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1384 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1385 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1386 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1387 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1388 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1389 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1390 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1391 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1392 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1393 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1394 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1395 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1396
1397 /* UD AV attributes */
1398
1399 /* multicast attributes */
1400
1401 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1402 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1403 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1404 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1405
1406 /* TPT attributes */
1407
1408 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1409 if (!mthca_is_memfree(dev))
1410 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1411 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1412 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1413
1414 /* UAR attributes */
1415 {
1416 u8 uar_page_sz = PAGE_SHIFT - 12;
1417 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1418 }
1419
1420 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1421
1422 if (mthca_is_memfree(dev)) {
1423 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1424 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1425 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1426 }
1427
1428 err = mthca_cmd(dev, mailbox->dma, 0, 0,
1429 CMD_INIT_HCA, CMD_TIME_CLASS_D);
1430
1431 mthca_free_mailbox(dev, mailbox);
1432 return err;
1433 }
1434
mthca_INIT_IB(struct mthca_dev * dev,struct mthca_init_ib_param * param,int port)1435 int mthca_INIT_IB(struct mthca_dev *dev,
1436 struct mthca_init_ib_param *param,
1437 int port)
1438 {
1439 struct mthca_mailbox *mailbox;
1440 u32 *inbox;
1441 int err;
1442 u32 flags;
1443
1444 #define INIT_IB_IN_SIZE 56
1445 #define INIT_IB_FLAGS_OFFSET 0x00
1446 #define INIT_IB_FLAG_SIG (1 << 18)
1447 #define INIT_IB_FLAG_NG (1 << 17)
1448 #define INIT_IB_FLAG_G0 (1 << 16)
1449 #define INIT_IB_VL_SHIFT 4
1450 #define INIT_IB_PORT_WIDTH_SHIFT 8
1451 #define INIT_IB_MTU_SHIFT 12
1452 #define INIT_IB_MAX_GID_OFFSET 0x06
1453 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1454 #define INIT_IB_GUID0_OFFSET 0x10
1455 #define INIT_IB_NODE_GUID_OFFSET 0x18
1456 #define INIT_IB_SI_GUID_OFFSET 0x20
1457
1458 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1459 if (IS_ERR(mailbox))
1460 return PTR_ERR(mailbox);
1461 inbox = mailbox->buf;
1462
1463 memset(inbox, 0, INIT_IB_IN_SIZE);
1464
1465 flags = 0;
1466 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1467 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1468 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1469 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1470 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1471 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1472 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1473
1474 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1475 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1476 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1477 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1478 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1479
1480 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1481 CMD_TIME_CLASS_A);
1482
1483 mthca_free_mailbox(dev, mailbox);
1484 return err;
1485 }
1486
mthca_CLOSE_IB(struct mthca_dev * dev,int port)1487 int mthca_CLOSE_IB(struct mthca_dev *dev, int port)
1488 {
1489 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A);
1490 }
1491
mthca_CLOSE_HCA(struct mthca_dev * dev,int panic)1492 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic)
1493 {
1494 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C);
1495 }
1496
mthca_SET_IB(struct mthca_dev * dev,struct mthca_set_ib_param * param,int port)1497 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1498 int port)
1499 {
1500 struct mthca_mailbox *mailbox;
1501 u32 *inbox;
1502 int err;
1503 u32 flags = 0;
1504
1505 #define SET_IB_IN_SIZE 0x40
1506 #define SET_IB_FLAGS_OFFSET 0x00
1507 #define SET_IB_FLAG_SIG (1 << 18)
1508 #define SET_IB_FLAG_RQK (1 << 0)
1509 #define SET_IB_CAP_MASK_OFFSET 0x04
1510 #define SET_IB_SI_GUID_OFFSET 0x08
1511
1512 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1513 if (IS_ERR(mailbox))
1514 return PTR_ERR(mailbox);
1515 inbox = mailbox->buf;
1516
1517 memset(inbox, 0, SET_IB_IN_SIZE);
1518
1519 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1520 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1521 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1522
1523 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1524 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1525
1526 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1527 CMD_TIME_CLASS_B);
1528
1529 mthca_free_mailbox(dev, mailbox);
1530 return err;
1531 }
1532
mthca_MAP_ICM(struct mthca_dev * dev,struct mthca_icm * icm,u64 virt)1533 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt)
1534 {
1535 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt);
1536 }
1537
mthca_MAP_ICM_page(struct mthca_dev * dev,u64 dma_addr,u64 virt)1538 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt)
1539 {
1540 struct mthca_mailbox *mailbox;
1541 __be64 *inbox;
1542 int err;
1543
1544 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1545 if (IS_ERR(mailbox))
1546 return PTR_ERR(mailbox);
1547 inbox = mailbox->buf;
1548
1549 inbox[0] = cpu_to_be64(virt);
1550 inbox[1] = cpu_to_be64(dma_addr);
1551
1552 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1553 CMD_TIME_CLASS_B);
1554
1555 mthca_free_mailbox(dev, mailbox);
1556
1557 if (!err)
1558 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1559 (unsigned long long) dma_addr, (unsigned long long) virt);
1560
1561 return err;
1562 }
1563
mthca_UNMAP_ICM(struct mthca_dev * dev,u64 virt,u32 page_count)1564 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count)
1565 {
1566 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1567 page_count, (unsigned long long) virt);
1568
1569 return mthca_cmd(dev, virt, page_count, 0,
1570 CMD_UNMAP_ICM, CMD_TIME_CLASS_B);
1571 }
1572
mthca_MAP_ICM_AUX(struct mthca_dev * dev,struct mthca_icm * icm)1573 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm)
1574 {
1575 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1);
1576 }
1577
mthca_UNMAP_ICM_AUX(struct mthca_dev * dev)1578 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev)
1579 {
1580 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B);
1581 }
1582
mthca_SET_ICM_SIZE(struct mthca_dev * dev,u64 icm_size,u64 * aux_pages)1583 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages)
1584 {
1585 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0,
1586 0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A);
1587
1588 if (ret)
1589 return ret;
1590
1591 /*
1592 * Round up number of system pages needed in case
1593 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1594 */
1595 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1596 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1597
1598 return 0;
1599 }
1600
mthca_SW2HW_MPT(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int mpt_index)1601 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1602 int mpt_index)
1603 {
1604 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1605 CMD_TIME_CLASS_B);
1606 }
1607
mthca_HW2SW_MPT(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int mpt_index)1608 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1609 int mpt_index)
1610 {
1611 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1612 !mailbox, CMD_HW2SW_MPT,
1613 CMD_TIME_CLASS_B);
1614 }
1615
mthca_WRITE_MTT(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int num_mtt)1616 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1617 int num_mtt)
1618 {
1619 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1620 CMD_TIME_CLASS_B);
1621 }
1622
mthca_SYNC_TPT(struct mthca_dev * dev)1623 int mthca_SYNC_TPT(struct mthca_dev *dev)
1624 {
1625 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B);
1626 }
1627
mthca_MAP_EQ(struct mthca_dev * dev,u64 event_mask,int unmap,int eq_num)1628 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1629 int eq_num)
1630 {
1631 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1632 unmap ? "Clearing" : "Setting",
1633 (unsigned long long) event_mask, eq_num);
1634 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1635 0, CMD_MAP_EQ, CMD_TIME_CLASS_B);
1636 }
1637
mthca_SW2HW_EQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int eq_num)1638 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1639 int eq_num)
1640 {
1641 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1642 CMD_TIME_CLASS_A);
1643 }
1644
mthca_HW2SW_EQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int eq_num)1645 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1646 int eq_num)
1647 {
1648 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1649 CMD_HW2SW_EQ,
1650 CMD_TIME_CLASS_A);
1651 }
1652
mthca_SW2HW_CQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int cq_num)1653 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1654 int cq_num)
1655 {
1656 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1657 CMD_TIME_CLASS_A);
1658 }
1659
mthca_HW2SW_CQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int cq_num)1660 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1661 int cq_num)
1662 {
1663 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1664 CMD_HW2SW_CQ,
1665 CMD_TIME_CLASS_A);
1666 }
1667
mthca_RESIZE_CQ(struct mthca_dev * dev,int cq_num,u32 lkey,u8 log_size)1668 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size)
1669 {
1670 struct mthca_mailbox *mailbox;
1671 __be32 *inbox;
1672 int err;
1673
1674 #define RESIZE_CQ_IN_SIZE 0x40
1675 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1676 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1677
1678 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1679 if (IS_ERR(mailbox))
1680 return PTR_ERR(mailbox);
1681 inbox = mailbox->buf;
1682
1683 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1684 /*
1685 * Leave start address fields zeroed out -- mthca assumes that
1686 * MRs for CQs always start at virtual address 0.
1687 */
1688 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1689 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1690
1691 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1692 CMD_TIME_CLASS_B);
1693
1694 mthca_free_mailbox(dev, mailbox);
1695 return err;
1696 }
1697
mthca_SW2HW_SRQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int srq_num)1698 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1699 int srq_num)
1700 {
1701 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1702 CMD_TIME_CLASS_A);
1703 }
1704
mthca_HW2SW_SRQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int srq_num)1705 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1706 int srq_num)
1707 {
1708 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1709 CMD_HW2SW_SRQ,
1710 CMD_TIME_CLASS_A);
1711 }
1712
mthca_QUERY_SRQ(struct mthca_dev * dev,u32 num,struct mthca_mailbox * mailbox)1713 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1714 struct mthca_mailbox *mailbox)
1715 {
1716 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1717 CMD_QUERY_SRQ, CMD_TIME_CLASS_A);
1718 }
1719
mthca_ARM_SRQ(struct mthca_dev * dev,int srq_num,int limit)1720 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit)
1721 {
1722 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1723 CMD_TIME_CLASS_B);
1724 }
1725
mthca_MODIFY_QP(struct mthca_dev * dev,enum ib_qp_state cur,enum ib_qp_state next,u32 num,int is_ee,struct mthca_mailbox * mailbox,u32 optmask)1726 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1727 enum ib_qp_state next, u32 num, int is_ee,
1728 struct mthca_mailbox *mailbox, u32 optmask)
1729 {
1730 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1731 [IB_QPS_RESET] = {
1732 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1733 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1734 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1735 },
1736 [IB_QPS_INIT] = {
1737 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1738 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1739 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1740 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1741 },
1742 [IB_QPS_RTR] = {
1743 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1744 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1745 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1746 },
1747 [IB_QPS_RTS] = {
1748 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1749 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1750 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1751 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1752 },
1753 [IB_QPS_SQD] = {
1754 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1755 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1756 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1757 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1758 },
1759 [IB_QPS_SQE] = {
1760 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1761 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1762 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1763 },
1764 [IB_QPS_ERR] = {
1765 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1766 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1767 }
1768 };
1769
1770 u8 op_mod = 0;
1771 int my_mailbox = 0;
1772 int err;
1773
1774 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1775 op_mod = 3; /* don't write outbox, any->reset */
1776
1777 /* For debugging */
1778 if (!mailbox) {
1779 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1780 if (!IS_ERR(mailbox)) {
1781 my_mailbox = 1;
1782 op_mod = 2; /* write outbox, any->reset */
1783 } else
1784 mailbox = NULL;
1785 }
1786
1787 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1788 (!!is_ee << 24) | num, op_mod,
1789 op[cur][next], CMD_TIME_CLASS_C);
1790
1791 if (0 && mailbox) {
1792 int i;
1793 mthca_dbg(dev, "Dumping QP context:\n");
1794 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1795 for (i = 0; i < 0x100 / 4; ++i) {
1796 if (i % 8 == 0)
1797 printk("[%02x] ", i * 4);
1798 printk(" %08x",
1799 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1800 if ((i + 1) % 8 == 0)
1801 printk("\n");
1802 }
1803 }
1804
1805 if (my_mailbox)
1806 mthca_free_mailbox(dev, mailbox);
1807 } else {
1808 if (0) {
1809 int i;
1810 mthca_dbg(dev, "Dumping QP context:\n");
1811 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1812 for (i = 0; i < 0x100 / 4; ++i) {
1813 if (i % 8 == 0)
1814 printk(" [%02x] ", i * 4);
1815 printk(" %08x",
1816 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1817 if ((i + 1) % 8 == 0)
1818 printk("\n");
1819 }
1820 }
1821
1822 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1823 op_mod, op[cur][next], CMD_TIME_CLASS_C);
1824 }
1825
1826 return err;
1827 }
1828
mthca_QUERY_QP(struct mthca_dev * dev,u32 num,int is_ee,struct mthca_mailbox * mailbox)1829 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1830 struct mthca_mailbox *mailbox)
1831 {
1832 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1833 CMD_QUERY_QPEE, CMD_TIME_CLASS_A);
1834 }
1835
mthca_CONF_SPECIAL_QP(struct mthca_dev * dev,int type,u32 qpn)1836 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn)
1837 {
1838 u8 op_mod;
1839
1840 switch (type) {
1841 case IB_QPT_SMI:
1842 op_mod = 0;
1843 break;
1844 case IB_QPT_GSI:
1845 op_mod = 1;
1846 break;
1847 case IB_QPT_RAW_IPV6:
1848 op_mod = 2;
1849 break;
1850 case IB_QPT_RAW_ETHERTYPE:
1851 op_mod = 3;
1852 break;
1853 default:
1854 return -EINVAL;
1855 }
1856
1857 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1858 CMD_TIME_CLASS_B);
1859 }
1860
mthca_MAD_IFC(struct mthca_dev * dev,int ignore_mkey,int ignore_bkey,int port,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const void * in_mad,void * response_mad)1861 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1862 int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1863 const void *in_mad, void *response_mad)
1864 {
1865 struct mthca_mailbox *inmailbox, *outmailbox;
1866 void *inbox;
1867 int err;
1868 u32 in_modifier = port;
1869 u8 op_modifier = 0;
1870
1871 #define MAD_IFC_BOX_SIZE 0x400
1872 #define MAD_IFC_MY_QPN_OFFSET 0x100
1873 #define MAD_IFC_RQPN_OFFSET 0x108
1874 #define MAD_IFC_SL_OFFSET 0x10c
1875 #define MAD_IFC_G_PATH_OFFSET 0x10d
1876 #define MAD_IFC_RLID_OFFSET 0x10e
1877 #define MAD_IFC_PKEY_OFFSET 0x112
1878 #define MAD_IFC_GRH_OFFSET 0x140
1879
1880 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1881 if (IS_ERR(inmailbox))
1882 return PTR_ERR(inmailbox);
1883 inbox = inmailbox->buf;
1884
1885 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1886 if (IS_ERR(outmailbox)) {
1887 mthca_free_mailbox(dev, inmailbox);
1888 return PTR_ERR(outmailbox);
1889 }
1890
1891 memcpy(inbox, in_mad, 256);
1892
1893 /*
1894 * Key check traps can't be generated unless we have in_wc to
1895 * tell us where to send the trap.
1896 */
1897 if (ignore_mkey || !in_wc)
1898 op_modifier |= 0x1;
1899 if (ignore_bkey || !in_wc)
1900 op_modifier |= 0x2;
1901
1902 if (in_wc) {
1903 u8 val;
1904
1905 memset(inbox + 256, 0, 256);
1906
1907 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
1908 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1909
1910 val = in_wc->sl << 4;
1911 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1912
1913 val = in_wc->dlid_path_bits |
1914 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1915 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1916
1917 MTHCA_PUT(inbox, ib_lid_cpu16(in_wc->slid), MAD_IFC_RLID_OFFSET);
1918 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1919
1920 if (in_grh)
1921 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1922
1923 op_modifier |= 0x4;
1924
1925 in_modifier |= ib_lid_cpu16(in_wc->slid) << 16;
1926 }
1927
1928 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1929 in_modifier, op_modifier,
1930 CMD_MAD_IFC, CMD_TIME_CLASS_C);
1931
1932 if (!err)
1933 memcpy(response_mad, outmailbox->buf, 256);
1934
1935 mthca_free_mailbox(dev, inmailbox);
1936 mthca_free_mailbox(dev, outmailbox);
1937 return err;
1938 }
1939
mthca_READ_MGM(struct mthca_dev * dev,int index,struct mthca_mailbox * mailbox)1940 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1941 struct mthca_mailbox *mailbox)
1942 {
1943 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1944 CMD_READ_MGM, CMD_TIME_CLASS_A);
1945 }
1946
mthca_WRITE_MGM(struct mthca_dev * dev,int index,struct mthca_mailbox * mailbox)1947 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1948 struct mthca_mailbox *mailbox)
1949 {
1950 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1951 CMD_TIME_CLASS_A);
1952 }
1953
mthca_MGID_HASH(struct mthca_dev * dev,struct mthca_mailbox * mailbox,u16 * hash)1954 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1955 u16 *hash)
1956 {
1957 u64 imm = 0;
1958 int err;
1959
1960 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1961 CMD_TIME_CLASS_A);
1962
1963 *hash = imm;
1964 return err;
1965 }
1966
mthca_NOP(struct mthca_dev * dev)1967 int mthca_NOP(struct mthca_dev *dev)
1968 {
1969 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100));
1970 }
1971